diff options
| author | Leah Rowe <leah@libreboot.org> | 2023-10-06 22:59:36 +0100 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2023-10-07 00:11:21 +0100 |
| commit | 4e39d5a5a808b0d59c6fb3426e1d9bc0195d6b08 (patch) | |
| tree | 26ccd90ebffb18c70132e6192f27bac1c4c3522c /config/coreboot/t440pmrc_12mb | |
| parent | 965b6a7ed73f1dbd78a353c83b99a88b50c86f38 (diff) | |
put all src downloads under src/
build/release/src was partly re-written to accomodate this
memtest86plus was patched to have a central Makefile, and
lbmk modified to use that, rather than mess with build32
and build64. the central Makefile just builds both targets
or cleans both targets
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/t440pmrc_12mb')
| -rw-r--r-- | config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb | 8 | ||||
| -rw-r--r-- | config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb index 96fe0b73..8801b7cd 100644 --- a/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb @@ -145,9 +145,9 @@ CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DRIVERS_INTEL_WIFI=y -CONFIG_IFD_BIN_PATH="../../config/ifd/t440p/ifd" -CONFIG_ME_BIN_PATH="../../blobs/t440p/me.bin" -CONFIG_GBE_BIN_PATH="../../config/ifd/t440p/gbe" +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../blobs/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y @@ -261,7 +261,7 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y CONFIG_HAVE_MRC=y -CONFIG_MRC_FILE="../../mrc/haswell/mrc.bin" +CONFIG_MRC_FILE="../../../mrc/haswell/mrc.bin" CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 diff --git a/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode index 7827b487..336cae08 100644 --- a/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode @@ -143,9 +143,9 @@ CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DRIVERS_INTEL_WIFI=y -CONFIG_IFD_BIN_PATH="../../config/ifd/t440p/ifd" -CONFIG_ME_BIN_PATH="../../blobs/t440p/me.bin" -CONFIG_GBE_BIN_PATH="../../config/ifd/t440p/gbe" +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../blobs/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y @@ -259,7 +259,7 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y CONFIG_HAVE_MRC=y -CONFIG_MRC_FILE="../../mrc/haswell/mrc.bin" +CONFIG_MRC_FILE="../../../mrc/haswell/mrc.bin" CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 |