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authorLeah Rowe <leah@libreboot.org>2024-08-06 01:43:57 +0100
committerLeah Rowe <leah@libreboot.org>2024-08-09 20:55:42 +0100
commita15347ef1e677ca711ce706877db2416ddfd451a (patch)
tree7ddea08641383688c22f3105eb9ef95fe2e6f7a7 /config/coreboot/r400_8mb
parentdbe24b039d381365b62c02802016f108c3efe8eb (diff)
coreboot/dell: merge into coreboot/default
The libgfxinit patch and other patches e.g. DDR2 fix, are now provided in coreboot/default. The Latitude E6400 is now using the newer coreboot revision from late July 2024. Some other configs had to change because of this, relating to the new way that Nicholas handles timing on LVDS displays with the E6400 port; a default 96MHz clock is still used for pixel reference clock, overridden with a value of 100MHz on other GM45 machines, where 96MHz was previously hardcoded. Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/r400_8mb')
-rw-r--r--config/coreboot/r400_8mb/config/libgfxinit_corebootfb1
-rw-r--r--config/coreboot/r400_8mb/config/libgfxinit_txtmode1
2 files changed, 2 insertions, 0 deletions
diff --git a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb
index cf2abe92..4faef26a 100644
--- a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb
@@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
+CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
diff --git a/config/coreboot/r400_8mb/config/libgfxinit_txtmode b/config/coreboot/r400_8mb/config/libgfxinit_txtmode
index 1eac7a90..21b32616 100644
--- a/config/coreboot/r400_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/r400_8mb/config/libgfxinit_txtmode
@@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
+CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"