diff options
62 files changed, 432 insertions, 836 deletions
diff --git a/config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0040-nb-intel-gm45-Make-DDR2-raminit-work.patch index 8de8060f..b673b5f6 100644 --- a/config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0040-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From f26df5dff7be4b0c9d8dced1cf6ed07472a174c7 Mon Sep 17 00:00:00 2001 +From fe5e1655be8cdb8eff1659e5ce6acbd06b9a7620 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 8/9] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 1/3] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values @@ -20,10 +20,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> 3 files changed, 106 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h -index d929533d92..997f8a0e5a 100644 +index 5d9ac56606..338260ea7a 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h -@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); +@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); int raminit_read_vco_index(void); u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank); diff --git a/config/coreboot/default/patches/0041-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0041-nb-intel-gm45-Make-DDR2-raminit-work.patch new file mode 100644 index 00000000..2f50be66 --- /dev/null +++ b/config/coreboot/default/patches/0041-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -0,0 +1,269 @@ +From 65510f6ea53d6f23f47df69d623810aa87041918 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Tue, 6 Aug 2024 00:50:24 +0100 +Subject: [PATCH 2/3] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards + +We add this patch: + +commit commit_id_here +Author: Angel Pons <th3fanbus@gmail.com> +Date: Mon May 10 22:40:59 2021 +0200 + + nb/intel/gm45: Make DDR2 raminit work + +This patch was original applied, in lbmk, only on coreboot/dell, +separately from coreboot/default, which was wasteful because it +meant having an entire coreboot tree just for a single board. We +did this, because the DDR2 RCOMP fix happened to break DDR3 init +on other boards. + +What *this* new patch does on top of Angel's patch, is make sure +that their changes only apply to DDR2, while DDR3 behaviour remains +unchanged. This means that the Dell Latitude E6400 can be supported +in the main coreboot tree, within lbmk. + +Essentially, this patch restores the old behaviour, prior to applying +Angel's patch, only when DDR3 memory is used. + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/northbridge/intel/gm45/raminit.c | 182 ++++++++++-------- + .../intel/gm45/raminit_rcomp_calibration.c | 9 +- + 2 files changed, 104 insertions(+), 87 deletions(-) + +diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c +index df8f46fbbc..b051374eaa 100644 +--- a/src/northbridge/intel/gm45/raminit.c ++++ b/src/northbridge/intel/gm45/raminit.c +@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi + reg = (reg & ~(0xf << 10)) | (2 << 10); + else + reg = (reg & ~(0xf << 10)) | (3 << 10); +- reg = (reg & ~(0x7 << 5)) | (2 << 5); ++ if (sysinfo->spd_type == DDR2) ++ reg = (reg & ~(0x7 << 5)) | (2 << 5); ++ else ++ reg = (reg & ~(0x7 << 5)) | (3 << 5); + } else if (timings->mem_clock != MEM_CLOCK_1067MT) { + reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); + reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); +@@ -1285,12 +1288,23 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff) + reg = (reg & ~(0x7 << (48 - 32))) | ((timings->CAS - 2) << (48 - 32)); + reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32)); + reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32)); +- if (timings->mem_clock == MEM_CLOCK_667MT) { +- reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32)); +- reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32)); ++ if (sysinfo->spd_type == DDR2) { ++ if (timings->mem_clock == MEM_CLOCK_667MT) { ++ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32)); ++ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32)); ++ } else { ++ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32)); ++ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32)); ++ } + } else { +- reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32)); +- reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32)); ++ /* DDR3 */ ++ if (timings->mem_clock == MEM_CLOCK_667MT) { ++ reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32)); ++ reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32)); ++ } else { ++ reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32)); ++ reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32)); ++ } + } + mchbar_write32(CxODT_HIGH(ch), reg); + +@@ -2209,83 +2223,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) + raminit_write_training(timings->mem_clock, dimms, s3resume); + } + +- /* +- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done +- * after receiver enable calibration, otherwise raminit sometimes +- * completes with non-working memory. +- */ +- mchbar_write32(0x0530, 0x06060005); +- mchbar_write32(0x0680, 0x06060606); +- mchbar_write32(0x0684, 0x08070606); +- mchbar_write32(0x0688, 0x0e0e0c0a); +- mchbar_write32(0x068c, 0x0e0e0e0e); +- mchbar_write32(0x0698, 0x06060606); +- mchbar_write32(0x069c, 0x08070606); +- mchbar_write32(0x06a0, 0x0c0c0b0a); +- mchbar_write32(0x06a4, 0x0c0c0c0c); +- +- mchbar_write32(0x06c0, 0x02020202); +- mchbar_write32(0x06c4, 0x03020202); +- mchbar_write32(0x06c8, 0x04040403); +- mchbar_write32(0x06cc, 0x04040404); +- mchbar_write32(0x06d8, 0x02020202); +- mchbar_write32(0x06dc, 0x03020202); +- mchbar_write32(0x06e0, 0x04040403); +- mchbar_write32(0x06e4, 0x04040404); +- +- mchbar_write32(0x0700, 0x02020202); +- mchbar_write32(0x0704, 0x03020202); +- mchbar_write32(0x0708, 0x04040403); +- mchbar_write32(0x070c, 0x04040404); +- mchbar_write32(0x0718, 0x02020202); +- mchbar_write32(0x071c, 0x03020202); +- mchbar_write32(0x0720, 0x04040403); +- mchbar_write32(0x0724, 0x04040404); +- +- mchbar_write32(0x0740, 0x02020202); +- mchbar_write32(0x0744, 0x03020202); +- mchbar_write32(0x0748, 0x04040403); +- mchbar_write32(0x074c, 0x04040404); +- mchbar_write32(0x0758, 0x02020202); +- mchbar_write32(0x075c, 0x03020202); +- mchbar_write32(0x0760, 0x04040403); +- mchbar_write32(0x0764, 0x04040404); +- +- mchbar_write32(0x0780, 0x06060606); +- mchbar_write32(0x0784, 0x09070606); +- mchbar_write32(0x0788, 0x0e0e0c0b); +- mchbar_write32(0x078c, 0x0e0e0e0e); +- mchbar_write32(0x0798, 0x06060606); +- mchbar_write32(0x079c, 0x09070606); +- mchbar_write32(0x07a0, 0x0d0d0c0b); +- mchbar_write32(0x07a4, 0x0d0d0d0d); +- +- mchbar_write32(0x07c0, 0x06060606); +- mchbar_write32(0x07c4, 0x09070606); +- mchbar_write32(0x07c8, 0x0e0e0c0b); +- mchbar_write32(0x07cc, 0x0e0e0e0e); +- mchbar_write32(0x07d8, 0x06060606); +- mchbar_write32(0x07dc, 0x09070606); +- mchbar_write32(0x07e0, 0x0d0d0c0b); +- mchbar_write32(0x07e4, 0x0d0d0d0d); +- +- mchbar_write32(0x0840, 0x06060606); +- mchbar_write32(0x0844, 0x08070606); +- mchbar_write32(0x0848, 0x0e0e0c0a); +- mchbar_write32(0x084c, 0x0e0e0e0e); +- mchbar_write32(0x0858, 0x06060606); +- mchbar_write32(0x085c, 0x08070606); +- mchbar_write32(0x0860, 0x0c0c0b0a); +- mchbar_write32(0x0864, 0x0c0c0c0c); +- +- mchbar_write32(0x0880, 0x02020202); +- mchbar_write32(0x0884, 0x03020202); +- mchbar_write32(0x0888, 0x04040403); +- mchbar_write32(0x088c, 0x04040404); +- mchbar_write32(0x0898, 0x02020202); +- mchbar_write32(0x089c, 0x03020202); +- mchbar_write32(0x08a0, 0x04040403); +- mchbar_write32(0x08a4, 0x04040404); ++ if (sysinfo->spd_type == DDR2) { ++ /* ++ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done ++ * after receiver enable calibration, otherwise raminit sometimes ++ * completes with non-working memory. ++ */ ++ mchbar_write32(0x0530, 0x06060005); ++ mchbar_write32(0x0680, 0x06060606); ++ mchbar_write32(0x0684, 0x08070606); ++ mchbar_write32(0x0688, 0x0e0e0c0a); ++ mchbar_write32(0x068c, 0x0e0e0e0e); ++ mchbar_write32(0x0698, 0x06060606); ++ mchbar_write32(0x069c, 0x08070606); ++ mchbar_write32(0x06a0, 0x0c0c0b0a); ++ mchbar_write32(0x06a4, 0x0c0c0c0c); ++ ++ mchbar_write32(0x06c0, 0x02020202); ++ mchbar_write32(0x06c4, 0x03020202); ++ mchbar_write32(0x06c8, 0x04040403); ++ mchbar_write32(0x06cc, 0x04040404); ++ mchbar_write32(0x06d8, 0x02020202); ++ mchbar_write32(0x06dc, 0x03020202); ++ mchbar_write32(0x06e0, 0x04040403); ++ mchbar_write32(0x06e4, 0x04040404); ++ ++ mchbar_write32(0x0700, 0x02020202); ++ mchbar_write32(0x0704, 0x03020202); ++ mchbar_write32(0x0708, 0x04040403); ++ mchbar_write32(0x070c, 0x04040404); ++ mchbar_write32(0x0718, 0x02020202); ++ mchbar_write32(0x071c, 0x03020202); ++ mchbar_write32(0x0720, 0x04040403); ++ mchbar_write32(0x0724, 0x04040404); ++ ++ mchbar_write32(0x0740, 0x02020202); ++ mchbar_write32(0x0744, 0x03020202); ++ mchbar_write32(0x0748, 0x04040403); ++ mchbar_write32(0x074c, 0x04040404); ++ mchbar_write32(0x0758, 0x02020202); ++ mchbar_write32(0x075c, 0x03020202); ++ mchbar_write32(0x0760, 0x04040403); ++ mchbar_write32(0x0764, 0x04040404); ++ ++ mchbar_write32(0x0780, 0x06060606); ++ mchbar_write32(0x0784, 0x09070606); ++ mchbar_write32(0x0788, 0x0e0e0c0b); ++ mchbar_write32(0x078c, 0x0e0e0e0e); ++ mchbar_write32(0x0798, 0x06060606); ++ mchbar_write32(0x079c, 0x09070606); ++ mchbar_write32(0x07a0, 0x0d0d0c0b); ++ mchbar_write32(0x07a4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x07c0, 0x06060606); ++ mchbar_write32(0x07c4, 0x09070606); ++ mchbar_write32(0x07c8, 0x0e0e0c0b); ++ mchbar_write32(0x07cc, 0x0e0e0e0e); ++ mchbar_write32(0x07d8, 0x06060606); ++ mchbar_write32(0x07dc, 0x09070606); ++ mchbar_write32(0x07e0, 0x0d0d0c0b); ++ mchbar_write32(0x07e4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x0840, 0x06060606); ++ mchbar_write32(0x0844, 0x08070606); ++ mchbar_write32(0x0848, 0x0e0e0c0a); ++ mchbar_write32(0x084c, 0x0e0e0e0e); ++ mchbar_write32(0x0858, 0x06060606); ++ mchbar_write32(0x085c, 0x08070606); ++ mchbar_write32(0x0860, 0x0c0c0b0a); ++ mchbar_write32(0x0864, 0x0c0c0c0c); ++ ++ mchbar_write32(0x0880, 0x02020202); ++ mchbar_write32(0x0884, 0x03020202); ++ mchbar_write32(0x0888, 0x04040403); ++ mchbar_write32(0x088c, 0x04040404); ++ mchbar_write32(0x0898, 0x02020202); ++ mchbar_write32(0x089c, 0x03020202); ++ mchbar_write32(0x08a0, 0x04040403); ++ mchbar_write32(0x08a4, 0x04040404); ++ } + + igd_compute_ggc(sysinfo); + +diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +index b74765fd9c..5d4505e063 100644 +--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c ++++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { + reg = mchbar_read32(0x518); + lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; + lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; +- if (i == 1) { ++ if ((i == 1) && (ddr_type == DDR2)) { + magic_comp[0] = (reg >> 8) & 0x3f; + magic_comp[1] = (reg >> 0) & 0x3f; + } +@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { + } + mchbar += 0x0040; + } +- +- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); +- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); ++ if (ddr_type == DDR2) { ++ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); ++ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); ++ } + } +-- +2.39.2 + diff --git a/config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index f64743a5..991dcf44 100644 --- a/config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/coreboot/default/patches/0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From 6f4968919cf4e801caacf8392492457b79efa9c6 Mon Sep 17 00:00:00 2001 +From b42ca30081b25cbabfb2659adca9d935ef3a8399 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 3/3] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For @@ -19,10 +19,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> 2 files changed, 7 insertions(+) diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig -index 034de4be2b..4cb16af697 100644 +index 417d95fd5d..6fe1b1c456 100644 --- a/src/mainboard/dell/e6400/Kconfig +++ b/src/mainboard/dell/e6400/Kconfig -@@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS +@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_GMA_HAVE_VBT select EC_DELL_MEC5035 @@ -33,10 +33,10 @@ index 034de4be2b..4cb16af697 100644 default "dell/e6400" diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index 2a266b9771..2432c9d78e 100644 +index 8059e7ee80..5df5a93296 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig -@@ -13,6 +13,10 @@ config NORTHBRIDGE_INTEL_GM45 +@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45 if NORTHBRIDGE_INTEL_GM45 @@ -48,5 +48,5 @@ index 2a266b9771..2432c9d78e 100644 select VBOOT_STARTS_IN_BOOTBLOCK -- -2.45.1 +2.39.2 diff --git a/config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch deleted file mode 100644 index cb1effa7..00000000 --- a/config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ /dev/null @@ -1,203 +0,0 @@ -From 4fbd327df271d613d4a56a36eafd88d9d642ec6b Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 1/9] util/ifdtool: add --nuke flag (all 0xFF on region) - -When this option is used, the region's contents are overwritten -with all ones (0xFF). - -Example: - -./ifdtool --nuke gbe coreboot.rom -./ifdtool --nuke bios coreboot.com -./ifdtool --nuke me coreboot.com - -Rebased since the last revision update in lbmk. - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------ - 1 file changed, 81 insertions(+), 31 deletions(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 191b3216de..38132b4a28 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -1942,6 +1942,7 @@ static void print_usage(const char *name) - " tgl - Tiger Lake\n" - " wbg - Wellsburg\n" - " -S | --setpchstrap Write a PCH strap\n" -+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n" - " -V | --newvalue The new value to write into PCH strap specified by -S\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" -@@ -1950,6 +1951,60 @@ static void print_usage(const char *name) - "\n"); - } - -+static int -+get_region_type_string(const char *region_type_string) -+{ -+ if (!strcasecmp("Descriptor", region_type_string)) -+ return 0; -+ else if (!strcasecmp("BIOS", region_type_string)) -+ return 1; -+ else if (!strcasecmp("ME", region_type_string)) -+ return 2; -+ else if (!strcasecmp("GbE", region_type_string)) -+ return 3; -+ else if (!strcasecmp("Platform Data", region_type_string)) -+ return 4; -+ else if (!strcasecmp("Device Exp1", region_type_string)) -+ return 5; -+ else if (!strcasecmp("Secondary BIOS", region_type_string)) -+ return 6; -+ else if (!strcasecmp("Reserved", region_type_string)) -+ return 7; -+ else if (!strcasecmp("EC", region_type_string)) -+ return 8; -+ else if (!strcasecmp("Device Exp2", region_type_string)) -+ return 9; -+ else if (!strcasecmp("IE", region_type_string)) -+ return 10; -+ else if (!strcasecmp("10GbE_0", region_type_string)) -+ return 11; -+ else if (!strcasecmp("10GbE_1", region_type_string)) -+ return 12; -+ else if (!strcasecmp("PTT", region_type_string)) -+ return 15; -+ return -1; -+} -+ -+static void -+nuke(const char *filename, char *image, int size, int region_type) -+{ -+ int i; -+ struct region region; -+ const struct frba *frba = find_frba(image, size); -+ if (!frba) -+ exit(EXIT_FAILURE); -+ -+ region = get_region(frba, region_type); -+ if (region.size > 0) { -+ for (i = region.base; i <= region.limit; i++) { -+ if ((i + 1) > (size)) -+ break; -+ image[i] = 0xFF; -+ } -+ write_image(filename, image, size); -+ } -+} -+ - int main(int argc, char *argv[]) - { - int opt, option_index = 0; -@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[]) - int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; - int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; - int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; -+ int mode_nuke = 0; - int mode_gpr0_disable = 0; - char *region_type_string = NULL, *region_fname = NULL; - const char *layout_fname = NULL; -@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[]) - {"validate", 0, NULL, 't'}, - {"setpchstrap", 1, NULL, 'S'}, - {"newvalue", 1, NULL, 'V'}, -+ {"nuke", 1, NULL, 'N'}, - {0, 0, 0, 0} - }; - -@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[]) - region_fname++; - // Descriptor, BIOS, ME, GbE, Platform - // valid type? -- if (!strcasecmp("Descriptor", region_type_string)) -- region_type = 0; -- else if (!strcasecmp("BIOS", region_type_string)) -- region_type = 1; -- else if (!strcasecmp("ME", region_type_string)) -- region_type = 2; -- else if (!strcasecmp("GbE", region_type_string)) -- region_type = 3; -- else if (!strcasecmp("Platform Data", region_type_string)) -- region_type = 4; -- else if (!strcasecmp("Device Exp1", region_type_string)) -- region_type = 5; -- else if (!strcasecmp("Secondary BIOS", region_type_string)) -- region_type = 6; -- else if (!strcasecmp("Reserved", region_type_string)) -- region_type = 7; -- else if (!strcasecmp("EC", region_type_string)) -- region_type = 8; -- else if (!strcasecmp("Device Exp2", region_type_string)) -- region_type = 9; -- else if (!strcasecmp("IE", region_type_string)) -- region_type = 10; -- else if (!strcasecmp("10GbE_0", region_type_string)) -- region_type = 11; -- else if (!strcasecmp("10GbE_1", region_type_string)) -- region_type = 12; -- else if (!strcasecmp("PTT", region_type_string)) -- region_type = 15; -- if (region_type == -1) { -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { - fprintf(stderr, "No such region type: '%s'\n\n", - region_type_string); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); -@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[]) - case 't': - mode_validate = 1; - break; -+ case 'N': -+ region_type_string = strdup(optarg); -+ if (!region_type_string) { -+ fprintf(stderr, "No region specified\n"); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { -+ fprintf(stderr, "No such region type: '%s'\n\n", -+ region_type_string); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ mode_nuke = 1; -+ break; - case 'v': - print_version(); - exit(EXIT_SUCCESS); -@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[]) - if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | - mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + -- mode_gpr0_disable) > 1) { -+ mode_gpr0_disable + mode_nuke) > 1) { - fprintf(stderr, "You may not specify more than one mode.\n\n"); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); - exit(EXIT_FAILURE); -@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[]) - if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + - mode_locked + mode_unlocked + mode_density + mode_altmedisable + -- mode_validate + mode_gpr0_disable) == 0) { -+ mode_validate + mode_gpr0_disable + mode_nuke) == 0) { - fprintf(stderr, "You need to specify a mode.\n\n"); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); - exit(EXIT_FAILURE); -@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[]) - write_image(new_filename, image, size); - } - -+ if (mode_nuke) { -+ nuke(new_filename, image, size, region_type); -+ } -+ - if (mode_altmedisable) { - struct fpsba *fpsba = find_fpsba(image, size); - struct fmsba *fmsba = find_fmsba(image, size); --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch deleted file mode 100644 index b0ac4e67..00000000 --- a/config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 362e86f89b3980699e7e794df9b98018397fe2d8 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Wed, 1 Dec 2021 02:53:00 +0000 -Subject: [PATCH 2/9] fix speedstep on x200/t400: Revert - "cpu/intel/model_1067x: enable PECI" - -This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f. - -Enabling PECI without microcode updates loaded causes the CPUID feature set -to become corrupted. And one consequence is broken SpeedStep. At least, that's -my understanding looking at Intel Errata. This revert is not a fix, because -upstream is correct (upstream assumes microcode updates). We will simply -maintain this revert patch in Libreboot, from now on. ---- - src/cpu/intel/model_1067x/model_1067x_init.c | 9 --------- - 1 file changed, 9 deletions(-) - -diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c -index 315e7c36fc..1423fd72bc 100644 ---- a/src/cpu/intel/model_1067x/model_1067x_init.c -+++ b/src/cpu/intel/model_1067x/model_1067x_init.c -@@ -141,8 +141,6 @@ static void configure_emttm_tables(void) - wrmsr(MSR_EMTTM_CR_TABLE(5), msr); - } - --#define IA32_PECI_CTL 0x5a0 -- - static void configure_misc(const int eist, const int tm2, const int emttm) - { - msr_t msr; -@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm) - msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - } -- -- /* Enable PECI -- WARNING: due to Erratum AW67 described in Intel document #318733 -- the microcode must be updated before this MSR is written to. */ -- msr = rdmsr(IA32_PECI_CTL); -- msr.lo |= 1; -- wrmsr(IA32_PECI_CTL, msr); - } - - #define PIC_SENS_CFG 0x1aa --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch deleted file mode 100644 index 3193ed97..00000000 --- a/config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch +++ /dev/null @@ -1,173 +0,0 @@ -From 883455573f07551eaf2b12ab80bedcd2b4904a17 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Mon, 17 Apr 2023 15:49:57 +0100 -Subject: [PATCH 3/9] GM45-type CPUs: don't enable alternative SMRR - -This reverts the changes in coreboot revision: -df7aecd92643d207feaf7fd840f8835097346644 - -While this fix is *technically correct*, the one in -coreboot, it breaks rebooting as tested on several -GM45 ThinkPads e.g. X200, T400, when microcode -updates are not applied. - -Since November 2022, Libreboot includes microcode -updates by default, but it tells users how to remove -it from the ROM (with cbfstool) if they wish. - -Well, with Libreboot 20221214, 20230319 and 20230413, -mitigations present in Libreboot 20220710 (which did -not have microcode updates) do not exist. - -This patch, along with the other patch to remove PECI -support (which breaks speedstep when microcode updates -are not applied) have now been re-added to Libreboot. - -It is still best to use microcode updates by default. -These patches in coreboot are not critically urgent, -and you can use the machines with or without them, -regardless of ucode. - -I'll probably re-write this and the other patch at -some point, applying the change conditionally upon -whether or not microcode is applied. - -Pragmatism is a good thing. I recommend it. ---- - src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++ - src/cpu/intel/model_1067x/mp_init.c | 26 -------------------- - src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++ - src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++ - src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++ - 5 files changed, 16 insertions(+), 26 deletions(-) - -diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c -index 1423fd72bc..d1f98ca43a 100644 ---- a/src/cpu/intel/model_1067x/model_1067x_init.c -+++ b/src/cpu/intel/model_1067x/model_1067x_init.c -@@ -8,6 +8,7 @@ - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> - #include <cpu/intel/smm_reloc.h> -+#include <cpu/intel/common/common.h> - - #define MSR_BBL_CR_CTL3 0x11e - -@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu) - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(quad); - -diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c -index bc53214310..72f40f6762 100644 ---- a/src/cpu/intel/model_1067x/mp_init.c -+++ b/src/cpu/intel/model_1067x/mp_init.c -@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void) - smm_initialize(); - } - --#define SMRR_SUPPORTED (1 << 11) -- - static void per_cpu_smm_trigger(void) - { -- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); -- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) { -- set_feature_ctrl_vmx(); -- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL); -- /* We don't care if the lock is already setting -- as our smm relocation handler is able to handle -- setups where SMRR is not enabled here. */ -- if (ia32_ft_ctrl.lo & (1 << 0)) { -- /* IA32_FEATURE_CONTROL locked. If we set it again we -- get an illegal instruction. */ -- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n"); -- printk(BIOS_DEBUG, "SMRR status: %senabled\n", -- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not "); -- } else { -- if (!CONFIG(SET_IA32_FC_LOCK_BIT)) -- printk(BIOS_INFO, -- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n"); -- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); -- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); -- } -- } else { -- set_vmx_and_lock(); -- } -- - /* Relocate the SMM handler. */ - smm_relocate(); - } -diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c -index 05f5f327cc..0450c2ad83 100644 ---- a/src/cpu/intel/model_106cx/model_106cx_init.c -+++ b/src/cpu/intel/model_106cx/model_106cx_init.c -@@ -7,6 +7,7 @@ - #include <cpu/intel/speedstep.h> - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> -+#include <cpu/intel/common/common.h> - - #define HIGHEST_CLEVEL 3 - static void configure_c_states(void) -@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu) - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(); - -diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c -index 5bd1c32815..f3bb08cde3 100644 ---- a/src/cpu/intel/model_6ex/model_6ex_init.c -+++ b/src/cpu/intel/model_6ex/model_6ex_init.c -@@ -7,6 +7,7 @@ - #include <cpu/intel/speedstep.h> - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> -+#include <cpu/intel/common/common.h> - - #define HIGHEST_CLEVEL 3 - static void configure_c_states(void) -@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu) - /* Setup Page Attribute Tables (PAT) */ - // TODO set up PAT - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(); - -diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c -index 535fb8fae7..f7b05facd2 100644 ---- a/src/cpu/intel/model_6fx/model_6fx_init.c -+++ b/src/cpu/intel/model_6fx/model_6fx_init.c -@@ -7,6 +7,7 @@ - #include <cpu/intel/speedstep.h> - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> -+#include <cpu/intel/common/common.h> - - #define HIGHEST_CLEVEL 3 - static void configure_c_states(void) -@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu) - /* Setup Page Attribute Tables (PAT) */ - // TODO set up PAT - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(); - --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch deleted file mode 100644 index c9b41c79..00000000 --- a/config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 458fe39e9cd2536cfa8671427e6f557396143339 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 4/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU - models - -Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e6400/devicetree.cb | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb -index bb954cbd7b..e9f3915d17 100644 ---- a/src/mainboard/dell/e6400/devicetree.cb -+++ b/src/mainboard/dell/e6400/devicetree.cb -@@ -19,7 +19,7 @@ chip northbridge/intel/gm45 - ops gm45_pci_domain_ops - - device pci 00.0 on end # host bridge -- device pci 01.0 off end -+ device pci 01.0 on end - device pci 02.0 on end # VGA - device pci 02.1 on end # Display - device pci 03.0 on end # ME --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch deleted file mode 100644 index 546bad7f..00000000 --- a/config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ /dev/null @@ -1,39 +0,0 @@ -From de4eeaf6d44cb05c60c0b0d54b43cdb88686b998 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 5/9] Remove warning for coreboot images built without a - payload - -I added this in upstream to prevent people from accidentally flashing -roms without a payload resulting in a no boot situation, but in -libreboot lbmk handles the payload and thus this warning always comes -up. This has caused confusion and concern so just patch it out. ---- - payloads/Makefile.mk | 13 +------------ - 1 file changed, 1 insertion(+), 12 deletions(-) - -diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk -index a2336aa876..4f1692a873 100644 ---- a/payloads/Makefile.mk -+++ b/payloads/Makefile.mk -@@ -49,16 +49,5 @@ distclean-payloads: - print-repo-info-payloads: - -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) - --ifeq ($(CONFIG_PAYLOAD_NONE),y) --show_notices:: warn_no_payload --endif -- --warn_no_payload: -- printf "\n\t** WARNING **\n" -- printf "coreboot has been built without a payload. Writing\n" -- printf "a coreboot image without a payload to your board's\n" -- printf "flash chip will result in a non-booting system. You\n" -- printf "can use cbfstool to add a payload to the image.\n\n" -- - .PHONY: force-payload coreinfo nvramcui --.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload -+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch b/config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch deleted file mode 100644 index 3ee38c29..00000000 --- a/config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 261454e47783b973b088e9dbea47bda02758dcb4 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 22 Oct 2023 15:02:25 +0100 -Subject: [PATCH 6/9] don't use github for the acpica download - -i have the tarball from a previous download, and i placed -it on libreboot rsync, which then got mirrored to princeton. - -today, github's ssl cert was b0rking the hell out and i really -really wanted to finish a build, and didn't want to wait for -github to fix their httpd. - -so i'm now hosting this specific acpica tarball on rsync. - -this patch makes that URL be used, instead of the github one. - -that's the 2nd time i've had to patch coreboot's acpica download! - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/crossgcc/buildgcc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 23a5caf2bb..36565a906c 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" - MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" - GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" - BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" --IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" -+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" - # CLANG toolchain archive locations - LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" - CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch deleted file mode 100644 index ff481081..00000000 --- a/config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 622daa7c46de01530de60a7be32c8b9e48b356fd Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 5 Nov 2023 22:57:08 +0000 -Subject: [PATCH 7/9] use mirrorservice.org for gcc downloads - -the gnu.org 302 redirect often fails - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/crossgcc/buildgcc | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 36565a906c..4d4ca06113 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" - # to the jenkins build as well, or the builder won't download it. - - # GCC toolchain archive locations --GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" --MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" --MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" --GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" --BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" -+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp" -+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" -+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" -+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" -+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" - IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" - # CLANG toolchain archive locations - LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch b/config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch deleted file mode 100644 index 8d48bfd9..00000000 --- a/config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch +++ /dev/null @@ -1,23 +0,0 @@ -From f318da0563ecb2386ac368e04bad88a8aacbc83d Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Wed, 1 Nov 2023 16:33:11 +0000 -Subject: [PATCH 9/9] dell/e6400: crank up vram to 256MB (max) - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - src/mainboard/dell/e6400/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default -index eeb6f47364..25dfa38cb5 100644 ---- a/src/mainboard/dell/e6400/cmos.default -+++ b/src/mainboard/dell/e6400/cmos.default -@@ -2,4 +2,4 @@ boot_option=Fallback - debug_level=Debug - power_on_after_fail=Disable - sata_mode=AHCI --gfx_uma_size=32M -+gfx_uma_size=256M --- -2.39.2 - diff --git a/config/coreboot/dell/target.cfg b/config/coreboot/dell/target.cfg deleted file mode 100644 index 45176407..00000000 --- a/config/coreboot/dell/target.cfg +++ /dev/null @@ -1,4 +0,0 @@ -tree="dell" -tree_depend="default" -xtree="default" -rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a" diff --git a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb index e61318e4..70eca296 100644 --- a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb @@ -6,7 +6,6 @@ # # General setup # -CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y @@ -37,7 +36,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +53,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +65,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +93,7 @@ CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -125,17 +126,36 @@ CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" CONFIG_VGA_BIOS=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_USBDEBUG_HCD_INDEX=1 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=1 +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_BOARD_DELL_E6400=y +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 @@ -152,6 +172,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd" CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom" CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y @@ -166,12 +187,13 @@ CONFIG_PS2K_EISAID="PNP0303" CONFIG_PS2M_EISAID="PNP0F13" CONFIG_GFX_GMA_PANEL_1_PORT="LVDS" CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set -# CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -212,9 +234,10 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -# CONFIG_USE_EXP_X86_64_SUPPORT is not set +# CONFIG_USE_X86_64_SUPPORT is not set # CONFIG_VGA_BIOS_SECOND is not set CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 CONFIG_EHCI_BAR=0xfef00000 CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 @@ -223,7 +246,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 @@ -256,6 +278,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y CONFIG_HAVE_SMI_HANDLER=y +CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 @@ -326,7 +349,7 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_HAVE_EXP_X86_64_SUPPORT=y +CONFIG_HAVE_X86_64_SUPPORT=y CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y @@ -342,6 +365,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -443,6 +467,8 @@ CONFIG_DRIVERS_MC146818=y CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y # end of Generic Drivers # @@ -495,7 +521,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode index 8e0b0131..2f8769cb 100644 --- a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode @@ -6,7 +6,6 @@ # # General setup # -CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y @@ -37,7 +36,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +53,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +65,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +93,7 @@ CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -123,17 +124,36 @@ CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" CONFIG_VGA_BIOS=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_USBDEBUG_HCD_INDEX=1 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=1 +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_BOARD_DELL_E6400=y +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 @@ -150,6 +170,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd" CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom" CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y @@ -164,12 +185,13 @@ CONFIG_PS2K_EISAID="PNP0303" CONFIG_PS2M_EISAID="PNP0F13" CONFIG_GFX_GMA_PANEL_1_PORT="LVDS" CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set -# CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -210,9 +232,10 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -# CONFIG_USE_EXP_X86_64_SUPPORT is not set +# CONFIG_USE_X86_64_SUPPORT is not set # CONFIG_VGA_BIOS_SECOND is not set CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 CONFIG_EHCI_BAR=0xfef00000 CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 @@ -221,7 +244,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 @@ -254,6 +276,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y CONFIG_HAVE_SMI_HANDLER=y +CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 @@ -324,7 +347,7 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_HAVE_EXP_X86_64_SUPPORT=y +CONFIG_HAVE_X86_64_SUPPORT=y CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y @@ -340,6 +363,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -439,6 +463,8 @@ CONFIG_DRIVERS_MC146818=y CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y # end of Generic Drivers # @@ -491,7 +517,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/e6400_4mb/target.cfg b/config/coreboot/e6400_4mb/target.cfg index f6d540d5..98eb8d3b 100644 --- a/config/coreboot/e6400_4mb/target.cfg +++ b/config/coreboot/e6400_4mb/target.cfg @@ -1,4 +1,4 @@ -tree="dell" +tree="default" xarch="i386-elf" payload_seabios="y" payload_grub="y" diff --git a/config/coreboot/e6400nvidia_4mb/config/normal b/config/coreboot/e6400nvidia_4mb/config/normal index 8cf79154..f5d6b16f 100644 --- a/config/coreboot/e6400nvidia_4mb/config/normal +++ b/config/coreboot/e6400nvidia_4mb/config/normal @@ -6,7 +6,6 @@ # # General setup # -CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y @@ -37,7 +36,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +53,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +65,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +93,7 @@ CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -123,16 +124,35 @@ CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" CONFIG_VGA_BIOS=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_USBDEBUG_HCD_INDEX=1 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=1 +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_BOARD_DELL_E6400=y +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 @@ -149,6 +169,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd" CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom" CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y @@ -162,12 +183,13 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 CONFIG_PS2K_EISAID="PNP0303" CONFIG_PS2M_EISAID="PNP0F13" CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set -# CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -208,9 +230,10 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -# CONFIG_USE_EXP_X86_64_SUPPORT is not set +# CONFIG_USE_X86_64_SUPPORT is not set # CONFIG_VGA_BIOS_SECOND is not set CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 CONFIG_EHCI_BAR=0xfef00000 CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 @@ -219,7 +242,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 @@ -252,6 +274,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y CONFIG_HAVE_SMI_HANDLER=y +CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 @@ -322,7 +345,7 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_HAVE_EXP_X86_64_SUPPORT=y +CONFIG_HAVE_X86_64_SUPPORT=y CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y @@ -338,6 +361,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -417,6 +441,8 @@ CONFIG_DRIVERS_MC146818=y CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y # end of Generic Drivers # @@ -469,7 +495,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/e6400nvidia_4mb/target.cfg b/config/coreboot/e6400nvidia_4mb/target.cfg index f6d540d5..98eb8d3b 100644 --- a/config/coreboot/e6400nvidia_4mb/target.cfg +++ b/config/coreboot/e6400nvidia_4mb/target.cfg @@ -1,4 +1,4 @@ -tree="dell" +tree="default" xarch="i386-elf" payload_seabios="y" payload_grub="y" diff --git a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb index 13b0fd5a..9a1af842 100644 --- a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/r400_16mb/config/libgfxinit_txtmode b/config/coreboot/r400_16mb/config/libgfxinit_txtmode index cfe25366..d2bd1d3c 100644 --- a/config/coreboot/r400_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_16mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb index 70213655..93499bad 100644 --- a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/r400_4mb/config/libgfxinit_txtmode b/config/coreboot/r400_4mb/config/libgfxinit_txtmode index 4eda9794..3bbf7aaa 100644 --- a/config/coreboot/r400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_4mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb index cf2abe92..4faef26a 100644 --- a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/r400_8mb/config/libgfxinit_txtmode b/config/coreboot/r400_8mb/config/libgfxinit_txtmode index 1eac7a90..21b32616 100644 --- a/config/coreboot/r400_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_8mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb index d277e12f..2d7e0b54 100644 --- a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/r500_4mb/config/libgfxinit_txtmode b/config/coreboot/r500_4mb/config/libgfxinit_txtmode index 5e38292c..8d437bd5 100644 --- a/config/coreboot/r500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/r500_4mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb index 43bfafd7..bda47e12 100644 --- a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t400_16mb/config/libgfxinit_txtmode b/config/coreboot/t400_16mb/config/libgfxinit_txtmode index a6a8be5c..92866ae0 100644 --- a/config/coreboot/t400_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_16mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb index d258e8d5..c25f6b21 100644 --- a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t400_4mb/config/libgfxinit_txtmode b/config/coreboot/t400_4mb/config/libgfxinit_txtmode index 3f2028e3..3eb566f6 100644 --- a/config/coreboot/t400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_4mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb index 076d088d..a23aa0d7 100644 --- a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t400_8mb/config/libgfxinit_txtmode b/config/coreboot/t400_8mb/config/libgfxinit_txtmode index fce03023..da7785f7 100644 --- a/config/coreboot/t400_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_8mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb index 76083169..951668c7 100644 --- a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t500_16mb/config/libgfxinit_txtmode b/config/coreboot/t500_16mb/config/libgfxinit_txtmode index ce75ce58..c1ed36e9 100644 --- a/config/coreboot/t500_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_16mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb index c04e512b..e090a1cc 100644 --- a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t500_4mb/config/libgfxinit_txtmode b/config/coreboot/t500_4mb/config/libgfxinit_txtmode index e6b554de..4d6a6fa9 100644 --- a/config/coreboot/t500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_4mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb index d9695250..2020124c 100644 --- a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/t500_8mb/config/libgfxinit_txtmode b/config/coreboot/t500_8mb/config/libgfxinit_txtmode index 8d7ecfec..80830324 100644 --- a/config/coreboot/t500_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_8mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb index 3e929c85..d8642c08 100644 --- a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/w500_16mb/config/libgfxinit_txtmode b/config/coreboot/w500_16mb/config/libgfxinit_txtmode index e65abef7..6e094553 100644 --- a/config/coreboot/w500_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_16mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb index 7b5733ee..0e2b4963 100644 --- a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/w500_4mb/config/libgfxinit_txtmode b/config/coreboot/w500_4mb/config/libgfxinit_txtmode index 7af28108..bc35cd23 100644 --- a/config/coreboot/w500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_4mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb index f050f1aa..ed2cd9ef 100644 --- a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb @@ -142,6 +142,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/w500_8mb/config/libgfxinit_txtmode b/config/coreboot/w500_8mb/config/libgfxinit_txtmode index 41517ef0..e998c77b 100644 --- a/config/coreboot/w500_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_8mb/config/libgfxinit_txtmode @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x200_16mb/config/libgfxinit_corebootfb b/config/coreboot/x200_16mb/config/libgfxinit_corebootfb index 88339de4..646aa044 100644 --- a/config/coreboot/x200_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_16mb/config/libgfxinit_corebootfb @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x200_16mb/config/libgfxinit_txtmode b/config/coreboot/x200_16mb/config/libgfxinit_txtmode index f74b382d..dd4c7e97 100644 --- a/config/coreboot/x200_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_16mb/config/libgfxinit_txtmode @@ -138,6 +138,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x200_4mb/config/libgfxinit_corebootfb b/config/coreboot/x200_4mb/config/libgfxinit_corebootfb index 33320bc5..0a7710f4 100644 --- a/config/coreboot/x200_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_4mb/config/libgfxinit_corebootfb @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x200_4mb/config/libgfxinit_txtmode b/config/coreboot/x200_4mb/config/libgfxinit_txtmode index ba2c3c41..68f067fa 100644 --- a/config/coreboot/x200_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_4mb/config/libgfxinit_txtmode @@ -138,6 +138,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x200_8mb/config/libgfxinit_corebootfb b/config/coreboot/x200_8mb/config/libgfxinit_corebootfb index 82a34881..15b698e4 100644 --- a/config/coreboot/x200_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_8mb/config/libgfxinit_corebootfb @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x200_8mb/config/libgfxinit_txtmode b/config/coreboot/x200_8mb/config/libgfxinit_txtmode index e73d9800..2d2f81f2 100644 --- a/config/coreboot/x200_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_8mb/config/libgfxinit_txtmode @@ -138,6 +138,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x301_16mb/config/libgfxinit_corebootfb b/config/coreboot/x301_16mb/config/libgfxinit_corebootfb index b066681e..6120c2a8 100644 --- a/config/coreboot/x301_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x301_16mb/config/libgfxinit_corebootfb @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x301_16mb/config/libgfxinit_txtmode b/config/coreboot/x301_16mb/config/libgfxinit_txtmode index 36942c01..96911b1e 100644 --- a/config/coreboot/x301_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x301_16mb/config/libgfxinit_txtmode @@ -138,6 +138,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x301_4mb/config/libgfxinit_corebootfb b/config/coreboot/x301_4mb/config/libgfxinit_corebootfb index e5931f9e..1600d752 100644 --- a/config/coreboot/x301_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x301_4mb/config/libgfxinit_corebootfb @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x301_4mb/config/libgfxinit_txtmode b/config/coreboot/x301_4mb/config/libgfxinit_txtmode index e1eb3b54..6931179e 100644 --- a/config/coreboot/x301_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/x301_4mb/config/libgfxinit_txtmode @@ -138,6 +138,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x301_8mb/config/libgfxinit_corebootfb b/config/coreboot/x301_8mb/config/libgfxinit_corebootfb index 9c2af247..c4aa7b1d 100644 --- a/config/coreboot/x301_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x301_8mb/config/libgfxinit_corebootfb @@ -140,6 +140,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/coreboot/x301_8mb/config/libgfxinit_txtmode b/config/coreboot/x301_8mb/config/libgfxinit_txtmode index ba96860c..7385ce0a 100644 --- a/config/coreboot/x301_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x301_8mb/config/libgfxinit_txtmode @@ -138,6 +138,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" diff --git a/config/submodule/coreboot/dell/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch b/config/submodule/coreboot/default/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch index bb772461..2d248941 100644 --- a/config/submodule/coreboot/dell/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch +++ b/config/submodule/coreboot/default/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch @@ -1,7 +1,7 @@ -From 2c29f01a18d0a104bcc4f785e3901de584d02d7e Mon Sep 17 00:00:00 2001 +From ba078864500de99c26b6ea7e3fdcef19bca582a7 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 20 May 2024 10:10:03 -0600 -Subject: [PATCH] g45/hw-gfx-gma-plls.adb: Make reference clock frequency +Subject: [PATCH 1/1] g45/hw-gfx-gma-plls.adb: Make reference clock frequency configurable Instead of assuming a 96 MHz reference clock frequency, use the value @@ -16,7 +16,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/common/g45/hw-gfx-gma-plls.adb b/common/g45/hw-gfx-gma-plls.adb -index 67242f2..1aee576 100644 +index 67242f2..5e970d7 100644 --- a/common/g45/hw-gfx-gma-plls.adb +++ b/common/g45/hw-gfx-gma-plls.adb @@ -12,6 +12,8 @@ @@ -38,5 +38,5 @@ index 67242f2..1aee576 100644 Valid => Success); else -- -2.45.1 +2.39.2 diff --git a/config/submodule/coreboot/dell/intel-microcode/module.cfg b/config/submodule/coreboot/dell/intel-microcode/module.cfg deleted file mode 100644 index 05a174b0..00000000 --- a/config/submodule/coreboot/dell/intel-microcode/module.cfg +++ /dev/null @@ -1,3 +0,0 @@ -subrepo="https://review.coreboot.org/intel-microcode.git" -subrepo_bkup="https://github.com/coreboot/intel-microcode" -subhash="ece0d294a29a1375397941a4e6f2f7217910bc89" diff --git a/config/submodule/coreboot/dell/libgfxinit/module.cfg b/config/submodule/coreboot/dell/libgfxinit/module.cfg deleted file mode 100644 index 7e2536f9..00000000 --- a/config/submodule/coreboot/dell/libgfxinit/module.cfg +++ /dev/null @@ -1,3 +0,0 @@ -subrepo="https://review.coreboot.org/libgfxinit.git" -subrepo_bkup="https://github.com/coreboot/libgfxinit" -subhash="a4be8a21b0e2c752da0042c79aae5942418f53e2" diff --git a/config/submodule/coreboot/dell/libhwbase/module.cfg b/config/submodule/coreboot/dell/libhwbase/module.cfg deleted file mode 100644 index 2937b8b7..00000000 --- a/config/submodule/coreboot/dell/libhwbase/module.cfg +++ /dev/null @@ -1,3 +0,0 @@ -subrepo="https://review.coreboot.org/libhwbase.git" -subrepo_bkup="https://github.com/coreboot/libhwbase" -subhash="584629b9f4771b7618951cec57df2ca3af9c6981" diff --git a/config/submodule/coreboot/dell/module.list b/config/submodule/coreboot/dell/module.list deleted file mode 100644 index 3d968b1a..00000000 --- a/config/submodule/coreboot/dell/module.list +++ /dev/null @@ -1,4 +0,0 @@ -3rdparty/intel-microcode -3rdparty/libgfxinit -3rdparty/libhwbase -3rdparty/vboot diff --git a/config/submodule/coreboot/dell/vboot/module.cfg b/config/submodule/coreboot/dell/vboot/module.cfg deleted file mode 100644 index 9a23ee96..00000000 --- a/config/submodule/coreboot/dell/vboot/module.cfg +++ /dev/null @@ -1,3 +0,0 @@ -subrepo="https://review.coreboot.org/vboot.git" -subrepo_bkup="https://github.com/coreboot/vboot" -subhash="3d37d2aafe1f941c532def2a1fbbb58c8dd84182" diff --git a/config/submodule/coreboot/dell/vboot/patches/0001-extract_vmlinuz.c-Fix-the-bounds-check-on-vmlinuz_he.patch b/config/submodule/coreboot/dell/vboot/patches/0001-extract_vmlinuz.c-Fix-the-bounds-check-on-vmlinuz_he.patch deleted file mode 100644 index 1ac41de6..00000000 --- a/config/submodule/coreboot/dell/vboot/patches/0001-extract_vmlinuz.c-Fix-the-bounds-check-on-vmlinuz_he.patch +++ /dev/null @@ -1,178 +0,0 @@ -From 195f61375aeec9eec16604ec59f6eda2e6058cc1 Mon Sep 17 00:00:00 2001 -From: "Luke T. Shumaker" <lukeshu@lukeshu.com> -Date: Thu, 30 May 2024 14:08:33 -0600 -Subject: [PATCH 1/1] extract_vmlinuz.c: Fix the bounds check on - vmlinuz_header_{offset,size} - -The check on vmlinuz_header_offset and vmlinuz_header_size is obviously -wrong: - - if (!vmlinuz_header_size || - kpart_data + vmlinuz_header_offset + vmlinuz_header_size > - kpart_data) { - return 1; - } - -`kpart_data + some_unsigned_values` can obviously never be `> kpart_data`, -unless something has overflowed! And `vmlinuz_header_offset` hasn't even -been set yet (besides being initialized to zero)! - -GCC will deduce that if the check didn't cause the function to bail, then -vmlinuz_header_size (a uint32_t) must be "negative"; that is: in the range -[2GiB,4GiB). - -On platforms where size_t is 32-bits, this is *especially* broken. -memcpy's size argument must be in the range [0,2GiB). Because GCC has -proved that vmlinuz_header_size is higher than that, it will fail to -compile: - - host/lib/extract_vmlinuz.c:67:9: error: 'memcpy' specified bound between 2147483648 and 4294967295 exceeds maximum object size 2147483647 [-Werror=stringop-overflow=] - -So, fix the check. - -I can now say that what I suspect the original author meant to write would -be the following patch, if `vmlinuz_header_offset` were already set: - - -kpart_data + vmlinuz_header_offset + vmlinuz_header_size > kpart_data - +now + vmlinuz_header_offset + vmlinuz_header_size > kpart_size - -This hypothesis is supported by `now` not getting incremented by -`kblob_size` the way it is for the keyblock and preamble sizes. - -However, we can also see that even this "corrected" bounds check is -insufficient: it does not detect the vmlinuz_header overflowing into -kblob_data. - -OK, so let's describe the fix: - -Have a `*vmlinuz_header` pointer instead of a -`uint64_t vmlinuz_header_offset`, to be more similar to all the other -regions. With this change, the correct check becomes a simple - - vmlinuz_header + vmlinuz_header_size > kblob_data - -While we're at it, make some changes that could have helped avoid this in -the first place: - - - Add comments. - - Calculate the vmlinuz_header offset right away, instead of waiting. - - Go ahead and increment `now` by `kblob_size`, to increase regularity. - -Change-Id: I5c03e49070b6dd2e04459566ef7dd129d27736e4 ---- - host/lib/extract_vmlinuz.c | 72 +++++++++++++++++++++++++++----------- - 1 file changed, 51 insertions(+), 21 deletions(-) - -diff --git a/host/lib/extract_vmlinuz.c b/host/lib/extract_vmlinuz.c -index 4ccfcf33..d2c09443 100644 ---- a/host/lib/extract_vmlinuz.c -+++ b/host/lib/extract_vmlinuz.c -@@ -15,16 +15,44 @@ - - int ExtractVmlinuz(void *kpart_data, size_t kpart_size, - void **vmlinuz_out, size_t *vmlinuz_size) { -+ // We're going to be extracting `vmlinuz_header` and -+ // `kblob_data`, and returning the concatenation of them. -+ // -+ // kpart_data = +-[kpart_size]------------------------------------+ -+ // | | -+ // keyblock = | +-[keyblock->keyblock_size]-------------------+ | -+ // | | struct vb2_keyblock keyblock | | -+ // | | char [] ...data... | | -+ // | +---------------------------------------------+ | -+ // | | -+ // preamble = | +-[preamble->preamble_size]-------------------+ | -+ // | | struct vb2_kernel_preamble preamble | | -+ // | | char [] ...data... | | -+ // | | char [] vmlinuz_header | | -+ // | | char [] ...data... | | -+ // | +---------------------------------------------+ | -+ // | | -+ // kblob_data= | +-[preamble->body_signature.data_size]--------+ | -+ // | | char [] ...data... | | -+ // | +---------------------------------------------+ | -+ // | | -+ // +-------------------------------------------------+ -+ - size_t now = 0; -+ // The 3 sections of kpart_data. -+ struct vb2_keyblock *keyblock = NULL; - struct vb2_kernel_preamble *preamble = NULL; - uint8_t *kblob_data = NULL; - uint32_t kblob_size = 0; -+ // vmlinuz_header -+ uint8_t *vmlinuz_header = NULL; - uint32_t vmlinuz_header_size = 0; -- uint64_t vmlinuz_header_address = 0; -- uint64_t vmlinuz_header_offset = 0; -+ // The concatenated result. - void *vmlinuz = NULL; - -- struct vb2_keyblock *keyblock = (struct vb2_keyblock *)kpart_data; -+ // Isolate the 3 sections of kpart_data. -+ -+ keyblock = (struct vb2_keyblock *)kpart_data; - now += keyblock->keyblock_size; - if (now > kpart_size) - return 1; -@@ -36,37 +64,39 @@ int ExtractVmlinuz(void *kpart_data, size_t kpart_size, - - kblob_data = kpart_data + now; - kblob_size = preamble->body_signature.data_size; -- -- if (!kblob_data || (now + kblob_size) > kpart_size) -+ now += kblob_size; -+ if (now > kpart_size) - return 1; - -+ // Find `vmlinuz_header` within `preamble`. -+ - if (preamble->header_version_minor > 0) { -- vmlinuz_header_address = preamble->vmlinuz_header_address; -+ // calculate the vmlinuz_header offset from -+ // the beginning of the kpart_data. The kblob doesn't -+ // include the body_load_offset, but does include -+ // the keyblock and preamble sections. -+ size_t vmlinuz_header_offset = -+ preamble->vmlinuz_header_address - -+ preamble->body_load_address + -+ keyblock->keyblock_size + -+ preamble->preamble_size; -+ -+ vmlinuz_header = kpart_data + vmlinuz_header_offset; - vmlinuz_header_size = preamble->vmlinuz_header_size; - } - -- if (!vmlinuz_header_size || -- kpart_data + vmlinuz_header_offset + vmlinuz_header_size > -- kpart_data) { -+ if (!vmlinuz_header || -+ !vmlinuz_header_size || -+ vmlinuz_header + vmlinuz_header_size > kblob_data) { - return 1; - } - -- // calculate the vmlinuz_header offset from -- // the beginning of the kpart_data. The kblob doesn't -- // include the body_load_offset, but does include -- // the keyblock and preamble sections. -- vmlinuz_header_offset = vmlinuz_header_address - -- preamble->body_load_address + -- keyblock->keyblock_size + -- preamble->preamble_size; -+ // Concatenate and return. - - vmlinuz = malloc(vmlinuz_header_size + kblob_size); - if (vmlinuz == NULL) - return 1; -- -- memcpy(vmlinuz, kpart_data + vmlinuz_header_offset, -- vmlinuz_header_size); -- -+ memcpy(vmlinuz, vmlinuz_header, vmlinuz_header_size); - memcpy(vmlinuz + vmlinuz_header_size, kblob_data, kblob_size); - - *vmlinuz_out = vmlinuz; --- -2.45.1 - |