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authorLeah Rowe <leah@libreboot.org>2024-12-02 16:32:15 +0000
committerLeah Rowe <leah@libreboot.org>2024-12-02 16:32:15 +0000
commitb95a411a3645b72036101aaa8f8ad28758eefd15 (patch)
treeaa65967708289c4593b61cacf28fd14d607f27de /config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch
parent046529abd98d7a98b57cfe9113f8c61dc3353cfc (diff)
Add SPD support for onboard ThinkPad T480S RAM
Patchset 20 from: https://review.coreboot.org/c/coreboot/+/83274/18..20 Updated to that. A bunch of changes I made locally have been copied here, thus removed from lbmk. The previous setup in lbmk was to have only the DIMM slot work, on the ThinkPad T480S, without setting up SPD for the onboard RAM> Mate Kukri reverse engineered the scheme by which the SPDs are chosen at boot, based on the wiring of the board. This should just about match the way Lenovo did it in their firmware. Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch')
-rw-r--r--config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch4
1 files changed, 2 insertions, 2 deletions
diff --git a/config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch
index b5a157a1..1b6b5372 100644
--- a/config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch
+++ b/config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch
@@ -1,7 +1,7 @@
-From b7b4f05005bfe46fc5ce67ae1f04d225e35cbd4d Mon Sep 17 00:00:00 2001
+From 18b68185f44599cf6ea6a20816bf6a5eb7aeda17 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Wed, 26 Jun 2024 04:24:31 +0200
-Subject: [PATCH 1/9] soc/intel/skylake: configure usb acpi
+Subject: [PATCH 1/8] soc/intel/skylake: configure usb acpi
Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
Signed-off-by: Felix Singer <felixsinger@posteo.net>