diff options
| author | Leah Rowe <leah@libreboot.org> | 2024-12-02 16:32:15 +0000 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2024-12-02 16:32:15 +0000 |
| commit | b95a411a3645b72036101aaa8f8ad28758eefd15 (patch) | |
| tree | aa65967708289c4593b61cacf28fd14d607f27de | |
| parent | 046529abd98d7a98b57cfe9113f8c61dc3353cfc (diff) | |
Add SPD support for onboard ThinkPad T480S RAM
Patchset 20 from:
https://review.coreboot.org/c/coreboot/+/83274/18..20
Updated to that. A bunch of changes I made locally have been
copied here, thus removed from lbmk.
The previous setup in lbmk was to have only the DIMM slot work,
on the ThinkPad T480S, without setting up SPD for the onboard RAM>
Mate Kukri reverse engineered the scheme by which the SPDs are
chosen at boot, based on the wiring of the board. This should
just about match the way Lenovo did it in their firmware.
Signed-off-by: Leah Rowe <leah@libreboot.org>
11 files changed, 809 insertions, 306 deletions
diff --git a/config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch index b5a157a1..1b6b5372 100644 --- a/config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch +++ b/config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch @@ -1,7 +1,7 @@ -From b7b4f05005bfe46fc5ce67ae1f04d225e35cbd4d Mon Sep 17 00:00:00 2001 +From 18b68185f44599cf6ea6a20816bf6a5eb7aeda17 Mon Sep 17 00:00:00 2001 From: Felix Singer <felixsinger@posteo.net> Date: Wed, 26 Jun 2024 04:24:31 +0200 -Subject: [PATCH 1/9] soc/intel/skylake: configure usb acpi +Subject: [PATCH 1/8] soc/intel/skylake: configure usb acpi Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d Signed-off-by: Felix Singer <felixsinger@posteo.net> diff --git a/config/coreboot/next/patches/0002-mb-lenovo-Add-initial-code-for-Lenovo-ThinkPad-E460.patch b/config/coreboot/next/patches/0002-mb-lenovo-Add-initial-code-for-Lenovo-ThinkPad-E460.patch index d268ddf3..77d7b080 100644 --- a/config/coreboot/next/patches/0002-mb-lenovo-Add-initial-code-for-Lenovo-ThinkPad-E460.patch +++ b/config/coreboot/next/patches/0002-mb-lenovo-Add-initial-code-for-Lenovo-ThinkPad-E460.patch @@ -1,7 +1,7 @@ -From 86a721209951605ad59aff31639a6be954a0fab8 Mon Sep 17 00:00:00 2001 +From a7cbcbc7037fe3473e5ebe475cbfd12f653e9827 Mon Sep 17 00:00:00 2001 From: Felix Singer <felixsinger@posteo.net> Date: Wed, 26 Jun 2024 00:59:03 +0200 -Subject: [PATCH 2/9] mb/lenovo: Add initial code for Lenovo ThinkPad E460 +Subject: [PATCH 2/8] mb/lenovo: Add initial code for Lenovo ThinkPad E460 Change-Id: Ia02f81750105c95c867d961dbdadcd5991ad371f Signed-off-by: Felix Singer <felixsinger@posteo.net> diff --git a/config/coreboot/next/patches/0003-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch b/config/coreboot/next/patches/0003-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch index 56834e40..6e7d4b7c 100644 --- a/config/coreboot/next/patches/0003-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch +++ b/config/coreboot/next/patches/0003-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch @@ -1,7 +1,7 @@ -From 46da5bb38caf3b5d523e79ca0e17b125179daaaf Mon Sep 17 00:00:00 2001 +From b3049cfd11aa0f3c124ed8f87e98a200201ecbdc Mon Sep 17 00:00:00 2001 From: Mate Kukri <km@mkukri.xyz> Date: Fri, 22 Nov 2024 21:26:48 +0000 -Subject: [PATCH 3/9] soc/intel/skylake: Enable 4E/4F PNP I/O ports in +Subject: [PATCH 3/8] soc/intel/skylake: Enable 4E/4F PNP I/O ports in bootblock Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173 diff --git a/config/coreboot/next/patches/0008-mb-lenovo-Add-ThinkPad-T480.patch b/config/coreboot/next/patches/0004-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch index a956a392..1ac1a536 100644 --- a/config/coreboot/next/patches/0008-mb-lenovo-Add-ThinkPad-T480.patch +++ b/config/coreboot/next/patches/0004-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch @@ -1,9 +1,9 @@ -From cc9876a374db2515cefc1e3a3a1745d643b19554 Mon Sep 17 00:00:00 2001 +From e905d7fd1ee1a791f27285715d420263e422ebee Mon Sep 17 00:00:00 2001 From: Mate Kukri <kukri.mate@gmail.com> -Date: Mon, 2 Dec 2024 01:36:35 +0000 -Subject: [PATCH 8/9] mb/lenovo: Add ThinkPad T480 +Date: Mon, 2 Dec 2024 16:10:22 +0000 +Subject: [PATCH 4/8] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s -This machine has BootGuard fused and requires deguard to boot coreboot. +These machine have BootGuard fused and requires deguard to boot coreboot. Works: - Intel GPU @@ -13,19 +13,18 @@ Works: - EC + Fan control + Keyboard - + Both batteries + + Battery (T480 has two) + Charging via both Type-C ports - + Debug UART + + Debug UART (on T480) - WLAN card: + WiFi works + Bluetooth works - M.2 main SSD -- Speakers, headphone jack +- HDA verbs, Speakers, headphone jack - S3 sleep Known issues: - Alpine Ridge Thunderbolt 3 controller does not work -- Missing HDA verbs, audio still works - Function keys are handled differently from stock firmware + These should inject XF86 keycodes instead of directly controlling, volume, brightness, etc in hardware. @@ -43,6 +42,8 @@ Untested (should work): - Webcam (USB) - External video outputs +Thanks to Leah Rowe for helping with the T480s. + Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I19d421412c771c1f242f6ff39453f824fa866163 --- @@ -50,9 +51,9 @@ Change-Id: I19d421412c771c1f242f6ff39453f824fa866163 src/ec/lenovo/h8/acpi/ec.asl | 2 +- src/ec/lenovo/h8/bluetooth.c | 12 +- src/ec/lenovo/h8/wwan.c | 12 +- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 39 +++- + src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 42 +++- .../lenovo/sklkbl_thinkpad/Kconfig.name | 6 + - .../lenovo/sklkbl_thinkpad/Makefile.mk | 8 +- + .../lenovo/sklkbl_thinkpad/Makefile.mk | 72 ++++++- .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 13 +- .../lenovo/sklkbl_thinkpad/bootblock.c | 50 +++++ .../lenovo/sklkbl_thinkpad/devicetree.cb | 36 ++++ @@ -61,29 +62,78 @@ Change-Id: I19d421412c771c1f242f6ff39453f824fa866163 src/mainboard/lenovo/sklkbl_thinkpad/ec.h | 99 +++++++++ src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 + .../lenovo/sklkbl_thinkpad/ramstage.c | 98 ++++++++- - .../lenovo/sklkbl_thinkpad/romstage.c | 24 +++ + .../lenovo/sklkbl_thinkpad/romstage.c | 7 - .../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes .../variants/t480/gma-mainboard.ads | 19 ++ .../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++ - .../sklkbl_thinkpad/variants/t480/hda_verb.c | 10 + + .../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++ + .../variants/t480/memory_init_params.c | 20 ++ .../variants/t480/overridetree.cb | 124 +++++++++++ - .../variants/t480s/gma-mainboard.ads | 15 ++ + .../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes + .../variants/t480s/gma-mainboard.ads | 19 ++ .../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++ - .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 10 + - .../variants/t480s/overridetree.cb | 121 +++++++++++ - 25 files changed, 1258 insertions(+), 32 deletions(-) + .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++ + .../variants/t480s/memory_init_params.c | 44 ++++ + .../variants/t480s/overridetree.cb | 124 +++++++++++ + .../sklkbl_thinkpad/variants/t480s/spd_0.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_1.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_10.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_11.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_12.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_13.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_14.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_15.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_16.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_17.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_18.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_19.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_2.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_20.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_3.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_4.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_5.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_6.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_7.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_8.bin | Bin 0 -> 512 bytes + .../sklkbl_thinkpad/variants/t480s/spd_9.bin | Bin 0 -> 512 bytes + 49 files changed, 1531 insertions(+), 40 deletions(-) create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.c create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.h create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h + delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/romstage.c create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_0.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_1.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_10.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_11.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_12.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_13.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_14.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_15.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_16.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_17.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_18.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_19.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_2.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_20.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_3.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_4.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_5.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_6.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_7.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_8.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_9.bin diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index d60720eb49..b18dfdd287 100644 @@ -197,10 +247,10 @@ index 685886fcce..5e0ae030e2 100644 printk(BIOS_INFO, "H8: WWAN not installed\n"); return false; diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index fcc80dffe3..13d71670e3 100644 +index fcc80dffe3..21076315ab 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -2,16 +2,19 @@ +@@ -2,16 +2,20 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON bool @@ -221,10 +271,11 @@ index fcc80dffe3..13d71670e3 100644 select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM2 - select NO_UART_ON_SUPERIO ++ select MAINBOARD_USES_IFD_GBE_REGION select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP -@@ -19,8 +22,22 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON +@@ -19,8 +23,22 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON config BOARD_LENOVO_E460 bool select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON @@ -247,7 +298,7 @@ index fcc80dffe3..13d71670e3 100644 if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON config MAINBOARD_DIR -@@ -28,19 +45,31 @@ config MAINBOARD_DIR +@@ -28,18 +46,30 @@ config MAINBOARD_DIR config VARIANT_DIR default "e460" if BOARD_LENOVO_E460 @@ -260,7 +311,7 @@ index fcc80dffe3..13d71670e3 100644 config MAINBOARD_PART_NUMBER default "E460" if BOARD_LENOVO_E460 + default "T480" if BOARD_LENOVO_T480 -+ default "T480S" if BOARD_LENOVO_T480S ++ default "T480s" if BOARD_LENOVO_T480S config CBFS_SIZE default 0x600000 if BOARD_LENOVO_E460 @@ -271,17 +322,17 @@ index fcc80dffe3..13d71670e3 100644 + default 2 config DIMM_SPD_SIZE - default 256 - +- default 256 ++ default 512 # DDR4 ++ +endif + +if BOARD_LENOVO_E460 -+ + config UART_FOR_CONSOLE default 2 - diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -index 61d971fe8d..54fc4f0065 100644 +index 61d971fe8d..15441c4264 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name @@ -2,3 +2,9 @@ @@ -293,12 +344,12 @@ index 61d971fe8d..54fc4f0065 100644 + bool "ThinkPad T480" + +config BOARD_LENOVO_T480S -+ bool "ThinkPad T480S" ++ bool "ThinkPad T480s" diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk -index 6e544fd6b9..348e3d4582 100644 +index 6e544fd6b9..49d6ebdb4e 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk -@@ -1,7 +1,9 @@ +@@ -1,7 +1,73 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += bootblock.c @@ -306,11 +357,75 @@ index 6e544fd6b9..348e3d4582 100644 -ramstage-y += ramstage.c -ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -+romstage-y += romstage.c ++romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c + +ramstage-y += ramstage.c ec.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads ++ ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_0.bin ++spd_0.bin-file := variants/$(VARIANT_DIR)/spd_0.bin ++spd_0.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_1.bin ++spd_1.bin-file := variants/$(VARIANT_DIR)/spd_1.bin ++spd_1.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_2.bin ++spd_2.bin-file := variants/$(VARIANT_DIR)/spd_2.bin ++spd_2.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_3.bin ++spd_3.bin-file := variants/$(VARIANT_DIR)/spd_3.bin ++spd_3.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_4.bin ++spd_4.bin-file := variants/$(VARIANT_DIR)/spd_4.bin ++spd_4.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_5.bin ++spd_5.bin-file := variants/$(VARIANT_DIR)/spd_5.bin ++spd_5.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_6.bin ++spd_6.bin-file := variants/$(VARIANT_DIR)/spd_6.bin ++spd_6.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_7.bin ++spd_7.bin-file := variants/$(VARIANT_DIR)/spd_7.bin ++spd_7.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_8.bin ++spd_8.bin-file := variants/$(VARIANT_DIR)/spd_8.bin ++spd_8.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_9.bin ++spd_9.bin-file := variants/$(VARIANT_DIR)/spd_9.bin ++spd_9.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_10.bin ++spd_10.bin-file := variants/$(VARIANT_DIR)/spd_10.bin ++spd_10.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_11.bin ++spd_11.bin-file := variants/$(VARIANT_DIR)/spd_11.bin ++spd_11.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_12.bin ++spd_12.bin-file := variants/$(VARIANT_DIR)/spd_12.bin ++spd_12.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_13.bin ++spd_13.bin-file := variants/$(VARIANT_DIR)/spd_13.bin ++spd_13.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_14.bin ++spd_14.bin-file := variants/$(VARIANT_DIR)/spd_14.bin ++spd_14.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_15.bin ++spd_15.bin-file := variants/$(VARIANT_DIR)/spd_15.bin ++spd_15.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_16.bin ++spd_16.bin-file := variants/$(VARIANT_DIR)/spd_16.bin ++spd_16.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_17.bin ++spd_17.bin-file := variants/$(VARIANT_DIR)/spd_17.bin ++spd_17.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_18.bin ++spd_18.bin-file := variants/$(VARIANT_DIR)/spd_18.bin ++spd_18.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_19.bin ++spd_19.bin-file := variants/$(VARIANT_DIR)/spd_19.bin ++spd_19.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_20.bin ++spd_20.bin-file := variants/$(VARIANT_DIR)/spd_20.bin ++spd_20.bin-type := raw diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl index 16990d45f4..514b95a60f 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl @@ -866,41 +981,18 @@ index 6c3b077cc4..b41cca02a7 100644 + .init = mainboard_init, }; diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/romstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/romstage.c -index 59a62f484e..4cc0591b4f 100644 +deleted file mode 100644 +index 59a62f484e..0000000000 --- a/src/mainboard/lenovo/sklkbl_thinkpad/romstage.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/romstage.c -@@ -1,7 +1,31 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ - - #include <soc/romstage.h> -+#include <spd_bin.h> -+ -+// FIXME: verify SPD addrs, DQ interleave, and CA vref for other SKL/KBL ThinkPads - - void mainboard_memory_init_params(FSPM_UPD *mupd) - { -+ /* T480 -+ * JDDR1 - 0x50 -+ * JDDR2 - 0x51 */ -+ struct spd_block blk = { .addr_map = { 0x50, 0x51, } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ -+ /* T480 (DDR_DQ pins wired in interleave mode) */ -+ mem_cfg->DqPinsInterleaved = true; -+ -+ /* T480 (VREF_CA to CH_A and VREF_DQ_B to CH_B) -+ * DDR_VREF_CA -> M_A_VREF_CA_CPU -+ * DDR0_VREF_DQ -> NC -+ * DDR1_VREF_DQ -> M_B_VREF_CA_CPU */ -+ mem_cfg->CaVrefConfig = 2; -+ -+ mem_cfg->MemorySpdDataLen = blk.len; -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; -+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; - } ++++ /dev/null +@@ -1,7 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +- +-#include <soc/romstage.h> +- +-void mainboard_memory_init_params(FSPM_UPD *mupd) +-{ +-} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3 @@ -1172,23 +1264,129 @@ index 0000000000..f7c29e1f39 +} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c new file mode 100644 -index 0000000000..d9d103f862 +index 0000000000..3a951ce0da --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -@@ -0,0 +1,10 @@ +@@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { ++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 ++ 0x17aa225d, // Subsystem ID ++ 11, ++ AZALIA_SUBVENDOR(0, 0x17aa225d), ++ ++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_MIC_IN, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_MIC_IN, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 15 ++ )), ++ ++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI ++ 0x80860101, // Subsystem ID ++ 4, ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c +new file mode 100644 +index 0000000000..5252a402f9 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c +@@ -0,0 +1,20 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <soc/romstage.h> ++#include <spd_bin.h> ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */ ++ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ ++ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; ++ ++ /* Get SPD for memory slots */ ++ struct spd_block blk = { .addr_map = { 0x50, 0x51, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; ++} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb new file mode 100644 -index 0000000000..c20f36fbfc +index 0000000000..4b68ec3f49 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb @@ -0,0 +1,124 @@ @@ -1305,7 +1503,7 @@ index 0000000000..c20f36fbfc + register "PcieRpHotPlug[8]" = "1" + end + -+ # M.2 caddy - x2 ++ # M.2 2280 caddy - x2 + device ref pcie_rp11 on + register "PcieRpEnable[10]" = "1" + register "PcieRpClkReqSupport[10]" = "1" @@ -1316,12 +1514,47 @@ index 0000000000..c20f36fbfc + end + end +end +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840 +GIT binary patch +literal 4106 +zcmeHJUu+a*5TCu>yW9JAmoD2P<t%lC2CfC#y%tU^HSGOq>9tqx`iFWXCLD09R<E?S +zMT)`nNScT-%9*GEA8a2?G`v`!jPV6yVlcd5OnC6Y;F}U&jJz1db9VRID@E)DLk#NN +z&9^i2&Hiq_`R2ZF8ipf7IM{nI5$^585@kULrrx0OPKv~ngNI__q41$dA{p()ui+v1 +zw(9rm09lUPAP4nOTm0CRnF|aw5^SQSH<G}<u_Gfnvn6IuK0h@!j;UxI!$*&rIdkIh +zl$piB;eBDWa1|CgK9bAg{^O%Z%!ziiz{neeJDb~fBI?1GV5p^44?a$ETl=n1d+;%Z +z#X6(OzEnIB9*QUTV{!mv@xk!mU}s+>aS&4j$?kY0KGYdgn6;MZ*!anbk!PNr!a%eU +zTXkLEL3ly5L&oUX#CS7?b2%Kad?s<goHQq1G_%bLv);c5qQC)gZtxnw!L3%1MWI_X +z0wUImYD_R11gsI%l%Zw})KN_c#&!YgM3v;Up{7+s1=lXlB>-#@;mhg8>>>#S&)d2I +zmP&-g0$k02szSQj(Y*j}YYtQnDH0;2ui<!ko-28Y){6ilAcrmz951v4RTWQ_ye!or +z4xOJya#Sr7{o)%XFUfJCndM%KM(c^ol_hzlb*1h&uC%Vy%U(P!_qUfwcb4r;SmPQ_ +zhxf($vVo)we+jxogb`7NQ^aS9eQpNT#2bmX5(kO*5O)$Mi4PJVB_1U{L42C{HR894 +z=ZJk70(Q~o{*COiRR#_fix0XaS3?igAuo2!)<NF8ARGWF&M7=h16xZaS|UxpZA)w3 +z1CQUC@^&oxtbG2HGk&WA9=_qa;$?8fdy_j;eY+H3ciR5U?|$2?oT;mPoV=Dx&CwUf +zv~zYWs{cR#vl*!ChO54O0k3UT#mpur4fXeCdE_aoNtZ|mgF!ck3Nmy<0BRuy4NwCa +zNZDP7XrHsU<-0NyB2=wXwgEqZPukelExAY+hyWVj0{)~A=X~17KK7XpzxQcB``9fX +zZf4pp#`ZEanRbG)(+odg+NX?t!SF|>{mPhI!flfFgv9nqI4Wr~5_?s`k0kALiCvcP +zCrRUFrpVYPYn?Jn%6MGXUXj_GGJYa!U&-tn8Gn&ANnz_0+@olH3VTw)mlf@-!p<v7 +zljhF5u5tObYwR{boRI14NxNkGd6QG=>8{!e#p0ct5}M(h16D>p?OGjSz6v3juERjS +z#z{?mXvVqrXs_rvUmYR40gNzg(QD6y9E94?4DWO|6eb83LI-smcVC6x1n2reH}rAp +zLM);f=tWDCr``UF5T>!;PYu^H1g>EBP8A}2*fM>s-@nC3pDV|}6+CtfhG(II7`pcw +z`jLfJ!?;*R@Bp=Nw2EPOC7FEs(cugIP_K6tN_$~tvS8nx6iOv|IMrO3&-m*N9ZP#b +znG^~>I|l1cUVSeD9r^k3h0TP}WWD9=MZxY<<azgO1@-W5<NTHW*-d)t{Q4yX9_+?a +zHawLe=uO6@%xqS#?JxafX%#$`BhkIqq>Z3B2yU!k71#YRpThOJtVheMDA50rV#s@U +z+nKbA{O(olYR}icuzQD*-cjBQ9;%!eMDVP>7mWsF@=%>o)wSgq=n%DHNOYwRr4Ao6 +zbNdgEn*RdDS>Rud+fIY0N8JkP3q6;>8o%R(CE2n3?Xg%qP+U%~6|{XFyxv7Y#;J2Z +XK$lk*wsY^m4}9|iz?mg_AjCfat$CyH + +literal 0 +HcmV?d00001 + diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads new file mode 100644 -index 0000000000..e0a166fe55 +index 0000000000..fcfbd75a92 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads -@@ -0,0 +1,15 @@ +@@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; @@ -1334,12 +1567,16 @@ index 0000000000..e0a166fe55 + + ports : constant Port_List := + (eDP, ++ DP1, ++ DP2, ++ HDMI1, ++ HDMI2, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c new file mode 100644 -index 0000000000..fd9cdbef6b +index 0000000000..a98dd2bc4e --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c @@ -0,0 +1,199 @@ @@ -1352,22 +1589,22 @@ index 0000000000..fd9cdbef6b + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), -+ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), ++ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ ++ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ ++ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ ++ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ ++ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ ++ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ ++ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ ++ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ ++ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), -+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), ++ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* -SUSWARN */ ++ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* -SUS_STAT */ ++ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* -SUSWARN */ + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), @@ -1382,18 +1619,18 @@ index 0000000000..fd9cdbef6b + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), -+ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), -+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), ++ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */ ++ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (dGPU) */ ++ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (WWAN) */ ++ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 (GBE) */ ++ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WLAN) */ ++ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 (TB3) */ ++ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 (SSD) */ + PAD_NC(GPP_B11, NONE), -+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -+ PAD_CFG_GPO(GPP_B15, 0, DEEP), ++ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ ++ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ ++ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* PCH_SPKR */ ++ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), @@ -1406,14 +1643,14 @@ index 0000000000..fd9cdbef6b + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), -+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ + PAD_NC(GPP_C5, NONE), -+ /* GPP_C6 - RESERVED */ -+ /* GPP_C7 - RESERVED */ ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), @@ -1422,14 +1659,14 @@ index 0000000000..fd9cdbef6b + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), -+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ ++ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), -+ PAD_CFG_GPO(GPP_C20, 0, DEEP), -+ PAD_CFG_GPO(GPP_C21, 0, DEEP), -+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), ++ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ ++ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ ++ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), @@ -1441,101 +1678,101 @@ index 0000000000..fd9cdbef6b + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */ + PAD_NC(GPP_D10, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */ + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), -+ PAD_CFG_GPO(GPP_D17, 0, DEEP), ++ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ -+ PAD_CFG_GPO(GPP_E0, 1, DEEP), ++ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ + PAD_NC(GPP_E1, NONE), -+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -+ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), -+ PAD_CFG_GPO(GPP_E4, 1, DEEP), ++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -SATA2_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */ ++ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ + PAD_NC(GPP_E5, NONE), -+ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), ++ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */ + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), -+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ ++ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ + PAD_NC(GPP_E11, NONE), -+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), -+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), ++ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ ++ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ ++ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), -+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ + PAD_NC(GPP_E18, NONE), + PAD_CFG_GPO(GPP_E19, 0, DEEP), -+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -+ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), -+ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), ++ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ ++ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ ++ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */ ++ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */ + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), -+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), -+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), -+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), -+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), -+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), -+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), ++ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ ++ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ ++ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ ++ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ ++ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ ++ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ ++ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ + PAD_NC(GPD7, NONE), -+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), -+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), -+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), -+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), ++ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ ++ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ ++ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ ++ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPO(GPP_F0, 0, DEEP), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), -+ PAD_CFG_GPO(GPP_F2, 1, DEEP), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), -+ PAD_NC(GPP_F4, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */ ++ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* DGFX_PWRGD */ ++ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ + PAD_NC(GPP_F5, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R37 to GND) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ + PAD_NC(GPP_F21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -TAMPER_SW_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */ + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), -+ PAD_CFG_GPO(GPP_G4, 0, DEEP), -+ PAD_CFG_GPO(GPP_G5, 0, DEEP), -+ PAD_CFG_GPO(GPP_G6, 0, DEEP), -+ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), ++ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ ++ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ ++ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ ++ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ +}; + +void variant_config_gpios(void) @@ -1544,26 +1781,156 @@ index 0000000000..fd9cdbef6b +} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c new file mode 100644 -index 0000000000..d9d103f862 +index 0000000000..b1d96c5a76 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -@@ -0,0 +1,10 @@ +@@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { ++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 ++ 0x17aa2258, // Subsystem ID ++ 11, ++ AZALIA_SUBVENDOR(0, 0x17aa2258), ++ ++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_MIC_IN, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_MIC_IN, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 15 ++ )), ++ ++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI ++ 0x80860101, // Subsystem ID ++ 4, ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c +new file mode 100644 +index 0000000000..085abebbcb +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c +@@ -0,0 +1,44 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <cbfs.h> ++#include <gpio.h> ++#include <soc/gpio.h> ++#include <soc/romstage.h> ++#include <spd_bin.h> ++#include <stdio.h> ++ ++static const struct pad_config memory_id_gpio_table[] = { ++ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ ++}; ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ int spd_idx; ++ char spd_name[20]; ++ size_t spd_size; ++ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */ ++ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ ++ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; ++ ++ /* Get SPD for soldered RAM SPD (CH A) */ ++ gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table)); ++ ++ spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 | ++ gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4; ++ printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx); ++ snprintf(spd_name, sizeof spd_name, "spd_%d.bin", spd_idx); ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map(spd_name, &spd_size); ++ ++ /* Get SPD for memory slot (CH B) */ ++ struct spd_block blk = { .addr_map = { [1] = 0x51, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; ++} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb new file mode 100644 -index 0000000000..2cac8c4a75 +index 0000000000..5f1c38bc03 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -@@ -0,0 +1,121 @@ +@@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake @@ -1587,29 +1954,33 @@ index 0000000000..2cac8c4a75 + + device domain 0 on + device ref south_xhci on -+ # TODO: USB ports + register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC_SKIP), -+ [1] = USB2_PORT_MID(OC_SKIP), -+ [2] = USB2_PORT_MID(OC_SKIP), -+ [3] = USB2_PORT_MID(OC_SKIP), -+ [4] = USB2_PORT_MID(OC_SKIP), -+ [5] = USB2_PORT_MID(OC_SKIP), -+ [6] = USB2_PORT_MID(OC_SKIP), -+ [7] = USB2_PORT_MID(OC_SKIP), -+ [8] = USB2_PORT_MID(OC_SKIP), -+ [9] = USB2_PORT_MID(OC_SKIP), ++ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) ++ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) ++ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) ++ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB-C) ++ [4] = USB2_PORT_MID(OC_SKIP), // JCAM (IR camera) ++ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) ++ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) ++ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) ++ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) ++ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) + }" + register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC_SKIP), -+ [1] = USB3_PORT_DEFAULT(OC_SKIP), -+ [2] = USB3_PORT_DEFAULT(OC_SKIP), -+ [3] = USB3_PORT_DEFAULT(OC_SKIP), ++ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) ++ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) ++ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) ++ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSBC (USB-C) + }" + end + + device ref sata on -+ # TODO: sata ports ++ # SATA_0 - NC ++ # SATA_1A - NC ++ # SATA_1B - NC ++ # SATA_2 - M.2 2280 SATA ++ register "SataPortsEnable[3]" = "1" ++ register "SataPortsDevSlp[3]" = "1" + end + + # PCIe controller 1 - 1x2+2x1 @@ -1673,7 +2044,7 @@ index 0000000000..2cac8c4a75 + register "PcieRpHotPlug[4]" = "1" + end + -+ # M.2 caddy - x2 ++ # M.2 2280 SSD - x2 + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" @@ -1681,10 +2052,248 @@ index 0000000000..2cac8c4a75 + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" -+ register "PcieRpHotPlug[8]" = "1" + end + end +end +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_0.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_0.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..86f39ddb55ea9fb58d5e5699637636ef597c734e +GIT binary patch +literal 512 +zcmY!u;9+)EWZ+<6U|?oq29gXMJYRrxPEL*>N67~+1r7#Qh7a1t+8`-(puhlu3{YAD +YT>%dM8_BI;nL`dsaHtp+rc($20I8n}l>h($ + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_1.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_1.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..df0f6e58b79286a4aeb690c5027adf7a1f5f668b +GIT binary patch +literal 512 +zcmY!u;9+i6oWQ}rz`)GN3?vyic)kGXoSYm%j*<^t3LFfq3@hZcwLwzoK!E`Q8KATR +Yx&j>hH(SqvWezd%<4`dwOs5b40B_I==>Px# + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_10.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_10.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..24f0d8992bc5244c62488da9633e4885f52f3e22 +GIT binary patch +literal 512 +zcmY!u<Y9JIWZ+;(U|?oqW&i?q-XHu740(BZf(&^dxD+@TSQ$QOn`kgpFo@WI<Pkv3 +zjN25185j^Oge*SRoUI_)=hwI&^9wTJQ%GaE+Z>cy&~OfFg0G3Wp`)phiHWn5fv$6q +PvjPw>z-1}5hGzN!nb#F$ + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_11.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_11.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..59b6b9e78263c42aae367ab7d4a784d888f30efe +GIT binary patch +literal 512 +zcmY!u<Y8`AWZ+;(U|?osW&i?q-XHu740(BZf(&^dxD+@TSQ%DGYiKZ3Fo@WI<Pm^J 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a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_2.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_2.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..b5b14cf2dfa06ae183b0379da4dc825129e1589f +GIT binary patch +literal 512 +zcmY!u;9+)EWZ+<6U|?oq29gXMJU@VRUS6IcN7)B11r7#Qh7a1tdLSuupuhlu3{YAD +XT>%b$v*cE=%%S%6I8=-Z(<uZ1pPdSg + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_20.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_20.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063 +GIT binary patch +literal 512 +NcmZQz7zHCa1ONg600961 + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_3.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_3.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..d73736008af1eb67456b2fd66f7dec3b6669a442 +GIT binary patch +literal 512 +zcmY!u;9+i&oWQ}rz`)GN3?vyic)kGXoSYm%juHh92G#;*h81$!dLSuupuhlu3{YAD +YT>%b$+tzbnnL|62aHtp+rc($20QGqazW@LL + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_4.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_4.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..829f149547bc24859646c33d5926938d7a1b90cb +GIT binary patch +literal 512 +zcmY!u;9+)EWZ+<6U|?oq29gXMJYRrxPEL*>N67~+1r7#Qh7a1tdLSuupuhlu3{YAD +XT>%b$o8(ro%%OI594bbI=@bG0z{d&v + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_5.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_5.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063 +GIT binary patch +literal 512 +NcmZQz7zHCa1ONg600961 + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_6.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_6.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063 +GIT binary patch +literal 512 +NcmZQz7zHCa1ONg600961 + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_7.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_7.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..940f1e3cd8e5bd9ea32a82a14edcdcbc8132d8c7 +GIT binary patch +literal 512 +zcmY!u<Y8`AWZ+;(U|?osW&i><-XH%N8S?V-1R3%^a4B#wurjQW(9mG0U=XnZ$x{Q& +z0UPq1A)%L_QJxwGl4(Y*BAFWD+8T7AOcTeDU_*B^6OSleBX=`bLy)jxgN`d)<=|uh +E020*^DF6Tf + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_8.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_8.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..30c84410d417ef7afa8705c93cdb64a9f4e915a0 +GIT binary patch +literal 512 +zcmY!u<Y9JIWZ+;(U|?oqW&i?q-XHZ040(BZf(&^dxD+@TSQ$QOn`kgpFo@WI<f#GX +zYz3L}{MzzRenxp}7)YiWinU~FgllWifig`TL)=Uajm%6uqI8Yijh&1X6cmgabe!NS +H2PXpn6CD!Q + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_9.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_9.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..7facef55b93fe1f67411c00bab84862769461f63 +GIT binary patch +literal 512 +zcmY!u<Y8`AWZ+;(U|?osW&i?q-XHZ040(BZf(&^dxD+@TSQ%DGYiKZ3Fo@WI<f#GX +zYz3L}{F>W!enxp}7)YiWinU~FgllWifig`TLxK(6%}hL^bdB7N9Ss$Lz^FmT39fQ* +FG5`?&65ap+ + +literal 0 +HcmV?d00001 + -- 2.39.5 diff --git a/config/coreboot/next/patches/0004-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/next/patches/0005-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch index 33e7a55d..e490a807 100644 --- a/config/coreboot/next/patches/0004-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ b/config/coreboot/next/patches/0005-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -1,7 +1,7 @@ -From bc884fae79664c0d606991b5e0d62c608f3bef35 Mon Sep 17 00:00:00 2001 +From 534d696a570a50057153669247933ec1a4a2480f Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 4/9] mb/dell: Add Optiplex 780 MT (x4x/ICH10) +Subject: [PATCH 5/8] mb/dell: Add Optiplex 780 MT (x4x/ICH10) Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/next/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/next/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index d623f57f..51bbfa5c 100644 --- a/config/coreboot/next/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/next/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From 13da22a18b2c13b8676c69e929ba51f2d5d188cf Mon Sep 17 00:00:00 2001 +From 851043846f589e718a69009a6b157b4ff5315471 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 5/9] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 6/8] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). diff --git a/config/coreboot/next/patches/0006-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/next/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch index 6ca8bee8..47f549a1 100644 --- a/config/coreboot/next/patches/0006-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/next/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From bc1c834506a749eb2b235e51bb75b04b5b939ad5 Mon Sep 17 00:00:00 2001 +From fa6ac5b7f134b98a4f68f0f6b8bdeb6c7b6871ab Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 6/9] Remove warning for coreboot images built without a +Subject: [PATCH 7/8] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing diff --git a/config/coreboot/next/patches/0007-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/next/patches/0008-mb-dell-optiplex_780-Add-USFF-variant.patch index 17168733..d49e0e9d 100644 --- a/config/coreboot/next/patches/0007-mb-dell-optiplex_780-Add-USFF-variant.patch +++ b/config/coreboot/next/patches/0008-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -1,7 +1,7 @@ -From 1fa342e9462503c871bc5f4a0e4508ff8eac3e68 Mon Sep 17 00:00:00 2001 +From 636cb8ae8610cd99b637448add778c8e4f364f3e Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 7/9] mb/dell/optiplex_780: Add USFF variant +Subject: [PATCH 8/8] mb/dell/optiplex_780: Add USFF variant Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/next/patches/0009-lenovo-t480-Add-MAINBOARD_USES_IFD_GBE_REGION.patch b/config/coreboot/next/patches/0009-lenovo-t480-Add-MAINBOARD_USES_IFD_GBE_REGION.patch deleted file mode 100644 index ee0e2785..00000000 --- a/config/coreboot/next/patches/0009-lenovo-t480-Add-MAINBOARD_USES_IFD_GBE_REGION.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 4bd27d11c2ccd65a3b2a2e465aab9922e8aee31a Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Sun, 1 Dec 2024 07:16:20 +0000 -Subject: [PATCH 9/9] lenovo/t480: Add MAINBOARD_USES_IFD_GBE_REGION - -This board does use a GbE region, so support it in menuconfig. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index 13d71670e3..a3593e3785 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -15,6 +15,7 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - select MAINBOARD_HAS_LIBGFXINIT - select MEMORY_MAPPED_TPM - select MAINBOARD_HAS_TPM2 -+ select MAINBOARD_USES_IFD_GBE_REGION - select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SPD_READ_BY_WORD - select SYSTEM_TYPE_LAPTOP --- -2.39.5 - diff --git a/config/coreboot/next/patches/0010-add-vbt-file-for-thinkpad-t480s.patch b/config/coreboot/next/patches/0010-add-vbt-file-for-thinkpad-t480s.patch deleted file mode 100644 index b9bde459..00000000 --- a/config/coreboot/next/patches/0010-add-vbt-file-for-thinkpad-t480s.patch +++ /dev/null @@ -1,49 +0,0 @@ -From c865010771f413d532713319b7b01e9da9dbf495 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Mon, 2 Dec 2024 03:12:52 +0000 -Subject: [PATCH 1/1] add vbt file for thinkpad t480s - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - .../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes - 1 file changed, 0 insertions(+), 0 deletions(-) - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840 -GIT binary patch -literal 4106 -zcmeHJUu+a*5TCu>yW9JAmoD2P<t%lC2CfC#y%tU^HSGOq>9tqx`iFWXCLD09R<E?S -zMT)`nNScT-%9*GEA8a2?G`v`!jPV6yVlcd5OnC6Y;F}U&jJz1db9VRID@E)DLk#NN -z&9^i2&Hiq_`R2ZF8ipf7IM{nI5$^585@kULrrx0OPKv~ngNI__q41$dA{p()ui+v1 -zw(9rm09lUPAP4nOTm0CRnF|aw5^SQSH<G}<u_Gfnvn6IuK0h@!j;UxI!$*&rIdkIh -zl$piB;eBDWa1|CgK9bAg{^O%Z%!ziiz{neeJDb~fBI?1GV5p^44?a$ETl=n1d+;%Z -z#X6(OzEnIB9*QUTV{!mv@xk!mU}s+>aS&4j$?kY0KGYdgn6;MZ*!anbk!PNr!a%eU -zTXkLEL3ly5L&oUX#CS7?b2%Kad?s<goHQq1G_%bLv);c5qQC)gZtxnw!L3%1MWI_X -z0wUImYD_R11gsI%l%Zw})KN_c#&!YgM3v;Up{7+s1=lXlB>-#@;mhg8>>>#S&)d2I -zmP&-g0$k02szSQj(Y*j}YYtQnDH0;2ui<!ko-28Y){6ilAcrmz951v4RTWQ_ye!or -z4xOJya#Sr7{o)%XFUfJCndM%KM(c^ol_hzlb*1h&uC%Vy%U(P!_qUfwcb4r;SmPQ_ -zhxf($vVo)we+jxogb`7NQ^aS9eQpNT#2bmX5(kO*5O)$Mi4PJVB_1U{L42C{HR894 -z=ZJk70(Q~o{*COiRR#_fix0XaS3?igAuo2!)<NF8ARGWF&M7=h16xZaS|UxpZA)w3 -z1CQUC@^&oxtbG2HGk&WA9=_qa;$?8fdy_j;eY+H3ciR5U?|$2?oT;mPoV=Dx&CwUf -zv~zYWs{cR#vl*!ChO54O0k3UT#mpur4fXeCdE_aoNtZ|mgF!ck3Nmy<0BRuy4NwCa -zNZDP7XrHsU<-0NyB2=wXwgEqZPukelExAY+hyWVj0{)~A=X~17KK7XpzxQcB``9fX -zZf4pp#`ZEanRbG)(+odg+NX?t!SF|>{mPhI!flfFgv9nqI4Wr~5_?s`k0kALiCvcP -zCrRUFrpVYPYn?Jn%6MGXUXj_GGJYa!U&-tn8Gn&ANnz_0+@olH3VTw)mlf@-!p<v7 -zljhF5u5tObYwR{boRI14NxNkGd6QG=>8{!e#p0ct5}M(h16D>p?OGjSz6v3juERjS -z#z{?mXvVqrXs_rvUmYR40gNzg(QD6y9E94?4DWO|6eb83LI-smcVC6x1n2reH}rAp -zLM);f=tWDCr``UF5T>!;PYu^H1g>EBP8A}2*fM>s-@nC3pDV|}6+CtfhG(II7`pcw -z`jLfJ!?;*R@Bp=Nw2EPOC7FEs(cugIP_K6tN_$~tvS8nx6iOv|IMrO3&-m*N9ZP#b -znG^~>I|l1cUVSeD9r^k3h0TP}WWD9=MZxY<<azgO1@-W5<NTHW*-d)t{Q4yX9_+?a -zHawLe=uO6@%xqS#?JxafX%#$`BhkIqq>Z3B2yU!k71#YRpThOJtVheMDA50rV#s@U -z+nKbA{O(olYR}icuzQD*-cjBQ9;%!eMDVP>7mWsF@=%>o)wSgq=n%DHNOYwRr4Ao6 -zbNdgEn*RdDS>Rud+fIY0N8JkP3q6;>8o%R(CE2n3?Xg%qP+U%~6|{XFyxv7Y#;J2Z -XK$lk*wsY^m4}9|iz?mg_AjCfat$CyH - -literal 0 -HcmV?d00001 - --- -2.39.5 - diff --git a/config/coreboot/next/patches/0011-Disable-m2-hotplug-in-lenovo-t480s-devicetree.patch b/config/coreboot/next/patches/0011-Disable-m2-hotplug-in-lenovo-t480s-devicetree.patch deleted file mode 100644 index 00a844c1..00000000 --- a/config/coreboot/next/patches/0011-Disable-m2-hotplug-in-lenovo-t480s-devicetree.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 44d0703b61156a19c6cbfb5cfe3f5d58e328daae Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Mon, 2 Dec 2024 11:16:43 +0000 -Subject: [PATCH 1/1] Disable m2 hotplug in lenovo t480s devicetree - -This fixes a bug where nvme disappears and gets renamed on -s3 resume. - -Thanks go to Mate Kukri who suggested this. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - .../lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -index 2cac8c4a75..9129d3a1b8 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -@@ -115,7 +115,6 @@ chip soc/intel/skylake - register "PcieRpClkSrcNumber[8]" = "5" - register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" -- register "PcieRpHotPlug[8]" = "1" - end - end - end --- -2.39.5 - |