diff options
Diffstat (limited to 'resources/coreboot/fam15h_udimm/patches')
4 files changed, 209 insertions, 0 deletions
diff --git a/resources/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch b/resources/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch new file mode 100644 index 00000000..3c131a86 --- /dev/null +++ b/resources/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch @@ -0,0 +1,31 @@ +From 8f2988cba4fffef1bd4f65e123c76bf4b7a18672 Mon Sep 17 00:00:00 2001 +From: "D.d.P.F. Lombard" <lombard@lombards.xyz> +Date: Sun, 7 Feb 2021 15:29:40 +0100 +Subject: [PATCH 1/6] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training + failure on Fam15h" (fixes a bug that prevent certain RAM modules from + booting) + +This reverts commit 610d1c67b2298a9840681c2b4492b6d3fdf44a46. + +After 610d1c67b2298a9840681c2b4492b6d3fdf44a46 many RAM modules wouldn't work and you couldn't even see any output on the screen. +--- + src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +index ddaaaab8d5..3b07786b91 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +@@ -71,6 +71,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, + misc2 |= ((cs_mux_67 & 0x1) << 27); + misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */ + misc2 |= ((cs_mux_45 & 0x1) << 26); ++ ++ if (pDCTstat->Status & (1 << SB_Registered)) ++ misc2 |= 1 << SubMemclkRegDly; + } else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { + if (pDCTstat->Status & (1 << SB_Registered)) { + misc2 |= 1 << SubMemclkRegDly; +-- +2.25.1 + diff --git a/resources/coreboot/fam15h_udimm/patches/0003-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch b/resources/coreboot/fam15h_udimm/patches/0003-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch new file mode 100644 index 00000000..5a39bd69 --- /dev/null +++ b/resources/coreboot/fam15h_udimm/patches/0003-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch @@ -0,0 +1,38 @@ +From 7a00638cea41ad939a59fc0e5996959435fbdb7f Mon Sep 17 00:00:00 2001 +From: "D.d.P.F. Lombard" <lombard@lombards.xyz> +Date: Sun, 7 Feb 2021 16:40:05 +0100 +Subject: [PATCH 3/6] Tweak cmos defaults for KCMA-D8 (for a little speed + boost) + +63xx CPUs have the option to use a reduced latency value inside the crossbar. +Setting "experimental_memory_speed_boost=Enable" aparently only has an effect +on 63xx CPUs and may, in certain cases, yield a slight memory bandwidth +increase (according to Timothy Pearson), but maybe it also works for +43xx CPUs. + +Setting "l3_cache_partitioning=Enable" will increase performance in certain +situations. See: +https://developer.arm.com/documentation/100453/0401/functional-description/l3-cache/l3-cache-partitioning?lang=en +--- + src/mainboard/asus/kcma-d8/cmos.default | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default +index 306687157f..4e033d756f 100644 +--- a/src/mainboard/asus/kcma-d8/cmos.default ++++ b/src/mainboard/asus/kcma-d8/cmos.default +@@ -21,9 +21,9 @@ sata_ahci_mode=Enable + sata_alpm=Disable + maximum_p_state_limit=0xf + probe_filter=Auto +-l3_cache_partitioning=Disable ++l3_cache_partitioning=Enable + gart=Enable + ehci_async_data_cache=Enable +-experimental_memory_speed_boost=Disable ++experimental_memory_speed_boost=Enable + power_on_after_fail=On + boot_option=Fallback +-- +2.25.1 + diff --git a/resources/coreboot/fam15h_udimm/patches/0004-Do-not-use-microcode-updates-on-AMD-platforms.patch b/resources/coreboot/fam15h_udimm/patches/0004-Do-not-use-microcode-updates-on-AMD-platforms.patch new file mode 100644 index 00000000..7f81fd2c --- /dev/null +++ b/resources/coreboot/fam15h_udimm/patches/0004-Do-not-use-microcode-updates-on-AMD-platforms.patch @@ -0,0 +1,108 @@ +From 2b1d40b970d9cbbb4f8fe30679e9b6909aa3d99a Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Thu, 6 May 2021 17:07:06 +0100 +Subject: [PATCH 4/6] Do not use microcode updates on AMD platforms + +Coreboot is hardcoding the use of microcode updates on some platforms. + +Just nuke it from orbit. This is the libre branch of osboot, so microcode must +not be used. +--- + src/cpu/Makefile.inc | 52 +------------------ + src/cpu/amd/family_10h-family_15h/Kconfig | 1 - + .../amd/family_10h-family_15h/Makefile.inc | 10 +--- + 3 files changed, 2 insertions(+), 61 deletions(-) + +diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc +index b80c30d72b..e7909d32ed 100644 +--- a/src/cpu/Makefile.inc ++++ b/src/cpu/Makefile.inc +@@ -14,54 +14,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) + ## Rules for building the microcode blob in CBFS + ################################################################################ + +-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) +-cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin +-endif +- +-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +-cbfs-files-y += cpu_microcode_blob.bin +-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin +- +-$(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER_FILES)) +- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" +- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +-endif +- +-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y) +-cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES)) +-endif +-# otherwise `cpu_microcode_bins` should be filled by platform makefiles +- +-# We just mash all microcode binaries together into one binary to rule them all. +-# This approach assumes that the microcode binaries are properly padded, and +-# their headers specify the correct size. This works fairly well on isolatied +-# updates, such as Intel and some AMD microcode, but won't work very well if the +-# updates are wrapped in a container, like AMD's microcode update container. If +-# there is only one microcode binary (i.e. one container), then we don't have +-# this issue, and this rule will continue to work. +-$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) +- for bin in $(cpu_microcode_bins); do \ +- if [ ! -f "$$bin" ]; then \ +- echo "Microcode error: $$bin does not exist"; \ +- NO_MICROCODE_FILE=1; \ +- fi; \ +- done; \ +- if [ -n "$$NO_MICROCODE_FILE" ]; then \ +- if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \ +- echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \ +- fi; \ +- false; \ +- fi +- $(if $^,,false) # fail if no file is given at all +- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" +- @echo $(cpu_microcode_bins) +- cat $^ > $@ +- +-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin +-cpu_microcode_blob.bin-type := microcode +- +-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +-cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +-else +-cpu_microcode_blob.bin-align := 16 +-endif ++# No microcode permitted in this version of coreboot. +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index ad4f5f4ba6..21150ab1a7 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -8,7 +8,6 @@ config CPU_AMD_MODEL_10XXX + select TSC_SYNC_LFENCE + select UDELAY_LAPIC + select SUPPORT_CPU_UCODE_IN_CBFS +- select CPU_MICROCODE_MULTIPLE_FILES + select CAR_GLOBAL_MIGRATION + + if CPU_AMD_MODEL_10XXX +diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc +index 7035323026..e0029f562d 100644 +--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc ++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc +@@ -14,12 +14,4 @@ ramstage-y += ram_calc.c + ramstage-y += monotonic_timer.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c + +-# Microcode for Family 10h, 11h, 12h, and 14h +-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin +-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin +-microcode_amd.bin-type := microcode +- +-# Microcode for Family 15h +-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-type := microcode ++# Microcode deleted in this version of coreboot. +-- +2.25.1 + diff --git a/resources/coreboot/fam15h_udimm/patches/0006-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch b/resources/coreboot/fam15h_udimm/patches/0006-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch new file mode 100644 index 00000000..5ada0dff --- /dev/null +++ b/resources/coreboot/fam15h_udimm/patches/0006-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch @@ -0,0 +1,32 @@ +From f0aac7261e16adc8e61eca7a506ff2de5112be47 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Fri, 7 May 2021 19:43:32 +0100 +Subject: [PATCH 6/6] asus/kgpe-d16: enable lc_cache_partitioning and + experimental_memory_speed_boost + +This really only benefits 63xx opterons which are less reliable in libreboot due +to lack of CPU microcode updates, but we might aswell enable this anyway. +--- + src/mainboard/asus/kgpe-d16/cmos.default | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default +index 7c496a50d7..8a25620e1d 100644 +--- a/src/mainboard/asus/kgpe-d16/cmos.default ++++ b/src/mainboard/asus/kgpe-d16/cmos.default +@@ -21,10 +21,10 @@ sata_ahci_mode=Enable + sata_alpm=Disable + maximum_p_state_limit=0xf + probe_filter=Auto +-l3_cache_partitioning=Disable ++l3_cache_partitioning=Enable + ieee1394_controller=Enable + gart=Enable + ehci_async_data_cache=Enable +-experimental_memory_speed_boost=Disable ++experimental_memory_speed_boost=Enable + power_on_after_fail=On + boot_option=Fallback +-- +2.25.1 + |