diff options
Diffstat (limited to 'resources/coreboot/default/patches')
21 files changed, 116 insertions, 751 deletions
diff --git a/resources/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/resources/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch new file mode 100644 index 00000000..74090dc0 --- /dev/null +++ b/resources/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch @@ -0,0 +1,23 @@ +From 4df63d823092dc06e3cfc27165a4850b996af90d Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@retroboot.org> +Date: Fri, 19 Mar 2021 05:54:58 +0000 +Subject: [PATCH 01/11] apple/macbook21: Set default VRAM to 64MiB instead of + 8MiB + +--- + src/mainboard/apple/macbook21/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default +index cf1bc4566e..dc0df3b6d6 100644 +--- a/src/mainboard/apple/macbook21/cmos.default ++++ b/src/mainboard/apple/macbook21/cmos.default +@@ -5,4 +5,4 @@ boot_devices='' + boot_default=0x40 + cmos_defaults_loaded=Yes + lpt=Enable +-gfx_uma_size=8M ++gfx_uma_size=64M +-- +2.25.1 + diff --git a/resources/coreboot/default/patches/0001-hardcode-tianocore-revisions-and-don-t-automatically.patch b/resources/coreboot/default/patches/0001-hardcode-tianocore-revisions-and-don-t-automatically.patch deleted file mode 100644 index a67448e1..00000000 --- a/resources/coreboot/default/patches/0001-hardcode-tianocore-revisions-and-don-t-automatically.patch +++ /dev/null @@ -1,128 +0,0 @@ -From 9000fe203d31e584bdc7d3e43d7ea615d9335205 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Thu, 13 May 2021 23:52:08 +0100 -Subject: [PATCH 01/19] hardcode tianocore revisions, and don't automatically - download - ---- - Makefile | 2 +- - payloads/external/tianocore/Makefile | 57 ++++++++-------------------- - 2 files changed, 17 insertions(+), 42 deletions(-) - -diff --git a/Makefile b/Makefile -index 02c6288f15..8290b45e89 100644 ---- a/Makefile -+++ b/Makefile -@@ -486,7 +486,7 @@ distclean-utils: - $(MAKE) -C util/$(tool) distclean MFLAGS= MAKEFLAGS= ; \ - rm -f /util/$(tool)/junit.xml;) - --distclean: clean clean-ctags clean-cscope distclean-payloads distclean-utils -+distclean: clean clean-ctags clean-cscope distclean-utils - rm -f .config .config.old ..config.tmp* .kconfig.d .tmpconfig* .ccwrap .xcompile - rm -rf coreboot-builds coreboot-builds-chromeos - rm -f abuild*.xml junit.xml* util/lint/junit.xml -diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile -index 7cd34f1732..3527b7a2ad 100644 ---- a/payloads/external/tianocore/Makefile -+++ b/payloads/external/tianocore/Makefile -@@ -1,5 +1,8 @@ - ## SPDX-License-Identifier: GPL-2.0-only - -+# This file has been modified for libreboot/osboot/osboot-libre. -+# The tianocore repo/branch/revision has been hardcoded, as have some options -+ - # force the shell to bash - the edksetup.sh script doesn't work with dash - export SHELL := env bash - -@@ -9,51 +12,31 @@ project_git_repo=https://github.com/mrchromebox/edk2 - project_git_branch=coreboot_fb - upstream_git_repo=https://github.com/tianocore/edk2 - --ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y) --bootloader=UefiPayloadPkg --logo_pkg=MdeModulePkg --build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE --TAG=upstream/master --else - bootloader=CorebootPayloadPkg - logo_pkg=CorebootPayloadPkg - # STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch --TAG=origin/$(project_git_branch) --endif -- --ifneq ($(CONFIG_TIANOCORE_REVISION_ID),) --TAG=$(CONFIG_TIANOCORE_REVISION_ID) --endif -+TAG=ca08920ded1649921a12105d1959df423733431f -+# above is a commit ID in MrChromebox's coreboot_fb branch - - export EDK_TOOLS_PATH=$(project_dir)/BaseTools - --ifeq ($(CONFIG_TIANOCORE_DEBUG),y) --BUILD_TYPE=DEBUG --else - BUILD_TYPE=RELEASE --endif - --ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y) - TIMER=-DUSE_HPET_TIMER --endif - --TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) -+# see coreboot 61a3c8a005922d46425c84f847c0ad26e9c3cdca -+# "2 seconds for board with internal display" -+# "5 seconds for board without internal display" -+# libreboot takes the shotgun approach. 5 seconds for all -+TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=5 - --ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y) --ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y) --ARCH=-a IA32 -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc --else - ARCH=-a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc --endif --else --ARCH=-a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc --endif - --BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor) -+BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) - - all: clean build - --$(project_dir): -+download: - echo " Cloning $(project_name) from Git" - git clone --branch $(project_git_branch) $(project_git_repo) $(project_dir); \ - cd $(project_dir); \ -@@ -76,17 +59,9 @@ update: $(project_dir) - git submodule update --init - - checktools: -- echo "Checking uuid-dev..." -- echo "#include <uuid/uuid.h>" > libtest.c -- echo "int main(int argc, char **argv) { (void) argc; (void) argv; return 0; }" >> libtest.c -- $(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo " found uuid-dev." || \ -- ( echo " Not found."; echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 ) -- rm -rf libtest.c libtest -- echo "Checking nasm..." -- type nasm > /dev/null 2>&1 && echo " found nasm." || \ -- ( echo " Not found."; echo "Error: Please install nasm."; exit 1 ) -- --build: update checktools -+ echo "tianocore tool check disabled" -+ -+build: checktools - unset CC; $(MAKE) -C $(project_dir)/BaseTools - echo " build $(project_name) $(TAG)" - if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \ -@@ -116,4 +91,4 @@ clean: - distclean: - rm -rf $(project_dir) - --.PHONY: all update checktools config build clean distclean -+.PHONY: all update checktools config build clean distclean download --- -2.25.1 - diff --git a/resources/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch b/resources/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch new file mode 100644 index 00000000..11c26913 --- /dev/null +++ b/resources/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch @@ -0,0 +1,68 @@ +From a43fee19b7a4615aceb9bdf96afda980c106445e Mon Sep 17 00:00:00 2001 +From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> +Date: Wed, 27 Oct 2021 13:36:01 +0200 +Subject: [PATCH 02/11] add c3 and clockgen to apple/macbook21 + +--- + src/mainboard/apple/macbook21/Kconfig | 1 + + src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++ + src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++ + 3 files changed, 20 insertions(+) + +diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig +index 5f5ffde588..27377b737c 100644 +--- a/src/mainboard/apple/macbook21/Kconfig ++++ b/src/mainboard/apple/macbook21/Kconfig +@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select I945_LVDS ++ select DRIVERS_I2C_CK505 + + config MAINBOARD_DIR + default "apple/macbook21" +diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c +index 13d06f0839..88b8669c61 100644 +--- a/src/mainboard/apple/macbook21/cstates.c ++++ b/src/mainboard/apple/macbook21/cstates.c +@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = { + .addrh = 0, + } + }, ++ { ++ .ctype = 3, ++ .latency = 17, ++ .power = 250, ++ .resource = { ++ .space_id = ACPI_ADDRESS_SPACE_FIXED, ++ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, ++ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, ++ .access_size = ACPI_ACCESS_SIZE_UNDEFINED, ++ .addrl = 0x20, ++ .addrh = 0, ++ } ++ }, + }; + + int get_cst_entries(const acpi_cstate_t **entries) +diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb +index bcce778cb1..16025d6fbb 100644 +--- a/src/mainboard/apple/macbook21/devicetree.cb ++++ b/src/mainboard/apple/macbook21/devicetree.cb +@@ -104,7 +104,13 @@ chip northbridge/intel/i945 + end + device pci 1f.3 on # SMBUS + subsystemid 0x8086 0x7270 ++ chip drivers/i2c/ck505 ++ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }" ++ register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }" ++ device i2c 69 on end ++ end + end ++ + end + end + end +-- +2.25.1 + diff --git a/resources/coreboot/default/patches/0002-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/resources/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch index 47a99bf0..08b289d7 100644 --- a/resources/coreboot/default/patches/0002-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch +++ b/resources/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch @@ -1,7 +1,7 @@ -From 7abacb9f5b07df89136751fbcc1569fe02f1c23b Mon Sep 17 00:00:00 2001 +From 6302d89dfd785330944ad091767c7e7eb8da4aed Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@osboot.org> Date: Sun, 3 Jan 2021 03:34:01 +0000 -Subject: [PATCH 02/19] lenovo/x60: 64MiB Video RAM changed to default +Subject: [PATCH 03/11] lenovo/x60: 64MiB Video RAM changed to default (previously it was 8MiB) --- diff --git a/resources/coreboot/default/patches/0003-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/resources/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch index f4ccc837..67c4a892 100644 --- a/resources/coreboot/default/patches/0003-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch +++ b/resources/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch @@ -1,7 +1,7 @@ -From d57e7edf35a923ebf0177b9a816179be0ad4b72f Mon Sep 17 00:00:00 2001 +From f13f10f6b61d0581970a508b626cd63adf607eff Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@osboot.org> Date: Mon, 22 Feb 2021 22:16:59 +0000 -Subject: [PATCH 03/19] lenovo/t60: make 64MiB VRAM the default in cmos.default +Subject: [PATCH 04/11] lenovo/t60: make 64MiB VRAM the default in cmos.default --- src/mainboard/lenovo/t60/cmos.default | 2 +- diff --git a/resources/coreboot/default/patches/0014-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch b/resources/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch index 48752583..d205f2a6 100644 --- a/resources/coreboot/default/patches/0014-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch +++ b/resources/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch @@ -1,7 +1,7 @@ -From ade5066801bbc20e88205299e3b66de7f1a1bc82 Mon Sep 17 00:00:00 2001 +From e3b971134ffc2f52e575efe53a571978ed291dc6 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:10:33 +0100 -Subject: [PATCH 14/19] lenovo/t400: set VRAM to 352MiB VRAM by default +Subject: [PATCH 05/11] lenovo/t400: set VRAM to 352MiB VRAM by default In the past, this caused stability issues so we set it to 256MiB. Nowadays, coreboot has fixed the issue preventing this. See: diff --git a/resources/coreboot/default/patches/0005-util-cbfstool-Do-not-set-D_XOPEN_SOURCE-on-FreeBSD.patch b/resources/coreboot/default/patches/0005-util-cbfstool-Do-not-set-D_XOPEN_SOURCE-on-FreeBSD.patch deleted file mode 100644 index 64bdb33c..00000000 --- a/resources/coreboot/default/patches/0005-util-cbfstool-Do-not-set-D_XOPEN_SOURCE-on-FreeBSD.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 58cd6e0c97c67fdd8948975b74567e1ff6d8d6ee Mon Sep 17 00:00:00 2001 -From: Idwer Vollering <vidwer@gmail.com> -Date: Sun, 9 May 2021 18:16:26 +0200 -Subject: [PATCH 05/19] util/cbfstool: Do not set -D_XOPEN_SOURCE on FreeBSD - -Fixes compilation on FreeBSD CURRENT, and possibly other releases. - -The compiler, clang, complained about: -util/cbfstool/cbfstool.c:181:40: error: implicit declaration of function 'memmem' is invalid in C99 [-Werror,-Wimplicit-function-declaration] -util/cbfstool/cbfstool.c:181:31: error: incompatible integer to pointer conversion initializing 'struct metadata_hash_anchor *' with an expression of type 'int' [-Werror,-Wint-conversion] - -Signed-off-by: Idwer Vollering <vidwer@gmail.com> -Change-Id: I45c02a21709160df44fc8da329f6c4a9bad24478 -Reviewed-on: https://review.coreboot.org/c/coreboot/+/53996 -Reviewed-by: Angel Pons <th3fanbus@gmail.com> -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> ---- - util/cbfstool/Makefile.inc | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc -index 5b49fe80ad..47b89e57b0 100644 ---- a/util/cbfstool/Makefile.inc -+++ b/util/cbfstool/Makefile.inc -@@ -95,7 +95,6 @@ TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings - TOOLCFLAGS += -O2 - TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h - TOOLCPPFLAGS += -D_BSD_SOURCE -D_SVID_SOURCE # _DEFAULT_SOURCE for older glibc --TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h - TOOLCPPFLAGS += -D_GNU_SOURCE # memmem() from string.h - TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap - TOOLCPPFLAGS += -I$(top)/util/cbfstool -@@ -113,6 +112,10 @@ TOOLCPPFLAGS += -I$(top)/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include - TOOLLDFLAGS ?= - HOSTCFLAGS += -fms-extensions - -+ifneq ($(shell uname -o 2>/dev/null), FreeBSD) -+TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h -+endif -+ - ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32) - TOOLCFLAGS += -mno-ms-bitfields - endif --- -2.25.1 - diff --git a/resources/coreboot/default/patches/0015-lenovo-x200-set-VRAM-to-352MiB-by-default.patch b/resources/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-352MiB-by-default.patch index c3d3bd64..9ff0ad8d 100644 --- a/resources/coreboot/default/patches/0015-lenovo-x200-set-VRAM-to-352MiB-by-default.patch +++ b/resources/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-352MiB-by-default.patch @@ -1,7 +1,7 @@ -From a4b575bf23bade522ac6a777793ef01abcb2b821 Mon Sep 17 00:00:00 2001 +From 383c273f0c44eec93cd55c3d21d6c1a8316d8dbe Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:11:59 +0100 -Subject: [PATCH 15/19] lenovo/x200: set VRAM to 352MiB by default +Subject: [PATCH 06/11] lenovo/x200: set VRAM to 352MiB by default This fix makes it possible: https://review.coreboot.org/c/coreboot/+/16831 diff --git a/resources/coreboot/default/patches/0006-src-security-intel-stm-Add-warning-for-non-reproduci.patch b/resources/coreboot/default/patches/0006-src-security-intel-stm-Add-warning-for-non-reproduci.patch deleted file mode 100644 index b01cf1c3..00000000 --- a/resources/coreboot/default/patches/0006-src-security-intel-stm-Add-warning-for-non-reproduci.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 1804c7cb2e6e62a363a18f237ecdf8337e58c20d Mon Sep 17 00:00:00 2001 -From: Martin Roth <martin@coreboot.org> -Date: Mon, 10 May 2021 11:28:45 -0600 -Subject: [PATCH 06/19] src/security/intel/stm: Add warning for - non-reproducible build - -Because the STM build doesn't use the coreboot toolchain it's not -reproducible. Make sure that's displayed during the build. - -Signed-off-by: Martin Roth <martin@coreboot.org> -Change-Id: I3f0101400dc221eca09c928705f30d30492f171f -Reviewed-on: https://review.coreboot.org/c/coreboot/+/54020 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Angel Pons <th3fanbus@gmail.com> -Reviewed-by: Patrick Georgi <pgeorgi@google.com> ---- - src/security/intel/stm/Makefile | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/src/security/intel/stm/Makefile b/src/security/intel/stm/Makefile -index 1493869e80..31e5bdd88a 100644 ---- a/src/security/intel/stm/Makefile -+++ b/src/security/intel/stm/Makefile -@@ -18,6 +18,8 @@ all: build - - build: - echo "STM - Build" -+ echo "-- WARNING: This uses the system toolchain instead of" -+ echo " the coreboot toolchain, so is not reproducible." - cd $(project_dir)/Stm; \ - mkdir -p build; \ - cd build; \ --- -2.25.1 - diff --git a/resources/coreboot/default/patches/0007-Makefile-Don-t-run-genbuild_h-if-not-doing-a-build.patch b/resources/coreboot/default/patches/0007-Makefile-Don-t-run-genbuild_h-if-not-doing-a-build.patch deleted file mode 100644 index 6b7a4341..00000000 --- a/resources/coreboot/default/patches/0007-Makefile-Don-t-run-genbuild_h-if-not-doing-a-build.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 65f0c7278ec0c1cb197e3110e2bc4ebb4bd5caf4 Mon Sep 17 00:00:00 2001 -From: Martin Roth <martin@coreboot.org> -Date: Sun, 9 May 2021 10:26:10 -0600 -Subject: [PATCH 07/19] Makefile: Don't run genbuild_h if not doing a build - -genbuild_h was being run on every make invocation - clean, distclean, -etc. to get the source date epoch value. This value isn't used unless -a build is being done, so don't run it on non-compile make invocations. - -Signed-off-by: Martin Roth <martin@coreboot.org> -Change-Id: I2afc0affc17116e0db849ea968474bc19dbb0ae1 -Reviewed-on: https://review.coreboot.org/c/coreboot/+/53997 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Angel Pons <th3fanbus@gmail.com> -Reviewed-by: Patrick Georgi <pgeorgi@google.com> ---- - Makefile | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Makefile b/Makefile -index 8290b45e89..1e6cca44b3 100644 ---- a/Makefile -+++ b/Makefile -@@ -24,7 +24,9 @@ COREBOOT_EXPORTS += top src srck obj objutil objk - LANG:=C - LC_ALL:=C - TZ:=UTC0 -+ifneq ($(NOCOMPILE),1) - SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"\(.*\)".*/\1/p') -+endif - # don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system - # are reproducible - export LANG LC_ALL TZ SOURCE_DATE_EPOCH --- -2.25.1 - diff --git a/resources/coreboot/default/patches/0016-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch b/resources/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch index 0e0bab05..7992b023 100644 --- a/resources/coreboot/default/patches/0016-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch +++ b/resources/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch @@ -1,7 +1,7 @@ -From 8b2eb25cdd1868e2e98eefa783e04b1797b1a701 Mon Sep 17 00:00:00 2001 +From 4f4f957ea967cc94841746821144ee807747f540 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:18:26 +0100 -Subject: [PATCH 16/19] gigabyte/ga-g41m-es2l: set VRAM to 352MiB by default +Subject: [PATCH 07/11] gigabyte/ga-g41m-es2l: set VRAM to 352MiB by default --- src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +- diff --git a/resources/coreboot/default/patches/0017-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch b/resources/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch index 46ef21a6..1536c15f 100644 --- a/resources/coreboot/default/patches/0017-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch +++ b/resources/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch @@ -1,7 +1,7 @@ -From f90a509e24ced459bc24ad9c34f363f9f413f558 Mon Sep 17 00:00:00 2001 +From 1ee893f9fc5251968500695824ab9fd39461d318 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:21:39 +0100 -Subject: [PATCH 17/19] acer/g43t-am3: set VRAM to 352MiB by default +Subject: [PATCH 08/11] acer/g43t-am3: set VRAM to 352MiB by default --- src/mainboard/acer/g43t-am3/cmos.default | 2 +- diff --git a/resources/coreboot/default/patches/0008-util-genbuild_h-Update-IASL-location-finding-code.patch b/resources/coreboot/default/patches/0008-util-genbuild_h-Update-IASL-location-finding-code.patch deleted file mode 100644 index e8cd7117..00000000 --- a/resources/coreboot/default/patches/0008-util-genbuild_h-Update-IASL-location-finding-code.patch +++ /dev/null @@ -1,74 +0,0 @@ -From aba6235d16b87706357d0fdb35afaf52968fac53 Mon Sep 17 00:00:00 2001 -From: Martin Roth <martin@coreboot.org> -Date: Sun, 9 May 2021 11:44:15 -0600 -Subject: [PATCH 08/19] util/genbuild_h: Update IASL location finding code - -Update the iasl path finding code to use XGCCPATH if it's set, and to -look for iasl on the path if it's not set and not under util/crossgcc. - -On the jenkins builders, iasl is in the path, not in util/crossgcc/xgcc. - -On the systems of people who have multiple copies of coreboot, it makes -sense to just have a single copy of the toolchain and define XGCCPATH in -the environment to point to it. - -Previously, either of these situations resulted in a warning from the -genbuild_h tool that iasl was not found under util/crossgcc, which was -true, but not particularly relevant, and generated confusion. - -If xcompile already existed before make was run, the correct path would -be found, but on an initial build, this check couldn't find iasl. - -BUG=None -TEST=Build with iasl in /util/crossgcc/xgcc/bin, in the path and in a -directory pointed to with XGCCPATH. - -Signed-off-by: Martin Roth <martin@coreboot.org> -Change-Id: Ic2f8dca0be8bfb54d3c672fab6cf6f005bb394c3 -Reviewed-on: https://review.coreboot.org/c/coreboot/+/54001 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Angel Pons <th3fanbus@gmail.com> -Reviewed-by: Patrick Georgi <pgeorgi@google.com> ---- - util/genbuild_h/genbuild_h.sh | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - -diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh -index 10ca0c5fa3..c898fb6e3f 100755 ---- a/util/genbuild_h/genbuild_h.sh -+++ b/util/genbuild_h/genbuild_h.sh -@@ -5,6 +5,7 @@ - DATE="" - GITREV="" - TIMESOURCE="" -+XGCCPATH="${XGCCPATH:-util/crossgcc/xgcc/bin/}" - - export LANG=C - export LC_ALL=C -@@ -47,8 +48,15 @@ NetBSD|OpenBSD|DragonFly|FreeBSD|Darwin) - esac - } - --IASL=util/crossgcc/xgcc/bin/iasl -+# Look for IASL in XGCCPATH and xcompile. Unfortunately, -+# xcompile isn't available on the first build. -+# If neither of those gives a valid iasl, check the path. -+IASL="${XGCCPATH}iasl" - eval $(grep ^IASL:= "$XCOMPILE" 2>/dev/null | sed s,:=,=,) -+if [ ! -x "${IASL}" ]; then -+ IASL=$(command -v iasl) -+fi -+IASLVERSION="$(${IASL} -v | grep version | sed 's/.*version //')" >/dev/null - - #Print out the information that goes into build.h - printf "/* build system definitions (autogenerated) */\n" -@@ -72,5 +80,5 @@ printf "#define COREBOOT_BUILD_EPOCH \"$(our_date "$DATE" +%s)\"\n" - printf "#define COREBOOT_DMI_DATE \"$(our_date "$DATE" +%m/%d/%Y)\"\n" - printf "\n" - printf "#define COREBOOT_COMPILE_TIME \"$(our_date "$DATE" +%T)\"\n" --printf "#define ASL_VERSION 0x%d\n" `$IASL -v | grep version | sed 's/.*version //'` -+printf "#define ASL_VERSION 0x%d\n" "${IASLVERSION}" - printf "#endif\n" --- -2.25.1 - diff --git a/resources/coreboot/default/patches/0018-Revert-cpu-intel-Configure-IA32_FEATURE_CONTROL-for-.patch b/resources/coreboot/default/patches/0009-Revert-cpu-intel-Configure-IA32_FEATURE_CONTROL-for-.patch index ededc2c2..36f4778d 100644 --- a/resources/coreboot/default/patches/0018-Revert-cpu-intel-Configure-IA32_FEATURE_CONTROL-for-.patch +++ b/resources/coreboot/default/patches/0009-Revert-cpu-intel-Configure-IA32_FEATURE_CONTROL-for-.patch @@ -1,7 +1,7 @@ -From f2b62dca2238ec7782739e81490846673d754629 Mon Sep 17 00:00:00 2001 +From 8e8704050aec67490a6d1f272840e5a04ee1bcff Mon Sep 17 00:00:00 2001 From: Rodrigo <rm@firemail.cc> Date: Mon, 23 Aug 2021 02:20:32 -0300 -Subject: [PATCH 18/19] Revert "cpu/intel: Configure IA32_FEATURE_CONTROL for +Subject: [PATCH 09/11] Revert "cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR" This rendered at least the x200 unable to reboot. @@ -30,10 +30,10 @@ index 3e4de1fa31..ca3ce274fc 100644 configure_c_states(quad); diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c -index fd6a82ac17..e2fa7c8f20 100644 +index bc53214310..72f40f6762 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c -@@ -42,34 +42,8 @@ static void pre_mp_smm_init(void) +@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void) smm_initialize(); } @@ -83,7 +83,7 @@ index 278d8dea81..a0917045dd 100644 configure_c_states(); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c -index 16c6866f45..31399bdbd7 100644 +index 34646ad5e9..36cfd51f01 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -109,6 +109,9 @@ static void model_6ex_init(struct device *cpu) @@ -97,7 +97,7 @@ index 16c6866f45..31399bdbd7 100644 configure_c_states(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c -index d0987b4a63..17a865c9f3 100644 +index 72ece23935..6f2d6ef599 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -123,6 +123,9 @@ static void model_6fx_init(struct device *cpu) diff --git a/resources/coreboot/default/patches/0009-util-crossgcc-Update-gmp-to-6.2.1.patch b/resources/coreboot/default/patches/0009-util-crossgcc-Update-gmp-to-6.2.1.patch deleted file mode 100644 index f9190e2e..00000000 --- a/resources/coreboot/default/patches/0009-util-crossgcc-Update-gmp-to-6.2.1.patch +++ /dev/null @@ -1,54 +0,0 @@ -From f2c8d0323f4d2f1abc4dc0402bd871d9234850f3 Mon Sep 17 00:00:00 2001 -From: Patrick Georgi <pgeorgi@google.com> -Date: Mon, 10 May 2021 23:34:18 +0200 -Subject: [PATCH 09/19] util/crossgcc: Update gmp to 6.2.1 - -Change-Id: I871942f66e8fc496ebe523fdab539ea20950a202 -Signed-off-by: Patrick Georgi <pgeorgi@google.com> -Reviewed-on: https://review.coreboot.org/c/coreboot/+/54047 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> ---- - util/crossgcc/buildgcc | 2 +- - ...-6.2.0_generic-build.patch => gmp-6.2.1_generic-build.patch} | 0 - util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum | 1 - - util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum | 1 + - 4 files changed, 2 insertions(+), 2 deletions(-) - rename util/crossgcc/patches/{gmp-6.2.0_generic-build.patch => gmp-6.2.1_generic-build.patch} (100%) - delete mode 100644 util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum - create mode 100644 util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index c947dd45ab..d8f25dbbb8 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -32,7 +32,7 @@ BOOTSTRAP=0 - THREADS=1 - - # GCC toolchain version numbers --GMP_VERSION=6.2.0 -+GMP_VERSION=6.2.1 - MPFR_VERSION=4.1.0 - MPC_VERSION=1.2.0 - GCC_VERSION=8.3.0 -diff --git a/util/crossgcc/patches/gmp-6.2.0_generic-build.patch b/util/crossgcc/patches/gmp-6.2.1_generic-build.patch -similarity index 100% -rename from util/crossgcc/patches/gmp-6.2.0_generic-build.patch -rename to util/crossgcc/patches/gmp-6.2.1_generic-build.patch -diff --git a/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum -deleted file mode 100644 -index b00b669fe7..0000000000 ---- a/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum -+++ /dev/null -@@ -1 +0,0 @@ --052a5411dc74054240eec58132d2cf41211d0ff6 tarballs/gmp-6.2.0.tar.xz -diff --git a/util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum b/util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum -new file mode 100644 -index 0000000000..3ea4232e59 ---- /dev/null -+++ b/util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum -@@ -0,0 +1 @@ -+0578d48607ec0e272177d175fd1807c30b00fdf2 tarballs/gmp-6.2.1.tar.xz --- -2.25.1 - diff --git a/resources/coreboot/default/patches/0019-Fix-missing-include.patch b/resources/coreboot/default/patches/0010-Fix-missing-include.patch index 372bb372..aaa3805c 100644 --- a/resources/coreboot/default/patches/0019-Fix-missing-include.patch +++ b/resources/coreboot/default/patches/0010-Fix-missing-include.patch @@ -1,7 +1,7 @@ -From 989abca57d4bcc2f7194a9dfb3a7fc67f62fbde3 Mon Sep 17 00:00:00 2001 +From e6960dec197491941254af48b60f1cf1592bcb2b Mon Sep 17 00:00:00 2001 From: Rodrigo <rm@firemail.cc> Date: Mon, 23 Aug 2021 03:51:21 -0300 -Subject: [PATCH 19/19] Fix missing include +Subject: [PATCH 10/11] Fix missing include --- src/cpu/intel/model_1067x/model_1067x_init.c | 1 + @@ -35,7 +35,7 @@ index a0917045dd..7b88f19ee0 100644 #define HIGHEST_CLEVEL 3 static void configure_c_states(void) diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c -index 31399bdbd7..7347400766 100644 +index 36cfd51f01..793474ffa5 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -8,6 +8,7 @@ @@ -47,7 +47,7 @@ index 31399bdbd7..7347400766 100644 #define HIGHEST_CLEVEL 3 static void configure_c_states(void) diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c -index 17a865c9f3..3b8a2f4708 100644 +index 6f2d6ef599..d0031ad741 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -8,6 +8,7 @@ diff --git a/resources/coreboot/default/patches/0010-util-crossgcc-Update-mpc-to-1.2.1.patch b/resources/coreboot/default/patches/0010-util-crossgcc-Update-mpc-to-1.2.1.patch deleted file mode 100644 index 1b8f7168..00000000 --- a/resources/coreboot/default/patches/0010-util-crossgcc-Update-mpc-to-1.2.1.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 7237b72a6693c14ba51c798bc53873a4d8751d52 Mon Sep 17 00:00:00 2001 -From: Patrick Georgi <pgeorgi@google.com> -Date: Mon, 10 May 2021 23:35:51 +0200 -Subject: [PATCH 10/19] util/crossgcc: Update mpc to 1.2.1 - -Change-Id: Ic1422464d0a95c9cba1c417aaa05e4f1fe799d26 -Signed-off-by: Patrick Georgi <pgeorgi@google.com> -Reviewed-on: https://review.coreboot.org/c/coreboot/+/54048 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> ---- - util/crossgcc/buildgcc | 2 +- - util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum | 1 - - util/crossgcc/sum/mpc-1.2.1.tar.gz.cksum | 1 + - 3 files changed, 2 insertions(+), 2 deletions(-) - delete mode 100644 util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum - create mode 100644 util/crossgcc/sum/mpc-1.2.1.tar.gz.cksum - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index d8f25dbbb8..abe602c821 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -34,7 +34,7 @@ THREADS=1 - # GCC toolchain version numbers - GMP_VERSION=6.2.1 - MPFR_VERSION=4.1.0 --MPC_VERSION=1.2.0 -+MPC_VERSION=1.2.1 - GCC_VERSION=8.3.0 - GCC_AUTOCONF_VERSION=2.69 - BINUTILS_VERSION=2.35.1 -diff --git a/util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum b/util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum -deleted file mode 100644 -index ed98cc0298..0000000000 ---- a/util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum -+++ /dev/null -@@ -1 +0,0 @@ --0abdc94acab0c9bfdaa391347cdfd7bbdb1cf017 tarballs/mpc-1.2.0.tar.gz -diff --git a/util/crossgcc/sum/mpc-1.2.1.tar.gz.cksum b/util/crossgcc/sum/mpc-1.2.1.tar.gz.cksum -new file mode 100644 -index 0000000000..84254eb5af ---- /dev/null -+++ b/util/crossgcc/sum/mpc-1.2.1.tar.gz.cksum -@@ -0,0 +1 @@ -+2a4919abf445c6eda4e120cd669b8733ce337227 tarballs/mpc-1.2.1.tar.gz --- -2.25.1 - diff --git a/resources/coreboot/default/patches/0020-lenovo-t400-Enable-all-SATA-ports.patch b/resources/coreboot/default/patches/0011-lenovo-t400-Enable-all-SATA-ports.patch index 5ca27c4d..dec2844e 100644 --- a/resources/coreboot/default/patches/0020-lenovo-t400-Enable-all-SATA-ports.patch +++ b/resources/coreboot/default/patches/0011-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 8027957b185313f2a9cecee21d14ae2c88407f5f Mon Sep 17 00:00:00 2001 +From c4ab3bd4c88d83ca3ca391519cec31fa7b7a6c2a Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 1/1] lenovo/t400: Enable all SATA ports +Subject: [PATCH 11/11] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its @@ -15,7 +15,7 @@ This patch unmasked all SATA ports found within t400s with factory firmware. 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb -index 5886aff48c..84cd4d87b1 100644 +index 670b4883f3..1fc60d9b24 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -59,8 +59,8 @@ chip northbridge/intel/gm45 diff --git a/resources/coreboot/default/patches/0011-tests-Enable-config-override-for-tests.patch b/resources/coreboot/default/patches/0011-tests-Enable-config-override-for-tests.patch deleted file mode 100644 index 00d74e06..00000000 --- a/resources/coreboot/default/patches/0011-tests-Enable-config-override-for-tests.patch +++ /dev/null @@ -1,76 +0,0 @@ -From d654c14aa2f150d7b15abc89a3c267b24ca123a1 Mon Sep 17 00:00:00 2001 -From: Jakub Czapiga <jacz@semihalf.com> -Date: Wed, 28 Apr 2021 16:50:51 +0200 -Subject: [PATCH 11/19] tests: Enable config override for tests - -Some tests require to change kconfig symbols values to cover the code. -This patch enables one to set these vaues using <test-name>-config -variable. - -Example for integer values. -timestamp-test-config += CONFIG_HAVE_MONOTONIC_TIMER=1 - -Example for string values. Notice escaped quotes. -spd_cache-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"SPD_CACHE_FMAP_NAME\" - -Signed-off-by: Jakub Czapiga <jacz@semihalf.com> -Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 -Reviewed-on: https://review.coreboot.org/c/coreboot/+/52937 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> -Reviewed-by: Julius Werner <jwerner@chromium.org> ---- - tests/Makefile.inc | 22 ++++++++++++++++++---- - 1 file changed, 18 insertions(+), 4 deletions(-) - -diff --git a/tests/Makefile.inc b/tests/Makefile.inc -index 44e3c69618..cd25e0f809 100644 ---- a/tests/Makefile.inc -+++ b/tests/Makefile.inc -@@ -11,7 +11,7 @@ CMAKE:= cmake - - TEST_DEFAULT_CONFIG = $(top)/configs/config.emulation_qemu_x86_i440fx - TEST_DOTCONFIG = $(testobj)/.config --TEST_KCONFIG_AUTOHEADER := $(testobj)/config.h -+TEST_KCONFIG_AUTOHEADER := $(testobj)/config.src.h - TEST_KCONFIG_AUTOCONFIG := $(testobj)/auto.conf - TEST_KCONFIG_DEPENDENCIES := $(testobj)/auto.conf.cmd - TEST_KCONFIG_SPLITCONFIG := $(testobj)/config -@@ -52,7 +52,7 @@ TEST_CFLAGS += -fno-pie -fno-pic - TEST_LDFLAGS += -no-pie - - # Extra attributes for unit tests, declared per test --attributes:= srcs cflags mocks stage -+attributes:= srcs cflags config mocks stage - - stages:= decompressor bootblock romstage smm verstage - stages+= ramstage rmodule postcar libagesa -@@ -83,9 +83,23 @@ $(call evaluate_subdirs) - # Create actual targets for unit test binaries - # $1 - test name - define TEST_CC_template --$($(1)-objs): TEST_CFLAGS+= \ -+ -+# Generate custom config.h redefining given symbols -+$(1)-config-file := $(obj)/$(1)/config.h -+$$($(1)-config-file): $(TEST_KCONFIG_AUTOHEADER) -+ mkdir -p $$(dir $$@) -+ printf '// File generated by tests/Makefile.inc\n// Do not change\n' > $$@ -+ printf '#include <%s>\n\n' "$(notdir $(TEST_KCONFIG_AUTOHEADER))" >> $$@ -+ for kv in $$($(1)-config); do \ -+ key="`echo $$$$kv | cut -d '=' -f -1`"; \ -+ value="`echo $$$$kv | cut -d '=' -f 2-`"; \ -+ printf '#undef %s\n' "$$$$key" >> $$@; \ -+ printf '#define %s %s\n\n' "$$$$key" "$$$$value" >> $$@; \ -+ done -+ -+$($(1)-objs): TEST_CFLAGS += -I$$(dir $$($(1)-config-file)) \ - -D__$$(shell echo $$($(1)-stage) | tr '[:lower:]' '[:upper:]')__ --$($(1)-objs): $(obj)/$(1)/%.o: $$$$*.c $(TEST_KCONFIG_AUTOHEADER) -+$($(1)-objs): $(obj)/$(1)/%.o: $$$$*.c $$($(1)-config-file) - mkdir -p $$(dir $$@) - $(HOSTCC) $(HOSTCFLAGS) $$(TEST_CFLAGS) $($(1)-cflags) -MMD \ - -MT $$@ -c $$< -o $$@ --- -2.25.1 - diff --git a/resources/coreboot/default/patches/0012-src-Match-array-format-in-function-declarations-and-.patch b/resources/coreboot/default/patches/0012-src-Match-array-format-in-function-declarations-and-.patch deleted file mode 100644 index 6079a668..00000000 --- a/resources/coreboot/default/patches/0012-src-Match-array-format-in-function-declarations-and-.patch +++ /dev/null @@ -1,193 +0,0 @@ -From f92b7f3c5c9da178e2417333895fe735796e7954 Mon Sep 17 00:00:00 2001 -From: Patrick Georgi <pgeorgi@google.com> -Date: Wed, 12 May 2021 14:52:12 +0200 -Subject: [PATCH 12/19] src: Match array format in function declarations and - definitions - -gcc 11.1 complains when we're passing a type* into a function that was -declared to get a type[], even if the ABI has identical parameter -passing for both. - -To prepare for newer compilers, adapt to this added constraint. - -Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f -Signed-off-by: Patrick Georgi <pgeorgi@google.com> -Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> -Reviewed-by: Felix Singer <felixsinger@posteo.net> -Reviewed-by: Angel Pons <th3fanbus@gmail.com> ---- - src/mainboard/lenovo/t400/romstage.c | 2 +- - src/mainboard/lenovo/x200/romstage.c | 2 +- - src/mainboard/roda/rk9/romstage.c | 2 +- - src/soc/intel/alderlake/espi.c | 2 +- - src/soc/intel/cannonlake/lpc.c | 2 +- - src/soc/intel/elkhartlake/espi.c | 2 +- - src/soc/intel/icelake/espi.c | 2 +- - src/soc/intel/jasperlake/espi.c | 2 +- - src/soc/intel/skylake/lpc.c | 2 +- - src/soc/intel/tigerlake/espi.c | 2 +- - src/soc/intel/xeon_sp/lpc.c | 2 +- - src/vendorcode/mediatek/mt8192/dramc/dramc_top.c | 2 +- - 12 files changed, 12 insertions(+), 12 deletions(-) - -diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c -index b4766ed737..aa3462a901 100644 ---- a/src/mainboard/lenovo/t400/romstage.c -+++ b/src/mainboard/lenovo/t400/romstage.c -@@ -15,7 +15,7 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo) - sysinfo->enable_peg = peg; - } - --void get_mb_spd_addrmap(u8 *spd_addrmap) -+void get_mb_spd_addrmap(u8 spd_addrmap[4]) - { - spd_addrmap[0] = 0x50; - spd_addrmap[2] = 0x51; -diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c -index 46cedfb07f..6764644274 100644 ---- a/src/mainboard/lenovo/x200/romstage.c -+++ b/src/mainboard/lenovo/x200/romstage.c -@@ -3,7 +3,7 @@ - #include <southbridge/intel/common/gpio.h> - #include <northbridge/intel/gm45/gm45.h> - --void get_mb_spd_addrmap(u8 *spd_addrmap) -+void get_mb_spd_addrmap(u8 spd_addrmap[4]) - { - spd_addrmap[0] = 0x50; - spd_addrmap[2] = 0x51; -diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c -index be8ba5dbb3..dabef34707 100644 ---- a/src/mainboard/roda/rk9/romstage.c -+++ b/src/mainboard/roda/rk9/romstage.c -@@ -2,7 +2,7 @@ - - #include <northbridge/intel/gm45/gm45.h> - --void get_mb_spd_addrmap(u8 *spd_addrmap) -+void get_mb_spd_addrmap(u8 spd_addrmap[4]) - { - spd_addrmap[0] = 0x50; - spd_addrmap[2] = 0x52; -diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c -index feec465a92..dd0edcde2c 100644 ---- a/src/soc/intel/alderlake/espi.c -+++ b/src/soc/intel/alderlake/espi.c -@@ -20,7 +20,7 @@ - #include <soc/pcr_ids.h> - #include <soc/soc_chip.h> - --void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) -+void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) - { - const config_t *config = config_of_soc(); - -diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c -index 20704e5bc6..0e63e0dc97 100644 ---- a/src/soc/intel/cannonlake/lpc.c -+++ b/src/soc/intel/cannonlake/lpc.c -@@ -17,7 +17,7 @@ - - #include "chip.h" - --void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) -+void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) - { - const config_t *config = config_of_soc(); - -diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c -index 1737a474ac..46646d8485 100644 ---- a/src/soc/intel/elkhartlake/espi.c -+++ b/src/soc/intel/elkhartlake/espi.c -@@ -16,7 +16,7 @@ - #include <soc/pcr_ids.h> - #include <soc/soc_chip.h> - --void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) -+void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) - { - const config_t *config = config_of_soc(); - -diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c -index 489fe34223..d634cf8943 100644 ---- a/src/soc/intel/icelake/espi.c -+++ b/src/soc/intel/icelake/espi.c -@@ -16,7 +16,7 @@ - #include <soc/pcr_ids.h> - #include <soc/soc_chip.h> - --void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) -+void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) - { - const config_t *config = config_of_soc(); - -diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c -index c3b50de8f0..1d1f94e328 100644 ---- a/src/soc/intel/jasperlake/espi.c -+++ b/src/soc/intel/jasperlake/espi.c -@@ -16,7 +16,7 @@ - #include <soc/pcr_ids.h> - #include <soc/soc_chip.h> - --void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) -+void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) - { - const config_t *config = config_of_soc(); - -diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c -index 5abae765c9..5d38bb8683 100644 ---- a/src/soc/intel/skylake/lpc.c -+++ b/src/soc/intel/skylake/lpc.c -@@ -14,7 +14,7 @@ - - #include "chip.h" - --void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) -+void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) - { - const config_t *config = config_of_soc(); - -diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c -index 8386cd9df1..427867622b 100644 ---- a/src/soc/intel/tigerlake/espi.c -+++ b/src/soc/intel/tigerlake/espi.c -@@ -22,7 +22,7 @@ - #include <soc/pcr_ids.h> - #include <soc/soc_chip.h> - --void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) -+void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) - { - const config_t *config = config_of_soc(); - -diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c -index f0cb6db63d..dad0a4914d 100644 ---- a/src/soc/intel/xeon_sp/lpc.c -+++ b/src/soc/intel/xeon_sp/lpc.c -@@ -8,7 +8,7 @@ - - #include <chip.h> - --void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) -+void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) - { - const config_t *config = config_of_soc(); - -diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c -index 8af6a36851..04fd62a27f 100644 ---- a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c -+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c -@@ -475,7 +475,7 @@ int get_dram_freq_cnt(void) - #if (FOR_DV_SIMULATION_USED==0) - #if !__FLASH_TOOL_DA__ && !__ETT__ - --void get_dram_rank_size(u64 dram_rank_size[DRAMC_MAX_RK]) -+void get_dram_rank_size(u64 dram_rank_size[]) - { - #ifdef COMBO_MCP - int index, rank_nr, i; --- -2.25.1 - diff --git a/resources/coreboot/default/patches/0013-src-security-tpm-Deal-with-zero-length-tlcl-writes.patch b/resources/coreboot/default/patches/0013-src-security-tpm-Deal-with-zero-length-tlcl-writes.patch deleted file mode 100644 index 4f3bff48..00000000 --- a/resources/coreboot/default/patches/0013-src-security-tpm-Deal-with-zero-length-tlcl-writes.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 6c9fe645f8444bd4586e26b545cc9dceb162f03a Mon Sep 17 00:00:00 2001 -From: Patrick Georgi <pgeorgi@google.com> -Date: Wed, 12 May 2021 14:54:49 +0200 -Subject: [PATCH 13/19] src/security/tpm: Deal with zero length tlcl writes - -While memcpy(foo, bar, 0) should be a no-op, that's hard to prove for a -compiler and so gcc 11.1 complains about the use of an uninitialized -"bar" even though it's harmless in this case. - -Change-Id: Idbffa508c2cd68790efbc0b4ab97ae1b4d85ad51 -Signed-off-by: Patrick Georgi <pgeorgi@google.com> -Reviewed-on: https://review.coreboot.org/c/coreboot/+/54095 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> -Reviewed-by: Angel Pons <th3fanbus@gmail.com> ---- - src/security/tpm/tss/tcg-1.2/tss.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c -index 8b7778ddb2..413b68193f 100644 ---- a/src/security/tpm/tss/tcg-1.2/tss.c -+++ b/src/security/tpm/tss/tcg-1.2/tss.c -@@ -215,7 +215,8 @@ uint32_t tlcl_write(uint32_t index, const void *data, uint32_t length) - - to_tpm_uint32(cmd.buffer + tpm_nv_write_cmd.index, index); - to_tpm_uint32(cmd.buffer + tpm_nv_write_cmd.length, length); -- memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length); -+ if (length > 0) -+ memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length); - - return tlcl_send_receive(cmd.buffer, response, sizeof(response)); - } --- -2.25.1 - |