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-rw-r--r--resources/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch4
-rw-r--r--resources/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch6
-rw-r--r--resources/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch4
-rw-r--r--resources/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch4
-rw-r--r--resources/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch (renamed from resources/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch)14
-rw-r--r--resources/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch (renamed from resources/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-352MiB-by-default.patch)11
-rw-r--r--resources/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch (renamed from resources/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch)9
-rw-r--r--resources/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch (renamed from resources/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch)9
-rw-r--r--resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch6
-rw-r--r--resources/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch4
-rw-r--r--resources/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch4
-rw-r--r--resources/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch44
-rw-r--r--resources/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch (renamed from resources/coreboot/default/patches/0014-lenovo-x230-introduce-FHD-variant.patch)10
-rw-r--r--resources/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch (renamed from resources/coreboot/default/patches/0015-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch)8
-rw-r--r--resources/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch205
-rw-r--r--resources/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch (renamed from resources/coreboot/default/patches/0019-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch)6
-rw-r--r--resources/coreboot/default/patches/0016-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch205
-rw-r--r--resources/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch (renamed from resources/coreboot/default/patches/0020-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch)6
-rw-r--r--resources/coreboot/default/patches/0017-util-ifdtool-fix-bad-patch.patch65
-rw-r--r--resources/coreboot/default/patches/0018-ich9m-boards-set-256MB-VRAM-instead.patch56
-rw-r--r--resources/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch (renamed from resources/coreboot/default/patches/0021-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch)8
-rw-r--r--resources/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch (renamed from resources/coreboot/default/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch)7
-rw-r--r--resources/coreboot/default/patches/0023-mb-dell-e6400-acpi-Route-Ricoh-R5C847-PCI-IRQ-lines-.patch125
-rw-r--r--resources/coreboot/default/patches/0024-Add-HP-8300-USDT-port.patch865
24 files changed, 297 insertions, 1388 deletions
diff --git a/resources/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/resources/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
index a06a5058..2e7dfbc0 100644
--- a/resources/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
+++ b/resources/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
@@ -1,7 +1,7 @@
-From 4c5971a6fcf7e948f7df4d0ce2ab0751060cb2ca Mon Sep 17 00:00:00 2001
+From 21270ad036cdd1ee708a04c41ba6c4f279e4e6c0 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@retroboot.org>
Date: Fri, 19 Mar 2021 05:54:58 +0000
-Subject: [PATCH 01/18] apple/macbook21: Set default VRAM to 64MiB instead of
+Subject: [PATCH 01/19] apple/macbook21: Set default VRAM to 64MiB instead of
8MiB
---
diff --git a/resources/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch b/resources/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
index 57c32ec7..deb6b1fb 100644
--- a/resources/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
+++ b/resources/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
@@ -1,7 +1,7 @@
-From ff523fd40649b72512b0f1253701509d83ca4a8d Mon Sep 17 00:00:00 2001
+From 6fa4c1488911b98e29d3e2858be68b9b72182573 Mon Sep 17 00:00:00 2001
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 02/18] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 02/19] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +
@@ -46,7 +46,7 @@ index 13d06f0839..88b8669c61 100644
int get_cst_entries(const acpi_cstate_t **entries)
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
-index dd701da7ed..5587c48d1f 100644
+index fd86e939b9..263fbabcd1 100644
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -100,7 +100,13 @@ chip northbridge/intel/i945
diff --git a/resources/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/resources/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
index d8ca5b1f..65606127 100644
--- a/resources/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
+++ b/resources/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
@@ -1,7 +1,7 @@
-From fe79712702002bf2044227d6c3cef7ae022e3539 Mon Sep 17 00:00:00 2001
+From 79d9155c71f6014ff6adb454fe65466642bc2413 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Sun, 3 Jan 2021 03:34:01 +0000
-Subject: [PATCH 03/18] lenovo/x60: 64MiB Video RAM changed to default
+Subject: [PATCH 03/19] lenovo/x60: 64MiB Video RAM changed to default
(previously it was 8MiB)
---
diff --git a/resources/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/resources/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
index 630e68a6..ca5d0a8f 100644
--- a/resources/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
+++ b/resources/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
@@ -1,7 +1,7 @@
-From 79440902866bdafeec651476a5a0e51d42b43b21 Mon Sep 17 00:00:00 2001
+From 51a20e0db3fb9bf26ce138c9a17abe963bb8b289 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Mon, 22 Feb 2021 22:16:59 +0000
-Subject: [PATCH 04/18] lenovo/t60: make 64MiB VRAM the default in cmos.default
+Subject: [PATCH 04/19] lenovo/t60: make 64MiB VRAM the default in cmos.default
---
src/mainboard/lenovo/t60/cmos.default | 2 +-
diff --git a/resources/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch b/resources/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch
index 63b515c0..a108a75c 100644
--- a/resources/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch
+++ b/resources/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch
@@ -1,19 +1,15 @@
-From 73ca2562e77c971c2e581a414dc57b4b9aa544d7 Mon Sep 17 00:00:00 2001
+From 400e23c5149ab53300f57d8334ab25645d27b0c8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:10:33 +0100
-Subject: [PATCH 05/18] lenovo/t400: set VRAM to 352MiB VRAM by default
+Subject: [PATCH 05/19] lenovo/t400: set VRAM to 256MiB VRAM by default
-In the past, this caused stability issues so we set it to 256MiB. Nowadays,
-coreboot has fixed the issue preventing this. See:
-https://review.coreboot.org/c/coreboot/+/16831
-
-So, set the VRAM to 352MiB
+Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/t400/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
-index a326e315b1..e74d15d030 100644
+index a326e315b1..b907a3e2df 100644
--- a/src/mainboard/lenovo/t400/cmos.default
+++ b/src/mainboard/lenovo/t400/cmos.default
@@ -13,4 +13,4 @@ power_management_beeps=Enable
@@ -21,7 +17,7 @@ index a326e315b1..e74d15d030 100644
sata_mode=AHCI
hybrid_graphics_mode=Integrated Only
-gfx_uma_size=32M
-+gfx_uma_size=352M
++gfx_uma_size=256M
--
2.39.2
diff --git a/resources/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-352MiB-by-default.patch b/resources/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch
index d8673368..3ba4b07a 100644
--- a/resources/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-352MiB-by-default.patch
+++ b/resources/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch
@@ -1,16 +1,15 @@
-From badcbb2f07ac0e3d8b53a23e324f709bf93c3dd5 Mon Sep 17 00:00:00 2001
+From 29e6f78973928ad9ae86b26d5cf308a2680c88bf Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:11:59 +0100
-Subject: [PATCH 06/18] lenovo/x200: set VRAM to 352MiB by default
+Subject: [PATCH 06/19] lenovo/x200: set VRAM to 256MiB by default
-This fix makes it possible:
-https://review.coreboot.org/c/coreboot/+/16831
+Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/x200/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
-index bb4323836e..33a6a69f59 100644
+index bb4323836e..458b3f19c5 100644
--- a/src/mainboard/lenovo/x200/cmos.default
+++ b/src/mainboard/lenovo/x200/cmos.default
@@ -12,4 +12,4 @@ sticky_fn=Disable
@@ -18,7 +17,7 @@ index bb4323836e..33a6a69f59 100644
low_battery_beep=Enable
sata_mode=AHCI
-gfx_uma_size=32M
-+gfx_uma_size=352M
++gfx_uma_size=256M
--
2.39.2
diff --git a/resources/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch b/resources/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch
index 41a00c55..5bbbccb4 100644
--- a/resources/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch
+++ b/resources/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch
@@ -1,14 +1,15 @@
-From 59e14decddd3a3d0eb9905196df045e34b7ce035 Mon Sep 17 00:00:00 2001
+From 9339fbdd36ceed6b1606b7a6ff07404f4f2a2d6d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:18:26 +0100
-Subject: [PATCH 07/18] gigabyte/ga-g41m-es2l: set VRAM to 352MiB by default
+Subject: [PATCH 07/19] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
+Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
-index 8372032119..3a9a8e2d72 100644
+index 8372032119..bedad54d2a 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
@@ -16,7 +17,7 @@ index 8372032119..3a9a8e2d72 100644
power_on_after_fail=Enable
nmi=Enable
-gfx_uma_size=64M
-+gfx_uma_size=352M
++gfx_uma_size=256M
--
2.39.2
diff --git a/resources/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch b/resources/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch
index d75571fa..ab5c2279 100644
--- a/resources/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch
+++ b/resources/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch
@@ -1,14 +1,15 @@
-From 794e082e64558678fe245c86a2c81b4edc582795 Mon Sep 17 00:00:00 2001
+From 54197e66c6ecf33743489be9ab0352cfc4b1ffe2 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:21:39 +0100
-Subject: [PATCH 08/18] acer/g43t-am3: set VRAM to 352MiB by default
+Subject: [PATCH 08/19] acer/g43t-am3: set VRAM to 256MiB by default
+Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/acer/g43t-am3/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
-index 706f5dd551..98899e8bf5 100644
+index 706f5dd551..e8b45ea22c 100644
--- a/src/mainboard/acer/g43t-am3/cmos.default
+++ b/src/mainboard/acer/g43t-am3/cmos.default
@@ -3,4 +3,4 @@ debug_level=Debug
@@ -16,7 +17,7 @@ index 706f5dd551..98899e8bf5 100644
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=64M
-+gfx_uma_size=352M
++gfx_uma_size=256M
--
2.39.2
diff --git a/resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch b/resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch
index f975e604..1aa74086 100644
--- a/resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch
+++ b/resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch
@@ -1,7 +1,7 @@
-From 62121b837771b0b05f6490943ff9f1ccaba45bdb Mon Sep 17 00:00:00 2001
+From bc4ef158c4c6836351a395e8f0ff24f7c6d1f2c6 Mon Sep 17 00:00:00 2001
From: persmule <persmule@gmail.com>
Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 09/18] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 09/19] lenovo/t400: Enable all SATA ports
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -15,7 +15,7 @@ This patch unmasked all SATA ports found within t400s with factory firmware.
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
-index 1df350ab67..21c8e2c9a1 100644
+index 259c3e1b21..3d007533a4 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
diff --git a/resources/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch b/resources/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch
index bba2f1b8..c16884c5 100644
--- a/resources/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch
+++ b/resources/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch
@@ -1,7 +1,7 @@
-From 13d95d2bf44e1c950e317e7c6fbbe5d96174c48a Mon Sep 17 00:00:00 2001
+From 5987d9e821931ce097e265c13ca80a2090d3d821 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 20 Dec 2021 01:29:31 +0000
-Subject: [PATCH 10/18] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
+Subject: [PATCH 10/19] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
default
---
diff --git a/resources/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/resources/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
index 20ca0461..3a96bc3a 100644
--- a/resources/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
+++ b/resources/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
@@ -1,7 +1,7 @@
-From fa8113f64fe320e0e75f3e53ccfa9037d3bdd074 Mon Sep 17 00:00:00 2001
+From e5a6fac5b3c75c5aa4ae5106ec336a18083fbab0 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 11/18] lenovo/x230: set me_state=Disabled in cmos.default
+Subject: [PATCH 11/19] lenovo/x230: set me_state=Disabled in cmos.default
I only recently found out about this. It's possible to use me_cleaner to
do the same thing, but some people might just flash coreboot and not do
diff --git a/resources/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch b/resources/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch
index 3613f685..9efc5198 100644
--- a/resources/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch
+++ b/resources/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch
@@ -1,19 +1,23 @@
-From 4bb3d60a1a1dfb2dac6320cef491a99b728ed25a Mon Sep 17 00:00:00 2001
+From 03610ab506bdaca92c1623abd18b4812f92273ed Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 12/18] set me_state=Disabled on all cmos.default files!
+Subject: [PATCH 12/19] set me_state=Disabled on all cmos.default files!
yeah. why the hell isn't this the default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/mainboard/lenovo/l520/cmos.default | 2 +-
- src/mainboard/lenovo/t420/cmos.default | 2 +-
- src/mainboard/lenovo/t420s/cmos.default | 2 +-
- src/mainboard/lenovo/t430/cmos.default | 2 +-
- src/mainboard/lenovo/t430s/cmos.default | 2 +-
- src/mainboard/lenovo/t520/cmos.default | 2 +-
- src/mainboard/lenovo/t530/cmos.default | 2 +-
- src/mainboard/lenovo/x220/cmos.default | 2 +-
- 8 files changed, 8 insertions(+), 8 deletions(-)
+ src/mainboard/lenovo/l520/cmos.default | 2 +-
+ src/mainboard/lenovo/t420/cmos.default | 2 +-
+ src/mainboard/lenovo/t420s/cmos.default | 2 +-
+ src/mainboard/lenovo/t430/cmos.default | 2 +-
+ src/mainboard/lenovo/t430s/cmos.default | 2 +-
+ src/mainboard/lenovo/t520/cmos.default | 2 +-
+ src/mainboard/lenovo/t530/cmos.default | 2 +-
+ src/mainboard/lenovo/x220/cmos.default | 2 +-
+ src/mainboard/protectli/vault_cml/cmos.default | 2 +-
+ src/mainboard/system76/tgl-u/cmos.default | 2 +-
+ 10 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
index 681c40e78b..57cdcf9162 100644
@@ -95,6 +99,24 @@ index 6d1d57a795..52f303dfdb 100644
trackpoint=Enable
-me_state=Normal
+me_state=Disabled
+diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
+index 62715bc6ba..129b5fd121 100644
+--- a/src/mainboard/protectli/vault_cml/cmos.default
++++ b/src/mainboard/protectli/vault_cml/cmos.default
+@@ -1,3 +1,3 @@
+ boot_option=Fallback
+ debug_level=Debug
+-me_state=Enable
++me_state=Disabled
+diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
+index 62715bc6ba..129b5fd121 100644
+--- a/src/mainboard/system76/tgl-u/cmos.default
++++ b/src/mainboard/system76/tgl-u/cmos.default
+@@ -1,3 +1,3 @@
+ boot_option=Fallback
+ debug_level=Debug
+-me_state=Enable
++me_state=Disabled
--
2.39.2
diff --git a/resources/coreboot/default/patches/0014-lenovo-x230-introduce-FHD-variant.patch b/resources/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch
index 9c2d49af..9bc43e78 100644
--- a/resources/coreboot/default/patches/0014-lenovo-x230-introduce-FHD-variant.patch
+++ b/resources/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch
@@ -1,7 +1,7 @@
-From f60a7e12526ca254b1d98830ad1e31296984e815 Mon Sep 17 00:00:00 2001
+From f4e5f11762e4c54829e1d6515d7fd369d86ac9d7 Mon Sep 17 00:00:00 2001
From: Alexander Couzens <lynxis@fe80.eu>
Date: Sat, 19 Mar 2022 13:42:33 +0000
-Subject: [PATCH 14/18] lenovo/x230: introduce FHD variant
+Subject: [PATCH 13/19] lenovo/x230: introduce FHD variant
There is a modification for the x230 which uses the 2nd DP from the dock
as the integrated panel's connection, which allows using a custom eDP
@@ -44,7 +44,7 @@ Signed-off-by: Felix Singer <felixsinger@posteo.net>
create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
-index f9667267d5..4d8325ea43 100644
+index 279095629b..acfd0ed561 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -1,4 +1,4 @@
@@ -71,7 +71,7 @@ index f9667267d5..4d8325ea43 100644
select MAINBOARD_HAS_LIBGFXINIT
select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
select INTEL_GMA_HAVE_VBT
-@@ -51,17 +51,20 @@ config MAINBOARD_DIR
+@@ -47,17 +47,20 @@ config MAINBOARD_DIR
default "lenovo/x230"
config VARIANT_DIR
@@ -94,7 +94,7 @@ index f9667267d5..4d8325ea43 100644
config USBDEBUG_HCD_INDEX
int
default 2
-@@ -83,4 +86,4 @@ config PS2M_EISAID
+@@ -79,4 +82,4 @@ config PS2M_EISAID
config THINKPADEC_HKEY_EISAID
default "LEN0068"
diff --git a/resources/coreboot/default/patches/0015-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch b/resources/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch
index 440b6543..d391d0c3 100644
--- a/resources/coreboot/default/patches/0015-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch
+++ b/resources/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch
@@ -1,17 +1,17 @@
-From b8bb450bef9f9a486917115bfe78519838558300 Mon Sep 17 00:00:00 2001
+From 982734642e0c8a960b99180371a5a12c3851b6e9 Mon Sep 17 00:00:00 2001
From: Alexei Sorokin <sor.alexei@meowr.ru>
Date: Sun, 27 Nov 2022 18:36:26 +0300
-Subject: [PATCH 15/18] lenovo/x230: fix the data.vbt path for the EDP variant
+Subject: [PATCH 14/19] lenovo/x230: fix the data.vbt path for the EDP variant
---
src/mainboard/lenovo/x230/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
-index 4d8325ea43..409892f3ab 100644
+index acfd0ed561..34108c3c04 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
-@@ -63,7 +63,7 @@ config OVERRIDE_DEVICETREE
+@@ -59,7 +59,7 @@ config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config INTEL_GMA_VBT_FILE
diff --git a/resources/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/resources/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
new file mode 100644
index 00000000..d8a701d9
--- /dev/null
+++ b/resources/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
@@ -0,0 +1,205 @@
+From 35425512e05c989d2d6789551cc448719ab1ca38 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 19 Feb 2023 18:21:43 +0000
+Subject: [PATCH 15/19] util/ifdtool: add --nuke flag (all 0xFF on region)
+
+When this option is used, the region's contents are overwritten
+with all ones (0xFF).
+
+Example:
+
+./ifdtool --nuke gbe coreboot.rom
+./ifdtool --nuke bios coreboot.com
+./ifdtool --nuke me coreboot.com
+
+Rebased since the last revision update in lbmk.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
+ 1 file changed, 83 insertions(+), 31 deletions(-)
+
+diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
+index ddbc0fb91b..7af9235ae3 100644
+--- a/util/ifdtool/ifdtool.c
++++ b/util/ifdtool/ifdtool.c
+@@ -1847,6 +1847,7 @@ static void print_usage(const char *name)
+ " wbg - Wellsburg\n"
+ " -S | --setpchstrap Write a PCH strap\n"
+ " -V | --newvalue The new value to write into PCH strap specified by -S\n"
++ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
+ " -v | --version: print the version\n"
+ " -h | --help: print this help\n\n"
+ "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
+@@ -1854,6 +1855,60 @@ static void print_usage(const char *name)
+ "\n");
+ }
+
++static int
++get_region_type_string(const char *region_type_string)
++{
++ if (!strcasecmp("Descriptor", region_type_string))
++ return 0;
++ else if (!strcasecmp("BIOS", region_type_string))
++ return 1;
++ else if (!strcasecmp("ME", region_type_string))
++ return 2;
++ else if (!strcasecmp("GbE", region_type_string))
++ return 3;
++ else if (!strcasecmp("Platform Data", region_type_string))
++ return 4;
++ else if (!strcasecmp("Device Exp1", region_type_string))
++ return 5;
++ else if (!strcasecmp("Secondary BIOS", region_type_string))
++ return 6;
++ else if (!strcasecmp("Reserved", region_type_string))
++ return 7;
++ else if (!strcasecmp("EC", region_type_string))
++ return 8;
++ else if (!strcasecmp("Device Exp2", region_type_string))
++ return 9;
++ else if (!strcasecmp("IE", region_type_string))
++ return 10;
++ else if (!strcasecmp("10GbE_0", region_type_string))
++ return 11;
++ else if (!strcasecmp("10GbE_1", region_type_string))
++ return 12;
++ else if (!strcasecmp("PTT", region_type_string))
++ return 15;
++ return -1;
++}
++
++static void
++nuke(const char *filename, char *image, int size, int region_type)
++{
++ int i;
++ struct region region;
++ const struct frba *frba = find_frba(image, size);
++ if (!frba)
++ exit(EXIT_FAILURE);
++
++ region = get_region(frba, region_type);
++ if (region.size > 0) {
++ for (i = region.base; i <= region.limit; i++) {
++ if ((i + 1) > (size))
++ break;
++ image[i] = 0xFF;
++ }
++ write_image(filename, image, size);
++ }
++}
++
+ int main(int argc, char *argv[])
+ {
+ int opt, option_index = 0;
+@@ -1861,6 +1916,7 @@ int main(int argc, char *argv[])
+ int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
+ int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
+ int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
++ int mode_nuke = 0;
+ char *region_type_string = NULL, *region_fname = NULL;
+ const char *layout_fname = NULL;
+ char *new_filename = NULL;
+@@ -1892,6 +1948,7 @@ int main(int argc, char *argv[])
+ {"validate", 0, NULL, 't'},
+ {"setpchstrap", 1, NULL, 'S'},
+ {"newvalue", 1, NULL, 'V'},
++ {"nuke", 1, NULL, 'N'},
+ {0, 0, 0, 0}
+ };
+
+@@ -1941,35 +1998,8 @@ int main(int argc, char *argv[])
+ region_fname++;
+ // Descriptor, BIOS, ME, GbE, Platform
+ // valid type?
+- if (!strcasecmp("Descriptor", region_type_string))
+- region_type = 0;
+- else if (!strcasecmp("BIOS", region_type_string))
+- region_type = 1;
+- else if (!strcasecmp("ME", region_type_string))
+- region_type = 2;
+- else if (!strcasecmp("GbE", region_type_string))
+- region_type = 3;
+- else if (!strcasecmp("Platform Data", region_type_string))
+- region_type = 4;
+- else if (!strcasecmp("Device Exp1", region_type_string))
+- region_type = 5;
+- else if (!strcasecmp("Secondary BIOS", region_type_string))
+- region_type = 6;
+- else if (!strcasecmp("Reserved", region_type_string))
+- region_type = 7;
+- else if (!strcasecmp("EC", region_type_string))
+- region_type = 8;
+- else if (!strcasecmp("Device Exp2", region_type_string))
+- region_type = 9;
+- else if (!strcasecmp("IE", region_type_string))
+- region_type = 10;
+- else if (!strcasecmp("10GbE_0", region_type_string))
+- region_type = 11;
+- else if (!strcasecmp("10GbE_1", region_type_string))
+- region_type = 12;
+- else if (!strcasecmp("PTT", region_type_string))
+- region_type = 15;
+- if (region_type == -1) {
++ if ((region_type =
++ get_region_type_string(region_type_string)) == -1) {
+ fprintf(stderr, "No such region type: '%s'\n\n",
+ region_type_string);
+ fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+@@ -2135,6 +2165,22 @@ int main(int argc, char *argv[])
+ case 't':
+ mode_validate = 1;
+ break;
++ case 'N':
++ region_type_string = strdup(optarg);
++ if (!region_type_string) {
++ fprintf(stderr, "No region specified\n");
++ print_usage(argv[0]);
++ exit(EXIT_FAILURE);
++ }
++ if ((region_type =
++ get_region_type_string(region_type_string)) == -1) {
++ fprintf(stderr, "No such region type: '%s'\n\n",
++ region_type_string);
++ print_usage(argv[0]);
++ exit(EXIT_FAILURE);
++ }
++ mode_nuke = 1;
++ break;
+ case 'v':
+ print_version();
+ exit(EXIT_SUCCESS);
+@@ -2150,7 +2196,8 @@ int main(int argc, char *argv[])
+
+ if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
+- mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) {
++ mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
++ mode_nuke) > 1) {
+ fprintf(stderr, "You may not specify more than one mode.\n\n");
+ fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ exit(EXIT_FAILURE);
+@@ -2158,7 +2205,8 @@ int main(int argc, char *argv[])
+
+ if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
+- mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
++ mode_locked + mode_unlocked + mode_density + mode_altmedisable +
++ mode_validate + mode_nuke) == 0) {
+ fprintf(stderr, "You need to specify a mode.\n\n");
+ fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ exit(EXIT_FAILURE);
+@@ -2262,6 +2310,10 @@ int main(int argc, char *argv[])
+ write_image(new_filename, image, size);
+ }
+
++ if (mode_nuke) {
++ nuke(new_filename, image, size, region_type);
++ }
++
+ if (mode_altmedisable) {
+ struct fpsba *fpsba = find_fpsba(image, size);
+ struct fmsba *fmsba = find_fmsba(image, size);
+--
+2.39.2
+
diff --git a/resources/coreboot/default/patches/0019-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/resources/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
index 3b1bd40d..df43eeb3 100644
--- a/resources/coreboot/default/patches/0019-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
+++ b/resources/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
@@ -1,7 +1,7 @@
-From 3cf315fd59f1388d60cce9290eb52bccb7b29625 Mon Sep 17 00:00:00 2001
+From 929974434bbd627ab7add5ef4ec4eb62e5412f57 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
-Subject: [PATCH 1/2] fix speedstep on x200/t400: Revert
+Subject: [PATCH 16/19] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
@@ -43,5 +43,5 @@ index 315e7c36fc..1423fd72bc 100644
#define PIC_SENS_CFG 0x1aa
--
-2.40.0
+2.39.2
diff --git a/resources/coreboot/default/patches/0016-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/resources/coreboot/default/patches/0016-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
deleted file mode 100644
index d4eb93f5..00000000
--- a/resources/coreboot/default/patches/0016-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
+++ /dev/null
@@ -1,205 +0,0 @@
-From 32a961895ed41cd2bb1f9ae00ab0200c4bfb0bf3 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 16/18] util/ifdtool: add --nuke flag (all 0xFF on region)
-
-When this option is used, the region's contents are overwritten
-with all ones (0xFF).
-
-Example:
-
-./ifdtool --nuke gbe coreboot.rom
-./ifdtool --nuke bios coreboot.com
-./ifdtool --nuke me coreboot.com
-
-Rebased since the last revision update in lbmk.
----
- util/ifdtool/ifdtool.c | 117 ++++++++++++++++++++++++++++++-----------
- 1 file changed, 85 insertions(+), 32 deletions(-)
-
-diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index 98afa4bbcf..5509721018 100644
---- a/util/ifdtool/ifdtool.c
-+++ b/util/ifdtool/ifdtool.c
-@@ -1771,6 +1771,7 @@ static void print_usage(const char *name)
- " wbg - Wellsburg\n"
- " -S | --setpchstrap Write a PCH strap\n"
- " -V | --newvalue The new value to write into PCH strap specified by -S\n"
-+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
- " -v | --version: print the version\n"
- " -h | --help: print this help\n\n"
- "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
-@@ -1778,13 +1779,70 @@ static void print_usage(const char *name)
- "\n");
- }
-
-+static int
-+get_region_type_string(const char *region_type_string)
-+{
-+ if (region_type_string == NULL)
-+ return -1;
-+ else if (!strcasecmp("Descriptor", region_type_string))
-+ region_type = 0;
-+ else if (!strcasecmp("BIOS", region_type_string))
-+ region_type = 1;
-+ else if (!strcasecmp("ME", region_type_string))
-+ region_type = 2;
-+ else if (!strcasecmp("GbE", region_type_string))
-+ region_type = 3;
-+ else if (!strcasecmp("Platform Data", region_type_string))
-+ region_type = 4;
-+ else if (!strcasecmp("Device Exp1", region_type_string))
-+ region_type = 5;
-+ else if (!strcasecmp("Secondary BIOS", region_type_string))
-+ region_type = 6;
-+ else if (!strcasecmp("Reserved", region_type_string))
-+ region_type = 7;
-+ else if (!strcasecmp("EC", region_type_string))
-+ region_type = 8;
-+ else if (!strcasecmp("Device Exp2", region_type_string))
-+ region_type = 9;
-+ else if (!strcasecmp("IE", region_type_string))
-+ region_type = 10;
-+ else if (!strcasecmp("10GbE_0", region_type_string))
-+ region_type = 11;
-+ else if (!strcasecmp("10GbE_1", region_type_string))
-+ region_type = 12;
-+ else if (!strcasecmp("PTT", region_type_string))
-+ region_type = 15;
-+ else
-+ return -1;
-+}
-+
-+static void
-+nuke(const char *filename, char *image, int size, int region_type)
-+{
-+ int i;
-+ region_t region;
-+ const frba_t *frba = find_frba(image, size);
-+ if (!frba)
-+ exit(EXIT_FAILURE);
-+
-+ region = get_region(frba, region_type);
-+ if (region.size > 0) {
-+ for (i = region.base; i <= region.limit; i++) {
-+ if ((i + 1) > (size))
-+ break;
-+ image[i] = 0xFF;
-+ }
-+ write_image(filename, image, size);
-+ }
-+}
-+
- int main(int argc, char *argv[])
- {
- int opt, option_index = 0;
- int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0;
- int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
- int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
-- int mode_read = 0, mode_altmedisable = 0, altmedisable = 0;
-+ int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_nuke = 0;
- char *region_type_string = NULL, *region_fname = NULL;
- const char *layout_fname = NULL;
- char *new_filename = NULL;
-@@ -1815,6 +1873,7 @@ int main(int argc, char *argv[])
- {"validate", 0, NULL, 't'},
- {"setpchstrap", 1, NULL, 'S'},
- {"newvalue", 1, NULL, 'V'},
-+ {"nuke", 1, NULL, 'N'},
- {0, 0, 0, 0}
- };
-
-@@ -1855,35 +1914,8 @@ int main(int argc, char *argv[])
- region_fname++;
- // Descriptor, BIOS, ME, GbE, Platform
- // valid type?
-- if (!strcasecmp("Descriptor", region_type_string))
-- region_type = 0;
-- else if (!strcasecmp("BIOS", region_type_string))
-- region_type = 1;
-- else if (!strcasecmp("ME", region_type_string))
-- region_type = 2;
-- else if (!strcasecmp("GbE", region_type_string))
-- region_type = 3;
-- else if (!strcasecmp("Platform Data", region_type_string))
-- region_type = 4;
-- else if (!strcasecmp("Device Exp1", region_type_string))
-- region_type = 5;
-- else if (!strcasecmp("Secondary BIOS", region_type_string))
-- region_type = 6;
-- else if (!strcasecmp("Reserved", region_type_string))
-- region_type = 7;
-- else if (!strcasecmp("EC", region_type_string))
-- region_type = 8;
-- else if (!strcasecmp("Device Exp2", region_type_string))
-- region_type = 9;
-- else if (!strcasecmp("IE", region_type_string))
-- region_type = 10;
-- else if (!strcasecmp("10GbE_0", region_type_string))
-- region_type = 11;
-- else if (!strcasecmp("10GbE_1", region_type_string))
-- region_type = 12;
-- else if (!strcasecmp("PTT", region_type_string))
-- region_type = 15;
-- if (region_type == -1) {
-+ if ((region_type =
-+ get_region_type_string(region_type_string)) == -1) {
- fprintf(stderr, "No such region type: '%s'\n\n",
- region_type_string);
- print_usage(argv[0]);
-@@ -2050,6 +2082,22 @@ int main(int argc, char *argv[])
- case 't':
- mode_validate = 1;
- break;
-+ case 'N':
-+ region_type_string = strdup(optarg);
-+ if (!region_type_string) {
-+ fprintf(stderr, "No region specified\n");
-+ print_usage(argv[0]);
-+ exit(EXIT_FAILURE);
-+ }
-+ if ((region_type =
-+ get_region_type_string(region_type_string)) == -1) {
-+ fprintf(stderr, "No such region type: '%s'\n\n",
-+ region_type_string);
-+ print_usage(argv[0]);
-+ exit(EXIT_FAILURE);
-+ }
-+ mode_nuke = 1;
-+ break;
- case 'v':
- print_version();
- exit(EXIT_SUCCESS);
-@@ -2065,7 +2113,7 @@ int main(int argc, char *argv[])
-
- if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_setstrap +
- mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked |
-- mode_locked) + mode_altmedisable + mode_validate) > 1) {
-+ mode_locked) + mode_altmedisable + mode_validate + mode_nuke) > 1) {
- fprintf(stderr, "You may not specify more than one mode.\n\n");
- print_usage(argv[0]);
- exit(EXIT_FAILURE);
-@@ -2073,7 +2121,8 @@ int main(int argc, char *argv[])
-
- if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_setstrap +
- mode_newlayout + mode_spifreq + mode_em100 + mode_locked +
-- mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
-+ mode_unlocked + mode_density + mode_altmedisable + mode_validate +
-+ mode_nuke) == 0) {
- fprintf(stderr, "You need to specify a mode.\n\n");
- print_usage(argv[0]);
- exit(EXIT_FAILURE);
-@@ -2171,6 +2220,10 @@ int main(int argc, char *argv[])
- write_image(new_filename, image, size);
- }
-
-+ if (mode_nuke) {
-+ nuke(new_filename, image, size, region_type);
-+ }
-+
- if (mode_altmedisable) {
- fpsba_t *fpsba = find_fpsba(image, size);
- fmsba_t *fmsba = find_fmsba(image, size);
---
-2.39.2
-
diff --git a/resources/coreboot/default/patches/0020-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/resources/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
index d29b83dd..750628cf 100644
--- a/resources/coreboot/default/patches/0020-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
+++ b/resources/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
@@ -1,7 +1,7 @@
-From 651292a204b00d7a39d8722f9d26fd9d7178fba2 Mon Sep 17 00:00:00 2001
+From f5859da443fc1ff2450051d1d88bee56346fe63b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
-Subject: [PATCH 1/1] GM45-type CPUs: don't enable alternative SMRR
+Subject: [PATCH 17/19] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
@@ -169,5 +169,5 @@ index 535fb8fae7..f7b05facd2 100644
configure_c_states();
--
-2.40.0
+2.39.2
diff --git a/resources/coreboot/default/patches/0017-util-ifdtool-fix-bad-patch.patch b/resources/coreboot/default/patches/0017-util-ifdtool-fix-bad-patch.patch
deleted file mode 100644
index 223a69d8..00000000
--- a/resources/coreboot/default/patches/0017-util-ifdtool-fix-bad-patch.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 05b8acae9a88b8dd13dd96facca30e4662399053 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 19 Feb 2023 23:20:10 +0000
-Subject: [PATCH 17/18] util/ifdtool: fix bad patch
-
-i messed up the "rebase" a few lbmk commits ago
----
- util/ifdtool/ifdtool.c | 28 ++++++++++++++--------------
- 1 file changed, 14 insertions(+), 14 deletions(-)
-
-diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index 5509721018..89feb99536 100644
---- a/util/ifdtool/ifdtool.c
-+++ b/util/ifdtool/ifdtool.c
-@@ -1785,33 +1785,33 @@ get_region_type_string(const char *region_type_string)
- if (region_type_string == NULL)
- return -1;
- else if (!strcasecmp("Descriptor", region_type_string))
-- region_type = 0;
-+ return 0;
- else if (!strcasecmp("BIOS", region_type_string))
-- region_type = 1;
-+ return 1;
- else if (!strcasecmp("ME", region_type_string))
-- region_type = 2;
-+ return 2;
- else if (!strcasecmp("GbE", region_type_string))
-- region_type = 3;
-+ return 3;
- else if (!strcasecmp("Platform Data", region_type_string))
-- region_type = 4;
-+ return 4;
- else if (!strcasecmp("Device Exp1", region_type_string))
-- region_type = 5;
-+ return 5;
- else if (!strcasecmp("Secondary BIOS", region_type_string))
-- region_type = 6;
-+ return 6;
- else if (!strcasecmp("Reserved", region_type_string))
-- region_type = 7;
-+ return 7;
- else if (!strcasecmp("EC", region_type_string))
-- region_type = 8;
-+ return 8;
- else if (!strcasecmp("Device Exp2", region_type_string))
-- region_type = 9;
-+ return 9;
- else if (!strcasecmp("IE", region_type_string))
-- region_type = 10;
-+ return 10;
- else if (!strcasecmp("10GbE_0", region_type_string))
-- region_type = 11;
-+ return 11;
- else if (!strcasecmp("10GbE_1", region_type_string))
-- region_type = 12;
-+ return 12;
- else if (!strcasecmp("PTT", region_type_string))
-- region_type = 15;
-+ return 15;
- else
- return -1;
- }
---
-2.39.2
-
diff --git a/resources/coreboot/default/patches/0018-ich9m-boards-set-256MB-VRAM-instead.patch b/resources/coreboot/default/patches/0018-ich9m-boards-set-256MB-VRAM-instead.patch
deleted file mode 100644
index f18f2d5e..00000000
--- a/resources/coreboot/default/patches/0018-ich9m-boards-set-256MB-VRAM-instead.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 30d8dd45ab489bed21398b04bd03a54e08eafaf2 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sat, 4 Mar 2023 23:55:41 +0000
-Subject: [PATCH 18/18] ich9m boards: set 256MB VRAM instead
-
-352MB causes some stability issues reported by a few people
----
- src/mainboard/acer/g43t-am3/cmos.default | 2 +-
- src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
- src/mainboard/lenovo/t400/cmos.default | 2 +-
- src/mainboard/lenovo/x200/cmos.default | 2 +-
- 4 files changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
-index 98899e8bf5..e8b45ea22c 100644
---- a/src/mainboard/acer/g43t-am3/cmos.default
-+++ b/src/mainboard/acer/g43t-am3/cmos.default
-@@ -3,4 +3,4 @@ debug_level=Debug
- power_on_after_fail=Disable
- nmi=Enable
- sata_mode=AHCI
--gfx_uma_size=352M
-+gfx_uma_size=256M
-diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
-index 3a9a8e2d72..bedad54d2a 100644
---- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
-+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
-@@ -2,4 +2,4 @@ boot_option=Fallback
- debug_level=Debug
- power_on_after_fail=Enable
- nmi=Enable
--gfx_uma_size=352M
-+gfx_uma_size=256M
-diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
-index e74d15d030..b907a3e2df 100644
---- a/src/mainboard/lenovo/t400/cmos.default
-+++ b/src/mainboard/lenovo/t400/cmos.default
-@@ -13,4 +13,4 @@ power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
- hybrid_graphics_mode=Integrated Only
--gfx_uma_size=352M
-+gfx_uma_size=256M
-diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
-index 33a6a69f59..458b3f19c5 100644
---- a/src/mainboard/lenovo/x200/cmos.default
-+++ b/src/mainboard/lenovo/x200/cmos.default
-@@ -12,4 +12,4 @@ sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
--gfx_uma_size=352M
-+gfx_uma_size=256M
---
-2.39.2
-
diff --git a/resources/coreboot/default/patches/0021-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/resources/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
index b03f2750..42fa8399 100644
--- a/resources/coreboot/default/patches/0021-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
+++ b/resources/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
@@ -1,8 +1,8 @@
-From 521a2edd13050fa39c896bf4f481ff0021c9213e Mon Sep 17 00:00:00 2001
+From 6dc133e52c1ede4dbd3207133dd8ed0eb053fcd0 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
- models
+Subject: [PATCH 18/19] mb/dell/e6400: Enable 01.0 device in devicetree for
+ dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644
device pci 02.1 on end # Display
device pci 03.0 on end # ME
--
-2.40.1
+2.39.2
diff --git a/resources/coreboot/default/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch b/resources/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
index 547c6392..85bf47a1 100644
--- a/resources/coreboot/default/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch
+++ b/resources/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
@@ -1,7 +1,8 @@
-From 1ce4f118b024a6367382b46016781f30fe622e3e Mon Sep 17 00:00:00 2001
+From eb0fa411af62bf33cac69f3ba082e2d513bd9ab2 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH] Remove warning for coreboot images built without a payload
+Subject: [PATCH 19/19] Remove warning for coreboot images built without a
+ payload
I added this in upstream to prevent people from accidentally flashing
roms without a payload resulting in a no boot situation, but in
@@ -34,5 +35,5 @@ index e735443a76..4f1692a873 100644
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
-2.40.1
+2.39.2
diff --git a/resources/coreboot/default/patches/0023-mb-dell-e6400-acpi-Route-Ricoh-R5C847-PCI-IRQ-lines-.patch b/resources/coreboot/default/patches/0023-mb-dell-e6400-acpi-Route-Ricoh-R5C847-PCI-IRQ-lines-.patch
deleted file mode 100644
index 483ea0e1..00000000
--- a/resources/coreboot/default/patches/0023-mb-dell-e6400-acpi-Route-Ricoh-R5C847-PCI-IRQ-lines-.patch
+++ /dev/null
@@ -1,125 +0,0 @@
-From 5c1455495e8d2030473d8194fcf2e1d1111696b7 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Tue, 23 May 2023 20:59:56 -0600
-Subject: [PATCH] mb/dell/e6400/acpi: Route Ricoh R5C847 PCI IRQ lines as DBC
-
-Based on the schematic and vendor ASL code, PCI interrupt lines ABC of
-the Ricoh R5C847 PC Card/Media Card/FireWire controller are routed DBC.
-From lspci and the schematic this chip is PCI device 1. The original
-config copied from the T400 was routed ABCD->BCDA, causing Linux to
-issue an "irq 18: nobody cared" message when inserting an SD card.
-This is fixed by this patch and the SD card now works properly.
-
-Change-Id: Iede1de72d5369f1aebbac170792733739add3431
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
-Reviewed-on: https://review.coreboot.org/c/coreboot/+/75411
-Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-Reviewed-by: Angel Pons <th3fanbus@gmail.com>
----
- .../dell/e6400/acpi/ich9_pci_irqs.asl | 85 ++-----------------
- 1 file changed, 8 insertions(+), 77 deletions(-)
-
-diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
-index 21066fbf3b..9a4cdfb75b 100644
---- a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
-+++ b/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
-@@ -4,87 +4,18 @@
- * 0:1e.0 PCI bridge of the ICH9
- */
-
--/* TODO: which slots are actually relevant? */
- If (PICM) {
- Return (Package() {
-- // PCI Slot 1 routes ABCD
-- Package() { 0x0000ffff, 0, 0, 16},
-- Package() { 0x0000ffff, 1, 0, 17},
-- Package() { 0x0000ffff, 2, 0, 18},
-- Package() { 0x0000ffff, 3, 0, 19},
--
-- // PCI Slot 2 routes BCDA
-- Package() { 0x0001ffff, 0, 0, 17},
-- Package() { 0x0001ffff, 1, 0, 18},
-- Package() { 0x0001ffff, 2, 0, 19},
-- Package() { 0x0001ffff, 3, 0, 16},
--
-- // PCI Slot 3 routes CDAB
-- Package() { 0x0002ffff, 0, 0, 18},
-- Package() { 0x0002ffff, 1, 0, 19},
-- Package() { 0x0002ffff, 2, 0, 16},
-- Package() { 0x0002ffff, 3, 0, 17},
--
-- // PCI Slot 4 routes ABCD
-- Package() { 0x0003ffff, 0, 0, 16},
-- Package() { 0x0003ffff, 1, 0, 17},
-- Package() { 0x0003ffff, 2, 0, 18},
-- Package() { 0x0003ffff, 3, 0, 19},
--
-- // PCI Slot 5 routes ABCD
-- Package() { 0x0004ffff, 0, 0, 16},
-- Package() { 0x0004ffff, 1, 0, 17},
-- Package() { 0x0004ffff, 2, 0, 18},
-- Package() { 0x0004ffff, 3, 0, 19},
--
-- // PCI Slot 6 routes BCDA
-- Package() { 0x0005ffff, 0, 0, 17},
-- Package() { 0x0005ffff, 1, 0, 18},
-- Package() { 0x0005ffff, 2, 0, 19},
-- Package() { 0x0005ffff, 3, 0, 16},
--
-- // FIXME: what's this supposed to mean? (adopted from ich7)
-- //Package() { 0x0008ffff, 0, 0, 20},
-+ // PCI Device 1, Ricoh R5C847 routes DBC
-+ Package() { 0x0001ffff, 0, 0, 19},
-+ Package() { 0x0001ffff, 1, 0, 17},
-+ Package() { 0x0001ffff, 2, 0, 18},
- })
- } Else {
- Return (Package() {
-- // PCI Slot 1 routes ABCD
-- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
-- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
-- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
-- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
--
-- // PCI Slot 2 routes BCDA
-- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
-- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
-- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
-- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
--
-- // PCI Slot 3 routes CDAB
-- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
-- Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
-- Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
-- Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},
--
-- // PCI Slot 4 routes ABCD
-- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
-- Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
-- Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
-- Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
--
-- // PCI Slot 5 routes ABCD
-- Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
-- Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
-- Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
-- Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
--
-- // PCI Slot 6 routes BCDA
-- Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
-- Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
-- Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
-- Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
--
-- // FIXME
-- // Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
-+ // PCI Device 1, Ricoh R5C847 routes DBC
-+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
-+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
-+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
- })
- }
---
-2.41.0
-
diff --git a/resources/coreboot/default/patches/0024-Add-HP-8300-USDT-port.patch b/resources/coreboot/default/patches/0024-Add-HP-8300-USDT-port.patch
deleted file mode 100644
index 1b6c4be4..00000000
--- a/resources/coreboot/default/patches/0024-Add-HP-8300-USDT-port.patch
+++ /dev/null
@@ -1,865 +0,0 @@
-From c2bc778648e649cc6f0a60d51d1124c1741f35d7 Mon Sep 17 00:00:00 2001
-From: Riku Viitanen <riku.viitanen@protonmail.com>
-Date: Fri, 16 Jun 2023 23:03:43 +0300
-Subject: [PATCH] Add HP 8300 USDT port
-
-In Coreboot Gerrit:
-https://review.coreboot.org/c/coreboot/+/74906
-
-The following is tested and is working:
-* Native raminit with both DIMMs
-* Libgfxinit textmode and framebuffer on both DisplayPorts and VGA
-* External USB2 and USB3 ports: they all work
-* USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports)
-* Ethernet
-* Mini-PCIe WLAN
-* SATA: 2.5" SSD and optical drive bay
-* Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1
-* PS/2 keyboard
-* S3 suspend and resume, wake using USB keyboard
-* Headphone output, line out, internal speaker
-* Wake on LAN
-* Rebooting
-* CMOS options & nvramcui
-
-Untested:
-* mSATA slot. The SATA port needs to be enabled on devicetree
- too, but I'm unable to test due to lack of hardware
-* Line in, mic input
-* MXM graphics card
-* PS/2 mouse
-* EHCI debug
-
-Not working:
-* Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so
- maybe it just isn't present
-* PS/2 keyboard wake from S3
----
- .../hp/compaq_elite_8300_usdt/Kconfig | 43 ++++
- .../hp/compaq_elite_8300_usdt/Kconfig.name | 2 +
- .../hp/compaq_elite_8300_usdt/Makefile.inc | 5 +
- .../hp/compaq_elite_8300_usdt/acpi/ec.asl | 1 +
- .../compaq_elite_8300_usdt/acpi/platform.asl | 10 +
- .../compaq_elite_8300_usdt/acpi/superio.asl | 29 +++
- .../hp/compaq_elite_8300_usdt/acpi_tables.c | 12 ++
- .../hp/compaq_elite_8300_usdt/board_info.txt | 6 +
- .../hp/compaq_elite_8300_usdt/cmos.default | 6 +
- .../hp/compaq_elite_8300_usdt/cmos.layout | 73 +++++++
- .../hp/compaq_elite_8300_usdt/devicetree.cb | 172 ++++++++++++++++
- .../hp/compaq_elite_8300_usdt/dsdt.asl | 30 +++
- .../hp/compaq_elite_8300_usdt/early_init.c | 39 ++++
- .../compaq_elite_8300_usdt/gma-mainboard.ads | 19 ++
- .../hp/compaq_elite_8300_usdt/gpio.c | 191 ++++++++++++++++++
- .../hp/compaq_elite_8300_usdt/hda_verb.c | 33 +++
- .../hp/compaq_elite_8300_usdt/mainboard.c | 16 ++
- 17 files changed, 687 insertions(+)
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/Kconfig
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/Kconfig.name
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/Makefile.inc
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/acpi/ec.asl
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/acpi/platform.asl
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/acpi/superio.asl
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/acpi_tables.c
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/board_info.txt
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/cmos.layout
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/dsdt.asl
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/early_init.c
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/gma-mainboard.ads
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/gpio.c
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c
- create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/mainboard.c
-
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig b/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig
-new file mode 100644
-index 0000000000..9450133065
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig
-@@ -0,0 +1,43 @@
-+if BOARD_HP_COMPAQ_ELITE_8300_USDT
-+
-+config BOARD_SPECIFIC_OPTIONS
-+ def_bool y
-+ select BOARD_ROMSIZE_KB_16384
-+ select HAVE_ACPI_RESUME
-+ select HAVE_ACPI_TABLES
-+ select INTEL_INT15
-+ select MAINBOARD_HAS_LIBGFXINIT
-+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+ select SERIRQ_CONTINUOUS_MODE
-+ select SOUTHBRIDGE_INTEL_C216
-+ select USE_NATIVE_RAMINIT
-+ select SUPERIO_NUVOTON_NPCD378
-+ select MAINBOARD_USES_IFD_GBE_REGION
-+ select MAINBOARD_HAS_TPM1
-+ select MEMORY_MAPPED_TPM
-+ select HAVE_CMOS_DEFAULT
-+ select HAVE_OPTION_TABLE
-+
-+config CBFS_SIZE
-+ default 0x570000
-+
-+config MAINBOARD_DIR
-+ string
-+ default "hp/compaq_elite_8300_usdt"
-+
-+config MAINBOARD_PART_NUMBER
-+ string
-+ default "HP Compaq Elite 8300 USDT"
-+
-+config VGA_BIOS_ID
-+ string
-+ default "8086,0152"
-+
-+config DRAM_RESET_GATE_GPIO
-+ int
-+ default 60
-+
-+config USBDEBUG_HCD_INDEX # FIXME: check this
-+ int
-+ default 2
-+endif
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig.name b/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig.name
-new file mode 100644
-index 0000000000..030d8560ab
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_HP_COMPAQ_ELITE_8300_USDT
-+ bool "Compaq Elite 8300 USDT"
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_usdt/Makefile.inc
-new file mode 100644
-index 0000000000..18391d8b18
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/Makefile.inc
-@@ -0,0 +1,5 @@
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/acpi/ec.asl b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/ec.asl
-new file mode 100644
-index 0000000000..73fa78ef14
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/ec.asl
-@@ -0,0 +1 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/acpi/platform.asl b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/platform.asl
-new file mode 100644
-index 0000000000..aff432b6f4
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/platform.asl
-@@ -0,0 +1,10 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+ Return(Package() {0, 0})
-+}
-+
-+Method(_PTS, 1)
-+{
-+}
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/acpi/superio.asl b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/superio.asl
-new file mode 100644
-index 0000000000..54f8e3fe95
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/superio.asl
-@@ -0,0 +1,29 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */
-+
-+#include <superio/nuvoton/npcd378/acpi/superio.asl>
-+
-+Scope (\_GPE)
-+{
-+ Method (_L0D, 0, NotSerialized)
-+ {
-+ Notify (\_SB.PCI0.EHC1, 0x02)
-+ Notify (\_SB.PCI0.EHC2, 0x02)
-+ //FIXME: Add GBE device
-+ //Notify (\_SB.PCI0.GBE, 0x02)
-+ }
-+
-+ Method (_L09, 0, NotSerialized)
-+ {
-+ Notify (\_SB.PCI0.RP01, 0x02)
-+ Notify (\_SB.PCI0.RP02, 0x02)
-+ Notify (\_SB.PCI0.RP03, 0x02)
-+ Notify (\_SB.PCI0.RP04, 0x02)
-+ Notify (\_SB.PCI0.RP05, 0x02)
-+ Notify (\_SB.PCI0.RP06, 0x02)
-+ Notify (\_SB.PCI0.RP07, 0x02)
-+ Notify (\_SB.PCI0.RP08, 0x02)
-+ Notify (\_SB.PCI0.PEGP, 0x02)
-+ }
-+}
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/acpi_tables.c b/src/mainboard/hp/compaq_elite_8300_usdt/acpi_tables.c
-new file mode 100644
-index 0000000000..8f4f83b826
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/acpi_tables.c
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi_gnvs.h>
-+#include <soc/nvs.h>
-+
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+ /* Temperature at which OS will shutdown */
-+ gnvs->tcrt = 100;
-+ /* Temperature at which OS will throttle CPU */
-+ gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/board_info.txt b/src/mainboard/hp/compaq_elite_8300_usdt/board_info.txt
-new file mode 100644
-index 0000000000..f47ea980b1
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: mini
-+ROM protocol: SPI
-+ROM socketed: n
-+ROM package: SOIC-16
-+Flashrom support: y
-+Release year: 2012
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
-new file mode 100644
-index 0000000000..6f3cec735e
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
-@@ -0,0 +1,6 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Enable
-+nmi=Enable
-+sata_mode=AHCI
-+gfx_uma_size=32M
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.layout b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.layout
-new file mode 100644
-index 0000000000..bdc06faed6
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.layout
-@@ -0,0 +1,73 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0 120 r 0 reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384 1 e 4 boot_option
-+388 4 h 0 reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395 4 e 6 debug_level
-+
-+# coreboot config options: southbridge
-+408 1 e 1 nmi
-+409 2 e 7 power_on_after_fail
-+
-+421 1 e 9 sata_mode
-+
-+# coreboot config options: northbridge
-+432 3 e 11 gfx_uma_size
-+
-+448 128 r 0 vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896 32 r 0 mrc_scrambler_seed
-+928 32 r 0 mrc_scrambler_seed_s3
-+960 16 r 0 mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984 16 h 0 check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID value text
-+1 0 Disable
-+1 1 Enable
-+2 0 Enable
-+2 1 Disable
-+4 0 Fallback
-+4 1 Normal
-+6 0 Emergency
-+6 1 Alert
-+6 2 Critical
-+6 3 Error
-+6 4 Warning
-+6 5 Notice
-+6 6 Info
-+6 7 Debug
-+6 8 Spew
-+7 0 Disable
-+7 1 Enable
-+7 2 Keep
-+9 0 AHCI
-+9 1 IDE
-+11 0 32M
-+11 1 64M
-+11 2 96M
-+11 3 128M
-+11 4 160M
-+11 5 192M
-+11 6 224M
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 415 984
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb
-new file mode 100644
-index 0000000000..008429505e
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb
-@@ -0,0 +1,172 @@
-+chip northbridge/intel/sandybridge
-+ register "gpu_dp_b_hotplug" = "4"
-+ register "gpu_dp_c_hotplug" = "4"
-+ register "gpu_dp_d_hotplug" = "0"
-+ device domain 0x0 on
-+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-+ register "docking_supported" = "0"
-+ register "gen1_dec" = "0x00fc0a01"
-+ register "gen2_dec" = "0x00fc0801"
-+ register "gen3_dec" = "0x00000000"
-+ register "gen4_dec" = "0x00000000"
-+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
-+ register "pcie_port_coalesce" = "1"
-+ register "sata_interface_speed_support" = "0x3"
-+ register "sata_port_map" = "0x3" # 0x1: 2.5" slot
-+ # 0x2: DVD
-+ # 0x?: mSATA
-+ register "spi_lvscc" = "0x2005"
-+ register "spi_uvscc" = "0x2005"
-+ register "superspeed_capable_ports" = "0x0000000f"
-+ register "xhci_overcurrent_mapping" = "0x00000c03"
-+ register "xhci_switchable_ports" = "0x0000000f"
-+ device ref xhci on # USB 3.0 Controller
-+ subsystemid 0x103c 0x3398
-+ end
-+ device ref mei1 off # Management Engine Interface 1
-+ end
-+ device ref mei2 off # Management Engine Interface 2
-+ end
-+ device ref me_ide_r off # Management Engine IDE-R
-+ end
-+ device ref me_kt off # Management Engine KT
-+ end
-+ device ref gbe on # Intel Gigabit Ethernet
-+ subsystemid 0x103c 0x3398
-+ end
-+ device ref ehci2 on # USB2 EHCI #2
-+ subsystemid 0x103c 0x3398
-+ end
-+ device ref hda on # High Definition Audio
-+ subsystemid 0x103c 0x3398
-+ end
-+ device ref pcie_rp1 on # Mini-PCIe WLAN
-+ end
-+ device ref pcie_rp2 off # PCIe Port #2
-+ end
-+ device ref pcie_rp3 off # PCIe Port #3
-+ end
-+ device ref pcie_rp4 off # PCIe Port #4
-+ end
-+ device ref pcie_rp5 off # PCIe Port #5
-+ end
-+ device ref pcie_rp6 off # PCIe Port #6
-+ end
-+ device ref pcie_rp7 off # PCIe Port #7
-+ end
-+ device ref pcie_rp8 off # PCIe Port #8
-+ end
-+ device ref ehci1 on # USB2 EHCI #1
-+ subsystemid 0x103c 0x3398
-+ end
-+ device ref pci_bridge on # PCI bridge
-+ subsystemid 0x103c 0x3398
-+ end
-+ device ref lpc on # LPC bridge
-+ chip superio/common # Super I/O grabbed from 8200SFF devicetree
-+ device pnp 2e.ff on # passes SIO base addr to SSDT gen
-+ chip superio/nuvoton/npcd378
-+ device pnp 2e.0 off end # Floppy
-+ device pnp 2e.1 off end # Parallel
-+ device pnp 2e.2 off # COM1
-+ io 0x60 = 0x2f8
-+ irq 0x70 = 3
-+ end
-+ device pnp 2e.3 on # COM2, IR
-+ io 0x60 = 0x3f8
-+ irq 0x70 = 4
-+ end
-+ device pnp 2e.4 on # LED control
-+ io 0x60 = 0x600
-+ # IOBASE[0h] = bit0 LED red / green
-+ # IOBASE[0h] = bit1-4 LED PWM duty cycle
-+ # IOBASE[1h] = bit6 SWCC
-+
-+ io 0x62 = 0x610
-+ # IOBASE [0h] = GPES
-+ # IOBASE [1h] = GPEE
-+ # IOBASE [4h:7h] = 32bit upcounter at 1Mhz
-+ # IOBASE [8h:bh] = GPS
-+ # IOBASE [ch:fh] = GPE
-+ end
-+ device pnp 2e.5 on # Mouse
-+ irq 0x70 = 0xc
-+ end
-+ device pnp 2e.6 on # Keyboard
-+ io 0x60 = 0x0060
-+ io 0x62 = 0x0064
-+ irq 0x70 = 0x01
-+ # serialice: Vendor writes:
-+ drq 0xf0 = 0x40
-+ end
-+ device pnp 2e.7 on # WDT ?
-+ io 0x60 = 0x620
-+ end
-+ device pnp 2e.8 on # HWM
-+ io 0x60 = 0x800
-+ # IOBASE[0h:feh] HWM page
-+ # IOBASE[ffh] bit0-bit3 page selector
-+
-+ drq 0xf0 = 0x20
-+ drq 0xf1 = 0x01
-+ drq 0xf2 = 0x40
-+ drq 0xf3 = 0x01
-+
-+ drq 0xf4 = 0x66
-+ drq 0xf5 = 0x67
-+ drq 0xf6 = 0x66
-+ drq 0xf7 = 0x01
-+ end
-+ device pnp 2e.f on # GPIO OD ?
-+ drq 0xf1 = 0x97
-+ drq 0xf2 = 0x01
-+ drq 0xf5 = 0x08
-+ drq 0xfe = 0x80
-+ end
-+ device pnp 2e.15 on # BUS ?
-+ io 0x60 = 0x0680
-+ io 0x62 = 0x0690
-+ end
-+ device pnp 2e.1c on # Suspend Control ?
-+ io 0x60 = 0x640
-+ # writing to IOBASE[5h]
-+ # 0x0: Power off
-+ # 0x9: Power off and bricked until CMOS battery removed
-+ end
-+ device pnp 2e.1e on # GPIO ?
-+ io 0x60 = 0x660
-+ drq 0xf4 = 0x01
-+ # skip the following, as it
-+ # looks like remapped registers
-+ #drq 0xf5 = 0x06
-+ #drq 0xf6 = 0x60
-+ #drq 0xfe = 0x03
-+ end
-+ end
-+ end
-+ end
-+ chip drivers/pc80/tpm
-+ device pnp 4e.0 on end # TPM module
-+ end
-+ end
-+ device ref sata1 on # SATA Controller 1
-+ subsystemid 0x103c 0x3398
-+ end
-+ device ref smbus on # SMBus
-+ subsystemid 0x103c 0x3398
-+ end
-+ device ref sata2 off # SATA Controller 2
-+ end
-+ device ref thermal off # Thermal
-+ end
-+ end
-+ device ref host_bridge on # Host bridge Host bridge
-+ subsystemid 0x103c 0x3398
-+ end
-+ device ref peg10 on # PEG
-+ end
-+ device ref igd on # iGPU
-+ subsystemid 0x103c 0x3398
-+ end
-+ end
-+end
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/dsdt.asl b/src/mainboard/hp/compaq_elite_8300_usdt/dsdt.asl
-new file mode 100644
-index 0000000000..7d13c55b08
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/dsdt.asl
-@@ -0,0 +1,30 @@
-+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <acpi/acpi.h>
-+
-+DefinitionBlock(
-+ "dsdt.aml",
-+ "DSDT",
-+ ACPI_DSDT_REV_2,
-+ OEM_ID,
-+ ACPI_TABLE_CREATOR,
-+ 0x20141018 /* OEM revision */
-+)
-+{
-+ #include <acpi/dsdt_top.asl>
-+ #include "acpi/platform.asl"
-+ #include <cpu/intel/common/acpi/cpu.asl>
-+ #include <southbridge/intel/common/acpi/platform.asl>
-+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-+ #include <southbridge/intel/common/acpi/sleepstates.asl>
-+
-+ Device (\_SB.PCI0)
-+ {
-+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
-+ }
-+}
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c b/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c
-new file mode 100644
-index 0000000000..857c25dd19
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c
-@@ -0,0 +1,39 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <bootblock_common.h>
-+#include <superio/nuvoton/npcd378/npcd378.h>
-+#include <superio/nuvoton/common/nuvoton.h>
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/sandybridge/raminit_native.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+ { 1, 0, 0 },
-+ { 1, 0, 0 },
-+ { 1, 0, 1 },
-+ { 1, 0, 1 },
-+ { 1, 0, 2 },
-+ { 1, 0, 2 },
-+ { 1, 0, 3 },
-+ { 1, 0, 3 },
-+ { 1, 0, 4 },
-+ { 1, 0, 4 },
-+ { 1, 0, 6 },
-+ { 1, 0, 5 },
-+ { 1, 0, 5 },
-+ { 1, 0, 6 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1408);
-+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
-+}
-+
-+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-+{
-+ read_spd(&spd[3], 0x50, id_only);
-+ read_spd(&spd[1], 0x52, id_only);
-+}
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/gma-mainboard.ads b/src/mainboard/hp/compaq_elite_8300_usdt/gma-mainboard.ads
-new file mode 100644
-index 0000000000..74b50645e6
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/gma-mainboard.ads
-@@ -0,0 +1,19 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+ ports : constant Port_List :=
-+ (DP1,
-+ DP2,
-+ HDMI1,
-+ HDMI2,
-+ Analog,
-+ others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/gpio.c b/src/mainboard/hp/compaq_elite_8300_usdt/gpio.c
-new file mode 100644
-index 0000000000..2ae852ae51
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/gpio.c
-@@ -0,0 +1,191 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+ .gpio0 = GPIO_MODE_GPIO,
-+ .gpio1 = GPIO_MODE_GPIO,
-+ .gpio2 = GPIO_MODE_NATIVE,
-+ .gpio3 = GPIO_MODE_NATIVE,
-+ .gpio4 = GPIO_MODE_NATIVE,
-+ .gpio5 = GPIO_MODE_NATIVE,
-+ .gpio6 = GPIO_MODE_GPIO,
-+ .gpio7 = GPIO_MODE_GPIO,
-+ .gpio8 = GPIO_MODE_GPIO,
-+ .gpio9 = GPIO_MODE_NATIVE,
-+ .gpio10 = GPIO_MODE_NATIVE,
-+ .gpio11 = GPIO_MODE_GPIO,
-+ .gpio12 = GPIO_MODE_NATIVE,
-+ .gpio13 = GPIO_MODE_GPIO,
-+ .gpio14 = GPIO_MODE_NATIVE,
-+ .gpio15 = GPIO_MODE_GPIO,
-+ .gpio16 = GPIO_MODE_GPIO,
-+ .gpio17 = GPIO_MODE_GPIO,
-+ .gpio18 = GPIO_MODE_NATIVE,
-+ .gpio19 = GPIO_MODE_NATIVE,
-+ .gpio20 = GPIO_MODE_NATIVE,
-+ .gpio21 = GPIO_MODE_GPIO,
-+ .gpio22 = GPIO_MODE_GPIO,
-+ .gpio23 = GPIO_MODE_NATIVE,
-+ .gpio24 = GPIO_MODE_GPIO,
-+ .gpio25 = GPIO_MODE_NATIVE,
-+ .gpio26 = GPIO_MODE_NATIVE,
-+ .gpio27 = GPIO_MODE_GPIO,
-+ .gpio28 = GPIO_MODE_GPIO,
-+ .gpio29 = GPIO_MODE_GPIO,
-+ .gpio30 = GPIO_MODE_NATIVE,
-+ .gpio31 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+ .gpio0 = GPIO_DIR_INPUT,
-+ .gpio1 = GPIO_DIR_INPUT,
-+ .gpio6 = GPIO_DIR_INPUT,
-+ .gpio7 = GPIO_DIR_INPUT,
-+ .gpio8 = GPIO_DIR_INPUT,
-+ .gpio11 = GPIO_DIR_INPUT,
-+ .gpio13 = GPIO_DIR_INPUT,
-+ .gpio15 = GPIO_DIR_OUTPUT,
-+ .gpio16 = GPIO_DIR_INPUT,
-+ .gpio17 = GPIO_DIR_OUTPUT,
-+ .gpio21 = GPIO_DIR_INPUT,
-+ .gpio22 = GPIO_DIR_INPUT,
-+ .gpio24 = GPIO_DIR_INPUT,
-+ .gpio27 = GPIO_DIR_INPUT,
-+ .gpio28 = GPIO_DIR_OUTPUT,
-+ .gpio29 = GPIO_DIR_OUTPUT,
-+ .gpio31 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+ .gpio15 = GPIO_LEVEL_LOW,
-+ .gpio17 = GPIO_LEVEL_LOW,
-+ .gpio28 = GPIO_LEVEL_LOW,
-+ .gpio29 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+ .gpio0 = GPIO_INVERT,
-+ .gpio1 = GPIO_INVERT,
-+ .gpio6 = GPIO_INVERT,
-+ .gpio11 = GPIO_INVERT,
-+ .gpio13 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+ .gpio32 = GPIO_MODE_GPIO,
-+ .gpio33 = GPIO_MODE_GPIO,
-+ .gpio34 = GPIO_MODE_GPIO,
-+ .gpio35 = GPIO_MODE_GPIO,
-+ .gpio36 = GPIO_MODE_GPIO,
-+ .gpio37 = GPIO_MODE_GPIO,
-+ .gpio38 = GPIO_MODE_GPIO,
-+ .gpio39 = GPIO_MODE_GPIO,
-+ .gpio40 = GPIO_MODE_NATIVE,
-+ .gpio41 = GPIO_MODE_NATIVE,
-+ .gpio42 = GPIO_MODE_NATIVE,
-+ .gpio43 = GPIO_MODE_GPIO,
-+ .gpio44 = GPIO_MODE_NATIVE,
-+ .gpio45 = GPIO_MODE_NATIVE,
-+ .gpio46 = GPIO_MODE_GPIO,
-+ .gpio47 = GPIO_MODE_NATIVE,
-+ .gpio48 = GPIO_MODE_GPIO,
-+ .gpio49 = GPIO_MODE_GPIO,
-+ .gpio50 = GPIO_MODE_NATIVE,
-+ .gpio51 = GPIO_MODE_NATIVE,
-+ .gpio52 = GPIO_MODE_NATIVE,
-+ .gpio53 = GPIO_MODE_NATIVE,
-+ .gpio54 = GPIO_MODE_GPIO,
-+ .gpio55 = GPIO_MODE_NATIVE,
-+ .gpio56 = GPIO_MODE_NATIVE,
-+ .gpio57 = GPIO_MODE_GPIO,
-+ .gpio58 = GPIO_MODE_NATIVE,
-+ .gpio59 = GPIO_MODE_NATIVE,
-+ .gpio60 = GPIO_MODE_NATIVE,
-+ .gpio61 = GPIO_MODE_GPIO,
-+ .gpio62 = GPIO_MODE_NATIVE,
-+ .gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+ .gpio32 = GPIO_DIR_INPUT,
-+ .gpio33 = GPIO_DIR_INPUT,
-+ .gpio34 = GPIO_DIR_INPUT,
-+ .gpio35 = GPIO_DIR_INPUT,
-+ .gpio36 = GPIO_DIR_INPUT,
-+ .gpio37 = GPIO_DIR_INPUT,
-+ .gpio38 = GPIO_DIR_INPUT,
-+ .gpio39 = GPIO_DIR_INPUT,
-+ .gpio43 = GPIO_DIR_INPUT,
-+ .gpio46 = GPIO_DIR_INPUT,
-+ .gpio48 = GPIO_DIR_INPUT,
-+ .gpio49 = GPIO_DIR_INPUT,
-+ .gpio54 = GPIO_DIR_INPUT,
-+ .gpio57 = GPIO_DIR_INPUT,
-+ .gpio61 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+ .gpio64 = GPIO_MODE_NATIVE,
-+ .gpio65 = GPIO_MODE_NATIVE,
-+ .gpio66 = GPIO_MODE_NATIVE,
-+ .gpio67 = GPIO_MODE_NATIVE,
-+ .gpio68 = GPIO_MODE_GPIO,
-+ .gpio69 = GPIO_MODE_GPIO,
-+ .gpio70 = GPIO_MODE_GPIO,
-+ .gpio71 = GPIO_MODE_GPIO,
-+ .gpio72 = GPIO_MODE_GPIO,
-+ .gpio73 = GPIO_MODE_NATIVE,
-+ .gpio74 = GPIO_MODE_NATIVE,
-+ .gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+ .gpio68 = GPIO_DIR_INPUT,
-+ .gpio69 = GPIO_DIR_INPUT,
-+ .gpio70 = GPIO_DIR_INPUT,
-+ .gpio71 = GPIO_DIR_OUTPUT,
-+ .gpio72 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+ .gpio71 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+ .set1 = {
-+ .mode = &pch_gpio_set1_mode,
-+ .direction = &pch_gpio_set1_direction,
-+ .level = &pch_gpio_set1_level,
-+ .blink = &pch_gpio_set1_blink,
-+ .invert = &pch_gpio_set1_invert,
-+ .reset = &pch_gpio_set1_reset,
-+ },
-+ .set2 = {
-+ .mode = &pch_gpio_set2_mode,
-+ .direction = &pch_gpio_set2_direction,
-+ .level = &pch_gpio_set2_level,
-+ .reset = &pch_gpio_set2_reset,
-+ },
-+ .set3 = {
-+ .mode = &pch_gpio_set3_mode,
-+ .direction = &pch_gpio_set3_direction,
-+ .level = &pch_gpio_set3_level,
-+ .reset = &pch_gpio_set3_reset,
-+ },
-+};
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c b/src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c
-new file mode 100644
-index 0000000000..9c0525b015
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+ 0x10ec0221, /* Codec Vendor / Device ID: Realtek */
-+ 0x103c3398, /* Subsystem ID */
-+ 11, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(0, 0x103c3398),
-+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
-+ AZALIA_PIN_CFG(0, 0x14, 0x01014020),
-+ AZALIA_PIN_CFG(0, 0x17, 0x90170110),
-+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
-+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
-+ AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f),
-+ AZALIA_PIN_CFG(0, 0x1b, 0x01813c30),
-+ AZALIA_PIN_CFG(0, 0x1d, 0x598301f0),
-+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
-+ AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
-+
-+ 0x80862806, /* Codec Vendor / Device ID: Intel */
-+ 0x80860101, /* Subsystem ID */
-+ 4, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(3, 0x80860101),
-+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+ AZALIA_PIN_CFG(3, 0x07, 0x58560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/mainboard.c b/src/mainboard/hp/compaq_elite_8300_usdt/mainboard.c
-new file mode 100644
-index 0000000000..8dbd95ef96
---- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/mainboard.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/device.h>
-+#include <drivers/intel/gma/int15.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
-+ GMA_INT15_PANEL_FIT_DEFAULT,
-+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+ .enable_dev = mainboard_enable,
-+};
---
-2.41.0
-