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-rw-r--r--config/coreboot/dell/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch205
-rw-r--r--config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch47
-rw-r--r--config/coreboot/dell/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch173
-rw-r--r--config/coreboot/dell/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch28
-rw-r--r--config/coreboot/dell/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch39
-rw-r--r--config/coreboot/dell/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch61
-rw-r--r--config/coreboot/dell/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch37
-rw-r--r--config/coreboot/dell/patches/0024-don-t-use-github-for-the-acpica-download.patch39
-rw-r--r--config/coreboot/dell/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch341
-rw-r--r--config/coreboot/dell/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch216
-rw-r--r--config/coreboot/dell/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch142
-rw-r--r--config/coreboot/dell/target.cfg4
12 files changed, 1332 insertions, 0 deletions
diff --git a/config/coreboot/dell/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/dell/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
new file mode 100644
index 00000000..6a293287
--- /dev/null
+++ b/config/coreboot/dell/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
@@ -0,0 +1,205 @@
+From 38c76afbea4abfed2976bfbe10977e41f21665b0 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 19 Feb 2023 18:21:43 +0000
+Subject: [PATCH 15/22] util/ifdtool: add --nuke flag (all 0xFF on region)
+
+When this option is used, the region's contents are overwritten
+with all ones (0xFF).
+
+Example:
+
+./ifdtool --nuke gbe coreboot.rom
+./ifdtool --nuke bios coreboot.com
+./ifdtool --nuke me coreboot.com
+
+Rebased since the last revision update in lbmk.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
+ 1 file changed, 83 insertions(+), 31 deletions(-)
+
+diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
+index ddbc0fb91b..7af9235ae3 100644
+--- a/util/ifdtool/ifdtool.c
++++ b/util/ifdtool/ifdtool.c
+@@ -1847,6 +1847,7 @@ static void print_usage(const char *name)
+ " wbg - Wellsburg\n"
+ " -S | --setpchstrap Write a PCH strap\n"
+ " -V | --newvalue The new value to write into PCH strap specified by -S\n"
++ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
+ " -v | --version: print the version\n"
+ " -h | --help: print this help\n\n"
+ "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
+@@ -1854,6 +1855,60 @@ static void print_usage(const char *name)
+ "\n");
+ }
+
++static int
++get_region_type_string(const char *region_type_string)
++{
++ if (!strcasecmp("Descriptor", region_type_string))
++ return 0;
++ else if (!strcasecmp("BIOS", region_type_string))
++ return 1;
++ else if (!strcasecmp("ME", region_type_string))
++ return 2;
++ else if (!strcasecmp("GbE", region_type_string))
++ return 3;
++ else if (!strcasecmp("Platform Data", region_type_string))
++ return 4;
++ else if (!strcasecmp("Device Exp1", region_type_string))
++ return 5;
++ else if (!strcasecmp("Secondary BIOS", region_type_string))
++ return 6;
++ else if (!strcasecmp("Reserved", region_type_string))
++ return 7;
++ else if (!strcasecmp("EC", region_type_string))
++ return 8;
++ else if (!strcasecmp("Device Exp2", region_type_string))
++ return 9;
++ else if (!strcasecmp("IE", region_type_string))
++ return 10;
++ else if (!strcasecmp("10GbE_0", region_type_string))
++ return 11;
++ else if (!strcasecmp("10GbE_1", region_type_string))
++ return 12;
++ else if (!strcasecmp("PTT", region_type_string))
++ return 15;
++ return -1;
++}
++
++static void
++nuke(const char *filename, char *image, int size, int region_type)
++{
++ int i;
++ struct region region;
++ const struct frba *frba = find_frba(image, size);
++ if (!frba)
++ exit(EXIT_FAILURE);
++
++ region = get_region(frba, region_type);
++ if (region.size > 0) {
++ for (i = region.base; i <= region.limit; i++) {
++ if ((i + 1) > (size))
++ break;
++ image[i] = 0xFF;
++ }
++ write_image(filename, image, size);
++ }
++}
++
+ int main(int argc, char *argv[])
+ {
+ int opt, option_index = 0;
+@@ -1861,6 +1916,7 @@ int main(int argc, char *argv[])
+ int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
+ int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
+ int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
++ int mode_nuke = 0;
+ char *region_type_string = NULL, *region_fname = NULL;
+ const char *layout_fname = NULL;
+ char *new_filename = NULL;
+@@ -1892,6 +1948,7 @@ int main(int argc, char *argv[])
+ {"validate", 0, NULL, 't'},
+ {"setpchstrap", 1, NULL, 'S'},
+ {"newvalue", 1, NULL, 'V'},
++ {"nuke", 1, NULL, 'N'},
+ {0, 0, 0, 0}
+ };
+
+@@ -1941,35 +1998,8 @@ int main(int argc, char *argv[])
+ region_fname++;
+ // Descriptor, BIOS, ME, GbE, Platform
+ // valid type?
+- if (!strcasecmp("Descriptor", region_type_string))
+- region_type = 0;
+- else if (!strcasecmp("BIOS", region_type_string))
+- region_type = 1;
+- else if (!strcasecmp("ME", region_type_string))
+- region_type = 2;
+- else if (!strcasecmp("GbE", region_type_string))
+- region_type = 3;
+- else if (!strcasecmp("Platform Data", region_type_string))
+- region_type = 4;
+- else if (!strcasecmp("Device Exp1", region_type_string))
+- region_type = 5;
+- else if (!strcasecmp("Secondary BIOS", region_type_string))
+- region_type = 6;
+- else if (!strcasecmp("Reserved", region_type_string))
+- region_type = 7;
+- else if (!strcasecmp("EC", region_type_string))
+- region_type = 8;
+- else if (!strcasecmp("Device Exp2", region_type_string))
+- region_type = 9;
+- else if (!strcasecmp("IE", region_type_string))
+- region_type = 10;
+- else if (!strcasecmp("10GbE_0", region_type_string))
+- region_type = 11;
+- else if (!strcasecmp("10GbE_1", region_type_string))
+- region_type = 12;
+- else if (!strcasecmp("PTT", region_type_string))
+- region_type = 15;
+- if (region_type == -1) {
++ if ((region_type =
++ get_region_type_string(region_type_string)) == -1) {
+ fprintf(stderr, "No such region type: '%s'\n\n",
+ region_type_string);
+ fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+@@ -2135,6 +2165,22 @@ int main(int argc, char *argv[])
+ case 't':
+ mode_validate = 1;
+ break;
++ case 'N':
++ region_type_string = strdup(optarg);
++ if (!region_type_string) {
++ fprintf(stderr, "No region specified\n");
++ print_usage(argv[0]);
++ exit(EXIT_FAILURE);
++ }
++ if ((region_type =
++ get_region_type_string(region_type_string)) == -1) {
++ fprintf(stderr, "No such region type: '%s'\n\n",
++ region_type_string);
++ print_usage(argv[0]);
++ exit(EXIT_FAILURE);
++ }
++ mode_nuke = 1;
++ break;
+ case 'v':
+ print_version();
+ exit(EXIT_SUCCESS);
+@@ -2150,7 +2196,8 @@ int main(int argc, char *argv[])
+
+ if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
+- mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) {
++ mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
++ mode_nuke) > 1) {
+ fprintf(stderr, "You may not specify more than one mode.\n\n");
+ fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ exit(EXIT_FAILURE);
+@@ -2158,7 +2205,8 @@ int main(int argc, char *argv[])
+
+ if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
+- mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
++ mode_locked + mode_unlocked + mode_density + mode_altmedisable +
++ mode_validate + mode_nuke) == 0) {
+ fprintf(stderr, "You need to specify a mode.\n\n");
+ fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ exit(EXIT_FAILURE);
+@@ -2262,6 +2310,10 @@ int main(int argc, char *argv[])
+ write_image(new_filename, image, size);
+ }
+
++ if (mode_nuke) {
++ nuke(new_filename, image, size, region_type);
++ }
++
+ if (mode_altmedisable) {
+ struct fpsba *fpsba = find_fpsba(image, size);
+ struct fmsba *fmsba = find_fmsba(image, size);
+--
+2.39.2
+
diff --git a/config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
new file mode 100644
index 00000000..0f9b192d
--- /dev/null
+++ b/config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
@@ -0,0 +1,47 @@
+From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Wed, 1 Dec 2021 02:53:00 +0000
+Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
+ "cpu/intel/model_1067x: enable PECI"
+
+This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
+
+Enabling PECI without microcode updates loaded causes the CPUID feature set
+to become corrupted. And one consequence is broken SpeedStep. At least, that's
+my understanding looking at Intel Errata. This revert is not a fix, because
+upstream is correct (upstream assumes microcode updates). We will simply
+maintain this revert patch in Libreboot, from now on.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 315e7c36fc..1423fd72bc 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
+ wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
+ }
+
+-#define IA32_PECI_CTL 0x5a0
+-
+ static void configure_misc(const int eist, const int tm2, const int emttm)
+ {
+ msr_t msr;
+@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
+ msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+ }
+-
+- /* Enable PECI
+- WARNING: due to Erratum AW67 described in Intel document #318733
+- the microcode must be updated before this MSR is written to. */
+- msr = rdmsr(IA32_PECI_CTL);
+- msr.lo |= 1;
+- wrmsr(IA32_PECI_CTL, msr);
+ }
+
+ #define PIC_SENS_CFG 0x1aa
+--
+2.39.2
+
diff --git a/config/coreboot/dell/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/dell/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
new file mode 100644
index 00000000..4d7b3421
--- /dev/null
+++ b/config/coreboot/dell/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
@@ -0,0 +1,173 @@
+From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 17 Apr 2023 15:49:57 +0100
+Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR
+
+This reverts the changes in coreboot revision:
+df7aecd92643d207feaf7fd840f8835097346644
+
+While this fix is *technically correct*, the one in
+coreboot, it breaks rebooting as tested on several
+GM45 ThinkPads e.g. X200, T400, when microcode
+updates are not applied.
+
+Since November 2022, Libreboot includes microcode
+updates by default, but it tells users how to remove
+it from the ROM (with cbfstool) if they wish.
+
+Well, with Libreboot 20221214, 20230319 and 20230413,
+mitigations present in Libreboot 20220710 (which did
+not have microcode updates) do not exist.
+
+This patch, along with the other patch to remove PECI
+support (which breaks speedstep when microcode updates
+are not applied) have now been re-added to Libreboot.
+
+It is still best to use microcode updates by default.
+These patches in coreboot are not critically urgent,
+and you can use the machines with or without them,
+regardless of ucode.
+
+I'll probably re-write this and the other patch at
+some point, applying the change conditionally upon
+whether or not microcode is applied.
+
+Pragmatism is a good thing. I recommend it.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
+ src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
+ src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
+ src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
+ src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
+ 5 files changed, 16 insertions(+), 26 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 1423fd72bc..d1f98ca43a 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -8,6 +8,7 @@
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
+ #include <cpu/intel/smm_reloc.h>
++#include <cpu/intel/common/common.h>
+
+ #define MSR_BBL_CR_CTL3 0x11e
+
+@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
+ fill_processor_name(processor_name);
+ printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
++ /* Set virtualization based on Kconfig option */
++ set_vmx_and_lock();
++
+ /* Configure C States */
+ configure_c_states(quad);
+
+diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
+index bc53214310..72f40f6762 100644
+--- a/src/cpu/intel/model_1067x/mp_init.c
++++ b/src/cpu/intel/model_1067x/mp_init.c
+@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
+ smm_initialize();
+ }
+
+-#define SMRR_SUPPORTED (1 << 11)
+-
+ static void per_cpu_smm_trigger(void)
+ {
+- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
+- set_feature_ctrl_vmx();
+- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
+- /* We don't care if the lock is already setting
+- as our smm relocation handler is able to handle
+- setups where SMRR is not enabled here. */
+- if (ia32_ft_ctrl.lo & (1 << 0)) {
+- /* IA32_FEATURE_CONTROL locked. If we set it again we
+- get an illegal instruction. */
+- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
+- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
+- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
+- } else {
+- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
+- printk(BIOS_INFO,
+- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
+- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
+- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
+- }
+- } else {
+- set_vmx_and_lock();
+- }
+-
+ /* Relocate the SMM handler. */
+ smm_relocate();
+ }
+diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
+index 05f5f327cc..0450c2ad83 100644
+--- a/src/cpu/intel/model_106cx/model_106cx_init.c
++++ b/src/cpu/intel/model_106cx/model_106cx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+
+ #define HIGHEST_CLEVEL 3
+ static void configure_c_states(void)
+@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
+ fill_processor_name(processor_name);
+ printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
++ /* Set virtualization based on Kconfig option */
++ set_vmx_and_lock();
++
+ /* Configure C States */
+ configure_c_states();
+
+diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
+index 5bd1c32815..f3bb08cde3 100644
+--- a/src/cpu/intel/model_6ex/model_6ex_init.c
++++ b/src/cpu/intel/model_6ex/model_6ex_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+
+ #define HIGHEST_CLEVEL 3
+ static void configure_c_states(void)
+@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
+ /* Setup Page Attribute Tables (PAT) */
+ // TODO set up PAT
+
++ /* Set virtualization based on Kconfig option */
++ set_vmx_and_lock();
++
+ /* Configure C States */
+ configure_c_states();
+
+diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
+index 535fb8fae7..f7b05facd2 100644
+--- a/src/cpu/intel/model_6fx/model_6fx_init.c
++++ b/src/cpu/intel/model_6fx/model_6fx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+
+ #define HIGHEST_CLEVEL 3
+ static void configure_c_states(void)
+@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
+ /* Setup Page Attribute Tables (PAT) */
+ // TODO set up PAT
+
++ /* Set virtualization based on Kconfig option */
++ set_vmx_and_lock();
++
+ /* Configure C States */
+ configure_c_states();
+
+--
+2.39.2
+
diff --git a/config/coreboot/dell/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/dell/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
new file mode 100644
index 00000000..04f3bd63
--- /dev/null
+++ b/config/coreboot/dell/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
@@ -0,0 +1,28 @@
+From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sat, 6 May 2023 15:53:41 -0600
+Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for
+ dGPU models
+
+Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6400/devicetree.cb | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
+index bb954cbd7b..e9f3915d17 100644
+--- a/src/mainboard/dell/e6400/devicetree.cb
++++ b/src/mainboard/dell/e6400/devicetree.cb
+@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
+ ops gm45_pci_domain_ops
+
+ device pci 00.0 on end # host bridge
+- device pci 01.0 off end
++ device pci 01.0 on end
+ device pci 02.0 on end # VGA
+ device pci 02.1 on end # Display
+ device pci 03.0 on end # ME
+--
+2.39.2
+
diff --git a/config/coreboot/dell/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/dell/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
new file mode 100644
index 00000000..3f21ad02
--- /dev/null
+++ b/config/coreboot/dell/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
@@ -0,0 +1,39 @@
+From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 12 May 2023 19:55:15 -0600
+Subject: [PATCH 19/22] Remove warning for coreboot images built without a
+ payload
+
+I added this in upstream to prevent people from accidentally flashing
+roms without a payload resulting in a no boot situation, but in
+libreboot lbmk handles the payload and thus this warning always comes
+up. This has caused confusion and concern so just patch it out.
+---
+ payloads/Makefile.inc | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
+index e735443a76..4f1692a873 100644
+--- a/payloads/Makefile.inc
++++ b/payloads/Makefile.inc
+@@ -49,16 +49,5 @@ distclean-payloads:
+ print-repo-info-payloads:
+ -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
+
+-ifeq ($(CONFIG_PAYLOAD_NONE),y)
+-files_added:: warn_no_payload
+-endif
+-
+-warn_no_payload:
+- printf "\n\t** WARNING **\n"
+- printf "coreboot has been built without a payload. Writing\n"
+- printf "a coreboot image without a payload to your board's\n"
+- printf "flash chip will result in a non-booting system. You\n"
+- printf "can use cbfstool to add a payload to the image.\n\n"
+-
+ .PHONY: force-payload coreinfo nvramcui
+-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
+--
+2.39.2
+
diff --git a/config/coreboot/dell/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch b/config/coreboot/dell/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch
new file mode 100644
index 00000000..2f2cddfe
--- /dev/null
+++ b/config/coreboot/dell/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch
@@ -0,0 +1,61 @@
+From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sun, 27 Aug 2023 17:36:36 -0600
+Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios
+
+These were determined by sniffing the LPC bus while toggling the
+hardware wireless switch on the Latitude E6400. To differentiate devices
+options in the vendor BIOS to change which radios the switch controlled
+were used.
+
+Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/ec/dell/mec5035/mec5035.c | 9 +++++++++
+ src/ec/dell/mec5035/mec5035.h | 8 ++++++++
+ 2 files changed, 17 insertions(+)
+
+diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
+index 8da11e5b1c..e0335a4635 100644
+--- a/src/ec/dell/mec5035/mec5035.c
++++ b/src/ec/dell/mec5035/mec5035.c
+@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting)
+ return buf[0];
+ }
+
++void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on)
++{
++ /* From LPC traces and userspace testing with other values,
++ the second byte has to be 2 for an unknown reason. */
++ u8 buf[3] = {dev, 2, on};
++ write_mailbox_regs(buf, 2, 3);
++ ec_command(CMD_RADIO_EN);
++}
++
+ void mec5035_early_init(void)
+ {
+ /* If this isn't sent the EC shuts down the system after about 15
+diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
+index e7a05b64d4..16512e2cc2 100644
+--- a/src/ec/dell/mec5035/mec5035.h
++++ b/src/ec/dell/mec5035/mec5035.h
+@@ -16,8 +16,16 @@
+
+ #define CMD_CPU_OK 0xc2
+
++#define CMD_RADIO_EN 0x2b
++enum mec5035_radio_dev {
++ RADIO_WLAN = 0,
++ RADIO_WWAN = 1,
++ RADIO_WPAN = 2,
++};
++
+ u8 mec5035_mouse_touchpad(u8 setting);
+ void mec5035_cpu_ok(void);
+ void mec5035_early_init(void);
++void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on);
+
+ #endif /* _EC_DELL_MEC5035_H_ */
+--
+2.39.2
+
diff --git a/config/coreboot/dell/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch b/config/coreboot/dell/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch
new file mode 100644
index 00000000..d02ad724
--- /dev/null
+++ b/config/coreboot/dell/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch
@@ -0,0 +1,37 @@
+From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sun, 27 Aug 2023 19:15:37 -0600
+Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API
+
+Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/ec/dell/mec5035/mec5035.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
+index e0335a4635..20a33cc0ad 100644
+--- a/src/ec/dell/mec5035/mec5035.c
++++ b/src/ec/dell/mec5035/mec5035.c
+@@ -4,6 +4,7 @@
+ #include <console/console.h>
+ #include <device/device.h>
+ #include <device/pnp.h>
++#include <option.h>
+ #include <pc80/keyboard.h>
+ #include <stdint.h>
+ #include "mec5035.h"
+@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev)
+ mec5035_mouse_touchpad(TP_PS2_MOUSE);
+
+ pc_keyboard_init(NO_AUX_DEVICE);
++
++ mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1));
++ mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1));
++ mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1));
+ }
+
+ static struct device_operations ops = {
+--
+2.39.2
+
diff --git a/config/coreboot/dell/patches/0024-don-t-use-github-for-the-acpica-download.patch b/config/coreboot/dell/patches/0024-don-t-use-github-for-the-acpica-download.patch
new file mode 100644
index 00000000..2c4c9e5f
--- /dev/null
+++ b/config/coreboot/dell/patches/0024-don-t-use-github-for-the-acpica-download.patch
@@ -0,0 +1,39 @@
+From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 22 Oct 2023 15:02:25 +0100
+Subject: [PATCH 1/1] don't use github for the acpica download
+
+i have the tarball from a previous download, and i placed
+it on libreboot rsync, which then got mirrored to princeton.
+
+today, github's ssl cert was b0rking the hell out and i really
+really wanted to finish a build, and didn't want to wait for
+github to fix their httpd.
+
+so i'm now hosting this specific acpica tarball on rsync.
+
+this patch makes that URL be used, instead of the github one.
+
+that's the 2nd time i've had to patch coreboot's acpica download!
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index ebc9fcb49a..a857110b4b 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+ GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+ BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
++IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+ CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+--
+2.39.2
+
diff --git a/config/coreboot/dell/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch b/config/coreboot/dell/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch
new file mode 100644
index 00000000..cca8901f
--- /dev/null
+++ b/config/coreboot/dell/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch
@@ -0,0 +1,341 @@
+From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 29 Oct 2023 01:18:50 +0000
+Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
+ value"
+
+This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
+
+NOTE:
+
+this is done instead of merging:
+https://review.coreboot.org/c/coreboot/+/78623
+
+which is still under review for now
+
+the patch i'm reverting is this one:
+https://review.coreboot.org/c/coreboot/+/78270
+
+this was actually only merged the day before i
+updated coreboot revs in lbmk to the 12 october rev,
+so there's no harm in quickly reverting this for now
+
+however, later on, we will rely on the other patch
+---
+ src/Kconfig | 3 ++-
+ src/cpu/qemu-x86/Kconfig | 3 +++
+ src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
+ src/northbridge/amd/pi/Kconfig | 4 ++++
+ src/soc/amd/picasso/Kconfig | 4 ++++
+ src/soc/amd/stoneyridge/Kconfig | 4 ++++
+ src/soc/cavium/cn81xx/Kconfig | 3 +++
+ src/soc/intel/alderlake/Kconfig | 5 +++++
+ src/soc/intel/apollolake/Kconfig | 4 ++++
+ src/soc/intel/cannonlake/Kconfig | 4 ++++
+ src/soc/intel/elkhartlake/Kconfig | 4 ++++
+ src/soc/intel/jasperlake/Kconfig | 4 ++++
+ src/soc/intel/meteorlake/Kconfig | 5 +++++
+ src/soc/intel/skylake/Kconfig | 4 ++++
+ src/soc/intel/tigerlake/Kconfig | 4 ++++
+ src/soc/intel/xeon_sp/Kconfig | 4 ++++
+ src/soc/intel/xeon_sp/cpx/Kconfig | 4 ++++
+ src/soc/intel/xeon_sp/skx/Kconfig | 4 ++++
+ src/soc/intel/xeon_sp/spr/Kconfig | 4 ++++
+ src/soc/qualcomm/ipq40xx/Kconfig | 4 ++++
+ 20 files changed, 77 insertions(+), 1 deletion(-)
+
+diff --git a/src/Kconfig b/src/Kconfig
+index ae8024089e..1549719dd0 100644
+--- a/src/Kconfig
++++ b/src/Kconfig
+@@ -751,7 +751,8 @@ config RTC
+
+ config HEAP_SIZE
+ hex
+- default 0x100000
++ default 0x100000 if FLATTENED_DEVICE_TREE
++ default 0x4000
+
+ config STACK_SIZE
+ hex
+diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
+index 0fa999e1ac..f3e2c4cea9 100644
+--- a/src/cpu/qemu-x86/Kconfig
++++ b/src/cpu/qemu-x86/Kconfig
+@@ -35,4 +35,7 @@ config MAX_CPUS
+ default 32 if SMM_TSEG
+ default 4
+
++config HEAP_SIZE
++ default 0x8000
++
+ endif
+diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
+index 7bc3b0bcbb..7f9300f2a7 100644
+--- a/src/mainboard/sifive/hifive-unleashed/Kconfig
++++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
+@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
+ select FLATTENED_DEVICE_TREE
+ select SPI_SDCARD
+
++config HEAP_SIZE
++ default 0x10000
++
+ config MAINBOARD_DIR
+ default "sifive/hifive-unleashed"
+
+diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
+index 4ffe82a15f..4518db149b 100644
+--- a/src/northbridge/amd/pi/Kconfig
++++ b/src/northbridge/amd/pi/Kconfig
+@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
++config HEAP_SIZE
++ hex
++ default 0xc0000
++
+ endif # NORTHBRIDGE_AMD_PI
+diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
+index c33f287067..796fe4eb13 100644
+--- a/src/soc/amd/picasso/Kconfig
++++ b/src/soc/amd/picasso/Kconfig
+@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
+ bool
+ default n
+
++config HEAP_SIZE
++ hex
++ default 0xc0000
++
+ config SERIRQ_CONTINUOUS_MODE
+ bool
+ default n
+diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
+index 6ff135e6a8..9af7455bae 100644
+--- a/src/soc/amd/stoneyridge/Kconfig
++++ b/src/soc/amd/stoneyridge/Kconfig
+@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
+ bool
+ default n
+
++config HEAP_SIZE
++ hex
++ default 0xc0000
++
+ config EHCI_BAR
+ hex
+ default 0xfef00000
+diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
+index 77ca97202b..368581f8f1 100644
+--- a/src/soc/cavium/cn81xx/Kconfig
++++ b/src/soc/cavium/cn81xx/Kconfig
+@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
+ int
+ default 1
+
++config HEAP_SIZE
++ default 0x10000
++
+ config STACK_SIZE
+ default 0x2000
+
+diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
+index 4b960c1d22..82ec8f263e 100644
+--- a/src/soc/intel/alderlake/Kconfig
++++ b/src/soc/intel/alderlake/Kconfig
+@@ -215,6 +215,11 @@ config IED_REGION_SIZE
+ hex
+ default 0x400000
+
++config HEAP_SIZE
++ hex
++ default 0x80000 if BMP_LOGO
++ default 0x10000
++
+ config GFX_GMA_DEFAULT_MMIO
+ default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
+
+diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
+index 78ec2987ce..bce935d800 100644
+--- a/src/soc/intel/apollolake/Kconfig
++++ b/src/soc/intel/apollolake/Kconfig
+@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
+ help
+ Name of file to store in the IFWI region.
+
++config HEAP_SIZE
++ hex
++ default 0x8000
++
+ config MAX_ROOT_PORTS
+ int
+ default 6
+diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
+index a42a3c365b..80237f9810 100644
+--- a/src/soc/intel/cannonlake/Kconfig
++++ b/src/soc/intel/cannonlake/Kconfig
+@@ -160,6 +160,10 @@ config IED_REGION_SIZE
+ hex
+ default 0x400000
+
++config HEAP_SIZE
++ hex
++ default 0x8000
++
+ config NHLT_DMIC_1CH_16B
+ bool
+ depends on ACPI_NHLT
+diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
+index 3361c0ddb9..7f1c767379 100644
+--- a/src/soc/intel/elkhartlake/Kconfig
++++ b/src/soc/intel/elkhartlake/Kconfig
+@@ -104,6 +104,10 @@ config IED_REGION_SIZE
+ hex
+ default 0x0
+
++config HEAP_SIZE
++ hex
++ default 0x8000
++
+ config MAX_ROOT_PORTS
+ int
+ default 7
+diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
+index 3d84991e09..ff5def3263 100644
+--- a/src/soc/intel/jasperlake/Kconfig
++++ b/src/soc/intel/jasperlake/Kconfig
+@@ -106,6 +106,10 @@ config IED_REGION_SIZE
+ hex
+ default 0x400000
+
++config HEAP_SIZE
++ hex
++ default 0x8000
++
+ config MAX_ROOT_PORTS
+ int
+ default 8
+diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
+index 590e8b80e1..48030a1911 100644
+--- a/src/soc/intel/meteorlake/Kconfig
++++ b/src/soc/intel/meteorlake/Kconfig
+@@ -197,6 +197,11 @@ config IED_REGION_SIZE
+ hex
+ default 0x400000
+
++config HEAP_SIZE
++ hex
++ default 0x80000 if BMP_LOGO
++ default 0x10000
++
+ # Intel recommends reserving the PCIe TBT root port resources as below:
+ # - 42 buses
+ # - 194 MiB Non-prefetchable memory
+diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
+index e0df501460..d6a11363ee 100644
+--- a/src/soc/intel/skylake/Kconfig
++++ b/src/soc/intel/skylake/Kconfig
+@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
+ help
+ If you set this option to n, will not use native SD controller.
+
++config HEAP_SIZE
++ hex
++ default 0x80000
++
+ config IED_REGION_SIZE
+ hex
+ default 0x400000
+diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
+index c07a0d8365..0a4b7bfdb8 100644
+--- a/src/soc/intel/tigerlake/Kconfig
++++ b/src/soc/intel/tigerlake/Kconfig
+@@ -152,6 +152,10 @@ config IED_REGION_SIZE
+ config INTEL_TME
+ default n
+
++config HEAP_SIZE
++ hex
++ default 0x10000
++
+ config MAX_ROOT_PORTS
+ int
+ default 24 if SOC_INTEL_TIGERLAKE_PCH_H
+diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
+index e63bee5451..63ced01067 100644
+--- a/src/soc/intel/xeon_sp/Kconfig
++++ b/src/soc/intel/xeon_sp/Kconfig
+@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
+ config ECAM_MMCONF_BUS_NUMBER
+ default 256
+
++config HEAP_SIZE
++ hex
++ default 0x80000
++
+ config HPET_MIN_TICKS
+ hex
+ default 0x80
+diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
+index ac166c3038..f54f7716b6 100644
+--- a/src/soc/intel/xeon_sp/cpx/Kconfig
++++ b/src/soc/intel/xeon_sp/cpx/Kconfig
+@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
+ hex
+ default 0x7C00
+
++config HEAP_SIZE
++ hex
++ default 0x80000
++
+ config STACK_SIZE
+ hex
+ default 0x4000
+diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
+index 5d843878e1..c2c3d4e2e8 100644
+--- a/src/soc/intel/xeon_sp/skx/Kconfig
++++ b/src/soc/intel/xeon_sp/skx/Kconfig
+@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
+ hex
+ default 0x7C00
+
++config HEAP_SIZE
++ hex
++ default 0x80000
++
+ config IED_REGION_SIZE
+ hex
+ default 0x400000
+diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
+index 43b87ade14..b1c4c783b7 100644
+--- a/src/soc/intel/xeon_sp/spr/Kconfig
++++ b/src/soc/intel/xeon_sp/spr/Kconfig
+@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
+ hex
+ default 0x8c00
+
++config HEAP_SIZE
++ hex
++ default 0x80000
++
+ config STACK_SIZE
+ hex
+ default 0x4000
+diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
+index 0ce92731c0..0eabb00752 100644
+--- a/src/soc/qualcomm/ipq40xx/Kconfig
++++ b/src/soc/qualcomm/ipq40xx/Kconfig
+@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
+ help
+ Path for utils to combine SBL_ELF and bootblock
+
++config HEAP_SIZE
++ hex
++ default 0x8000
++
+ endif
+--
+2.39.2
+
diff --git a/config/coreboot/dell/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/dell/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch
new file mode 100644
index 00000000..454e3e7b
--- /dev/null
+++ b/config/coreboot/dell/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch
@@ -0,0 +1,216 @@
+From e047dc3c95063f27517cd6754e9cbe496ac9313d Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Mon, 10 May 2021 22:40:59 +0200
+Subject: [PATCH] [NOT FOR MERGE] nb/intel/gm45: Make DDR2 raminit work
+
+List of changes:
+ - Update some timing and ODT values
+ - Patch RCOMP calibration to better match what MRC binaries do
+ - Replay a hardcoded list of RCOMP codes after RcvEn
+
+This makes raminit work at DDR2-800 speeds and fixes S3 resume as well.
+Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs.
+
+Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+
+diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
+index f28c6d1..bdf0432 100644
+--- a/src/northbridge/intel/gm45/gm45.h
++++ b/src/northbridge/intel/gm45/gm45.h
+@@ -419,7 +419,7 @@
+ int raminit_read_vco_index(void);
+ u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
+
+-void raminit_rcomp_calibration(stepping_t stepping);
++void raminit_rcomp_calibration(int ddr_type, stepping_t stepping);
+ void raminit_reset_readwrite_pointers(void);
+ void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
+ void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
+diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
+index ecada7b..2b8c44e 100644
+--- a/src/northbridge/intel/gm45/raminit.c
++++ b/src/northbridge/intel/gm45/raminit.c
+@@ -1049,7 +1049,7 @@
+ }
+
+ /* Perform RCOMP calibration for DDR3. */
+- raminit_rcomp_calibration(stepping);
++ raminit_rcomp_calibration(spd_type, stepping);
+
+ /* Run initial RCOMP. */
+ mchbar_setbits32(0x418, 1 << 17);
+@@ -1119,7 +1119,7 @@
+ reg = (reg & ~(0xf << 10)) | (2 << 10);
+ else
+ reg = (reg & ~(0xf << 10)) | (3 << 10);
+- reg = (reg & ~(0x7 << 5)) | (3 << 5);
++ reg = (reg & ~(0x7 << 5)) | (2 << 5);
+ } else if (timings->mem_clock != MEM_CLOCK_1067MT) {
+ reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
+ reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
+@@ -1288,11 +1288,11 @@
+ reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32));
+ reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32));
+ if (timings->mem_clock == MEM_CLOCK_667MT) {
+- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32));
+- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32));
++ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32));
++ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32));
+ } else {
+- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32));
+- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32));
++ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32));
++ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32));
+ }
+ mchbar_write32(CxODT_HIGH(ch), reg);
+
+@@ -2217,6 +2217,84 @@
+ raminit_write_training(timings->mem_clock, dimms, s3resume);
+ }
+
++ /*
++ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
++ * after receiver enable calibration, otherwise raminit sometimes
++ * completes with non-working memory.
++ */
++ mchbar_write32(0x0530, 0x06060005);
++ mchbar_write32(0x0680, 0x06060606);
++ mchbar_write32(0x0684, 0x08070606);
++ mchbar_write32(0x0688, 0x0e0e0c0a);
++ mchbar_write32(0x068c, 0x0e0e0e0e);
++ mchbar_write32(0x0698, 0x06060606);
++ mchbar_write32(0x069c, 0x08070606);
++ mchbar_write32(0x06a0, 0x0c0c0b0a);
++ mchbar_write32(0x06a4, 0x0c0c0c0c);
++
++ mchbar_write32(0x06c0, 0x02020202);
++ mchbar_write32(0x06c4, 0x03020202);
++ mchbar_write32(0x06c8, 0x04040403);
++ mchbar_write32(0x06cc, 0x04040404);
++ mchbar_write32(0x06d8, 0x02020202);
++ mchbar_write32(0x06dc, 0x03020202);
++ mchbar_write32(0x06e0, 0x04040403);
++ mchbar_write32(0x06e4, 0x04040404);
++
++ mchbar_write32(0x0700, 0x02020202);
++ mchbar_write32(0x0704, 0x03020202);
++ mchbar_write32(0x0708, 0x04040403);
++ mchbar_write32(0x070c, 0x04040404);
++ mchbar_write32(0x0718, 0x02020202);
++ mchbar_write32(0x071c, 0x03020202);
++ mchbar_write32(0x0720, 0x04040403);
++ mchbar_write32(0x0724, 0x04040404);
++
++ mchbar_write32(0x0740, 0x02020202);
++ mchbar_write32(0x0744, 0x03020202);
++ mchbar_write32(0x0748, 0x04040403);
++ mchbar_write32(0x074c, 0x04040404);
++ mchbar_write32(0x0758, 0x02020202);
++ mchbar_write32(0x075c, 0x03020202);
++ mchbar_write32(0x0760, 0x04040403);
++ mchbar_write32(0x0764, 0x04040404);
++
++ mchbar_write32(0x0780, 0x06060606);
++ mchbar_write32(0x0784, 0x09070606);
++ mchbar_write32(0x0788, 0x0e0e0c0b);
++ mchbar_write32(0x078c, 0x0e0e0e0e);
++ mchbar_write32(0x0798, 0x06060606);
++ mchbar_write32(0x079c, 0x09070606);
++ mchbar_write32(0x07a0, 0x0d0d0c0b);
++ mchbar_write32(0x07a4, 0x0d0d0d0d);
++
++ mchbar_write32(0x07c0, 0x06060606);
++ mchbar_write32(0x07c4, 0x09070606);
++ mchbar_write32(0x07c8, 0x0e0e0c0b);
++ mchbar_write32(0x07cc, 0x0e0e0e0e);
++ mchbar_write32(0x07d8, 0x06060606);
++ mchbar_write32(0x07dc, 0x09070606);
++ mchbar_write32(0x07e0, 0x0d0d0c0b);
++ mchbar_write32(0x07e4, 0x0d0d0d0d);
++
++ mchbar_write32(0x0840, 0x06060606);
++ mchbar_write32(0x0844, 0x08070606);
++ mchbar_write32(0x0848, 0x0e0e0c0a);
++ mchbar_write32(0x084c, 0x0e0e0e0e);
++ mchbar_write32(0x0858, 0x06060606);
++ mchbar_write32(0x085c, 0x08070606);
++ mchbar_write32(0x0860, 0x0c0c0b0a);
++ mchbar_write32(0x0864, 0x0c0c0c0c);
++
++ mchbar_write32(0x0880, 0x02020202);
++ mchbar_write32(0x0884, 0x03020202);
++ mchbar_write32(0x0888, 0x04040403);
++ mchbar_write32(0x088c, 0x04040404);
++ mchbar_write32(0x0898, 0x02020202);
++ mchbar_write32(0x089c, 0x03020202);
++ mchbar_write32(0x08a0, 0x04040403);
++ mchbar_write32(0x08a4, 0x04040404);
++
+ igd_compute_ggc(sysinfo);
+
+ /* Program final memory map (with real values). */
+diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+index aef863f..b74765f 100644
+--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
++++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+@@ -161,11 +161,13 @@
+ mchbar += 4;
+ }
+ }
+-void raminit_rcomp_calibration(const stepping_t stepping) {
++void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
+ const int a1step = stepping >= STEPPING_CONVERSION_A1;
+
+ int i;
+
++ char magic_comp[2] = {0};
++
+ enum {
+ PULL_UP = 0,
+ PULL_DOWN = 1,
+@@ -196,6 +198,10 @@
+ reg = mchbar_read32(0x518);
+ lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
+ lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
++ if (i == 1) {
++ magic_comp[0] = (reg >> 8) & 0x3f;
++ magic_comp[1] = (reg >> 0) & 0x3f;
++ }
+ }
+ /* Cleanup? */
+ mchbar_setbits32(0x400, 1 << 3);
+@@ -216,13 +222,19 @@
+ for (channel = 0; channel < 2; ++channel) {
+ for (group = 0; group < 6; ++group) {
+ for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) {
+- lookup_and_write(
+- a1step,
+- lut_idx[channel][group][pu_pd] - 7,
+- ddr3_lookup_schedule[group][pu_pd],
+- mchbar);
++ if (ddr_type == DDR3) {
++ lookup_and_write(
++ a1step,
++ lut_idx[channel][group][pu_pd] - 7,
++ ddr3_lookup_schedule[group][pu_pd],
++ mchbar);
++ }
+ mchbar += 0x0018;
+ }
++ if (ddr_type == DDR2) {
++ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24);
++ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0);
++ }
+ mchbar += 0x0010;
+ /* Channel B knows only the first two groups. */
+ if ((1 == channel) && (1 == group))
+@@ -230,4 +242,7 @@
+ }
+ mchbar += 0x0040;
+ }
++
++ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
++ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
+ }
diff --git a/config/coreboot/dell/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch b/config/coreboot/dell/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch
new file mode 100644
index 00000000..afce453d
--- /dev/null
+++ b/config/coreboot/dell/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch
@@ -0,0 +1,142 @@
+From 0721e7e984bc83861bce3d47632b717848673749 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Tue, 31 Oct 2023 18:24:39 +0000
+Subject: [PATCH 1/1] crank up vram allocation on more intel boards
+
+these were added to libreboot, and it's a policy of
+libreboot to max out the vram settings. this was
+overlooked, in prior revisions and releases.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/dell/e6400/cmos.default | 2 +-
+ src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
+ src/mainboard/hp/compaq_8200_elite_sff/cmos.default | 2 +-
+ src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
+ src/mainboard/hp/snb_ivb_laptops/cmos.default | 1 +
+ src/mainboard/lenovo/t420/cmos.default | 1 +
+ src/mainboard/lenovo/t420s/cmos.default | 1 +
+ src/mainboard/lenovo/t430/cmos.default | 1 +
+ src/mainboard/lenovo/t520/cmos.default | 1 +
+ src/mainboard/lenovo/t530/cmos.default | 1 +
+ src/mainboard/lenovo/x201/cmos.default | 1 +
+ src/mainboard/lenovo/x220/cmos.default | 1 +
+ 12 files changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
+index eeb6f47364..25dfa38cb5 100644
+--- a/src/mainboard/dell/e6400/cmos.default
++++ b/src/mainboard/dell/e6400/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Disable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=256M
+diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
+index ccc7e64625..7c97b84baf 100644
+--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
++++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
+@@ -3,5 +3,5 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=128M
++gfx_uma_size=224M
+ fan_full_speed=Disable
+diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+index 6d27a79c66..4517ffc7c2 100644
+--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
++++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+@@ -3,5 +3,5 @@ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=224M
+ psu_fan_lvl=3
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+index 6f3cec735e..9fc4db2990 100644
+--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+@@ -3,4 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=224M
+diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
+index ad822d5043..89418a4cfc 100644
+--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
++++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
+@@ -3,3 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
+index c011867916..83f590d39d 100644
+--- a/src/mainboard/lenovo/t420/cmos.default
++++ b/src/mainboard/lenovo/t420/cmos.default
+@@ -15,3 +15,4 @@ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
+index c011867916..83f590d39d 100644
+--- a/src/mainboard/lenovo/t420s/cmos.default
++++ b/src/mainboard/lenovo/t420s/cmos.default
+@@ -15,3 +15,4 @@ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
+index 55e1e6c04e..a72108f47e 100644
+--- a/src/mainboard/lenovo/t430/cmos.default
++++ b/src/mainboard/lenovo/t430/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ usb_always_on=Disable
+ hybrid_graphics_mode=Integrated Only
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
+index b66f7034dc..a73ea6e9ee 100644
+--- a/src/mainboard/lenovo/t520/cmos.default
++++ b/src/mainboard/lenovo/t520/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
+index b66f7034dc..a73ea6e9ee 100644
+--- a/src/mainboard/lenovo/t530/cmos.default
++++ b/src/mainboard/lenovo/t530/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
+index 2cf484fd5a..46294d91ca 100644
+--- a/src/mainboard/lenovo/x201/cmos.default
++++ b/src/mainboard/lenovo/x201/cmos.default
+@@ -15,3 +15,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ usb_always_on=Disable
++gfx_uma_size=128M
+diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
+index 52f303dfdb..92a2026542 100644
+--- a/src/mainboard/lenovo/x220/cmos.default
++++ b/src/mainboard/lenovo/x220/cmos.default
+@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable
+ sticky_fn=Disable
+ trackpoint=Enable
+ me_state=Disabled
++gfx_uma_size=224M
+--
+2.39.2
+
diff --git a/config/coreboot/dell/target.cfg b/config/coreboot/dell/target.cfg
new file mode 100644
index 00000000..678e48c4
--- /dev/null
+++ b/config/coreboot/dell/target.cfg
@@ -0,0 +1,4 @@
+tree="dell"
+romtype="normal"
+rev="d862695f5f432b5c78dada5f16c293a4c3f9fce6"
+arch="x86_64"