diff options
Diffstat (limited to 'config/coreboot/dell/patches')
10 files changed, 0 insertions, 863 deletions
diff --git a/config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch deleted file mode 100644 index cb1effa7..00000000 --- a/config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ /dev/null @@ -1,203 +0,0 @@ -From 4fbd327df271d613d4a56a36eafd88d9d642ec6b Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 1/9] util/ifdtool: add --nuke flag (all 0xFF on region) - -When this option is used, the region's contents are overwritten -with all ones (0xFF). - -Example: - -./ifdtool --nuke gbe coreboot.rom -./ifdtool --nuke bios coreboot.com -./ifdtool --nuke me coreboot.com - -Rebased since the last revision update in lbmk. - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------ - 1 file changed, 81 insertions(+), 31 deletions(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 191b3216de..38132b4a28 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -1942,6 +1942,7 @@ static void print_usage(const char *name) - " tgl - Tiger Lake\n" - " wbg - Wellsburg\n" - " -S | --setpchstrap Write a PCH strap\n" -+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n" - " -V | --newvalue The new value to write into PCH strap specified by -S\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" -@@ -1950,6 +1951,60 @@ static void print_usage(const char *name) - "\n"); - } - -+static int -+get_region_type_string(const char *region_type_string) -+{ -+ if (!strcasecmp("Descriptor", region_type_string)) -+ return 0; -+ else if (!strcasecmp("BIOS", region_type_string)) -+ return 1; -+ else if (!strcasecmp("ME", region_type_string)) -+ return 2; -+ else if (!strcasecmp("GbE", region_type_string)) -+ return 3; -+ else if (!strcasecmp("Platform Data", region_type_string)) -+ return 4; -+ else if (!strcasecmp("Device Exp1", region_type_string)) -+ return 5; -+ else if (!strcasecmp("Secondary BIOS", region_type_string)) -+ return 6; -+ else if (!strcasecmp("Reserved", region_type_string)) -+ return 7; -+ else if (!strcasecmp("EC", region_type_string)) -+ return 8; -+ else if (!strcasecmp("Device Exp2", region_type_string)) -+ return 9; -+ else if (!strcasecmp("IE", region_type_string)) -+ return 10; -+ else if (!strcasecmp("10GbE_0", region_type_string)) -+ return 11; -+ else if (!strcasecmp("10GbE_1", region_type_string)) -+ return 12; -+ else if (!strcasecmp("PTT", region_type_string)) -+ return 15; -+ return -1; -+} -+ -+static void -+nuke(const char *filename, char *image, int size, int region_type) -+{ -+ int i; -+ struct region region; -+ const struct frba *frba = find_frba(image, size); -+ if (!frba) -+ exit(EXIT_FAILURE); -+ -+ region = get_region(frba, region_type); -+ if (region.size > 0) { -+ for (i = region.base; i <= region.limit; i++) { -+ if ((i + 1) > (size)) -+ break; -+ image[i] = 0xFF; -+ } -+ write_image(filename, image, size); -+ } -+} -+ - int main(int argc, char *argv[]) - { - int opt, option_index = 0; -@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[]) - int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; - int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; - int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; -+ int mode_nuke = 0; - int mode_gpr0_disable = 0; - char *region_type_string = NULL, *region_fname = NULL; - const char *layout_fname = NULL; -@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[]) - {"validate", 0, NULL, 't'}, - {"setpchstrap", 1, NULL, 'S'}, - {"newvalue", 1, NULL, 'V'}, -+ {"nuke", 1, NULL, 'N'}, - {0, 0, 0, 0} - }; - -@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[]) - region_fname++; - // Descriptor, BIOS, ME, GbE, Platform - // valid type? -- if (!strcasecmp("Descriptor", region_type_string)) -- region_type = 0; -- else if (!strcasecmp("BIOS", region_type_string)) -- region_type = 1; -- else if (!strcasecmp("ME", region_type_string)) -- region_type = 2; -- else if (!strcasecmp("GbE", region_type_string)) -- region_type = 3; -- else if (!strcasecmp("Platform Data", region_type_string)) -- region_type = 4; -- else if (!strcasecmp("Device Exp1", region_type_string)) -- region_type = 5; -- else if (!strcasecmp("Secondary BIOS", region_type_string)) -- region_type = 6; -- else if (!strcasecmp("Reserved", region_type_string)) -- region_type = 7; -- else if (!strcasecmp("EC", region_type_string)) -- region_type = 8; -- else if (!strcasecmp("Device Exp2", region_type_string)) -- region_type = 9; -- else if (!strcasecmp("IE", region_type_string)) -- region_type = 10; -- else if (!strcasecmp("10GbE_0", region_type_string)) -- region_type = 11; -- else if (!strcasecmp("10GbE_1", region_type_string)) -- region_type = 12; -- else if (!strcasecmp("PTT", region_type_string)) -- region_type = 15; -- if (region_type == -1) { -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { - fprintf(stderr, "No such region type: '%s'\n\n", - region_type_string); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); -@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[]) - case 't': - mode_validate = 1; - break; -+ case 'N': -+ region_type_string = strdup(optarg); -+ if (!region_type_string) { -+ fprintf(stderr, "No region specified\n"); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { -+ fprintf(stderr, "No such region type: '%s'\n\n", -+ region_type_string); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ mode_nuke = 1; -+ break; - case 'v': - print_version(); - exit(EXIT_SUCCESS); -@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[]) - if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | - mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + -- mode_gpr0_disable) > 1) { -+ mode_gpr0_disable + mode_nuke) > 1) { - fprintf(stderr, "You may not specify more than one mode.\n\n"); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); - exit(EXIT_FAILURE); -@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[]) - if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + - mode_locked + mode_unlocked + mode_density + mode_altmedisable + -- mode_validate + mode_gpr0_disable) == 0) { -+ mode_validate + mode_gpr0_disable + mode_nuke) == 0) { - fprintf(stderr, "You need to specify a mode.\n\n"); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); - exit(EXIT_FAILURE); -@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[]) - write_image(new_filename, image, size); - } - -+ if (mode_nuke) { -+ nuke(new_filename, image, size, region_type); -+ } -+ - if (mode_altmedisable) { - struct fpsba *fpsba = find_fpsba(image, size); - struct fmsba *fmsba = find_fmsba(image, size); --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch deleted file mode 100644 index b0ac4e67..00000000 --- a/config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 362e86f89b3980699e7e794df9b98018397fe2d8 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Wed, 1 Dec 2021 02:53:00 +0000 -Subject: [PATCH 2/9] fix speedstep on x200/t400: Revert - "cpu/intel/model_1067x: enable PECI" - -This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f. - -Enabling PECI without microcode updates loaded causes the CPUID feature set -to become corrupted. And one consequence is broken SpeedStep. At least, that's -my understanding looking at Intel Errata. This revert is not a fix, because -upstream is correct (upstream assumes microcode updates). We will simply -maintain this revert patch in Libreboot, from now on. ---- - src/cpu/intel/model_1067x/model_1067x_init.c | 9 --------- - 1 file changed, 9 deletions(-) - -diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c -index 315e7c36fc..1423fd72bc 100644 ---- a/src/cpu/intel/model_1067x/model_1067x_init.c -+++ b/src/cpu/intel/model_1067x/model_1067x_init.c -@@ -141,8 +141,6 @@ static void configure_emttm_tables(void) - wrmsr(MSR_EMTTM_CR_TABLE(5), msr); - } - --#define IA32_PECI_CTL 0x5a0 -- - static void configure_misc(const int eist, const int tm2, const int emttm) - { - msr_t msr; -@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm) - msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - } -- -- /* Enable PECI -- WARNING: due to Erratum AW67 described in Intel document #318733 -- the microcode must be updated before this MSR is written to. */ -- msr = rdmsr(IA32_PECI_CTL); -- msr.lo |= 1; -- wrmsr(IA32_PECI_CTL, msr); - } - - #define PIC_SENS_CFG 0x1aa --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch deleted file mode 100644 index 3193ed97..00000000 --- a/config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch +++ /dev/null @@ -1,173 +0,0 @@ -From 883455573f07551eaf2b12ab80bedcd2b4904a17 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Mon, 17 Apr 2023 15:49:57 +0100 -Subject: [PATCH 3/9] GM45-type CPUs: don't enable alternative SMRR - -This reverts the changes in coreboot revision: -df7aecd92643d207feaf7fd840f8835097346644 - -While this fix is *technically correct*, the one in -coreboot, it breaks rebooting as tested on several -GM45 ThinkPads e.g. X200, T400, when microcode -updates are not applied. - -Since November 2022, Libreboot includes microcode -updates by default, but it tells users how to remove -it from the ROM (with cbfstool) if they wish. - -Well, with Libreboot 20221214, 20230319 and 20230413, -mitigations present in Libreboot 20220710 (which did -not have microcode updates) do not exist. - -This patch, along with the other patch to remove PECI -support (which breaks speedstep when microcode updates -are not applied) have now been re-added to Libreboot. - -It is still best to use microcode updates by default. -These patches in coreboot are not critically urgent, -and you can use the machines with or without them, -regardless of ucode. - -I'll probably re-write this and the other patch at -some point, applying the change conditionally upon -whether or not microcode is applied. - -Pragmatism is a good thing. I recommend it. ---- - src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++ - src/cpu/intel/model_1067x/mp_init.c | 26 -------------------- - src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++ - src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++ - src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++ - 5 files changed, 16 insertions(+), 26 deletions(-) - -diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c -index 1423fd72bc..d1f98ca43a 100644 ---- a/src/cpu/intel/model_1067x/model_1067x_init.c -+++ b/src/cpu/intel/model_1067x/model_1067x_init.c -@@ -8,6 +8,7 @@ - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> - #include <cpu/intel/smm_reloc.h> -+#include <cpu/intel/common/common.h> - - #define MSR_BBL_CR_CTL3 0x11e - -@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu) - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(quad); - -diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c -index bc53214310..72f40f6762 100644 ---- a/src/cpu/intel/model_1067x/mp_init.c -+++ b/src/cpu/intel/model_1067x/mp_init.c -@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void) - smm_initialize(); - } - --#define SMRR_SUPPORTED (1 << 11) -- - static void per_cpu_smm_trigger(void) - { -- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); -- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) { -- set_feature_ctrl_vmx(); -- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL); -- /* We don't care if the lock is already setting -- as our smm relocation handler is able to handle -- setups where SMRR is not enabled here. */ -- if (ia32_ft_ctrl.lo & (1 << 0)) { -- /* IA32_FEATURE_CONTROL locked. If we set it again we -- get an illegal instruction. */ -- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n"); -- printk(BIOS_DEBUG, "SMRR status: %senabled\n", -- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not "); -- } else { -- if (!CONFIG(SET_IA32_FC_LOCK_BIT)) -- printk(BIOS_INFO, -- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n"); -- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); -- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); -- } -- } else { -- set_vmx_and_lock(); -- } -- - /* Relocate the SMM handler. */ - smm_relocate(); - } -diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c -index 05f5f327cc..0450c2ad83 100644 ---- a/src/cpu/intel/model_106cx/model_106cx_init.c -+++ b/src/cpu/intel/model_106cx/model_106cx_init.c -@@ -7,6 +7,7 @@ - #include <cpu/intel/speedstep.h> - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> -+#include <cpu/intel/common/common.h> - - #define HIGHEST_CLEVEL 3 - static void configure_c_states(void) -@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu) - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(); - -diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c -index 5bd1c32815..f3bb08cde3 100644 ---- a/src/cpu/intel/model_6ex/model_6ex_init.c -+++ b/src/cpu/intel/model_6ex/model_6ex_init.c -@@ -7,6 +7,7 @@ - #include <cpu/intel/speedstep.h> - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> -+#include <cpu/intel/common/common.h> - - #define HIGHEST_CLEVEL 3 - static void configure_c_states(void) -@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu) - /* Setup Page Attribute Tables (PAT) */ - // TODO set up PAT - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(); - -diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c -index 535fb8fae7..f7b05facd2 100644 ---- a/src/cpu/intel/model_6fx/model_6fx_init.c -+++ b/src/cpu/intel/model_6fx/model_6fx_init.c -@@ -7,6 +7,7 @@ - #include <cpu/intel/speedstep.h> - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> -+#include <cpu/intel/common/common.h> - - #define HIGHEST_CLEVEL 3 - static void configure_c_states(void) -@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu) - /* Setup Page Attribute Tables (PAT) */ - // TODO set up PAT - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(); - --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch deleted file mode 100644 index c9b41c79..00000000 --- a/config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 458fe39e9cd2536cfa8671427e6f557396143339 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 4/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU - models - -Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e6400/devicetree.cb | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb -index bb954cbd7b..e9f3915d17 100644 ---- a/src/mainboard/dell/e6400/devicetree.cb -+++ b/src/mainboard/dell/e6400/devicetree.cb -@@ -19,7 +19,7 @@ chip northbridge/intel/gm45 - ops gm45_pci_domain_ops - - device pci 00.0 on end # host bridge -- device pci 01.0 off end -+ device pci 01.0 on end - device pci 02.0 on end # VGA - device pci 02.1 on end # Display - device pci 03.0 on end # ME --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch deleted file mode 100644 index 546bad7f..00000000 --- a/config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ /dev/null @@ -1,39 +0,0 @@ -From de4eeaf6d44cb05c60c0b0d54b43cdb88686b998 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 5/9] Remove warning for coreboot images built without a - payload - -I added this in upstream to prevent people from accidentally flashing -roms without a payload resulting in a no boot situation, but in -libreboot lbmk handles the payload and thus this warning always comes -up. This has caused confusion and concern so just patch it out. ---- - payloads/Makefile.mk | 13 +------------ - 1 file changed, 1 insertion(+), 12 deletions(-) - -diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk -index a2336aa876..4f1692a873 100644 ---- a/payloads/Makefile.mk -+++ b/payloads/Makefile.mk -@@ -49,16 +49,5 @@ distclean-payloads: - print-repo-info-payloads: - -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) - --ifeq ($(CONFIG_PAYLOAD_NONE),y) --show_notices:: warn_no_payload --endif -- --warn_no_payload: -- printf "\n\t** WARNING **\n" -- printf "coreboot has been built without a payload. Writing\n" -- printf "a coreboot image without a payload to your board's\n" -- printf "flash chip will result in a non-booting system. You\n" -- printf "can use cbfstool to add a payload to the image.\n\n" -- - .PHONY: force-payload coreinfo nvramcui --.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload -+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch b/config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch deleted file mode 100644 index 3ee38c29..00000000 --- a/config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 261454e47783b973b088e9dbea47bda02758dcb4 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 22 Oct 2023 15:02:25 +0100 -Subject: [PATCH 6/9] don't use github for the acpica download - -i have the tarball from a previous download, and i placed -it on libreboot rsync, which then got mirrored to princeton. - -today, github's ssl cert was b0rking the hell out and i really -really wanted to finish a build, and didn't want to wait for -github to fix their httpd. - -so i'm now hosting this specific acpica tarball on rsync. - -this patch makes that URL be used, instead of the github one. - -that's the 2nd time i've had to patch coreboot's acpica download! - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/crossgcc/buildgcc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 23a5caf2bb..36565a906c 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" - MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" - GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" - BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" --IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" -+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" - # CLANG toolchain archive locations - LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" - CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch deleted file mode 100644 index ff481081..00000000 --- a/config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 622daa7c46de01530de60a7be32c8b9e48b356fd Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 5 Nov 2023 22:57:08 +0000 -Subject: [PATCH 7/9] use mirrorservice.org for gcc downloads - -the gnu.org 302 redirect often fails - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/crossgcc/buildgcc | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 36565a906c..4d4ca06113 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" - # to the jenkins build as well, or the builder won't download it. - - # GCC toolchain archive locations --GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" --MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" --MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" --GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" --BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" -+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp" -+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" -+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" -+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" -+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" - IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" - # CLANG toolchain archive locations - LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch deleted file mode 100644 index 8de8060f..00000000 --- a/config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ /dev/null @@ -1,223 +0,0 @@ -From f26df5dff7be4b0c9d8dced1cf6ed07472a174c7 Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 8/9] nb/intel/gm45: Make DDR2 raminit work - -List of changes: - - Update some timing and ODT values - - Patch RCOMP calibration to better match what MRC binaries do - - Replay a hardcoded list of RCOMP codes after RcvEn - -This makes raminit work at DDR2-800 speeds and fixes S3 resume as well. -Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs. - -Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - src/northbridge/intel/gm45/gm45.h | 2 +- - src/northbridge/intel/gm45/raminit.c | 90 +++++++++++++++++-- - .../intel/gm45/raminit_rcomp_calibration.c | 27 ++++-- - 3 files changed, 106 insertions(+), 13 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h -index d929533d92..997f8a0e5a 100644 ---- a/src/northbridge/intel/gm45/gm45.h -+++ b/src/northbridge/intel/gm45/gm45.h -@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); - int raminit_read_vco_index(void); - u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank); - --void raminit_rcomp_calibration(stepping_t stepping); -+void raminit_rcomp_calibration(int ddr_type, stepping_t stepping); - void raminit_reset_readwrite_pointers(void); - void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); - void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume); -diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index b7e013959a..df8f46fbbc 100644 ---- a/src/northbridge/intel/gm45/raminit.c -+++ b/src/northbridge/intel/gm45/raminit.c -@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping, - } - - /* Perform RCOMP calibration for DDR3. */ -- raminit_rcomp_calibration(stepping); -+ raminit_rcomp_calibration(spd_type, stepping); - - /* Run initial RCOMP. */ - mchbar_setbits32(0x418, 1 << 17); -@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi - reg = (reg & ~(0xf << 10)) | (2 << 10); - else - reg = (reg & ~(0xf << 10)) | (3 << 10); -- reg = (reg & ~(0x7 << 5)) | (3 << 5); -+ reg = (reg & ~(0x7 << 5)) | (2 << 5); - } else if (timings->mem_clock != MEM_CLOCK_1067MT) { - reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); - reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); -@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff) - reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32)); - reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32)); - if (timings->mem_clock == MEM_CLOCK_667MT) { -- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32)); -- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32)); -+ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32)); -+ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32)); - } else { -- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32)); -- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32)); -+ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32)); -+ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32)); - } - mchbar_write32(CxODT_HIGH(ch), reg); - -@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) - raminit_write_training(timings->mem_clock, dimms, s3resume); - } - -+ /* -+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done -+ * after receiver enable calibration, otherwise raminit sometimes -+ * completes with non-working memory. -+ */ -+ mchbar_write32(0x0530, 0x06060005); -+ mchbar_write32(0x0680, 0x06060606); -+ mchbar_write32(0x0684, 0x08070606); -+ mchbar_write32(0x0688, 0x0e0e0c0a); -+ mchbar_write32(0x068c, 0x0e0e0e0e); -+ mchbar_write32(0x0698, 0x06060606); -+ mchbar_write32(0x069c, 0x08070606); -+ mchbar_write32(0x06a0, 0x0c0c0b0a); -+ mchbar_write32(0x06a4, 0x0c0c0c0c); -+ -+ mchbar_write32(0x06c0, 0x02020202); -+ mchbar_write32(0x06c4, 0x03020202); -+ mchbar_write32(0x06c8, 0x04040403); -+ mchbar_write32(0x06cc, 0x04040404); -+ mchbar_write32(0x06d8, 0x02020202); -+ mchbar_write32(0x06dc, 0x03020202); -+ mchbar_write32(0x06e0, 0x04040403); -+ mchbar_write32(0x06e4, 0x04040404); -+ -+ mchbar_write32(0x0700, 0x02020202); -+ mchbar_write32(0x0704, 0x03020202); -+ mchbar_write32(0x0708, 0x04040403); -+ mchbar_write32(0x070c, 0x04040404); -+ mchbar_write32(0x0718, 0x02020202); -+ mchbar_write32(0x071c, 0x03020202); -+ mchbar_write32(0x0720, 0x04040403); -+ mchbar_write32(0x0724, 0x04040404); -+ -+ mchbar_write32(0x0740, 0x02020202); -+ mchbar_write32(0x0744, 0x03020202); -+ mchbar_write32(0x0748, 0x04040403); -+ mchbar_write32(0x074c, 0x04040404); -+ mchbar_write32(0x0758, 0x02020202); -+ mchbar_write32(0x075c, 0x03020202); -+ mchbar_write32(0x0760, 0x04040403); -+ mchbar_write32(0x0764, 0x04040404); -+ -+ mchbar_write32(0x0780, 0x06060606); -+ mchbar_write32(0x0784, 0x09070606); -+ mchbar_write32(0x0788, 0x0e0e0c0b); -+ mchbar_write32(0x078c, 0x0e0e0e0e); -+ mchbar_write32(0x0798, 0x06060606); -+ mchbar_write32(0x079c, 0x09070606); -+ mchbar_write32(0x07a0, 0x0d0d0c0b); -+ mchbar_write32(0x07a4, 0x0d0d0d0d); -+ -+ mchbar_write32(0x07c0, 0x06060606); -+ mchbar_write32(0x07c4, 0x09070606); -+ mchbar_write32(0x07c8, 0x0e0e0c0b); -+ mchbar_write32(0x07cc, 0x0e0e0e0e); -+ mchbar_write32(0x07d8, 0x06060606); -+ mchbar_write32(0x07dc, 0x09070606); -+ mchbar_write32(0x07e0, 0x0d0d0c0b); -+ mchbar_write32(0x07e4, 0x0d0d0d0d); -+ -+ mchbar_write32(0x0840, 0x06060606); -+ mchbar_write32(0x0844, 0x08070606); -+ mchbar_write32(0x0848, 0x0e0e0c0a); -+ mchbar_write32(0x084c, 0x0e0e0e0e); -+ mchbar_write32(0x0858, 0x06060606); -+ mchbar_write32(0x085c, 0x08070606); -+ mchbar_write32(0x0860, 0x0c0c0b0a); -+ mchbar_write32(0x0864, 0x0c0c0c0c); -+ -+ mchbar_write32(0x0880, 0x02020202); -+ mchbar_write32(0x0884, 0x03020202); -+ mchbar_write32(0x0888, 0x04040403); -+ mchbar_write32(0x088c, 0x04040404); -+ mchbar_write32(0x0898, 0x02020202); -+ mchbar_write32(0x089c, 0x03020202); -+ mchbar_write32(0x08a0, 0x04040403); -+ mchbar_write32(0x08a4, 0x04040404); -+ - igd_compute_ggc(sysinfo); - - /* Program final memory map (with real values). */ -diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -index aef863f05a..b74765fd9c 100644 ---- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step, - mchbar += 4; - } - } --void raminit_rcomp_calibration(const stepping_t stepping) { -+void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { - const int a1step = stepping >= STEPPING_CONVERSION_A1; - - int i; - -+ char magic_comp[2] = {0}; -+ - enum { - PULL_UP = 0, - PULL_DOWN = 1, -@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) { - reg = mchbar_read32(0x518); - lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; - lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; -+ if (i == 1) { -+ magic_comp[0] = (reg >> 8) & 0x3f; -+ magic_comp[1] = (reg >> 0) & 0x3f; -+ } - } - /* Cleanup? */ - mchbar_setbits32(0x400, 1 << 3); -@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) { - for (channel = 0; channel < 2; ++channel) { - for (group = 0; group < 6; ++group) { - for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) { -- lookup_and_write( -- a1step, -- lut_idx[channel][group][pu_pd] - 7, -- ddr3_lookup_schedule[group][pu_pd], -- mchbar); -+ if (ddr_type == DDR3) { -+ lookup_and_write( -+ a1step, -+ lut_idx[channel][group][pu_pd] - 7, -+ ddr3_lookup_schedule[group][pu_pd], -+ mchbar); -+ } - mchbar += 0x0018; - } -+ if (ddr_type == DDR2) { -+ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24); -+ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0); -+ } - mchbar += 0x0010; - /* Channel B knows only the first two groups. */ - if ((1 == channel) && (1 == group)) -@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) { - } - mchbar += 0x0040; - } -+ -+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); -+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); - } --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch b/config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch deleted file mode 100644 index 8d48bfd9..00000000 --- a/config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch +++ /dev/null @@ -1,23 +0,0 @@ -From f318da0563ecb2386ac368e04bad88a8aacbc83d Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Wed, 1 Nov 2023 16:33:11 +0000 -Subject: [PATCH 9/9] dell/e6400: crank up vram to 256MB (max) - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - src/mainboard/dell/e6400/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default -index eeb6f47364..25dfa38cb5 100644 ---- a/src/mainboard/dell/e6400/cmos.default -+++ b/src/mainboard/dell/e6400/cmos.default -@@ -2,4 +2,4 @@ boot_option=Fallback - debug_level=Debug - power_on_after_fail=Disable - sata_mode=AHCI --gfx_uma_size=32M -+gfx_uma_size=256M --- -2.39.2 - diff --git a/config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch deleted file mode 100644 index f64743a5..00000000 --- a/config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 6f4968919cf4e801caacf8392492457b79efa9c6 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH] mb/dell/e6400: Use 100 MHz reference clock for display - -The E6400 uses a 100 MHz reference clock for spread spectrum support on -LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For -the more common 1280 x 800 display panels, the numerical error was not -large enough to cause noticable issues, but the actual pixel clock -frequency derived from a 100 MHz reference using PLL configs calculated -assuming a 96 MHz reference was not close enough for 1440 x 900 panels, -which require a much higher pixel clock. This resulted in a garbled -display in the pre-OS graphics environment provided by libgfxinit. - -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e6400/Kconfig | 3 +++ - src/northbridge/intel/gm45/Kconfig | 4 ++++ - 2 files changed, 7 insertions(+) - -diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig -index 034de4be2b..4cb16af697 100644 ---- a/src/mainboard/dell/e6400/Kconfig -+++ b/src/mainboard/dell/e6400/Kconfig -@@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS - select INTEL_GMA_HAVE_VBT - select EC_DELL_MEC5035 - -+config INTEL_GMA_DPLL_REF_FREQ -+ default 100000000 -+ - config MAINBOARD_DIR - default "dell/e6400" - -diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index 2a266b9771..2432c9d78e 100644 ---- a/src/northbridge/intel/gm45/Kconfig -+++ b/src/northbridge/intel/gm45/Kconfig -@@ -13,6 +13,10 @@ config NORTHBRIDGE_INTEL_GM45 - - if NORTHBRIDGE_INTEL_GM45 - -+config INTEL_GMA_DPLL_REF_FREQ -+ int -+ default 96000000 -+ - config VBOOT - select VBOOT_STARTS_IN_BOOTBLOCK - --- -2.45.1 - |