diff options
Diffstat (limited to 'config/coreboot/default')
| -rw-r--r-- | config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch | 44 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch | 1097 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch (renamed from config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch (renamed from config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch (renamed from config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch (renamed from config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch) | 24 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch (renamed from config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch (renamed from config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch (renamed from config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch (renamed from config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch (renamed from config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch (renamed from config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch) | 21 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch (renamed from config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch (renamed from config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch (renamed from config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch (renamed from config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch) | 39 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch (renamed from config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch) | 6 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch (renamed from config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch (renamed from config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch (renamed from config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch (renamed from config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch (renamed from config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch (renamed from config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch (renamed from config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch (renamed from config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch (renamed from config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch (renamed from config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch (renamed from config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch (renamed from config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch (renamed from config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch (renamed from config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch (renamed from config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch (renamed from config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch (renamed from config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch) | 6 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch (renamed from config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch (renamed from config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch) | 6 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch (renamed from config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch (renamed from config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch (renamed from config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch (renamed from config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0041-fix-ifdtool-build.patch (renamed from config/coreboot/default/patches/0040-fix-ifdtool-build.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch (renamed from config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch (renamed from config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch (renamed from config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch (renamed from config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch) | 8 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch (renamed from config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch) | 6 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0047-util-ifdtool-option-to-allow-region-override.patch (renamed from config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch) | 26 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch (renamed from config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch) | 4 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0049-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch (renamed from config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch) | 12 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch (renamed from config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch) | 61 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch (renamed from config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch) | 60 | ||||
| -rw-r--r-- | config/coreboot/default/patches/0051-mb-supermicro-x11-lga1151-series-Enable-SATA-hotplug.patch | 46 | ||||
| -rw-r--r-- | config/coreboot/default/target.cfg | 2 |
53 files changed, 1355 insertions, 297 deletions
diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index b654b32c..5fc4b8b5 100644 --- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,30 +1,30 @@ -From 03e8f5f33723fd291e30c5305fa2f5eb22bdf656 Mon Sep 17 00:00:00 2001 +From 11f759cb05a4d9f4656982a8afea40d7dadfb93e Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 01/48] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/51] add c3 and clockgen to apple/macbook21 --- - src/mainboard/apple/macbook21/Kconfig | 1 + - src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++ - src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++ + src/mainboard/apple/i945_macs/Kconfig | 1 + + src/mainboard/apple/i945_macs/cstates.c | 13 +++++++++++++ + src/mainboard/apple/i945_macs/devicetree.cb | 6 ++++++ 3 files changed, 20 insertions(+) -diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig -index 330d8efae2..cf10343554 100644 ---- a/src/mainboard/apple/macbook21/Kconfig -+++ b/src/mainboard/apple/macbook21/Kconfig -@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS - select HAVE_ACPI_TABLES - select HAVE_ACPI_RESUME +diff --git a/src/mainboard/apple/i945_macs/Kconfig b/src/mainboard/apple/i945_macs/Kconfig +index 42774e484a..cd5155e81a 100644 +--- a/src/mainboard/apple/i945_macs/Kconfig ++++ b/src/mainboard/apple/i945_macs/Kconfig +@@ -20,6 +20,7 @@ config BOARD_APPLE_MACBOOK11 + bool + select BOARD_APPLE_I945_MACS_COMMON select I945_LVDS + select DRIVERS_I2C_CK505 - config MAINBOARD_DIR - default "apple/macbook21" -diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c + config BOARD_APPLE_MACBOOK21 + bool +diff --git a/src/mainboard/apple/i945_macs/cstates.c b/src/mainboard/apple/i945_macs/cstates.c index 13d06f0839..88b8669c61 100644 ---- a/src/mainboard/apple/macbook21/cstates.c -+++ b/src/mainboard/apple/macbook21/cstates.c +--- a/src/mainboard/apple/i945_macs/cstates.c ++++ b/src/mainboard/apple/i945_macs/cstates.c @@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = { .addrh = 0, } @@ -45,11 +45,11 @@ index 13d06f0839..88b8669c61 100644 }; int get_cst_entries(const acpi_cstate_t **entries) -diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb -index fd86e939b9..263fbabcd1 100644 ---- a/src/mainboard/apple/macbook21/devicetree.cb -+++ b/src/mainboard/apple/macbook21/devicetree.cb -@@ -100,7 +100,13 @@ chip northbridge/intel/i945 +diff --git a/src/mainboard/apple/i945_macs/devicetree.cb b/src/mainboard/apple/i945_macs/devicetree.cb +index b17f8ae529..18731b067f 100644 +--- a/src/mainboard/apple/i945_macs/devicetree.cb ++++ b/src/mainboard/apple/i945_macs/devicetree.cb +@@ -89,7 +89,13 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x8086 0x7270 diff --git a/config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch b/config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch new file mode 100644 index 00000000..d905e5cf --- /dev/null +++ b/config/coreboot/default/patches/0002-Revert-mb-lenovo-t430-Merge-into-t430-into-t530.patch @@ -0,0 +1,1097 @@ +From 3c5b15f0aa0ba2c9e7d4db6f893e13978c045032 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Thu, 23 Apr 2026 20:00:33 +0100 +Subject: [PATCH 02/51] Revert "mb/lenovo/t430: Merge into t430 into t530" + +This reverts commit 091ae533b9fdb5b78a5edbc2b68c2faee083f1dd. +--- + src/mainboard/lenovo/t430/Kconfig | 80 +++++++++ + src/mainboard/lenovo/t430/Kconfig.name | 4 + + src/mainboard/lenovo/t430/Makefile.mk | 8 + + src/mainboard/lenovo/t430/acpi/ec.asl | 4 + + src/mainboard/lenovo/t430/acpi/platform.asl | 23 +++ + src/mainboard/lenovo/t430/acpi/superio.asl | 3 + + src/mainboard/lenovo/t430/acpi_tables.c | 15 ++ + src/mainboard/lenovo/t430/board_info.txt | 6 + + src/mainboard/lenovo/t430/cmos.default | 20 +++ + src/mainboard/lenovo/t430/cmos.layout | 108 ++++++++++++ + .../lenovo/{t530/variants => }/t430/data.vbt | Bin + src/mainboard/lenovo/t430/devicetree.cb | 166 ++++++++++++++++++ + src/mainboard/lenovo/t430/dsdt.asl | 39 ++++ + src/mainboard/lenovo/t430/early_init.c | 40 +++++ + src/mainboard/lenovo/t430/gma-mainboard.ads | 22 +++ + .../lenovo/{t530/variants => }/t430/gpio.c | 0 + .../{t530/variants => }/t430/hda_verb.c | 0 + src/mainboard/lenovo/t430/mainboard.c | 15 ++ + src/mainboard/lenovo/t430/smihandler.c | 68 +++++++ + .../lenovo/t430/vboot-ro-me_clean.fmd | 21 +++ + src/mainboard/lenovo/t430/vboot-ro.fmd | 21 +++ + src/mainboard/lenovo/t430/vboot-rwab.fmd | 35 ++++ + src/mainboard/lenovo/t530/Kconfig | 7 - + src/mainboard/lenovo/t530/Kconfig.name | 3 - + src/mainboard/lenovo/t530/Makefile.mk | 1 - + .../t530/{variants/t530 => }/hda_verb.c | 0 + .../lenovo/t530/variants/t430/overridetree.cb | 58 ------ + .../lenovo/t530/variants/w530/hda_verb.c | 75 -------- + 28 files changed, 698 insertions(+), 144 deletions(-) + create mode 100644 src/mainboard/lenovo/t430/Kconfig + create mode 100644 src/mainboard/lenovo/t430/Kconfig.name + create mode 100644 src/mainboard/lenovo/t430/Makefile.mk + create mode 100644 src/mainboard/lenovo/t430/acpi/ec.asl + create mode 100644 src/mainboard/lenovo/t430/acpi/platform.asl + create mode 100644 src/mainboard/lenovo/t430/acpi/superio.asl + create mode 100644 src/mainboard/lenovo/t430/acpi_tables.c + create mode 100644 src/mainboard/lenovo/t430/board_info.txt + create mode 100644 src/mainboard/lenovo/t430/cmos.default + create mode 100644 src/mainboard/lenovo/t430/cmos.layout + rename src/mainboard/lenovo/{t530/variants => }/t430/data.vbt (100%) + create mode 100644 src/mainboard/lenovo/t430/devicetree.cb + create mode 100644 src/mainboard/lenovo/t430/dsdt.asl + create mode 100644 src/mainboard/lenovo/t430/early_init.c + create mode 100644 src/mainboard/lenovo/t430/gma-mainboard.ads + rename src/mainboard/lenovo/{t530/variants => }/t430/gpio.c (100%) + rename src/mainboard/lenovo/{t530/variants => }/t430/hda_verb.c (100%) + create mode 100644 src/mainboard/lenovo/t430/mainboard.c + create mode 100644 src/mainboard/lenovo/t430/smihandler.c + create mode 100644 src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd + create mode 100644 src/mainboard/lenovo/t430/vboot-ro.fmd + create mode 100644 src/mainboard/lenovo/t430/vboot-rwab.fmd + rename src/mainboard/lenovo/t530/{variants/t530 => }/hda_verb.c (100%) + delete mode 100644 src/mainboard/lenovo/t530/variants/t430/overridetree.cb + delete mode 100644 src/mainboard/lenovo/t530/variants/w530/hda_verb.c + +diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig +new file mode 100644 +index 0000000000..2b6eb17e9c +--- /dev/null ++++ b/src/mainboard/lenovo/t430/Kconfig +@@ -0,0 +1,80 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++if BOARD_LENOVO_THINKPAD_T430 ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select AZALIA_USE_LEGACY_VERB_TABLE ++ select BOARD_ROMSIZE_KB_12288 ++ select DRIVERS_LENOVO_HYBRID_GRAPHICS ++ select DRIVER_LENOVO_SERIALS ++ select DRIVER_LENOVO_SERIALS_EARLY_LOCK ++ select DRIVERS_RICOH_RCE822 ++ select EC_LENOVO_H8 ++ select EC_LENOVO_PMH7 ++ select GFX_GMA_PANEL_1_ON_LVDS ++ select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION ++ select H8_HAS_WWAN_GPIO_DETECTION ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT ++ select INTEL_INT15 ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_HAS_TPM1 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select MEMORY_MAPPED_TPM ++ select NO_UART_ON_SUPERIO ++ select NORTHBRIDGE_INTEL_SANDYBRIDGE ++ select SERIRQ_CONTINUOUS_MODE ++ select SOUTHBRIDGE_INTEL_C216 ++ select SYSTEM_TYPE_LAPTOP ++ select USE_NATIVE_RAMINIT ++ ++config VBOOT ++ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC ++ select GBB_FLAG_DISABLE_FWMP ++ select GBB_FLAG_DISABLE_LID_SHUTDOWN ++ select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC ++ select HAS_RECOVERY_MRC_CACHE ++ select VBOOT_VBNV_FLASH ++ ++config VBOOT_SLOTS_RW_AB ++ default y ++ ++config CBFS_SIZE ++ default 0x700000 ++ ++config FMDFILE ++ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT ++ ++config MAINBOARD_DIR ++ default "lenovo/t430" ++ ++config MAINBOARD_PART_NUMBER ++ default "ThinkPad T430" ++ ++config VGA_BIOS_ID ++ string ++ default "8086,0166" ++ ++config DRAM_RESET_GATE_GPIO ++ int ++ default 10 ++ ++config USBDEBUG_HCD_INDEX ++ int ++ default 2 ++ ++config PS2K_EISAID ++ default "PNP0303" ++ ++config PS2M_EISAID ++ default "LEN0015" ++ ++config THINKPADEC_HKEY_EISAID ++ default "LEN0068" ++ ++endif +diff --git a/src/mainboard/lenovo/t430/Kconfig.name b/src/mainboard/lenovo/t430/Kconfig.name +new file mode 100644 +index 0000000000..f14a1a2d78 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_LENOVO_THINKPAD_T430 ++ bool "ThinkPad T430" +diff --git a/src/mainboard/lenovo/t430/Makefile.mk b/src/mainboard/lenovo/t430/Makefile.mk +new file mode 100644 +index 0000000000..e4b6fbf0f0 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/Makefile.mk +@@ -0,0 +1,8 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++bootblock-y += gpio.c ++romstage-y += gpio.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads ++bootblock-y += early_init.c ++romstage-y += early_init.c +diff --git a/src/mainboard/lenovo/t430/acpi/ec.asl b/src/mainboard/lenovo/t430/acpi/ec.asl +new file mode 100644 +index 0000000000..987593e919 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/acpi/ec.asl +@@ -0,0 +1,4 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <ec/lenovo/h8/acpi/ec.asl> ++#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl> +diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl +new file mode 100644 +index 0000000000..9dee90edc3 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/acpi/platform.asl +@@ -0,0 +1,23 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* The _PTS method (Prepare To Sleep) is called before the OS is ++ * entering a sleep state. The sleep state number is passed in Arg0 ++ */ ++ ++Method(_PTS,1) ++{ ++ \_SB.PCI0.LPCB.EC.MUTE(1) ++ \_SB.PCI0.LPCB.EC.USBP(0) ++ \_SB.PCI0.LPCB.EC.RADI(0) ++} ++ ++/* The _WAK method is called on system wakeup */ ++ ++Method(_WAK,1) ++{ ++ /* Wake the HKEY to init BT/WWAN */ ++ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) ++ ++ /* Not implemented. */ ++ Return(Package(){0,0}) ++} +diff --git a/src/mainboard/lenovo/t430/acpi/superio.asl b/src/mainboard/lenovo/t430/acpi/superio.asl +new file mode 100644 +index 0000000000..ee2eabeb75 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include <drivers/pc80/pc/ps2_controller.asl> +diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c +new file mode 100644 +index 0000000000..36d3e85c1e +--- /dev/null ++++ b/src/mainboard/lenovo/t430/acpi_tables.c +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <acpi/acpi_gnvs.h> ++#include <soc/nvs.h> ++ ++void mainboard_fill_gnvs(struct global_nvs *gnvs) ++{ ++ /* The lid is open by default */ ++ gnvs->lids = 1; ++ ++ /* Temperature at which OS will shutdown */ ++ gnvs->tcrt = 100; ++ /* Temperature at which OS will throttle CPU */ ++ gnvs->tpsv = 90; ++} +diff --git a/src/mainboard/lenovo/t430/board_info.txt b/src/mainboard/lenovo/t430/board_info.txt +new file mode 100644 +index 0000000000..09ddde1f85 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/board_info.txt +@@ -0,0 +1,6 @@ ++Category: laptop ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: n ++Release year: 2012 +diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default +new file mode 100644 +index 0000000000..4857f92f67 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/cmos.default +@@ -0,0 +1,20 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++volume=0x3 ++first_battery=Primary ++bluetooth=Enable ++wwan=Enable ++wlan=Enable ++touchpad=Enable ++sata_mode=AHCI ++fn_ctrl_swap=Disable ++sticky_fn=Disable ++trackpoint=Enable ++backlight=Both ++hybrid_graphics_mode=Integrated Only ++usb_always_on=Disable ++me_state=Normal +diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout +new file mode 100644 +index 0000000000..d109a61b4e +--- /dev/null ++++ b/src/mainboard/lenovo/t430/cmos.layout +@@ -0,0 +1,108 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++#400 8 r 0 reserved for century byte ++ ++# coreboot config options: southbridge ++408 1 e 1 nmi ++409 2 e 7 power_on_after_fail ++ ++# coreboot config options: EC ++411 1 e 8 first_battery ++412 1 e 1 bluetooth ++413 1 e 1 wwan ++414 1 e 1 touchpad ++415 1 e 1 wlan ++416 1 e 1 trackpoint ++417 1 e 1 fn_ctrl_swap ++418 1 e 1 sticky_fn ++419 2 e 13 usb_always_on ++421 1 e 9 sata_mode ++422 2 e 10 backlight ++ ++# coreboot config options: ME ++424 1 e 14 me_state ++425 2 h 0 me_state_prev ++ ++# coreboot config options: northbridge ++432 3 e 11 gfx_uma_size ++435 2 e 12 hybrid_graphics_mode ++ ++440 8 h 0 volume ++ ++# VBOOT ++448 128 r 0 vbnv ++ ++# SandyBridge MRC Scrambler Seed values ++896 32 r 0 mrc_scrambler_seed ++928 32 r 0 mrc_scrambler_seed_s3 ++960 16 r 0 mrc_scrambler_seed_chk ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++8 0 Secondary ++8 1 Primary ++9 0 AHCI ++9 1 Compatible ++10 0 Both ++10 1 Keyboard only ++10 2 Thinklight only ++10 3 None ++11 0 32M ++11 1 64M ++11 2 96M ++11 3 128M ++11 4 160M ++11 5 192M ++11 6 224M ++12 0 Integrated Only ++12 1 Discrete Only ++12 2 Dual Graphics ++13 0 Disable ++13 1 AC and battery ++13 2 AC only ++14 0 Normal ++14 1 Disabled ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 447 984 +diff --git a/src/mainboard/lenovo/t530/variants/t430/data.vbt b/src/mainboard/lenovo/t430/data.vbt +similarity index 100% +rename from src/mainboard/lenovo/t530/variants/t430/data.vbt +rename to src/mainboard/lenovo/t430/data.vbt +diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb +new file mode 100644 +index 0000000000..198900b399 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/devicetree.cb +@@ -0,0 +1,166 @@ ++chip northbridge/intel/sandybridge ++ register "gfx" = "GMA_STATIC_DISPLAYS(1)" ++ ++ # Enable DisplayPort Hotplug with 6ms pulse ++ register "gpu_dp_d_hotplug" = "0x06" ++ ++ # Enable Panel as LVDS and configure power delays ++ register "gpu_panel_port_select" = "PANEL_PORT_LVDS" ++ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms ++ register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms ++ register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms ++ register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms ++ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms ++ register "gpu_cpu_backlight" = "0x1155" ++ register "gpu_pch_backlight" = "0x11551155" ++ ++ register "spd_addresses" = "{0x50, 0, 0x51, 0}" ++ ++ device domain 0 on ++ subsystemid 0x17aa 0x21f3 inherit ++ ++ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH ++ register "docking_supported" = "true" ++ register "gen1_dec" = "0x000c15e1" ++ register "gen2_dec" = "0x007c1601" ++ register "gen3_dec" = "0x000c06a1" ++ register "gpi13_routing" = "2" ++ register "gpi1_routing" = "2" ++ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" ++ register "pcie_port_coalesce" = "true" ++ register "sata_interface_speed_support" = "0x3" ++ register "sata_port_map" = "0x17" ++ ++ # Do not enable xHCI Port 4 since WWAN USB is EHCI-only ++ register "superspeed_capable_ports" = "0x7" ++ register "xhci_switchable_ports" = "0x7" ++ register "usb_port_config" = "{ ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 2, 3 }, ++ { 1, 1, -1 }, ++ { 1, 1, 2 }, ++ { 1, 0, -1 }, ++ { 0, 0, -1 }, ++ { 1, 2, -1 }, ++ { 1, 0, -1 }, ++ { 1, 1, 5 }, ++ { 1, 0, -1 }, ++ { 1, 0, -1 }, ++ { 1, 3, -1 }, ++ { 1, 1, -1 } ++ }" ++ ++ # device specific SPI configuration ++ register "spi_uvscc" = "0x2005" ++ register "spi_lvscc" = "0x2005" ++ ++ device ref xhci on end # USB 3.0 Controller ++ device ref mei1 on end # Management Engine Interface 1 ++ device ref mei2 off end # Management Engine Interface 2 ++ device ref me_ide_r off end # Management Engine IDE-R ++ device ref me_kt off end # Management Engine KT ++ device ref gbe on end # Intel Gigabit Ethernet ++ device ref ehci2 on end # USB2 EHCI #2 ++ device ref hda on end # High Definition Audio controller ++ device ref pcie_rp1 on # PCIe Port #1 ++ chip drivers/ricoh/rce822 # Ricoh cardreader ++ register "disable_mask" = "0x87" ++ register "sdwppol" = "1" ++ device pci 00.0 on end # Ricoh SD card reader ++ end ++ end ++ device ref pcie_rp2 on end # PCIe Port #2 ++ device ref pcie_rp3 on # PCIe Port #3 ++ smbios_slot_desc "7" "3" "ExpressCard Slot" "8" ++ end ++ device ref pcie_rp4 off end # PCIe Port #4 ++ device ref pcie_rp5 off end # PCIe Port #5 ++ device ref pcie_rp6 off end # PCIe Port #6 ++ device ref pcie_rp7 off end # PCIe Port #7 ++ device ref pcie_rp8 off end # PCIe Port #8 ++ device ref ehci1 on end # USB2 EHCI #1 ++ device ref pci_bridge off end # PCI bridge ++ device ref lpc on # LPC bridge PCI-LPC bridge ++ chip ec/lenovo/pmh7 ++ register "backlight_enable" = "true" ++ register "dock_event_enable" = "true" ++ device pnp ff.1 on end # dummy ++ end ++ chip drivers/pc80/tpm ++ device pnp 0c31.0 on end ++ end ++ chip ec/lenovo/h8 ++ device pnp ff.2 on # dummy ++ io 0x60 = 0x62 ++ io 0x62 = 0x66 ++ io 0x64 = 0x1600 ++ io 0x66 = 0x1604 ++ end ++ register "config0" = "0xa7" ++ register "config1" = "0x01" ++ register "config2" = "0xa0" ++ register "config3" = "0xe2" ++ ++ register "has_keyboard_backlight" = "0" ++ ++ register "beepmask0" = "0x02" ++ register "beepmask1" = "0x86" ++ register "has_power_management_beeps" = "1" ++ register "event2_enable" = "0xff" ++ register "event3_enable" = "0xff" ++ register "event4_enable" = "0xf0" ++ register "event5_enable" = "0x3c" ++ register "event6_enable" = "0x00" ++ register "event7_enable" = "0xa1" ++ register "event8_enable" = "0x7b" ++ register "event9_enable" = "0xff" ++ register "eventa_enable" = "0x00" ++ register "eventb_enable" = "0x00" ++ register "eventc_enable" = "0xff" ++ register "eventd_enable" = "0xff" ++ register "evente_enable" = "0x0d" ++ ++ register "bdc_gpio_num" = "54" ++ register "bdc_gpio_lvl" = "0" ++ ++ register "wwan_gpio_num" = "70" ++ register "wwan_gpio_lvl" = "0" ++ end ++ chip drivers/lenovo/hybrid_graphics ++ device pnp ff.f on end # dummy ++ ++ register "detect_gpio" = "21" ++ ++ register "has_panel_hybrid_gpio" = "true" ++ register "panel_hybrid_gpio" = "52" ++ register "panel_integrated_lvl" = "true" ++ ++ register "has_backlight_gpio" = "false" ++ register "has_dgpu_power_gpio" = "false" ++ ++ register "has_thinker1" = "true" ++ end ++ end ++ device ref sata1 on end # SATA Controller 1 ++ device ref smbus on # SMBus ++ chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip ++ device i2c 54 on end ++ device i2c 55 on end ++ device i2c 56 on end ++ device i2c 57 on end ++ device i2c 5c on end ++ device i2c 5d on end ++ device i2c 5e on end ++ device i2c 5f on end ++ end ++ end ++ device ref sata2 off end # SATA Controller 2 ++ device ref thermal off end # Thermal ++ end ++ device ref host_bridge on end # Host bridge Host bridge ++ device ref peg10 on end # PCIe Bridge for discrete graphics ++ device ref igd on end # Internal graphics VGA controller ++ device ref dev4 off end # Signal processing controller ++ end ++end +diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl +new file mode 100644 +index 0000000000..1134782675 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/dsdt.asl +@@ -0,0 +1,39 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#define THINKPAD_EC_GPE 17 ++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB ++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB ++ ++#include <acpi/acpi.h> ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20110725 // OEM revision ++) ++{ ++ #include <acpi/dsdt_top.asl> ++ #include <southbridge/intel/common/acpi/platform.asl> ++ ++ #include "acpi/platform.asl" ++ ++ // global NVS and variables ++ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> ++ ++ #include <cpu/intel/common/acpi/cpu.asl> ++ ++ Scope (\_SB) { ++ Device (PCI0) ++ { ++ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> ++ #include <southbridge/intel/bd82x6x/acpi/pch.asl> ++ ++ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> ++ } ++ } ++ ++ #include <southbridge/intel/common/acpi/sleepstates.asl> ++ #include <ec/lenovo/h8/acpi/thinklight.asl> ++} +diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c +new file mode 100644 +index 0000000000..d982660856 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/early_init.c +@@ -0,0 +1,40 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/pci_ops.h> ++#include <device/pci_def.h> ++#include <ec/lenovo/pmh7/pmh7.h> ++#include <drivers/i2c/at24rf08c/lenovo.h> ++#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> ++#include <northbridge/intel/sandybridge/sandybridge.h> ++ ++static void hybrid_graphics_init(void) ++{ ++ bool peg, igd; ++ u32 reg32; ++ ++ early_hybrid_graphics(&igd, &peg); ++ ++ if (peg && igd) ++ return; ++ ++ /* Hide disabled devices */ ++ reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); ++ reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); ++ ++ if (peg) ++ reg32 |= DEVEN_PEG10; ++ ++ if (igd) ++ reg32 |= DEVEN_IGD; ++ else ++ /* Disable IGD VGA decode, no GTT or GFX stolen */ ++ pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); ++ ++ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); ++} ++ ++void mainboard_early_init(bool s3resume) ++{ ++ hybrid_graphics_init(); ++ lenovo_mainboard_eeprom_lock(); ++} +diff --git a/src/mainboard/lenovo/t430/gma-mainboard.ads b/src/mainboard/lenovo/t430/gma-mainboard.ads +new file mode 100644 +index 0000000000..3df1e37f3e +--- /dev/null ++++ b/src/mainboard/lenovo/t430/gma-mainboard.ads +@@ -0,0 +1,22 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP1, ++ DP2, ++ DP3, ++ HDMI1, ++ HDMI2, ++ HDMI3, ++ Analog, ++ LVDS, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/lenovo/t530/variants/t430/gpio.c b/src/mainboard/lenovo/t430/gpio.c +similarity index 100% +rename from src/mainboard/lenovo/t530/variants/t430/gpio.c +rename to src/mainboard/lenovo/t430/gpio.c +diff --git a/src/mainboard/lenovo/t530/variants/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c +similarity index 100% +rename from src/mainboard/lenovo/t530/variants/t430/hda_verb.c +rename to src/mainboard/lenovo/t430/hda_verb.c +diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c +new file mode 100644 +index 0000000000..50c944e341 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/mainboard.c +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/device.h> ++#include <drivers/intel/gma/int15.h> ++ ++static void mainboard_enable(struct device *dev) ++{ ++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, ++ GMA_INT15_PANEL_FIT_DEFAULT, ++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++}; +diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c +new file mode 100644 +index 0000000000..03c899e0d9 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/smihandler.c +@@ -0,0 +1,68 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <arch/io.h> ++#include <console/console.h> ++#include <cpu/x86/smm.h> ++#include <ec/acpi/ec.h> ++#include <ec/lenovo/h8/h8.h> ++#include <southbridge/intel/common/pmutil.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++#define GPE_EC_SCI 1 ++#define GPE_EC_WAKE 13 ++ ++static void mainboard_smi_handle_ec_sci(void) ++{ ++ u8 status = inb(EC_SC); ++ u8 event; ++ ++ if (!(status & EC_SCI_EVT)) ++ return; ++ ++ event = ec_query(); ++ printk(BIOS_DEBUG, "EC event %#02x\n", event); ++} ++ ++void mainboard_smi_gpi(u32 gpi_sts) ++{ ++ if (gpi_sts & (1 << GPE_EC_SCI)) ++ mainboard_smi_handle_ec_sci(); ++} ++ ++int mainboard_smi_apmc(u8 data) ++{ ++ switch (data) { ++ case APM_CNT_ACPI_ENABLE: ++ /* use 0x1600/0x1604 to prevent races with userspace */ ++ ec_set_ports(0x1604, 0x1600); ++ /* route EC_SCI to SCI */ ++ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); ++ /* discard all events, and enable attention */ ++ ec_write(0x80, 0x01); ++ break; ++ case APM_CNT_ACPI_DISABLE: ++ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't ++ provide a EC query function */ ++ ec_set_ports(0x66, 0x62); ++ /* route EC_SCI to SMI */ ++ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); ++ /* discard all events, and enable attention */ ++ ec_write(0x80, 0x01); ++ break; ++ default: ++ break; ++ } ++ return 0; ++} ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ if (slp_typ == 3) { ++ u8 ec_wake = ec_read(0x32); ++ /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ ++ if (ec_wake & 0x14) { ++ /* Redirect EC WAKE GPE to SCI. */ ++ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); ++ } ++ } ++} +diff --git a/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd +new file mode 100644 +index 0000000000..5101caa59c +--- /dev/null ++++ b/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd +@@ -0,0 +1,21 @@ ++FLASH 0xc00000 { ++ SI_ALL 0x20000 { ++ SI_DESC 0x1000 ++ SI_GBE 0x2000 ++ SI_ME ++ } ++ SI_BIOS 0xbe0000 { ++ UNIFIED_MRC_CACHE 0x20000 { ++ RECOVERY_MRC_CACHE 0x10000 ++ RW_MRC_CACHE 0x10000 ++ } ++ ++ WP_RO { ++ FMAP 0x800 ++ RO_FRID 0x40 ++ RO_PADDING 0x7c0 ++ GBB 0x1e000 ++ COREBOOT(CBFS) ++ } ++ } ++} +diff --git a/src/mainboard/lenovo/t430/vboot-ro.fmd b/src/mainboard/lenovo/t430/vboot-ro.fmd +new file mode 100644 +index 0000000000..027849bfe9 +--- /dev/null ++++ b/src/mainboard/lenovo/t430/vboot-ro.fmd +@@ -0,0 +1,21 @@ ++FLASH 0xc00000 { ++ SI_ALL 0x500000 { ++ SI_DESC 0x1000 ++ SI_GBE 0x2000 ++ SI_ME ++ } ++ SI_BIOS 0x700000 { ++ UNIFIED_MRC_CACHE 0x20000 { ++ RECOVERY_MRC_CACHE 0x10000 ++ RW_MRC_CACHE 0x10000 ++ } ++ ++ WP_RO { ++ FMAP 0x800 ++ RO_FRID 0x40 ++ RO_PADDING 0x7c0 ++ GBB 0x1e000 ++ COREBOOT(CBFS) ++ } ++ } ++} +diff --git a/src/mainboard/lenovo/t430/vboot-rwab.fmd b/src/mainboard/lenovo/t430/vboot-rwab.fmd +new file mode 100644 +index 0000000000..8819959dfe +--- /dev/null ++++ b/src/mainboard/lenovo/t430/vboot-rwab.fmd +@@ -0,0 +1,35 @@ ++FLASH 0xc00000 { ++ SI_ALL@0x0 0x500000 { ++ SI_DESC@0x0 0x1000 ++ SI_GBE@0x1000 0x2000 ++ SI_ME ++ } ++ SI_BIOS@0x500000 0x700000 { ++ RW_SECTION_A 0x280000 { ++ VBLOCK_A 0x10000 ++ FW_MAIN_A(CBFS) ++ RW_FWID_A 0x40 ++ } ++ RW_SECTION_B 0x280000 { ++ VBLOCK_B 0x10000 ++ FW_MAIN_B(CBFS) ++ RW_FWID_B 0x40 ++ } ++ UNIFIED_MRC_CACHE@0x500000 0x20000 { ++ RECOVERY_MRC_CACHE@0x0 0x10000 ++ RW_MRC_CACHE@0x10000 0x10000 ++ } ++ RW_VPD(PRESERVE) 0x1000 ++ SMMSTORE(PRESERVE)@0x521000 0x40000 ++ RW_NVRAM(PRESERVE)@0x561000 0x2000 ++ ++ WP_RO { ++ FMAP 0x800 ++ RO_FRID 0x40 ++ RO_PADDING 0x7c0 ++ RO_VPD(PRESERVE) 0x1000 ++ GBB 0x1e000 ++ COREBOOT(CBFS) ++ } ++ } ++} +diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig +index 4f0002f536..8830c39301 100644 +--- a/src/mainboard/lenovo/t530/Kconfig ++++ b/src/mainboard/lenovo/t530/Kconfig +@@ -38,10 +38,6 @@ config BOARD_LENOVO_W530 + select BOARD_LENOVO_BASEBOARD_T530 + select DRIVERS_RICOH_RCE822 + +-config BOARD_LENOVO_T430 +- select BOARD_LENOVO_BASEBOARD_T530 +- select DRIVERS_RICOH_RCE822 +- + if BOARD_LENOVO_BASEBOARD_T530 + + config VBOOT +@@ -64,7 +60,6 @@ config FMDFILE + config VARIANT_DIR + default "t530" if BOARD_LENOVO_T530 + default "w530" if BOARD_LENOVO_W530 +- default "t430" if BOARD_LENOVO_T430 + + config MAINBOARD_DIR + default "lenovo/t530" +@@ -75,7 +70,6 @@ config OVERRIDE_DEVICETREE + config MAINBOARD_PART_NUMBER + default "ThinkPad T530" if BOARD_LENOVO_T530 + default "ThinkPad W530" if BOARD_LENOVO_W530 +- default "ThinkPad T430" if BOARD_LENOVO_T430 + + config USBDEBUG_HCD_INDEX + int +@@ -90,7 +84,6 @@ config VGA_BIOS_ID + default "8086,0166" + + config PS2K_EISAID +- default "PNP0303" if BOARD_LENOVO_T430 + default "LEN0071" + + config PS2M_EISAID +diff --git a/src/mainboard/lenovo/t530/Kconfig.name b/src/mainboard/lenovo/t530/Kconfig.name +index 5b42bd2f89..d8b1925f65 100644 +--- a/src/mainboard/lenovo/t530/Kconfig.name ++++ b/src/mainboard/lenovo/t530/Kconfig.name +@@ -5,6 +5,3 @@ config BOARD_LENOVO_T530 + + config BOARD_LENOVO_W530 + bool "ThinkPad W530" +- +-config BOARD_LENOVO_T430 +- bool "ThinkPad T430" +diff --git a/src/mainboard/lenovo/t530/Makefile.mk b/src/mainboard/lenovo/t530/Makefile.mk +index 1c72bfe045..69ef08873b 100644 +--- a/src/mainboard/lenovo/t530/Makefile.mk ++++ b/src/mainboard/lenovo/t530/Makefile.mk +@@ -5,4 +5,3 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + bootblock-y += early_init.c + romstage-y += early_init.c +-ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +diff --git a/src/mainboard/lenovo/t530/variants/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c +similarity index 100% +rename from src/mainboard/lenovo/t530/variants/t530/hda_verb.c +rename to src/mainboard/lenovo/t530/hda_verb.c +diff --git a/src/mainboard/lenovo/t530/variants/t430/overridetree.cb b/src/mainboard/lenovo/t530/variants/t430/overridetree.cb +deleted file mode 100644 +index 72cc6b54e1..0000000000 +--- a/src/mainboard/lenovo/t530/variants/t430/overridetree.cb ++++ /dev/null +@@ -1,58 +0,0 @@ +-chip northbridge/intel/sandybridge +- register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms +- register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms +- +- register "spd_addresses" = "{0x50, 0, 0x51, 0}" +- device domain 0 on +- subsystemid 0x17aa 0x21f3 inherit +- chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH +- register "sata_interface_speed_support" = "0x3" +- register "sata_port_map" = "0x17" +- +- # Do not enable xHCI Port 4 since WWAN USB is EHCI-only +- register "superspeed_capable_ports" = "0x7" +- register "xhci_switchable_ports" = "0x7" +- register "usb_port_config" = "{ +- { 1, 1, 0 }, +- { 1, 1, 1 }, +- { 1, 2, 3 }, +- { 1, 1, -1 }, +- { 1, 1, 2 }, +- { 1, 0, -1 }, +- { 0, 0, -1 }, +- { 1, 2, -1 }, +- { 1, 0, -1 }, +- { 1, 1, 5 }, +- { 1, 0, -1 }, +- { 1, 0, -1 }, +- { 1, 3, -1 }, +- { 1, 1, -1 } +- }" +- +- device ref pcie_rp1 on # PCIe Port #1 +- chip drivers/ricoh/rce822 # Ricoh cardreader +- register "disable_mask" = "0x87" +- register "sdwppol" = "1" +- device pci 00.0 on end # Ricoh SD card reader +- end +- end +- device ref lpc on +- chip ec/lenovo/h8 +- device pnp ff.2 on end # dummy +- register "wwan_gpio_num" = "70" +- register "wwan_gpio_lvl" = "0" +- register "config1" = "0x01" +- register "config3" = "0xe2" +- register "has_keyboard_backlight" = "0" +- register "beepmask0" = "0x02" +- register "has_power_management_beeps" = "1" +- register "event4_enable" = "0xf0" +- register "event5_enable" = "0x3c" +- register "event7_enable" = "0xa1" +- register "eventa_enable" = "0x00" +- end +- end +- device ref thermal off end # Thermal +- end +- end +-end +diff --git a/src/mainboard/lenovo/t530/variants/w530/hda_verb.c b/src/mainboard/lenovo/t530/variants/w530/hda_verb.c +deleted file mode 100644 +index 564aff2d77..0000000000 +--- a/src/mainboard/lenovo/t530/variants/w530/hda_verb.c ++++ /dev/null +@@ -1,75 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +- +-/* Bits 31:28 - Codec Address */ +-/* Bits 27:20 - NID */ +-/* Bits 19:8 - Verb ID */ +-/* Bits 7:0 - Payload */ +- +-#include <device/azalia_device.h> +- +-const u32 cim_verb_data[] = { +- 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ +- 0x17aa21fa, /* Subsystem ID */ +- 18, /* Number of 4 dword sets */ +- AZALIA_SUBVENDOR(0, 0x17aa21fa), +- +- /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ +- AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), +- +- /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ +- AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), +- +- /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ +- AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), +- +- /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ +- AZALIA_PIN_CFG(0, 0x0d, 0x90170110), +- +- /* Not connected */ +- AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), +- +- /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ +- AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), +- AZALIA_PIN_CFG(0, 0x12, 0x90a60140), +- AZALIA_PIN_CFG(0, 0x14, 0x90170110), +- AZALIA_PIN_CFG(0, 0x15, 0x03211020), +- AZALIA_PIN_CFG(0, 0x18, 0x03a11830), +- AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), +- +- 0x01970804, +- 0x01870803, +- 0x01470740, +- 0x00970600, +- +- AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x1d, 0x40138205), +- AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), +- +- /* Misc entries */ +- 0x00370600, +- 0x00270600, +- 0x00b707C0, /* Enable PortB as Output with HP amp */ +- 0x00d70740, /* Enable PortD as Output */ +- 0x0017a200, /* Disable ClkEn of PortSenseTst */ +- 0x0017c621, /* Slave Port - Port A used as microphone input for +- combo Jack +- Master Port - Port B used for Jack Presence Detect +- Enable Combo Jack Detection */ +- 0x0017a208, /* Enable ClkEn of PortSenseTst */ +- 0x00170500, /* Set power state to D0 */ +- +- /* --- Codec #3 --- */ +- 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ +- 0x80860101, /* Subsystem ID */ +- 4, /* Number of 4 dword sets */ +- AZALIA_SUBVENDOR(3, 0x80860101), +- AZALIA_PIN_CFG(3, 0x05, 0x18560010), +- AZALIA_PIN_CFG(3, 0x06, 0x18560020), +- AZALIA_PIN_CFG(3, 0x07, 0x18560030), +-}; +- +-const u32 pc_beep_verbs[] = { +- 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +-}; +- +-AZALIA_ARRAY_SIZES; +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch index 20fff9eb..bad82d0f 100644 --- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0003-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From da742084f51bb7e97472605d6eff0726fd7a5863 Mon Sep 17 00:00:00 2001 +From 33b89af06765839c0f9a6e599789c520e794a22a Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 02/48] lenovo/t400: Enable all SATA ports +Subject: [PATCH 03/51] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index 8e814be3..2d4b145c 100644 --- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0004-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From 278c2a989c025c1b3a097966968c8d253c973a3e Mon Sep 17 00:00:00 2001 +From 6bf8a87bdea4b7d5876e20f734821e6496b51cb9 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 03/48] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 04/51] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch index 43830448..5ada54ef 100644 --- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0005-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From 63357b7f8c9da3a8d644542c70f50fc9bc77a8fc Mon Sep 17 00:00:00 2001 +From 05f20d18bf572ebe80875d506dd686efd3eb7e4e Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 04/48] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 05/51] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default @@ -50,13 +50,13 @@ index 6fd26c5fe3..27a62d07b3 100644 -me_state=Normal +me_state=Disabled diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default -index c896eadec1..6d1e172056 100644 +index 4857f92f67..ab1be1a678 100644 --- a/src/mainboard/lenovo/t430/cmos.default +++ b/src/mainboard/lenovo/t430/cmos.default @@ -17,4 +17,4 @@ trackpoint=Enable backlight=Both - usb_always_on=Disable hybrid_graphics_mode=Integrated Only + usb_always_on=Disable -me_state=Normal +me_state=Disabled diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default diff --git a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 8490157a..7b5c1a3d 100644 --- a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0006-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From 434136e0aca4839e449e3841a5e993688b4586f0 Mon Sep 17 00:00:00 2001 +From 68e1738c5a46181b1fd1fcd44fe314da297b95d0 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 05/48] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 06/51] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). @@ -20,10 +20,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 84 insertions(+), 32 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 0592785bf6..cab934c3a5 100644 +index 0b75db54bd..7f0c10bd0b 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c -@@ -2240,6 +2240,7 @@ static void print_usage(const char *name) +@@ -2252,6 +2252,7 @@ static void print_usage(const char *name) " tgl - Tiger Lake\n" " wbg - Wellsburg\n" " -S | --setpchstrap Write a PCH strap\n" @@ -31,7 +31,7 @@ index 0592785bf6..cab934c3a5 100644 " -V | --newvalue The new value to write into PCH strap specified by -S\n" " -T | --topswapsize Set the Top Swap Block Size PCH strap value\n" " Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n" -@@ -2251,6 +2252,60 @@ static void print_usage(const char *name) +@@ -2263,6 +2264,60 @@ static void print_usage(const char *name) "\n"); } @@ -92,7 +92,7 @@ index 0592785bf6..cab934c3a5 100644 int main(int argc, char *argv[]) { int opt, option_index = 0; -@@ -2258,6 +2313,7 @@ int main(int argc, char *argv[]) +@@ -2270,6 +2325,7 @@ int main(int argc, char *argv[]) int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; @@ -100,7 +100,7 @@ index 0592785bf6..cab934c3a5 100644 int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0; int mode_settopswapsize = 0; char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL; -@@ -2294,6 +2350,7 @@ int main(int argc, char *argv[]) +@@ -2306,6 +2362,7 @@ int main(int argc, char *argv[]) {"setpchstrap", 1, NULL, 'S'}, {"newvalue", 1, NULL, 'V'}, {"topswapsize", 1, NULL, 'T'}, @@ -108,7 +108,7 @@ index 0592785bf6..cab934c3a5 100644 {0, 0, 0, 0} }; -@@ -2343,35 +2400,8 @@ int main(int argc, char *argv[]) +@@ -2355,35 +2412,8 @@ int main(int argc, char *argv[]) region_fname++; // Descriptor, BIOS, ME, GbE, Platform // valid type? @@ -146,7 +146,7 @@ index 0592785bf6..cab934c3a5 100644 fprintf(stderr, "No such region type: '%s'\n\n", region_type_string); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); -@@ -2552,7 +2582,23 @@ int main(int argc, char *argv[]) +@@ -2564,7 +2594,23 @@ int main(int argc, char *argv[]) mode_settopswapsize = 1; top_swap_size_arg = optarg; break; @@ -171,7 +171,7 @@ index 0592785bf6..cab934c3a5 100644 print_version(); exit(EXIT_SUCCESS); break; -@@ -2571,7 +2617,8 @@ int main(int argc, char *argv[]) +@@ -2583,7 +2629,8 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + @@ -181,7 +181,7 @@ index 0592785bf6..cab934c3a5 100644 fprintf(stderr, "You may not specify more than one mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); -@@ -2580,7 +2627,8 @@ int main(int argc, char *argv[]) +@@ -2592,7 +2639,8 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 + mode_locked + mode_unlocked + mode_density + mode_altmedisable + @@ -191,7 +191,7 @@ index 0592785bf6..cab934c3a5 100644 fprintf(stderr, "You need to specify a mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); -@@ -2746,6 +2794,10 @@ int main(int argc, char *argv[]) +@@ -2758,6 +2806,10 @@ int main(int argc, char *argv[]) write_image(new_filename, image, size); } diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index 725c6380..bdab3fa6 100644 --- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0007-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From 91e4334541da6522d5a0bf5277ac478c891e7117 Mon Sep 17 00:00:00 2001 +From 6c626f71a4ec9f887d1b82da071011423a3fd24e Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 06/48] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 07/51] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch index e583accc..03401a8b 100644 --- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From 3ebe9e03ec563e5adb43337340fe973aa66a984a Mon Sep 17 00:00:00 2001 +From bd349e86429cd0e83bbd6251ec507f3273b80854 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 07/48] Remove warning for coreboot images built without a +Subject: [PATCH 08/51] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch index a450cb4e..158ff60b 100644 --- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0009-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From 0e2fa472354b2e68ffbfc01d5bb225ca9d8973f0 Mon Sep 17 00:00:00 2001 +From bd98f54b50b66d291641f88ec3169b9518855862 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 08/48] HACK: Disable coreboot related BL31 features +Subject: [PATCH 09/51] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. @@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation. 1 file changed, 3 deletions(-) diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk -index efd628fee7..6c4f3d702e 100644 +index 7310ce1c1f..b0a6ed1f84 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk -@@ -156,9 +156,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 +@@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 # Always enable crash reporting, even on a release build BL31_MAKEARGS += CRASH_REPORTING=1 diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch index d67bdf03..3451cc67 100644 --- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0010-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From f692cd96a4484b8e60bd112454d1bdbc3c689017 Mon Sep 17 00:00:00 2001 +From ae01730cad059bb3707b6d938a082dee9494bde5 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 09/48] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 10/51] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. diff --git a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index e01800af..c3fee8c7 100644 --- a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0011-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From 78db6c595ff816ad4344d541688605ae720a83c4 Mon Sep 17 00:00:00 2001 +From ae7d23355be8efbbe3a1216d8e28c30a07e2e0ef Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 10/48] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 11/51] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. diff --git a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index 235ee880..883590fc 100644 --- a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0012-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From beb9b1650fb3aec96544b683fbe53ee16584f3d8 Mon Sep 17 00:00:00 2001 +From 0d418d44f61dda7670cfe02226150c2e5d3d6308 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 11/48] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 12/51] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless @@ -34,8 +34,8 @@ Signed-off-by: Leah Rowe <info@minifree.org> src/mainboard/lenovo/haswell/cmos.layout | 3 +++ src/mainboard/supermicro/x10slm-f/cmos.default | 1 + src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++ - src/northbridge/intel/haswell/early_init.c | 5 +++++ - 14 files changed, 48 insertions(+) + src/northbridge/intel/haswell/early_init.c | 6 ++++++ + 14 files changed, 49 insertions(+) diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default index 01bf20ad16..dfc8b80fb0 100644 @@ -265,28 +265,29 @@ index 38ba87aa45..24d39e97ee 100644 checksums diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c -index e47deb5da6..1a7e0b1076 100644 +index 6a5ce53a40..5f07fa0b17 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c -@@ -5,6 +5,7 @@ - #include <device/mmio.h> +@@ -6,6 +6,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> + #include <types.h> +#include <option.h> #include "haswell.h" -@@ -157,6 +158,10 @@ static void haswell_setup_misc(void) - static void haswell_setup_iommu(void) +@@ -80,6 +81,11 @@ static void haswell_setup_misc(void) + static void northbridge_setup_iommu(void) { const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); + u8 enable_iommu = get_uint_option("iommu", 1); + + if (!enable_iommu) + return; - ++ if (capid0_a & VTD_DISABLE) return; + -- 2.47.3 diff --git a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch index 3e6b8085..a5eb5de2 100644 --- a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0013-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From 0f76a919522c9624c2b5df2a9c17525ab21bd6b9 Mon Sep 17 00:00:00 2001 +From 2bd978a08ffee969bbf61af8f145b9e6b050d321 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 12/48] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 13/51] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off diff --git a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index 56b61882..aa5483c8 100644 --- a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0014-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From df64f2825157226b98e002e746114e25b0047438 Mon Sep 17 00:00:00 2001 +From 1179f45055fffb383fffe806e313a315de7c4205 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 13/48] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 14/51] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I @@ -33,10 +33,10 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 3 insertions(+) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c -index f7fad3183d..1b188e92e1 100644 +index fc44a98a57..451147d082 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c -@@ -466,6 +466,9 @@ static void gma_func0_disable(struct device *dev) +@@ -655,6 +655,9 @@ static void gma_func0_disable(struct device *dev) { /* Disable VGA decode */ pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); diff --git a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index 722e895d..7cadcb56 100644 --- a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0015-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,7 +1,7 @@ -From fdf4774a6e80b1f94079abb346049113dfbf5241 Mon Sep 17 00:00:00 2001 +From 59b741bf1b74a2c4e108755fbfd1580894c7d783 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 14/48] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 15/51] ec/dell/mec5035: Add S3 suspend SMI handler This is necessary for S3 resume to work on SNB and newer Dell Latitude laptops. If a command isn't sent, the EC cuts power to the DIMMs, diff --git a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index ac672295..17cfdac2 100644 --- a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From 18216387e5c40ec3c80c63ec25e9b0c55a009cff Mon Sep 17 00:00:00 2001 +From 3c1416797f2deafbd6b56774d890706aaea3614f Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 15/48] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 16/51] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 @@ -18,28 +18,17 @@ on the 9020, so that users can install graphics cards easily. Signed-off-by: Leah Rowe <info@minifree.org> --- - src/northbridge/intel/haswell/early_init.c | 15 +++++++-------- - 1 file changed, 7 insertions(+), 8 deletions(-) + src/northbridge/intel/haswell/early_init.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c -index 1a7e0b1076..e9506ee830 100644 +index 5f07fa0b17..30660e3903 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c -@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void) - const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); - u8 enable_iommu = get_uint_option("iommu", 1); - -- if (!enable_iommu) -- return; -- - if (capid0_a & VTD_DISABLE) +@@ -86,15 +86,17 @@ static void northbridge_setup_iommu(void) + if (!enable_iommu) return; -- /* Setup BARs: zeroize top 32 bits; set enable bit */ -- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); -- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); -- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); -- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); + if (enable_iommu) { + /* Setup BARs: zeroize top 32 bits; set enable bit */ + mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); @@ -47,9 +36,19 @@ index 1a7e0b1076..e9506ee830 100644 + mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); + mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); + } ++ + if (capid0_a & VTD_DISABLE) + return; - /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ - u32 reg32; +- /* Setup BARs: zeroize top 32 bits; set enable bit */ +- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); +- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); +- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); +- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); +- + if (cpu_is_haswell()) { + /* + * Intel Document 492662 (Haswell System Agent BIOS Spec), Rev 1.6.0 -- 2.47.3 diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch index e7c8d0a9..6161d4f8 100644 --- a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0017-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From d797b9d19c6bc3224897000756caef29e98dd266 Mon Sep 17 00:00:00 2001 +From 4347eae3a819dff7b6715630208d4be74b8245e4 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 16/48] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 17/51] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values @@ -20,7 +20,7 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> 3 files changed, 106 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h -index f68bfdee7a..b76117bc3a 100644 +index 90ab570524..d537ef82af 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch index 51ba3ae7..04b00c86 100644 --- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ b/config/coreboot/default/patches/0018-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -1,7 +1,7 @@ -From e573065ac900d4decfd4dbd0a1464d82501ac3c5 Mon Sep 17 00:00:00 2001 +From 8effb91216e331655ab64bc0aa114a3b38baec9c Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 17/48] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards +Subject: [PATCH 18/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards We add this patch: diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index fdb225e8..8ed6a3f4 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/coreboot/default/patches/0019-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From 130a5ca25fbedb58e49b613e4a7cece715b545ae Mon Sep 17 00:00:00 2001 +From c7b85347f892432b31000c67efccc02c84d9394a Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 18/48] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 19/51] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch index b7af55b4..753e8c6f 100644 --- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ b/config/coreboot/default/patches/0020-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -1,7 +1,7 @@ -From 7641a4b9b91c385223026cd566e0ffc2a2aa0d8f Mon Sep 17 00:00:00 2001 +From 6d1cbaedc747afe4acd8b13240c56232ba870639 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 19/48] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ +Subject: [PATCH 20/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ set it to 96MHz. fixes the following build error when building for x4x boards e.g. gigabyte ga-g41m-es2l: diff --git a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch index c9603f71..7266646e 100644 --- a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -1,7 +1,7 @@ -From 36126c093a9b9e01d41f0a68977cd09070c3c276 Mon Sep 17 00:00:00 2001 +From bd1594c9025dbd84cdce4aac02152b809b67b108 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 20/48] mb/dell/gm45_latitudes: Add E4300 variant +Subject: [PATCH 21/51] mb/dell/gm45_latitudes: Add E4300 variant Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch index 238e4799..cc67346f 100644 --- a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -1,7 +1,7 @@ -From 4caca6e6e349fa1913df622081025ea53bfd136f Mon Sep 17 00:00:00 2001 +From 7fda207316f80a5bdffe428309df32a278d13c93 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 21/48] mb/dell: Add S3 SMI handler for Dell Latitudes +Subject: [PATCH 22/51] mb/dell: Add S3 SMI handler for Dell Latitudes Integrate the previously added mec5035_smi_sleep() function into mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. diff --git a/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch index deaefbfd..1205b3bf 100644 --- a/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch +++ b/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch @@ -1,7 +1,7 @@ -From 669ef0d2c72326134f64a4fe70f67220ec690c5e Mon Sep 17 00:00:00 2001 +From 8f5399ac24599f6d0f1912d46f253a91d67536cf Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 22/48] Disable compression on refcode insertion +Subject: [PATCH 23/51] Disable compression on refcode insertion Compression is not reliably reproducible. In an lbmk release context, this means we cannot rely on vendorfile insertion. @@ -14,10 +14,10 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.mk b/Makefile.mk -index 5fccb4a52d..c40e06c453 100644 +index dbad313911..8f541ad187 100644 --- a/Makefile.mk +++ b/Makefile.mk -@@ -1414,7 +1414,7 @@ endif +@@ -1432,7 +1432,7 @@ endif cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) $(CONFIG_CBFS_PREFIX)/refcode-type := stage diff --git a/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch index 3bb55c37..2d4b8dad 100644 --- a/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch +++ b/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch @@ -1,7 +1,7 @@ -From c7b136f1f4fa2bc1a783711b5a1ee82c5d9ce69f Mon Sep 17 00:00:00 2001 +From 1e3e9ea40f4b43b9ffbb390222d8c4a4a67dd332 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 23/48] nb/intel/*: Disable stack overflow debug options +Subject: [PATCH 24/51] nb/intel/*: Disable stack overflow debug options Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -52,10 +52,10 @@ index 35e89b0c88..c5456d0ddf 100644 + endif diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig -index c57f1ec380..0a5181b183 100644 +index d67cc14660..fa22e35ccb 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig -@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL +@@ -9,6 +9,15 @@ config NORTHBRIDGE_INTEL_HASWELL if NORTHBRIDGE_INTEL_HASWELL diff --git a/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch index 22061393..28df4126 100644 --- a/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ b/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -1,7 +1,7 @@ -From c15a0ef9b964e9df9a5578ed271af4f1c0419f38 Mon Sep 17 00:00:00 2001 +From d83715448c0f7467ddf94e5c0a53560c5ff3b86b Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 24/48] mb/dell: Add Optiplex 780 MT (x4x/ICH10) +Subject: [PATCH 25/51] mb/dell: Add Optiplex 780 MT (x4x/ICH10) Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch index c126ee58..8948aee7 100644 --- a/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch +++ b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -1,7 +1,7 @@ -From bfd5f6628a69d8704a84b30c4027149fe1b21efa Mon Sep 17 00:00:00 2001 +From 3a5fa257c1b74c6e9e3556147114fc7691dc9e49 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 25/48] mb/dell/optiplex_780: Add USFF variant +Subject: [PATCH 26/51] mb/dell/optiplex_780: Add USFF variant Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch index 4c693f65..1cbae3bf 100644 --- a/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch +++ b/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -1,7 +1,7 @@ -From 82f47133c20abc720f5d5fa8a54be465ebd95f28 Mon Sep 17 00:00:00 2001 +From 5573eeadf45023d49f09606c6219004e20ba4b3c Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:53:53 +0000 -Subject: [PATCH 26/48] src/intel/x4x: Disable stack overflow debug +Subject: [PATCH 27/51] src/intel/x4x: Disable stack overflow debug Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch index da5ae94d..d42b03fc 100644 --- a/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch +++ b/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -1,7 +1,7 @@ -From 5c4439fb513c315ef3effff19146b331c492fa9b Mon Sep 17 00:00:00 2001 +From 2973ad1738fb6c1ebd2a92d008e1cbd39c74abb2 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 22 Apr 2025 10:21:59 +0100 -Subject: [PATCH 27/48] hp/8300cmt: remove xhci_overcurrent_mapping +Subject: [PATCH 28/51] hp/8300cmt: remove xhci_overcurrent_mapping No longer needed, as per the following commit: diff --git a/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch index 52b49b36..fcfdf827 100644 --- a/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch +++ b/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch @@ -1,7 +1,7 @@ -From 71ec1f7a6480e72b77a567f8cc0c2673a5e7905f Mon Sep 17 00:00:00 2001 +From ff57e763d1f966584ac9b68fa1a1f204626a577b Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 11 Dec 2024 01:06:01 +0000 -Subject: [PATCH 28/48] dell/3050micro: disable nvme hotplug +Subject: [PATCH 29/51] dell/3050micro: disable nvme hotplug in my testing, when running my 3050micro for a few days, the nvme would sometimes randomly rename. diff --git a/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch index 78ccf785..695a03a7 100644 --- a/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ b/config/coreboot/default/patches/0030-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -1,7 +1,7 @@ -From 95a0af0eea56e1bddcb243ed135835448b90fa56 Mon Sep 17 00:00:00 2001 +From 7c4df892425e076b1d2768f9b99362f58e7872dc Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 29/48] src/intel/skylake: Disable stack overflow debug options +Subject: [PATCH 30/51] src/intel/skylake: Disable stack overflow debug options The option was appearing in T480/3050micro configs of lbmk, after updating on the coreboot/next uprev for 20241206 rev8: @@ -37,10 +37,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 7c530f2c75..70c2a7643c 100644 +index c76239936a..f8ff8cfa7a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig -@@ -131,6 +131,15 @@ config DCACHE_RAM_SIZE +@@ -136,6 +136,15 @@ config DCACHE_RAM_SIZE The size of the cache-as-ram region required during bootblock and/or romstage. diff --git a/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch index e5f4987b..42578730 100644 --- a/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch +++ b/config/coreboot/default/patches/0031-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From 7d94457ba0e2be10d781c5fd0659d895c9b558b1 Mon Sep 17 00:00:00 2001 +From 564634f7f83f4118e44972c91e391125a7aa6e27 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Thu, 26 Dec 2024 19:45:20 +0000 -Subject: [PATCH 30/48] soc/intel/skylake: Don't compress FSP-S +Subject: [PATCH 31/51] soc/intel/skylake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. @@ -19,10 +19,10 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 70c2a7643c..a2854923e7 100644 +index f8ff8cfa7a..97354cdaa5 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig -@@ -14,7 +14,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE +@@ -15,7 +15,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE select DRAM_SUPPORT_DDR4 select DRIVERS_USB_ACPI select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 diff --git a/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch index d1d47338..b5f1435e 100644 --- a/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch +++ b/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -1,7 +1,7 @@ -From 8768e53f3b2ceb00ec0c8abf0fc0af03993820b1 Mon Sep 17 00:00:00 2001 +From 9e50b19e8d892819bebbebafe25c175f5a8faece Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 18 Dec 2024 02:06:18 +0000 -Subject: [PATCH 31/48] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN +Subject: [PATCH 32/51] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN This is used by lbmk to know where a tb.bin file goes, when extracting and padding TBT.bin from Lenovo ThunderBolt diff --git a/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch b/config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch index 6ed150e7..a5a69887 100644 --- a/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch +++ b/config/coreboot/default/patches/0033-Conditional-TBFW-setting-for-kabylake-thinkpads.patch @@ -1,7 +1,7 @@ -From 579c60fd77517497eb18dfeca8d73cdca94c15da Mon Sep 17 00:00:00 2001 +From eb332dd2c30c54a78cd0ce573c3358df458ad8c5 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 05:14:45 +0100 -Subject: [PATCH 32/48] Conditional TBFW setting for kabylake thinkpads +Subject: [PATCH 33/51] Conditional TBFW setting for kabylake thinkpads Otherwise, other boards will define it, which might trigger the vendor download script, and diff --git a/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch index 64f257e4..fabd23d4 100644 --- a/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch +++ b/config/coreboot/default/patches/0034-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch @@ -1,7 +1,7 @@ -From 23d8a97ff213f744b4e6333d92fc90e9ea97e879 Mon Sep 17 00:00:00 2001 +From 97c167555bec5e8a69b90379c3350766fc5b1107 Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 27 Sep 2025 23:30:46 +0300 -Subject: [PATCH 33/48] soc/intel/alderlake: Disable +Subject: [PATCH 34/51] soc/intel/alderlake: Disable MRC_CACHE_USING_MRC_VERSION There's some issue with building against the FSP headers in src/vendorcode. @@ -14,7 +14,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 34c9baf544..e0ab6b10fd 100644 +index 334ea26e5b..0f1404ea49 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE diff --git a/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch index bb6e39c0..8d5fa92f 100644 --- a/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch +++ b/config/coreboot/default/patches/0035-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch @@ -1,7 +1,7 @@ -From e2e070ab1f080c0ae59c43131faa57f3499fd813 Mon Sep 17 00:00:00 2001 +From fd552921d0a34b8ac2f9c21f8c1abf47f2f0c160 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 28 Sep 2025 03:17:50 +0100 -Subject: [PATCH 34/48] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) +Subject: [PATCH 35/51] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) if you pass -k (keep fptr modules), don't use -r, don't use -t, you can essentially just use me_cleaner to diff --git a/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch index 2292605e..a5fa5bb5 100644 --- a/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch +++ b/config/coreboot/default/patches/0036-soc-intel-alderlake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From fee89a6c872ec26c2ea128ecdce62d6c3abe53f1 Mon Sep 17 00:00:00 2001 +From f91e6c35aa0ff7111e65a89a4828b773d038a69c Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 4 Oct 2025 21:57:43 +0100 -Subject: [PATCH 35/48] soc/intel/alderlake: Don't compress FSP-S +Subject: [PATCH 36/51] soc/intel/alderlake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. @@ -18,7 +18,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index e0ab6b10fd..a2e7cff6f6 100644 +index 0f1404ea49..f78729a9c4 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE diff --git a/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch index a4f9068d..5c9f8fbd 100644 --- a/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch +++ b/config/coreboot/default/patches/0037-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch @@ -1,7 +1,7 @@ -From abd26006eff71c9570bc90fdbce3a76f8f559cea Mon Sep 17 00:00:00 2001 +From ab4937af6e193b057a8b0212f0667e57eb7ba7d7 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 4 Oct 2025 22:20:11 +0100 -Subject: [PATCH 36/48] alderlake: don't require full fsp repo for fd path +Subject: [PATCH 37/51] alderlake: don't require full fsp repo for fd path Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index a2e7cff6f6..3402c1e3d5 100644 +index f78729a9c4..c05d06289e 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig -@@ -430,7 +430,14 @@ config FSP_HEADER_PATH +@@ -442,7 +442,14 @@ config FSP_HEADER_PATH config FSP_FD_PATH string diff --git a/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch index d740f7a7..4a3130ac 100644 --- a/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch +++ b/config/coreboot/default/patches/0038-soc-alderlake-disable-stack-overflow-debug-option.patch @@ -1,7 +1,7 @@ -From 6a4a79d82df982c2fca859101040e407623f519c Mon Sep 17 00:00:00 2001 +From dec241cc53669870365e103a22d21a9a3111abcc Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Oct 2025 04:47:06 +0100 -Subject: [PATCH 37/48] soc/alderlake: disable stack overflow debug option +Subject: [PATCH 38/51] soc/alderlake: disable stack overflow debug option same as on other boards. based on this commit: @@ -22,10 +22,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 3402c1e3d5..06b9199e84 100644 +index c05d06289e..acb87275d4 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig -@@ -331,6 +331,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ +@@ -343,6 +343,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ int default 19200000 diff --git a/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch index dd5412a2..6518493e 100644 --- a/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch +++ b/config/coreboot/default/patches/0039-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch @@ -1,7 +1,7 @@ -From bb286d13cb7702e9396deab04023cc58dcc01a15 Mon Sep 17 00:00:00 2001 +From fa7d21faf931756d8adb84071bc503a0fe8e64c3 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 11 May 2025 15:41:22 -0600 -Subject: [PATCH 38/48] ec/dell/mec5035: Add command to disable EC-initiated +Subject: [PATCH 39/51] ec/dell/mec5035: Add command to disable EC-initiated thermal shutdown If command 0xBF isn't sent, the EC shuts down the system without warning diff --git a/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch index 1814806f..0ebfe02a 100644 --- a/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch +++ b/config/coreboot/default/patches/0040-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch @@ -1,7 +1,7 @@ -From a93c01173c2f88b4a09286740c030314040c39fc Mon Sep 17 00:00:00 2001 +From 0397a0966953d47210a5ae1f7f0cd71a9a10dc68 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 11 May 2025 16:28:23 -0600 -Subject: [PATCH 39/48] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown +Subject: [PATCH 40/51] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown at 87 degrees If command 0xBF isn't sent, the EC will shut down the system without diff --git a/config/coreboot/default/patches/0040-fix-ifdtool-build.patch b/config/coreboot/default/patches/0041-fix-ifdtool-build.patch index b39fbc0b..3124f7c3 100644 --- a/config/coreboot/default/patches/0040-fix-ifdtool-build.patch +++ b/config/coreboot/default/patches/0041-fix-ifdtool-build.patch @@ -1,7 +1,7 @@ -From dc4036353483c5fc0c140fc269d9bddb0bb7a967 Mon Sep 17 00:00:00 2001 +From 42fb6f08310a35587643bdfd75bcdca5318f1022 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 20 Dec 2025 20:12:48 +0100 -Subject: [PATCH 40/48] fix ifdtool build +Subject: [PATCH 41/51] fix ifdtool build not my mistake. someone messed up. @@ -11,10 +11,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index cab934c3a5..d181888e0f 100644 +index 7f0c10bd0b..2a5365efe7 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c -@@ -2598,7 +2598,7 @@ int main(int argc, char *argv[]) +@@ -2610,7 +2610,7 @@ int main(int argc, char *argv[]) } mode_nuke = 1; break; diff --git a/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch b/config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch index 8f61bcd0..a8206276 100644 --- a/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch +++ b/config/coreboot/default/patches/0042-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch @@ -1,7 +1,7 @@ -From 5b7bbc6fcc6f737f259906f1919c1e28b6628a7e Mon Sep 17 00:00:00 2001 +From 5bcd048c8ded00a7c12e863a1a9a76c9bba1606a Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 20 Dec 2025 22:36:18 +0100 -Subject: [PATCH 41/48] tests/Makefile.mk: use 3rdparty/cmocka by default +Subject: [PATCH 42/51] tests/Makefile.mk: use 3rdparty/cmocka by default (tests) diff --git a/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch b/config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch index 4ce1241c..1c614c17 100644 --- a/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch +++ b/config/coreboot/default/patches/0043-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch @@ -1,7 +1,7 @@ -From ecbf5a133d839b6c8579e384e9db0a036eca939d Mon Sep 17 00:00:00 2001 +From ac1c23e215f791c46094377f2f4c7a398e63cc80 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 23 Dec 2025 18:41:27 +0100 -Subject: [PATCH 42/48] mb/dell/optiplex_780: use legacy HDA verb table +Subject: [PATCH 43/51] mb/dell/optiplex_780: use legacy HDA verb table See: diff --git a/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch b/config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch index e5ea4f3c..b210ce34 100644 --- a/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch +++ b/config/coreboot/default/patches/0044-hp8300cmt-use-legacy-verb-table.patch @@ -1,7 +1,7 @@ -From 962bfe1366598145a93cf6a7ed0f78393e5e9ff7 Mon Sep 17 00:00:00 2001 +From 8802ad95c158e09e89c4bc0c14755d17b5f532bd Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 23 Dec 2025 18:46:45 +0100 -Subject: [PATCH 43/48] hp8300cmt: use legacy verb table +Subject: [PATCH 44/51] hp8300cmt: use legacy verb table same as for the 780 optiplex patch diff --git a/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch b/config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch index ae70996f..ef6f94a2 100644 --- a/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch +++ b/config/coreboot/default/patches/0045-topton-x2e-n150-use-old-fsp.patch @@ -1,7 +1,7 @@ -From 88d29f792de89bb0a138e671432227cb5679b5ae Mon Sep 17 00:00:00 2001 +From ea848531d1a4ddd9952b8b8d3570770e5ac128cd Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 6 Jan 2026 21:42:21 +0000 -Subject: [PATCH 44/48] topton x2e n150: use old fsp +Subject: [PATCH 45/51] topton x2e n150: use old fsp i added the old fsp back, so that we didn't have to mess around with vendor files in lbmk, because coreboot @@ -18,10 +18,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 06b9199e84..f260d10285 100644 +index acb87275d4..6f1e8b9107 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig -@@ -451,6 +451,7 @@ config FSP_FD_PATH +@@ -463,6 +463,7 @@ config FSP_FD_PATH default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S diff --git a/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch b/config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch index e4622ce4..49318070 100644 --- a/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch +++ b/config/coreboot/default/patches/0046-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch @@ -1,7 +1,7 @@ -From 5b52abaa8529f7493f9d4ecf402e9ee130f4f8d2 Mon Sep 17 00:00:00 2001 +From 276e29864adfaaa1234d1263a8bf751f7dfd357d Mon Sep 17 00:00:00 2001 From: Ron Nazarov <ron@noisytoot.org> Date: Sat, 14 Feb 2026 20:13:01 +0000 -Subject: [PATCH 45/48] mb/supermicro/x11-lga1151-series: Disable ME HECI in +Subject: [PATCH 46/51] mb/supermicro/x11-lga1151-series: Disable ME HECI in devicetree Since we always use me_cleaner, this speeds up boot time by preventing @@ -14,7 +14,7 @@ Signed-off-by: Ron Nazarov <ron@noisytoot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -index fbf896c6ae..aa09a41f2f 100644 +index d25288420f..edbb485969 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/skylake diff --git a/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch b/config/coreboot/default/patches/0047-util-ifdtool-option-to-allow-region-override.patch index 45539084..30879e5b 100644 --- a/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch +++ b/config/coreboot/default/patches/0047-util-ifdtool-option-to-allow-region-override.patch @@ -1,15 +1,15 @@ -From b9cc1be6f9d591dbc4f73b1448f8fce5ea20a0b4 Mon Sep 17 00:00:00 2001 +From 37f24d5775dd9d29e91e42d6de952d8d791cf7c5 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 20 Feb 2026 01:23:32 +0000 -Subject: [PATCH 46/48] util/ifdtool: option to allow region override +Subject: [PATCH 47/51] util/ifdtool: option to allow region override Signed-off-by: Leah Rowe <leah@libreboot.org> --- - util/ifdtool/ifdtool.c | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) + util/ifdtool/ifdtool.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index d181888e0f..dfefe316a9 100644 +index 2a5365efe7..c5c3570e6a 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -78,6 +78,8 @@ static unsigned int max_regions = 0; @@ -21,7 +21,7 @@ index d181888e0f..dfefe316a9 100644 static const struct region_name region_names[MAX_REGIONS] = { { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" }, { "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" }, -@@ -2093,7 +2095,9 @@ static void new_layout(const char *filename, char *image, int size, +@@ -2094,7 +2096,9 @@ static void new_layout(const char *filename, char *image, int size, } for (j = i + 1; j < max_regions; j++) { @@ -29,10 +29,18 @@ index d181888e0f..dfefe316a9 100644 + if (ignore_region_override) { + printf("Ignoring region overlap by user's will.\n"); + } else if (regions_collide(&new_regions[i], &new_regions[j])) { - fprintf(stderr, "Regions would overlap.\n"); + fprintf(stderr, "Regions would overlap:\n"); + + /* See which string is longer and make sure we pad the shorter one */ +@@ -2107,6 +2111,7 @@ static void new_layout(const char *filename, char *image, int size, + new_regions[i].base, new_regions[i].limit); + fprintf(stderr, " %*s : %x-%x\n", padding, region_name(j), + new_regions[j].base, new_regions[j].limit); ++ exit(EXIT_FAILURE); } -@@ -2351,10 +2355,11 @@ int main(int argc, char *argv[]) + } +@@ -2363,10 +2368,11 @@ int main(int argc, char *argv[]) {"newvalue", 1, NULL, 'V'}, {"topswapsize", 1, NULL, 'T'}, {"nuke", 1, NULL, 'N'}, @@ -45,7 +53,7 @@ index d181888e0f..dfefe316a9 100644 long_options, &option_index)) != EOF) { switch (opt) { case 'd': -@@ -2598,6 +2603,9 @@ int main(int argc, char *argv[]) +@@ -2610,6 +2616,9 @@ int main(int argc, char *argv[]) } mode_nuke = 1; break; diff --git a/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch b/config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch index cfd5c6c9..db705b60 100644 --- a/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch +++ b/config/coreboot/default/patches/0048-me_cleaner-don-t-modify-if-k-is-used.patch @@ -1,7 +1,7 @@ -From 1bc6028bf88ca6306ad89fc17fa6f31b9788b248 Mon Sep 17 00:00:00 2001 +From fb4bc4ed6e1fca747e54a34127ca927cb70318ad Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 20 Feb 2026 19:31:19 +0000 -Subject: [PATCH 47/48] me_cleaner: don't modify if -k is used +Subject: [PATCH 48/51] me_cleaner: don't modify if -k is used don't remove *anything*. in libreboot, we only ever use -k when we werely want to extract the diff --git a/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch b/config/coreboot/default/patches/0049-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch index 76fc54e2..32160591 100644 --- a/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch +++ b/config/coreboot/default/patches/0049-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch @@ -1,7 +1,7 @@ -From f5f73c2539e05cf85bf5eec795e4f91da50838ba Mon Sep 17 00:00:00 2001 +From 3535480a7ec3fbf789ff734570d8213f21ee7be1 Mon Sep 17 00:00:00 2001 From: Kat Inskip <kat@inskip.me> Date: Tue, 17 Feb 2026 16:18:15 -0800 -Subject: [PATCH 48/48] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant +Subject: [PATCH 49/51] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant This machine is somewhat dissimilar from the X280 in the PCIe allocations in the overridetree. It also lacks soldered RAM, having a single SODIMM slot. @@ -28,10 +28,10 @@ An untested variety allowing for a Skylake CPU (for 20K5 and 20K6) has been incl create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index b7cc705699..5945fe7b99 100644 +index 9d4b5f4965..1aaef40a0c 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -58,6 +58,16 @@ config BOARD_LENOVO_X280 +@@ -59,6 +59,16 @@ config BOARD_LENOVO_X280 select SOC_INTEL_KABYLAKE select HAVE_SPD_IN_CBFS @@ -48,7 +48,7 @@ index b7cc705699..5945fe7b99 100644 if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON config MAINBOARD_DIR -@@ -69,6 +79,8 @@ config VARIANT_DIR +@@ -70,6 +80,8 @@ config VARIANT_DIR default "t480s" if BOARD_LENOVO_T480S default "t580" if BOARD_LENOVO_T580 default "x280" if BOARD_LENOVO_X280 @@ -57,7 +57,7 @@ index b7cc705699..5945fe7b99 100644 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -@@ -79,6 +91,8 @@ config MAINBOARD_PART_NUMBER +@@ -80,6 +92,8 @@ config MAINBOARD_PART_NUMBER default "T480s" if BOARD_LENOVO_T480S default "T580" if BOARD_LENOVO_T580 default "X280" if BOARD_LENOVO_X280 diff --git a/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch b/config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch index df86ee01..b55797ca 100644 --- a/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch +++ b/config/coreboot/default/patches/0050-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch @@ -1,7 +1,7 @@ -From 9d39437b9447ab6e6164440bddf459111bd4903f Mon Sep 17 00:00:00 2001 +From 15cfc08cea1e4a091a2dd729bf88fa2a10ef0a3d Mon Sep 17 00:00:00 2001 From: Kat Inskip <kat@inskip.me> Date: Sat, 21 Feb 2026 19:48:17 +0000 -Subject: [PATCH] mb/lenovo/x270: Provide correct vbt and hda_verb +Subject: [PATCH 50/51] mb/lenovo/x270: Provide correct vbt and hda_verb --- .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 6144 -> 4449 bytes @@ -12,37 +12,34 @@ diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/m index bfb312850e0ab4ea834c535df35edb45834ed248..c6561a9c57e4e600bc0adb5f6679f2f5d6b6c640 100644 GIT binary patch delta 1043 -zcmZoLc&Ic%f;Calfx%$%L?+>h1_E+-8N?V21pmEaU`SzPl;klqFfjDYD@o1K2+~vt -z_MVtzqhMg55a6s}XrgCqqM%@?Z)B)%WMF8jpkQcVWoTw)YB_PgJ|n}#S5l0olUW%J -zmH8bQ7#aQ=F)(m2Ft9K%I51!UfyozHMC%0@m~0uDSQr@8IT+X^kQH$;FffDp4h#xl -z8bl~CurORpU|?Wi|HJ{}Gcd3-Ft9R!tPx;TV1x)UFbFU>fRs5fu(NPN#30UK;9yW- -zRA7P#ft0y`jTR8#5QD0NNii@mDnP7fU|>*S5CDk_2ry`1Q#Lt(Nn)}ATY5b+BLl;q -zDh37ys6!YT7(sx6fsfIEA&*mz!Jk=!p@x}>p^e#sL5t-Cg8-)jgE6N7gBzy+LnNmF -z!(~=3hP$j>49{7)7(TLcG5lubVqj(CV&G@vVvuCxVo+w|V$fydVlZdpVsK>RV(@0; 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-- -2.52.0 +2.47.3 diff --git a/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch b/config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch index a2e5d5a2..b6473d8e 100644 --- a/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch +++ b/config/coreboot/default/patches/0051-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch @@ -1,7 +1,8 @@ -From 24856e5e383b1b9aa078b879064b8c2b99f4494c Mon Sep 17 00:00:00 2001 +From 24cb7949962e910c22ccb3e388699709591f2834 Mon Sep 17 00:00:00 2001 From: Todd Baker <todd_baker@student.uml.edu> Date: Thu, 12 Mar 2026 13:12:04 -0400 -Subject: [PATCH] mb/dell: Add OptiPlex 3040 Micro port (upstream-compatible) +Subject: [PATCH 51/51] mb/dell: Add OptiPlex 3040 Micro port + (upstream-compatible) Based on the OptiPlex 3050 Micro (same Skylake H110 PCH-H platform). Key differences from 3050: @@ -347,32 +348,33 @@ new file mode 100644 index 0000000000000000000000000000000000000000..b503dfc20277775982256a4bdc9108c2ad96f856 GIT binary patch literal 4300 -zcmeHJU2GIp6#nLSXYbBzr$d#pV7($jx3pz;m0GlwX?H0tEiwzWuF-@o*+oezEo~tM -zf4YX6kSJy!)Szid6JN~w(!}_rMiOHr!Jldr9_@>X5=}_J_yVk%JJapDM0Z0%l!R}R -zIrp4<=DX+Id*|M>Zm4^Z?&*JOpsRly^^k^%uk_0>aU;6>cJ0|4?;7md+dZ%=)=$5~ -z-I&#{Uj)(|w@Qten<IS(Co?0ByTi1<dw>o(A5h19#EjB-JKfpSLz9t6Gqt-rd*eI% -zXydjXI}&cDcC0gQN0=IQ)OcsyjxzPZa5LT3V@D}H&^<ajF-bEAhxd(S(l<s|39-?! -zqvHpjeQuIA#=<menr2JXj6^64nZ`!P$69IE$Ozr-_)O5<nTgE!kxaT(BN_qDKoL1` -zoP?SzI9!V&Wx=)(w_sAN6HzB(%tG42poNDhCav;#bnu%wUIf;c_D}!>5CAB!m<l+8 -z6Y+ftx~?3nb9DO$4v;=M3`pQ8$0(d{Eu3dwuQRX33ko1QTt3QCe#y&i=(=*6c>#Vv -zb~=3~N1dVBi0<IJj(LwOz<L1QD)Dj#E#hxV5#`o$-9@>zTwnGQIN<6r&rpgWXJWs< -z0o#Q}ObR?+7TU2^JPXB7vC*&NF~5$4U&lF#;75tzCyC%!iQuwCa7`lc$pp1B!D^Y{ -z0hwTvOt3{Jh{*&yWr8PVf?=6JK8&jcJ_{ckJj;2q)|Jpjyb(rr*0axgcK;=3B>>{d -zfG4X(q2Tl3df}UT6beeG6M=O}1P5?&kEz#_1565n?dgNAACjJ4DELzVqKMv-x4@Xm -zIcFogC=_n@mbwBvAVN?&W<+Ft?P3S`&rfOsra)?yrR-p+&Vm$CcN%iY)qEXAYZ?B_ -zo{)1Ctp1H(@DVKdu5c$-{6AaHl<5_oCDeLY((m97O0lLF=l$6nUA#wEQfu9whMTk8 -z`;2pqD-fZ=LL9xN;}oHQ@5Pdn3ucO=v?x%(i|o!{2BoNR@9KX<V+b{vDDTeZ^Z7gw -zeiOo@gbov9f{>R8eUBI)5%L+KKNI6mLbw3k5HPj`NGw1P1dJB~<kbNEAYgnNAYTUP -z?*XF_Abyo@QjIQ^^sDrcY8+R|NtJ%68egd7Tb2Hy8a|EGYV={v=+np^jULsE*EI5$ -zMnBe!uQhT(qt`T}CP-EV>DHi;2$H9RT9YAV`9&^U8)Su!GOl95m*iC@uW<Uf3aMrT -z3WXaNrEQvX4_K87Nxm|}Tn$AexrR1o>)bhNXq)EU`bTw+^U4hARj|6S-mE{-<}%c` -zO$)3(g9-_v!_Xn%U$QWpa4G@QGRN341}6rIRb^18q)=51Q#29MExm++%Slc=RWiK4 -zX=*VMT5ly!Eyuv+Sk0$e@_ZFB^lr7xee+SvI<w3myA_Z+Bvmt$`|lgdC(vN_<h-?T -zW-`a_PA(@`GY>De=H^nN2Fs-0S~Rpxi#b1=hpexfEE+qqb7S-OTPAHP?guHy>J)WO -znyF$xyc?cdNX)D??RQod83eG>SheJ87|bT?Y-%QL)+gM0(8)r8%Cfl0J;@j}mqDUc -zWN|TsIh(FDRWr7nMJ~t~oa(0Xf5AVJtv}S>VkKLa*Fr#z8-oJ5@_!Mwkji33O4q%s -znq{FghJhY?uRVM)GxGTG^O@UI$;9oJ$<daf?OpB+SHQ+sAn(vOAerBB7PsO}lKDaz -g_%bx#h2uQ{`atjmY^2f5y^UXl)_LGW5w}J2FT+;79{>OV +zcmeHJU2GIp6h1SvzjtP~vs09^U_BzjZlPs%m0GmOY<DRwEwT%>uF-@o*+oezEo~tM +ze;7keND#9RYS0kU#1~Uvni!wdNMej6_=85_(Y}}{(ZmFdFTi^4%(PpVU{|7163*n@ +z^D}3@x%b>Ncg~9bjy~Mc^F(j5XA`<q00TbPF41^Bb#!mru``|QOYZFG-InUXui;KO +zsa?AWP!NPAO59i%@7_CB9E@&{VNXXd_VWjjyAK!%Ot<0I&Q8q5<7+U}v7sxywHu?G +zIy3PY*{KcbOx!jT+)R_1u+96)q@V=io{piR(J?IU9oRKkEL=akg*>UD;e#W4o_=Nw +zqp27s48v$n81XpTQ^wTL$Z!iL2M2LGj~T`7#nIx(fnuRWWhw(W4FQh;g5ZTZ3k0~D +zfV>GA6VfIa2rE3W$OFSB6inzd;Q@p(vwA)ni0cH=1F&-b9VCO`B@zKJfty4KAb8-L +zJZM_r&?0VUz7+txAMU3C1SFjZiA^|fN4;W4&0Gio&?_L|M*&4r>?lVetW$OrKoG#k +z@A(Y@`Kui)<cg-jw2LKkn@BY0MIkxn2<No<O0~Dzc4Di&)pjLHqUByW<k){2LxKUj +zgN?9Rio%#A!i!QHEccv&KoDVdP=iN^v&3h;489}&p7<x?OT<@+{XPa^;-$p*5w9g) +zPn;s&O8hwS0I_dBTq%nd`0ck_f-A$01kD4l#=tu1`cJz4;IDiqXnS2LyV7>nFqF%F +zKU^z+*#PBoU<03lNeGk+A?+e{xw6-ml9X}nK9amda;{x22lHem==wKC$wp>pc_BMg +zF5l{!QV(0`OOgWZ6CSYqZJu@zKRK>SFb*tCADK(KVkdgmTyzS25y$Yi&pNB+e|aau +zkAkH?i|70d&iOA3N9+He8qb-wz%`rKuuHS{ZFxHb^E0rl3(g0v63*PE1@g<CJB>Hz +zx%(-qNijeNg97yLhpzeWnbQLxcG2J5339x)D^1T-h+H1~pI>nyLLL7=|AL|ssDsh! +z0Bec}Aodza4>KHK`Y2;BFnpWo?=$u>!ylObJ7a>3t7Lt>%u+J$k@e?f_Oguc%KAq# +z`%K1PWW6l2pn_`^J*luB1@|fX5rrLB@I6KURAFB!_?x2pRTft9K~?Wo*$x#Cs`@dN +zy{_U1s{Vz_E~t1_)$2lRNeDNF^lXSd8B&{cuO-e1RybrgI)M>|&Yqm8*z&TVk@VKB +zqQBhro6>rinl8Rt1*M$0Fv4UVLOiz&qZairoElpXi(uze;m7&H2!$nJCSj$~aJ1Dy +zXlOkw+5H*qxfeVfp`CiB8?VA>f)iOVOk=p-L7+L%gIrg}y^)#_#xWbwOl=;5Q1bo_ +zgm>1C&txMj&D@E~9E6hH^C_lpx`sJ)Z8VKt(+Sf&T|w|U9gx!RttFGY@9Ce)LZi`H +za`%E~vSj}|X)3kk;rW)*WIobp8tCo?Wztik=9MyO`D<B4wB4E<p1zk5n)p+8J$OrY +zpQ229Cu*pNw_=m$vJ=aV%$tkn5G1f$W6ESL2u726CO=Uy8nRA5$ZJxfVj{ZPnzRvA +z2f>Rqtm0w>CNsF$P>fV%6(#x}?M$}W^}vh###JpoWHsz-Yc_MumA#PYEaC`sjQJM+ +zE@CF+EvV0HT9`j&?}bF?DUs6Knc0~c*jpTYbl}<It!Wg~ndY&f=Kjq|zM=(b^-JK} +zqOF45)Rr^UssHmM%T1N5NUWkYcfgTOnrSz6?vFtR3b00a1AdfRrU8!5(Ji6=0mD|k +A9{>OV literal 0 HcmV?d00001 @@ -1524,5 +1526,5 @@ index 0000000000..9d262d5787 + +#endif -- -2.53.0 +2.47.3 diff --git a/config/coreboot/default/patches/0051-mb-supermicro-x11-lga1151-series-Enable-SATA-hotplug.patch b/config/coreboot/default/patches/0051-mb-supermicro-x11-lga1151-series-Enable-SATA-hotplug.patch deleted file mode 100644 index 58c1a1d9..00000000 --- a/config/coreboot/default/patches/0051-mb-supermicro-x11-lga1151-series-Enable-SATA-hotplug.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 88519aed6c7f305f7f2319e335c1421137df7ce3 Mon Sep 17 00:00:00 2001 -From: Ron Nazarov <ron@noisytoot.org> -Date: Mon, 23 Mar 2026 17:04:03 +0000 -Subject: [PATCH] mb/supermicro/x11-lga1151-series: Enable SATA hotplug - -Before this patch, hotplugging only worked to replace drives (if you -tried to plug a drive into a SATA port that no drive was plugged in to -at boot, it wouldn't be detected) and you'd have to manually rescan -the bus (echo "- - -" > /sys/class/scsi_host/host*/scan) to make -plugs/unplugs get detected by the operating system. - -Now, hotplugging works for all ports (tested and working on Supermicro -X11SSH-LN4F) and there's no need to manually rescan (it sometimes -takes a few seconds for unplugs to be detected, but plugs are detected -instantly). - -Change-Id: Id978a047697795ea657048fb6dc6665736c293f9 -Signed-off-by: Ron Nazarov <ron@noisytoot.org> ---- - .../supermicro/x11-lga1151-series/devicetree.cb | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -index fbf896c6ae..d25288420f 100644 ---- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -@@ -28,6 +28,16 @@ chip soc/intel/skylake - [6] = 1, - [7] = 1, - }" -+ register "SataPortsHotPlug" = "{ -+ [0] = 1, -+ [1] = 1, -+ [2] = 1, -+ [3] = 1, -+ [4] = 1, -+ [5] = 1, -+ [6] = 1, -+ [7] = 1, -+ }" - end - device ref lpc_espi on - register "serirq_mode" = "SERIRQ_CONTINUOUS" --- -2.52.0 - diff --git a/config/coreboot/default/target.cfg b/config/coreboot/default/target.cfg index 3cd3e96e..4876cb09 100644 --- a/config/coreboot/default/target.cfg +++ b/config/coreboot/default/target.cfg @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-3.0-or-later tree="default" -rev="ed5a993f0f98a47d5e780e375e5861860019b183" +rev="62c8197dd25376cb7b18d272af167cb176d28bcf" |