diff options
Diffstat (limited to 'config/coreboot/default')
66 files changed, 1017 insertions, 1732 deletions
diff --git a/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index b163d5d2..da4ab420 100644 --- a/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From e60ec1c7304e3f167fd2bf762f28b7eacd0b169a Mon Sep 17 00:00:00 2001 +From f625e31ee3abb867e775ab0cb724550825699c36 Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 02/39] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/51] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + @@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644 end end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch deleted file mode 100644 index 8bbffb53..00000000 --- a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 2d9f38a12b883e1ddcdae5de107f204e522146e2 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@retroboot.org> -Date: Fri, 19 Mar 2021 05:54:58 +0000 -Subject: [PATCH 01/39] apple/macbook21: Set default VRAM to 64MiB instead of - 8MiB - ---- - src/mainboard/apple/macbook21/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default -index b744b11cda..9749e26547 100644 ---- a/src/mainboard/apple/macbook21/cmos.default -+++ b/src/mainboard/apple/macbook21/cmos.default -@@ -7,4 +7,4 @@ boot_devices='' - boot_default=0x40 - cmos_defaults_loaded=Yes - lpt=Enable --gfx_uma_size=8M -+gfx_uma_size=64M --- -2.39.2 - diff --git a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch index f655f93c..ee605e58 100644 --- a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 3659aec797baa40e4336e88361a705295fb72b0f Mon Sep 17 00:00:00 2001 +From 8821f229d4fe48153ec7a45e0e04c3b2a3cd8c7c Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 09/39] lenovo/t400: Enable all SATA ports +Subject: [PATCH 02/51] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its @@ -30,5 +30,5 @@ index 259c3e1b21..3d007533a4 100644 register "sata_traffic_monitor" = "0" -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index 868b65d5..a4b430fe 100644 --- a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From 6bc13399517009917538cd4ddb426c4b1550bfad Mon Sep 17 00:00:00 2001 +From 0298639b6e80c8950fbb4484180b7195883ab8c1 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 11/39] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 03/51] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do @@ -23,16 +23,15 @@ Date: Thu Nov 21 21:47:31 2019 +0300 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default -index 3bb78960b9..ae47202aac 100644 +index 732e214b32..8454f0eac0 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default -@@ -17,5 +17,5 @@ trackpoint=Enable +@@ -17,4 +17,4 @@ trackpoint=Enable backlight=Both usb_always_on=Disable f1_to_f12_as_primary=Enable -me_state=Normal +me_state=Disabled - gfx_uma_size=224M -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch deleted file mode 100644 index 8bf9a049..00000000 --- a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 9a0157b1459365cf52f90e66b78dd6b60a259587 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@osboot.org> -Date: Sun, 3 Jan 2021 03:34:01 +0000 -Subject: [PATCH 03/39] lenovo/x60: 64MiB Video RAM changed to default - (previously it was 8MiB) - ---- - src/mainboard/lenovo/x60/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default -index 58825c8a36..8e0aaf427d 100644 ---- a/src/mainboard/lenovo/x60/cmos.default -+++ b/src/mainboard/lenovo/x60/cmos.default -@@ -17,4 +17,4 @@ trackpoint=Enable - sticky_fn=Disable - power_management_beeps=Enable - low_battery_beep=Enable --gfx_uma_size=8M -+gfx_uma_size=64M --- -2.39.2 - diff --git a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch deleted file mode 100644 index 80f3023d..00000000 --- a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 5b2a26e72bce37f7b0a92f1ed93fd607cea8de9b Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@osboot.org> -Date: Mon, 22 Feb 2021 22:16:59 +0000 -Subject: [PATCH 04/39] lenovo/t60: make 64MiB VRAM the default in cmos.default - ---- - src/mainboard/lenovo/t60/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default -index 283a5747ee..91f6c0e6e2 100644 ---- a/src/mainboard/lenovo/t60/cmos.default -+++ b/src/mainboard/lenovo/t60/cmos.default -@@ -17,4 +17,4 @@ trackpoint=Enable - sticky_fn=Disable - power_management_beeps=Enable - low_battery_beep=Enable --gfx_uma_size=8M -+gfx_uma_size=64M --- -2.39.2 - diff --git a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch index 09981df8..71695404 100644 --- a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From 72c9e1403fb93c025be75536f5520e2ef9d4da9e Mon Sep 17 00:00:00 2001 +From c697c90ace86edfe724c86bd6a680cf0ae0e4b58 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 12/39] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 04/51] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default @@ -120,5 +120,5 @@ index d61046df6b..8c793fd1c3 100644 -me_state=Enable +me_state=Disabled -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch deleted file mode 100644 index 2140071d..00000000 --- a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 945d84782e706e8f3effab57edca68d9463d21fc Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Fri, 14 May 2021 13:10:33 +0100 -Subject: [PATCH 05/39] lenovo/t400: set VRAM to 256MiB VRAM by default - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - src/mainboard/lenovo/t400/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default -index a16d386dd1..e7bb32306c 100644 ---- a/src/mainboard/lenovo/t400/cmos.default -+++ b/src/mainboard/lenovo/t400/cmos.default -@@ -15,4 +15,4 @@ power_management_beeps=Enable - low_battery_beep=Enable - sata_mode=AHCI - hybrid_graphics_mode=Integrated Only --gfx_uma_size=32M -+gfx_uma_size=256M --- -2.39.2 - diff --git a/config/coreboot/default/patches/0013-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 9d4270e7..b7b514cd 100644 --- a/config/coreboot/default/patches/0013-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From 70cf6905b54d39285025373dae1c897c9c727f83 Mon Sep 17 00:00:00 2001 +From d2f579b82921c2c35e4cf756db0ca476fbadfac1 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 13/39] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 05/51] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). @@ -201,5 +201,5 @@ index 32b2081d93..1473cf058b 100644 struct fpsba *fpsba = find_fpsba(image, size); struct fmsba *fmsba = find_fmsba(image, size); -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch deleted file mode 100644 index 07434470..00000000 --- a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 112470b4f7b046ec2656699336211ba63ff448fa Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Fri, 14 May 2021 13:11:59 +0100 -Subject: [PATCH 06/39] lenovo/x200: set VRAM to 256MiB by default - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - src/mainboard/lenovo/x200/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default -index 434af5d227..443ef54e41 100644 ---- a/src/mainboard/lenovo/x200/cmos.default -+++ b/src/mainboard/lenovo/x200/cmos.default -@@ -14,4 +14,4 @@ sticky_fn=Disable - power_management_beeps=Enable - low_battery_beep=Enable - sata_mode=AHCI --gfx_uma_size=32M -+gfx_uma_size=256M --- -2.39.2 - diff --git a/config/coreboot/default/patches/0016-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index 9ebeffa2..71f2f22d 100644 --- a/config/coreboot/default/patches/0016-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From 6426e07c7da50d588ee1ca30e0911040d89e4c96 Mon Sep 17 00:00:00 2001 +From a5bc59037dabd95b6595c5aaf38b83da2a91de54 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 16/39] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 06/51] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed @@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644 device pci 02.1 on end # Display device pci 03.0 on end # ME -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0017-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch index b575453c..fa364ca1 100644 --- a/config/coreboot/default/patches/0017-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From 29a654eaaa7bf924f9681a2520dbabfe12619269 Mon Sep 17 00:00:00 2001 +From f883599a362f1383f3712b72516f76187d0a9cbe Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 17/39] Remove warning for coreboot images built without a +Subject: [PATCH 07/51] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing @@ -35,5 +35,5 @@ index 5f988dac1b..516133880f 100644 -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch deleted file mode 100644 index ad619606..00000000 --- a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 37418629a56cb740cae2870317458ea52daad8c9 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Fri, 14 May 2021 13:18:26 +0100 -Subject: [PATCH 07/39] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default -index fe79c83570..4a1f97a9d8 100644 ---- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default -+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default -@@ -4,4 +4,4 @@ boot_option=Fallback - debug_level=Debug - power_on_after_fail=Enable - nmi=Enable --gfx_uma_size=64M -+gfx_uma_size=256M --- -2.39.2 - diff --git a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch deleted file mode 100644 index e0ac6cf1..00000000 --- a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch +++ /dev/null @@ -1,23 +0,0 @@ -From e785387dffe382a02d4c0cb006cced48c235484c Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Fri, 14 May 2021 13:21:39 +0100 -Subject: [PATCH 08/39] acer/g43t-am3: set VRAM to 256MiB by default - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - src/mainboard/acer/g43t-am3/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default -index 23f0e55f3e..8d6c4db1ce 100644 ---- a/src/mainboard/acer/g43t-am3/cmos.default -+++ b/src/mainboard/acer/g43t-am3/cmos.default -@@ -5,4 +5,4 @@ debug_level=Debug - power_on_after_fail=Disable - nmi=Enable - sata_mode=AHCI --gfx_uma_size=64M -+gfx_uma_size=256M --- -2.39.2 - diff --git a/config/coreboot/default/patches/0018-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch b/config/coreboot/default/patches/0008-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch index bfcdb6cf..48b9d21e 100644 --- a/config/coreboot/default/patches/0018-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch +++ b/config/coreboot/default/patches/0008-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch @@ -1,7 +1,7 @@ -From 892b6244c27590cbf1d82125340c57273e42b911 Mon Sep 17 00:00:00 2001 +From 40545928c415c27d3a30748e4bfdee7f9d8f82f9 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 19 Aug 2023 16:19:10 -0600 -Subject: [PATCH 18/39] mb/dell: Add Latitude E6530 (Ivy Bridge) +Subject: [PATCH 08/51] mb/dell: Add Latitude E6530 (Ivy Bridge) Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was not tested. I do not physically have this system; someone with physical @@ -426,5 +426,5 @@ index 0000000000..8b9c82fba4 + end +end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0019-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch b/config/coreboot/default/patches/0009-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch index 97055b7c..a2a13166 100644 --- a/config/coreboot/default/patches/0019-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch +++ b/config/coreboot/default/patches/0009-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch @@ -1,7 +1,7 @@ -From 9b0766b86ac010b7edfe27d1f7edbb3f27dc742e Mon Sep 17 00:00:00 2001 +From 423e2e28618b08a4107aea0a2fbc1096f5a8be02 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 31 Jan 2024 22:57:07 -0700 -Subject: [PATCH 19/39] mb/dell: Add Latitude E5530 (Ivy Bridge) +Subject: [PATCH 09/51] mb/dell: Add Latitude E5530 (Ivy Bridge) Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board; someone with physical access to one sent me the output of autoport which @@ -426,5 +426,5 @@ index 0000000000..85c448d010 + end +end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch deleted file mode 100644 index db6d64f8..00000000 --- a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 820c2d64a7415f7159fd7cdac4746049c91f89a2 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Mon, 20 Dec 2021 01:29:31 +0000 -Subject: [PATCH 10/39] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by - default - ---- - src/mainboard/lenovo/x230/cmos.default | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default -index 732e214b32..3bb78960b9 100644 ---- a/src/mainboard/lenovo/x230/cmos.default -+++ b/src/mainboard/lenovo/x230/cmos.default -@@ -18,3 +18,4 @@ backlight=Both - usb_always_on=Disable - f1_to_f12_as_primary=Enable - me_state=Normal -+gfx_uma_size=224M --- -2.39.2 - diff --git a/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch b/config/coreboot/default/patches/0010-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch index 2f6629b2..80b2c147 100644 --- a/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch +++ b/config/coreboot/default/patches/0010-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch @@ -1,7 +1,7 @@ -From 5d8a651a71d19918130f58c637700539dd320789 Mon Sep 17 00:00:00 2001 +From 200668a694f1c534a94a0bc8996416e246fe91b0 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 26 Nov 2023 17:08:52 -0700 -Subject: [PATCH 20/39] mb/dell: Add Latitude E6420 (Sandy Bridge) +Subject: [PATCH 10/51] mb/dell: Add Latitude E6420 (Sandy Bridge) Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was not tested. I do not physically have this system; someone with physical @@ -431,5 +431,5 @@ index 0000000000..3012a3177f + end +end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch b/config/coreboot/default/patches/0011-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch index 5d4139e8..2b378406 100644 --- a/config/coreboot/default/patches/0021-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch +++ b/config/coreboot/default/patches/0011-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch @@ -1,7 +1,7 @@ -From 1111dcab65ca83f175f1bb9c0496cae24fbfb7c2 Mon Sep 17 00:00:00 2001 +From 53abe363f2fa038080a976f2d3a2c63ee8da9022 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 31 Jan 2024 22:07:25 -0700 -Subject: [PATCH 21/39] mb/dell: Add Latitude E6520 (Sandy Bridge) +Subject: [PATCH 11/51] mb/dell: Add Latitude E6520 (Sandy Bridge) Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was not tested. I do not physically have this system; someone with physical @@ -445,5 +445,5 @@ index 0000000000..f90f2dee1f + end +end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch b/config/coreboot/default/patches/0012-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch index cec59dbe..4fd3bba2 100644 --- a/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch +++ b/config/coreboot/default/patches/0012-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch @@ -1,7 +1,7 @@ -From 39dcb2dcada8821c49a3a042d9e70a6cda81a4ab Mon Sep 17 00:00:00 2001 +From 3f8eade6150f582129332f6347e9a685f8a7b500 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 7 Feb 2024 10:23:38 -0700 -Subject: [PATCH 22/39] mb/dell: Add Latitude E5520 (Sandy Bridge) +Subject: [PATCH 12/51] mb/dell: Add Latitude E5520 (Sandy Bridge) Mainboard is Krug 15". I do not physically have this system; someone with physical access to one sent me the output of autoport which I then @@ -438,5 +438,5 @@ index 0000000000..479d1b696e + end +end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch b/config/coreboot/default/patches/0013-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch index dda8313a..5944535f 100644 --- a/config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch +++ b/config/coreboot/default/patches/0013-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch @@ -1,7 +1,7 @@ -From 948221e226340c1c5852a73d005ada18120de393 Mon Sep 17 00:00:00 2001 +From bbcd6a7f09ee99f3b26b0931f1dcd70970242ee8 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 4 Mar 2024 18:05:43 -0700 -Subject: [PATCH 23/39] mb/dell: Add Latitude E5420 (Sandy Bridge) +Subject: [PATCH 13/51] mb/dell: Add Latitude E5420 (Sandy Bridge) Mainboard is Krug 14". I do not physically have this system; someone with physical access to one sent me the output of autoport which I then @@ -438,5 +438,5 @@ index 0000000000..3f55bfd49d + end +end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0014-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/default/patches/0014-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch deleted file mode 100644 index bfcc486a..00000000 --- a/config/coreboot/default/patches/0014-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch +++ /dev/null @@ -1,47 +0,0 @@ -From c53e5035b612710595abc93f0b4c3c65ca61ebad Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Wed, 1 Dec 2021 02:53:00 +0000 -Subject: [PATCH 14/39] fix speedstep on x200/t400: Revert - "cpu/intel/model_1067x: enable PECI" - -This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f. - -Enabling PECI without microcode updates loaded causes the CPUID feature set -to become corrupted. And one consequence is broken SpeedStep. At least, that's -my understanding looking at Intel Errata. This revert is not a fix, because -upstream is correct (upstream assumes microcode updates). We will simply -maintain this revert patch in Libreboot, from now on. ---- - src/cpu/intel/model_1067x/model_1067x_init.c | 9 --------- - 1 file changed, 9 deletions(-) - -diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c -index d051e8915b..30ba2bf0c6 100644 ---- a/src/cpu/intel/model_1067x/model_1067x_init.c -+++ b/src/cpu/intel/model_1067x/model_1067x_init.c -@@ -141,8 +141,6 @@ static void configure_emttm_tables(void) - wrmsr(MSR_EMTTM_CR_TABLE(5), msr); - } - --#define IA32_PECI_CTL 0x5a0 -- - static void configure_misc(const int eist, const int tm2, const int emttm) - { - msr_t msr; -@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm) - msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - } -- -- /* Enable PECI -- WARNING: due to Erratum AW67 described in Intel document #318733 -- the microcode must be updated before this MSR is written to. */ -- msr = rdmsr(IA32_PECI_CTL); -- msr.lo |= 1; -- wrmsr(IA32_PECI_CTL, msr); - } - - #define PIC_SENS_CFG 0x1aa --- -2.39.2 - diff --git a/config/coreboot/default/patches/0024-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch b/config/coreboot/default/patches/0014-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch index 0b731f5a..e8c46203 100644 --- a/config/coreboot/default/patches/0024-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch +++ b/config/coreboot/default/patches/0014-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch @@ -1,7 +1,7 @@ -From 5ebb21be501cf43d41d1690c29d047bd98fbc942 Mon Sep 17 00:00:00 2001 +From cd6e699649459fa5ff2623018ccf3585eb3d3821 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 7 Feb 2024 15:23:46 -0700 -Subject: [PATCH 24/39] mb/dell: Add Latitude E6320 (Sandy Bridge) +Subject: [PATCH 14/51] mb/dell: Add Latitude E6320 (Sandy Bridge) Mainboard is PAL70/LA-6611P. I do not physically have this system; someone with physical access to one sent me the output of autoport which @@ -431,5 +431,5 @@ index 0000000000..3bfe6b57ed + end +end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0015-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/default/patches/0015-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch deleted file mode 100644 index 4e0c8172..00000000 --- a/config/coreboot/default/patches/0015-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch +++ /dev/null @@ -1,173 +0,0 @@ -From dabe942b006082f6e592a26f1d0f13a2586b53d6 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Mon, 17 Apr 2023 15:49:57 +0100 -Subject: [PATCH 15/39] GM45-type CPUs: don't enable alternative SMRR - -This reverts the changes in coreboot revision: -df7aecd92643d207feaf7fd840f8835097346644 - -While this fix is *technically correct*, the one in -coreboot, it breaks rebooting as tested on several -GM45 ThinkPads e.g. X200, T400, when microcode -updates are not applied. - -Since November 2022, Libreboot includes microcode -updates by default, but it tells users how to remove -it from the ROM (with cbfstool) if they wish. - -Well, with Libreboot 20221214, 20230319 and 20230413, -mitigations present in Libreboot 20220710 (which did -not have microcode updates) do not exist. - -This patch, along with the other patch to remove PECI -support (which breaks speedstep when microcode updates -are not applied) have now been re-added to Libreboot. - -It is still best to use microcode updates by default. -These patches in coreboot are not critically urgent, -and you can use the machines with or without them, -regardless of ucode. - -I'll probably re-write this and the other patch at -some point, applying the change conditionally upon -whether or not microcode is applied. - -Pragmatism is a good thing. I recommend it. ---- - src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++ - src/cpu/intel/model_1067x/mp_init.c | 26 -------------------- - src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++ - src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++ - src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++ - 5 files changed, 16 insertions(+), 26 deletions(-) - -diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c -index 30ba2bf0c6..312046901a 100644 ---- a/src/cpu/intel/model_1067x/model_1067x_init.c -+++ b/src/cpu/intel/model_1067x/model_1067x_init.c -@@ -8,6 +8,7 @@ - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> - #include <cpu/intel/smm_reloc.h> -+#include <cpu/intel/common/common.h> - - #define MSR_BBL_CR_CTL3 0x11e - -@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu) - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(quad); - -diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c -index bc53214310..72f40f6762 100644 ---- a/src/cpu/intel/model_1067x/mp_init.c -+++ b/src/cpu/intel/model_1067x/mp_init.c -@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void) - smm_initialize(); - } - --#define SMRR_SUPPORTED (1 << 11) -- - static void per_cpu_smm_trigger(void) - { -- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); -- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) { -- set_feature_ctrl_vmx(); -- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL); -- /* We don't care if the lock is already setting -- as our smm relocation handler is able to handle -- setups where SMRR is not enabled here. */ -- if (ia32_ft_ctrl.lo & (1 << 0)) { -- /* IA32_FEATURE_CONTROL locked. If we set it again we -- get an illegal instruction. */ -- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n"); -- printk(BIOS_DEBUG, "SMRR status: %senabled\n", -- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not "); -- } else { -- if (!CONFIG(SET_IA32_FC_LOCK_BIT)) -- printk(BIOS_INFO, -- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n"); -- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); -- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); -- } -- } else { -- set_vmx_and_lock(); -- } -- - /* Relocate the SMM handler. */ - smm_relocate(); - } -diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c -index 05f5f327cc..0450c2ad83 100644 ---- a/src/cpu/intel/model_106cx/model_106cx_init.c -+++ b/src/cpu/intel/model_106cx/model_106cx_init.c -@@ -7,6 +7,7 @@ - #include <cpu/intel/speedstep.h> - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> -+#include <cpu/intel/common/common.h> - - #define HIGHEST_CLEVEL 3 - static void configure_c_states(void) -@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu) - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(); - -diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c -index 5bd1c32815..f3bb08cde3 100644 ---- a/src/cpu/intel/model_6ex/model_6ex_init.c -+++ b/src/cpu/intel/model_6ex/model_6ex_init.c -@@ -7,6 +7,7 @@ - #include <cpu/intel/speedstep.h> - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> -+#include <cpu/intel/common/common.h> - - #define HIGHEST_CLEVEL 3 - static void configure_c_states(void) -@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu) - /* Setup Page Attribute Tables (PAT) */ - // TODO set up PAT - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(); - -diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c -index 535fb8fae7..f7b05facd2 100644 ---- a/src/cpu/intel/model_6fx/model_6fx_init.c -+++ b/src/cpu/intel/model_6fx/model_6fx_init.c -@@ -7,6 +7,7 @@ - #include <cpu/intel/speedstep.h> - #include <cpu/x86/cache.h> - #include <cpu/x86/name.h> -+#include <cpu/intel/common/common.h> - - #define HIGHEST_CLEVEL 3 - static void configure_c_states(void) -@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu) - /* Setup Page Attribute Tables (PAT) */ - // TODO set up PAT - -+ /* Set virtualization based on Kconfig option */ -+ set_vmx_and_lock(); -+ - /* Configure C States */ - configure_c_states(); - --- -2.39.2 - diff --git a/config/coreboot/default/patches/0025-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch b/config/coreboot/default/patches/0015-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch index 0df0a822..e2be42c9 100644 --- a/config/coreboot/default/patches/0025-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch +++ b/config/coreboot/default/patches/0015-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch @@ -1,7 +1,7 @@ -From fbe48205a55b4a03082affe9f66e81ee509d5f44 Mon Sep 17 00:00:00 2001 +From a32431d5f7574ffa6391221c7740f1739203eaa7 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 8 Mar 2024 09:27:36 -0700 -Subject: [PATCH 25/39] mb/dell: Add Latitude E6220 (Sandy Bridge) +Subject: [PATCH 15/51] mb/dell: Add Latitude E6220 (Sandy Bridge) Mainboard is codenamed Vida. I do not physically have this system; someone with physical access to one sent me the output of autoport which @@ -434,5 +434,5 @@ index 0000000000..9faf27e27b + end +end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch b/config/coreboot/default/patches/0016-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch index c542ef86..7d2133ef 100644 --- a/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch +++ b/config/coreboot/default/patches/0016-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch @@ -1,7 +1,7 @@ -From 87e6f8bf38c5dcb4075d0df32507bf9151338b92 Mon Sep 17 00:00:00 2001 +From 0889cc6b6f62cba616feff5ae8558be31f298069 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 8 Mar 2024 09:33:03 -0700 -Subject: [PATCH 26/39] mb/dell: Add Latitude E6330 (Ivy Bridge) +Subject: [PATCH 16/51] mb/dell: Add Latitude E6330 (Ivy Bridge) Mainboard is QAL70/LA-7741P. I do not physically have this system; someone with physical access to one sent me the output of autoport which @@ -432,5 +432,5 @@ index 0000000000..4125159367 + end +end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0027-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch b/config/coreboot/default/patches/0017-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch index 6e49c8c2..412b8471 100644 --- a/config/coreboot/default/patches/0027-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch +++ b/config/coreboot/default/patches/0017-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch @@ -1,7 +1,7 @@ -From 611b5b3b4794eeda7ffb0a1876e1033705c50545 Mon Sep 17 00:00:00 2001 +From 84d7f3201eb4492acd7d290a02d19c4850c85791 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Thu, 26 Oct 2017 21:26:43 +0800 -Subject: [PATCH 27/39] mb/dell: Add Latitude E6230 (Ivy Bridge) +Subject: [PATCH 17/51] mb/dell: Add Latitude E6230 (Ivy Bridge) This was adapted from CB:22693 from Iru Cai, which was based on autoport. I do not physically have this system. Someone with physical @@ -436,5 +436,5 @@ index 0000000000..3a0fa720da + end +end -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0028-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0018-HACK-Disable-coreboot-related-BL31-features.patch index 04e4c6d0..9592215d 100644 --- a/config/coreboot/default/patches/0028-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0018-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From ea6e8749112dee4f458e9cf591e13e9097d56bab Mon Sep 17 00:00:00 2001 +From ec27f5414c78d493ec7be4cd055ac877ce9ea178 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 28/39] HACK: Disable coreboot related BL31 features +Subject: [PATCH 18/51] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. @@ -24,5 +24,5 @@ index cb43897efd..a9e5ff399a 100644 BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)" -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0031-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0019-dell-e6430-use-ME-Soft-Temporary-Disable.patch index 50fa15f2..b3d2d12c 100644 --- a/config/coreboot/default/patches/0031-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0019-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From dc02595f99566f71513ee16f1883e315b725241a Mon Sep 17 00:00:00 2001 +From a15b59616e00c43c05d7853080859d4aefe26c5d Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 31/39] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 19/51] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. @@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644 -me_state=Normal +me_state=Disabled -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0033-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0020-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index beb65908..46e38925 100644 --- a/config/coreboot/default/patches/0033-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0020-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From 67b7a9e4d06d595adf8382ee83e82b5019e23afa Mon Sep 17 00:00:00 2001 +From 440ebbe1e10911dc3d8c53cf9eecb5519c2ecd67 Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 1/1] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 20/51] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. @@ -868,5 +868,5 @@ index 0000000000..8dbd95ef96 + .enable_dev = mainboard_enable, +}; -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0034-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index ed6c0d65..b3305e58 100644 --- a/config/coreboot/default/patches/0034-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From eef3e0d517bde40d4761a9af3c004801a89db887 Mon Sep 17 00:00:00 2001 +From 4c7577314f19e934d690c4cce3642fe693400c07 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 34/39] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 21/51] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless @@ -288,5 +288,5 @@ index e47deb5da6..1a7e0b1076 100644 if (capid0_a & VTD_DISABLE) return; -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0035-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch index 1b9497c2..f18f119e 100644 --- a/config/coreboot/default/patches/0035-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From b7a80abe673c279e755efbe92851ec0600467fae Mon Sep 17 00:00:00 2001 +From b5695d0f0dc44ed1eb1feac008e601040feda55d Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 35/39] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 22/51] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off @@ -25,5 +25,5 @@ index 8000eea8c0..0700f971ee 100644 -iommu=Enable +iommu=Disable -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0036-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0023-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index b5606617..f9d80b9f 100644 --- a/config/coreboot/default/patches/0036-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0023-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From 4c0f0d139cdc0fbfadf76ee576d69503b81dc9dc Mon Sep 17 00:00:00 2001 +From d86824305f11bc684f1e91e3826158b8c7d7e0ee Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 36/39] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 23/51] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I @@ -47,5 +47,5 @@ index f7fad3183d..1b188e92e1 100644 static struct device_operations gma_func0_ops = { -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0024-ec-dell-mec5035-Replace-defines-with-enums.patch b/config/coreboot/default/patches/0024-ec-dell-mec5035-Replace-defines-with-enums.patch new file mode 100644 index 00000000..6c1118bb --- /dev/null +++ b/config/coreboot/default/patches/0024-ec-dell-mec5035-Replace-defines-with-enums.patch @@ -0,0 +1,91 @@ +From a1566875789469ebd91e472301be4b359aac0a4c Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Tue, 28 May 2024 17:23:21 -0600 +Subject: [PATCH 24/51] ec/dell/mec5035: Replace defines with enums + +Instead of using defines for command IDs and argument values, use enums +to provide more type safety. This also has the effect of moving the +command IDs to a more central location instead of defines spread out +throughout the header. + +Change-Id: I788531e8b70e79541213853f177326d217235ef2 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +Reviewed-on: https://review.coreboot.org/c/coreboot/+/82998 +Tested-by: build bot (Jenkins) <no-reply@coreboot.org> +Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> +--- + src/ec/dell/mec5035/mec5035.c | 10 +++++----- + src/ec/dell/mec5035/mec5035.h | 20 ++++++++++++-------- + 2 files changed, 17 insertions(+), 13 deletions(-) + +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index 68b6b2f7fb..dffbb7960c 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -66,17 +66,17 @@ static enum cb_err write_mailbox_regs(const u8 *data, u8 start, u8 count) + return CB_SUCCESS; + } + +-static void ec_command(u8 cmd) ++static void ec_command(enum mec5035_cmd cmd) + { + outb(0, MAILBOX_INDEX); +- outb(cmd, MAILBOX_DATA); ++ outb((u8)cmd, MAILBOX_DATA); + wait_ec(); + } + +-u8 mec5035_mouse_touchpad(u8 setting) ++u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting) + { +- u8 buf[15] = {0}; +- write_mailbox_regs(&setting, 2, 1); ++ u8 buf[15] = {(u8)setting}; ++ write_mailbox_regs(buf, 2, 1); + ec_command(CMD_MOUSE_TP); + /* The vendor firmware reads 15 bytes starting at index 1, presumably + to get some sort of return code. Though I don't know for sure if +diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h +index fa15a9d621..32f791cb01 100644 +--- a/src/ec/dell/mec5035/mec5035.h ++++ b/src/ec/dell/mec5035/mec5035.h +@@ -7,16 +7,20 @@ + + #define NUM_REGISTERS 32 + ++enum mec5035_cmd { ++ CMD_MOUSE_TP = 0x1a, ++ CMD_RADIO_CTRL = 0x2b, ++ CMD_CPU_OK = 0xc2, ++}; ++ + /* Touchpad (TP) and mouse related. The EC seems to + default to 0 which results in the TP not working. */ +-#define CMD_MOUSE_TP 0x1a +-#define SERIAL_MOUSE 0 /* Disable TP, force use of a serial mouse */ +-#define PS2_MOUSE 1 /* Disable TP when using a PS/2 mouse */ +-#define TP_PS2_MOUSE 2 /* Leave TP enabled when using a PS/2 mouse */ +- +-#define CMD_CPU_OK 0xc2 ++enum ec_mouse_setting { ++ SERIAL_MOUSE = 0, /* Disable TP, force use of a serial mouse */ ++ PS2_MOUSE, /* Disable TP when using a PS/2 mouse */ ++ TP_PS2_MOUSE /* Leave TP enabled when using a PS/2 mouse */ ++}; + +-#define CMD_RADIO_CTRL 0x2b + #define RADIO_CTRL_NUM_ARGS 3 + enum ec_radio_dev { + RADIO_WLAN = 0, +@@ -29,7 +33,7 @@ enum ec_radio_state { + RADIO_ON + }; + +-u8 mec5035_mouse_touchpad(u8 setting); ++u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting); + void mec5035_cpu_ok(void); + void mec5035_early_init(void); + void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state); +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0037-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0025-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index 8947fe3c..ed620a3e 100644 --- a/config/coreboot/default/patches/0037-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0025-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,16 +1,37 @@ -From 7e921212d3113320b2d28e66cd6a6788533fcab7 Mon Sep 17 00:00:00 2001 +From 2fdd5bbb2bbec76c3c2238c4cd471b9b63073942 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 37/39] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 25/51] ec/dell/mec5035: Add S3 suspend SMI handler + +This is necessary for S3 resume to work on SNB and newer Dell Latitude +laptops. If a command isn't sent, the EC cuts power to the DIMMs, +preventing the system from resuming. These commands were found using an +FPGA to log all LPC bus transactions between the host and the EC and +then narrowing down which ones were actually necessary. + +Interestingly, the command IDs appear to be identical to those in +ec/google/wilco, the EC used on Dell Latitude Chromebooks, and that EC +implements a similar S3 SMI handler as the one implemented in this +commit. The Wilco EC Kconfig does suggest that its firmware is a +modified version of Dell's usual Latitude EC firmware, so the +similarities seem to be intentional. + +These similarities also identified a command to enable or disable wake +sources like the power button and lid switch, and this was added to the +SMI handler to disable lid wake as the system does not yet resume +properly from a like wake with coreboot. + +Tested on the Latitude E6430 (Ivy Bridge) and the Precision M6800 +(Haswell, not yet pushed). Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> --- src/ec/dell/mec5035/Makefile.mk | 1 + src/ec/dell/mec5035/mec5035.c | 14 ++++++++++++++ - src/ec/dell/mec5035/mec5035.h | 19 +++++++++++++++++++ + src/ec/dell/mec5035/mec5035.h | 22 ++++++++++++++++++++++ src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++ - 4 files changed, 51 insertions(+) + 4 files changed, 54 insertions(+) create mode 100644 src/ec/dell/mec5035/smihandler.c diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk @@ -25,20 +46,13 @@ index 4ebdd811f9..be557e4599 100644 endif diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index 68b6b2f7fb..33bf046634 100644 +index dffbb7960c..85c2ab0140 100644 --- a/src/ec/dell/mec5035/mec5035.c +++ b/src/ec/dell/mec5035/mec5035.c @@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state) ec_command(CMD_RADIO_CTRL); } -+void mec5035_sleep_enable(void) -+{ -+ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0}; -+ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS); -+ ec_command(CMD_SLEEP_ENABLE); -+} -+ +void mec5035_change_wake(u8 source, enum ec_wake_change change) +{ + u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40}; @@ -46,14 +60,21 @@ index 68b6b2f7fb..33bf046634 100644 + ec_command(CMD_ACPI_WAKEUP_CHANGE); +} + ++void mec5035_sleep_enable(void) ++{ ++ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0}; ++ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS); ++ ec_command(CMD_SLEEP_ENABLE); ++} ++ void mec5035_early_init(void) { /* If this isn't sent the EC shuts down the system after about 15 diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index fa15a9d621..069616fbc5 100644 +index 32f791cb01..8d4fded28b 100644 --- a/src/ec/dell/mec5035/mec5035.h +++ b/src/ec/dell/mec5035/mec5035.h -@@ -4,6 +4,7 @@ +@@ -4,12 +4,15 @@ #define _EC_DELL_MEC5035_H_ #include <stdint.h> @@ -61,37 +82,46 @@ index fa15a9d621..069616fbc5 100644 #define NUM_REGISTERS 32 -@@ -29,9 +30,27 @@ enum ec_radio_state { + enum mec5035_cmd { + CMD_MOUSE_TP = 0x1a, + CMD_RADIO_CTRL = 0x2b, ++ CMD_ACPI_WAKEUP_CHANGE = 0x4a, ++ CMD_SLEEP_ENABLE = 0x64, + CMD_CPU_OK = 0xc2, + }; + +@@ -33,9 +36,28 @@ enum ec_radio_state { RADIO_ON }; -+#define CMD_ACPI_WAKEUP_CHANGE 0x4a +#define ACPI_WAKEUP_NUM_ARGS 4 +enum ec_wake_change { + WAKE_OFF = 0, + WAKE_ON +}; ++ ++/* Copied from ec/google/wilco/commands.h. Not sure if these all apply */ +enum ec_acpi_wake_events { + EC_ACPI_WAKE_PWRB = BIT(0), /* Wake up by power button */ + EC_ACPI_WAKE_LID = BIT(1), /* Wake up by lid switch */ + EC_ACPI_WAKE_RTC = BIT(5), /* Wake up by RTC */ +}; + -+#define CMD_SLEEP_ENABLE 0x64 +#define SLEEP_EN_NUM_ARGS 2 + - u8 mec5035_mouse_touchpad(u8 setting); + u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting); void mec5035_cpu_ok(void); void mec5035_early_init(void); void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state); -+void mec5035_sleep(int slp_type); +void mec5035_change_wake(u8 source, enum ec_wake_change change); +void mec5035_sleep_enable(void); ++ ++void mec5035_smi_sleep(int slp_type); #endif /* _EC_DELL_MEC5035_H_ */ diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c new file mode 100644 -index 0000000000..1db834773d +index 0000000000..958733bf97 --- /dev/null +++ b/src/ec/dell/mec5035/smihandler.c @@ -0,0 +1,17 @@ @@ -102,7 +132,7 @@ index 0000000000..1db834773d +#include <ec/acpi/ec.h> +#include "mec5035.h" + -+void mec5035_sleep(int slp_type) ++void mec5035_smi_sleep(int slp_type) +{ + switch (slp_type) { + case ACPI_S3: @@ -113,5 +143,5 @@ index 0000000000..1db834773d + } +} -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0039-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0026-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index f658b6d0..fe9034b0 100644 --- a/config/coreboot/default/patches/0039-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/coreboot/default/patches/0026-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From 919cbfa034db5d2ef9e56dd71ef329c38c5ede3c Mon Sep 17 00:00:00 2001 +From ce7d65790b9b8656ebbaa0ca715adff6a9c25588 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 39/39] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 26/51] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 @@ -51,5 +51,5 @@ index 1a7e0b1076..e9506ee830 100644 /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ u32 reg32; -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0040-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch index b673b5f6..28fc679f 100644 --- a/config/coreboot/default/patches/0040-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From fe5e1655be8cdb8eff1659e5ce6acbd06b9a7620 Mon Sep 17 00:00:00 2001 +From c6181fe0c8b58cb5a4523d5763fc5fcdf61b3f10 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 1/3] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 27/51] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values @@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644 + mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); } -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0041-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0028-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch index 30af9273..92e59129 100644 --- a/config/coreboot/default/patches/0041-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0028-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -1,7 +1,7 @@ -From 88a9c562b77316f1217139e62425f9af1c351c6f Mon Sep 17 00:00:00 2001 +From b6f75374fa38e0b097c9eadb4916112707cb6747 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 41/59] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards +Subject: [PATCH 28/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards We add this patch: @@ -236,5 +236,5 @@ index b74765fd9c..5d4505e063 100644 + } } -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0029-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index 991dcf44..e31cb64c 100644 --- a/config/coreboot/default/patches/0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/coreboot/default/patches/0029-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From b42ca30081b25cbabfb2659adca9d935ef3a8399 Mon Sep 17 00:00:00 2001 +From d3045b3dcebd94b78df2129cd81a20adf215e46a Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 3/3] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 29/51] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For @@ -48,5 +48,5 @@ index 8059e7ee80..5df5a93296 100644 select VBOOT_STARTS_IN_BOOTBLOCK -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0029-use-own-mirror-for-acpica-files.patch b/config/coreboot/default/patches/0029-use-own-mirror-for-acpica-files.patch deleted file mode 100644 index a06a5d23..00000000 --- a/config/coreboot/default/patches/0029-use-own-mirror-for-acpica-files.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 5c385ef4b4424ed8c37e549a00866edda960563f Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Wed, 31 Jul 2024 00:03:02 +0100 -Subject: [PATCH 29/39] use own mirror for acpica files - -intel likes to break links for no reason, -so we host our own backups of acpica. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - util/crossgcc/buildgcc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index ad756652ed..5faff337b4 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -74,7 +74,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" - MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" - GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" - BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" --IASL_BASE_URL="https://downloadmirror.intel.com/783534" -+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" - # CLANG toolchain archive locations - LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" - CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" --- -2.39.2 - diff --git a/config/coreboot/default/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch b/config/coreboot/default/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch deleted file mode 100644 index 55c95022..00000000 --- a/config/coreboot/default/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch +++ /dev/null @@ -1,142 +0,0 @@ -From c1065a638f2af40d8ef2c8586074bb82b96c02db Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Tue, 31 Oct 2023 18:24:39 +0000 -Subject: [PATCH 30/39] crank up vram allocation on more intel boards - -these were added to libreboot, and it's a policy of -libreboot to max out the vram settings. this was -overlooked, in prior revisions and releases. - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - src/mainboard/dell/e6400/cmos.default | 2 +- - src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +- - src/mainboard/hp/compaq_8200_elite_sff/cmos.default | 2 +- - src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +- - src/mainboard/hp/snb_ivb_laptops/cmos.default | 1 + - src/mainboard/lenovo/t420/cmos.default | 1 + - src/mainboard/lenovo/t420s/cmos.default | 1 + - src/mainboard/lenovo/t430/cmos.default | 1 + - src/mainboard/lenovo/t520/cmos.default | 1 + - src/mainboard/lenovo/t530/cmos.default | 1 + - src/mainboard/lenovo/x201/cmos.default | 1 + - src/mainboard/lenovo/x220/cmos.default | 1 + - 12 files changed, 12 insertions(+), 4 deletions(-) - -diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default -index 744a599708..6b8d478f06 100644 ---- a/src/mainboard/dell/e6400/cmos.default -+++ b/src/mainboard/dell/e6400/cmos.default -@@ -4,4 +4,4 @@ boot_option=Fallback - debug_level=Debug - power_on_after_fail=Disable - sata_mode=AHCI --gfx_uma_size=32M -+gfx_uma_size=256M -diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default -index 76c16e6a8d..19364aae6e 100644 ---- a/src/mainboard/dell/snb_ivb_workstations/cmos.default -+++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default -@@ -5,5 +5,5 @@ debug_level=Debug - power_on_after_fail=Disable - nmi=Enable - sata_mode=AHCI --gfx_uma_size=128M -+gfx_uma_size=224M - fan_full_speed=Disable -diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default -index 497ae92e1f..64d43a07f7 100644 ---- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default -+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default -@@ -5,5 +5,5 @@ debug_level=Debug - power_on_after_fail=Enable - nmi=Enable - sata_mode=AHCI --gfx_uma_size=32M -+gfx_uma_size=224M - psu_fan_lvl=3 -diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default -index f3dad88670..b60f28447b 100644 ---- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default -+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default -@@ -5,4 +5,4 @@ debug_level=Debug - power_on_after_fail=Enable - nmi=Enable - sata_mode=AHCI --gfx_uma_size=32M -+gfx_uma_size=224M -diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default -index e6042c0c27..a04026b70c 100644 ---- a/src/mainboard/hp/snb_ivb_laptops/cmos.default -+++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default -@@ -5,3 +5,4 @@ debug_level=Debug - power_on_after_fail=Disable - nmi=Enable - sata_mode=AHCI -+gfx_uma_size=224M -diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default -index 27a62d07b3..d1c9fcaaaf 100644 ---- a/src/mainboard/lenovo/t420/cmos.default -+++ b/src/mainboard/lenovo/t420/cmos.default -@@ -17,3 +17,4 @@ trackpoint=Enable - hybrid_graphics_mode=Integrated Only - usb_always_on=Disable - me_state=Disabled -+gfx_uma_size=224M -diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default -index 27a62d07b3..d1c9fcaaaf 100644 ---- a/src/mainboard/lenovo/t420s/cmos.default -+++ b/src/mainboard/lenovo/t420s/cmos.default -@@ -17,3 +17,4 @@ trackpoint=Enable - hybrid_graphics_mode=Integrated Only - usb_always_on=Disable - me_state=Disabled -+gfx_uma_size=224M -diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default -index 6d1e172056..c00b358314 100644 ---- a/src/mainboard/lenovo/t430/cmos.default -+++ b/src/mainboard/lenovo/t430/cmos.default -@@ -18,3 +18,4 @@ backlight=Both - usb_always_on=Disable - hybrid_graphics_mode=Integrated Only - me_state=Disabled -+gfx_uma_size=224M -diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default -index ab1be1a678..c7ee9564f3 100644 ---- a/src/mainboard/lenovo/t520/cmos.default -+++ b/src/mainboard/lenovo/t520/cmos.default -@@ -18,3 +18,4 @@ backlight=Both - hybrid_graphics_mode=Integrated Only - usb_always_on=Disable - me_state=Disabled -+gfx_uma_size=224M -diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default -index ab1be1a678..c7ee9564f3 100644 ---- a/src/mainboard/lenovo/t530/cmos.default -+++ b/src/mainboard/lenovo/t530/cmos.default -@@ -18,3 +18,4 @@ backlight=Both - hybrid_graphics_mode=Integrated Only - usb_always_on=Disable - me_state=Disabled -+gfx_uma_size=224M -diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default -index 94f8e08a75..a1f2eacf11 100644 ---- a/src/mainboard/lenovo/x201/cmos.default -+++ b/src/mainboard/lenovo/x201/cmos.default -@@ -17,3 +17,4 @@ power_management_beeps=Enable - low_battery_beep=Enable - sata_mode=AHCI - usb_always_on=Disable -+gfx_uma_size=128M -diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default -index b318ab9772..82292ea5d6 100644 ---- a/src/mainboard/lenovo/x220/cmos.default -+++ b/src/mainboard/lenovo/x220/cmos.default -@@ -16,3 +16,4 @@ fn_ctrl_swap=Disable - sticky_fn=Disable - trackpoint=Enable - me_state=Disabled -+gfx_uma_size=224M --- -2.39.2 - diff --git a/config/coreboot/default/patches/0043-haswell-NRI-Initialise-MPLL.patch b/config/coreboot/default/patches/0030-haswell-NRI-Initialise-MPLL.patch index 9b733998..a1cf9b75 100644 --- a/config/coreboot/default/patches/0043-haswell-NRI-Initialise-MPLL.patch +++ b/config/coreboot/default/patches/0030-haswell-NRI-Initialise-MPLL.patch @@ -1,7 +1,7 @@ -From 8b584165a99c69cc808f86efcdd55acb06a4464c Mon Sep 17 00:00:00 2001 +From 0966980e52286985fcd0fac6325bdd99f35ebcb8 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Thu, 11 Apr 2024 17:25:07 +0200 -Subject: [PATCH 01/17] haswell NRI: Initialise MPLL +Subject: [PATCH 30/51] haswell NRI: Initialise MPLL Add code to initialise the MPLL (Memory PLL). The procedure is similar to the one for Sandy/Ivy Bridge, but it is not worth factoring out. @@ -344,5 +344,5 @@ index 5610e7089a..45f8174995 100644 #define SAPMCTL 0x5f00 -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch b/config/coreboot/default/patches/0031-haswell-NRI-Post-process-selected-timings.patch index 924385ed..426cef35 100644 --- a/config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch +++ b/config/coreboot/default/patches/0031-haswell-NRI-Post-process-selected-timings.patch @@ -1,7 +1,7 @@ -From adde2e8d038b2d07ab7287eedab5888d92a56a60 Mon Sep 17 00:00:00 2001 +From 1dc22174b9b28b9ea9af59183ffd5d86d19a2721 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 16:29:55 +0200 -Subject: [PATCH 02/17] haswell NRI: Post-process selected timings +Subject: [PATCH 31/51] haswell NRI: Post-process selected timings Once the MPLL has been initialised, convert the timings from the SPD to be in DCLKs, which is what the hardware expects. In addition, calculate @@ -245,5 +245,5 @@ index eff993800b..4f7fe46494 100644 + return RAMINIT_STATUS_SUCCESS; +} -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0045-haswell-NRI-Configure-initial-MC-settings.patch b/config/coreboot/default/patches/0032-haswell-NRI-Configure-initial-MC-settings.patch index b51839d2..e16f4e3d 100644 --- a/config/coreboot/default/patches/0045-haswell-NRI-Configure-initial-MC-settings.patch +++ b/config/coreboot/default/patches/0032-haswell-NRI-Configure-initial-MC-settings.patch @@ -1,7 +1,7 @@ -From 0001039f5ea6be6700a453f511069be2ce1b4e7e Mon Sep 17 00:00:00 2001 +From a4f5deb78c2d4132bf857c57ffd53684f942ba62 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 17:22:07 +0200 -Subject: [PATCH 03/17] haswell NRI: Configure initial MC settings +Subject: [PATCH 32/51] haswell NRI: Configure initial MC settings Program initial memory controller settings. Many of these values will be adjusted later during training. @@ -1590,5 +1590,5 @@ index 45f8174995..4c3f399b5d 100644 #define HDAUDRID 0x6008 #define UMAGFXCTL 0x6020 -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch deleted file mode 100644 index e7cfab6f..00000000 --- a/config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch +++ /dev/null @@ -1,36 +0,0 @@ -From adb6121970034aa63da8c6303292ff81f340d9db Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 5 Nov 2023 22:57:08 +0000 -Subject: [PATCH 32/39] use mirrorservice.org for gcc downloads - -the gnu.org 302 redirect often fails - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/crossgcc/buildgcc | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 5faff337b4..2743f96903 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -69,11 +69,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" - # to the jenkins build as well, or the builder won't download it. - - # GCC toolchain archive locations --GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" --MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" --MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" --GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" --BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" -+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp" -+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" -+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" -+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" -+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" - IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" - # CLANG toolchain archive locations - LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" --- -2.39.2 - diff --git a/config/coreboot/default/patches/0046-haswell-NRI-Add-timings-refresh-programming.patch b/config/coreboot/default/patches/0033-haswell-NRI-Add-timings-refresh-programming.patch index 2b8b453e..3ec3b57b 100644 --- a/config/coreboot/default/patches/0046-haswell-NRI-Add-timings-refresh-programming.patch +++ b/config/coreboot/default/patches/0033-haswell-NRI-Add-timings-refresh-programming.patch @@ -1,7 +1,7 @@ -From 44032c7df6f4537c43ba80ae2f4a239616bd8d2d Mon Sep 17 00:00:00 2001 +From 8f94c0428eea2145a97de943b093dee29001c4f9 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 20:59:58 +0200 -Subject: [PATCH 04/17] haswell NRI: Add timings/refresh programming +Subject: [PATCH 33/51] haswell NRI: Add timings/refresh programming Program the registers with timing and refresh parameters. @@ -537,5 +537,5 @@ index 4c3f399b5d..2acc5cbbc8 100644 /* MCMAIN broadcast */ #define MCSCHEDS_CBIT 0x4c20 -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0047-haswell-NRI-Program-memory-map.patch b/config/coreboot/default/patches/0034-haswell-NRI-Program-memory-map.patch index 5628286a..bb3ed03d 100644 --- a/config/coreboot/default/patches/0047-haswell-NRI-Program-memory-map.patch +++ b/config/coreboot/default/patches/0034-haswell-NRI-Program-memory-map.patch @@ -1,7 +1,7 @@ -From 406e474c7f9f83dc10c7c0fa7cd9765ae822ad4e Mon Sep 17 00:00:00 2001 +From ded914f236f76715aa43cb439a3de7df9a3dfa11 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 21:24:50 +0200 -Subject: [PATCH 05/17] haswell NRI: Program memory map +Subject: [PATCH 34/51] haswell NRI: Program memory map This is very similar to Sandy/Ivy Bridge, except that there's several registers to program in GDXCBAR. One of these GDXCBAR registers has a @@ -259,5 +259,5 @@ index 1ee0ab2890..0228cf6bb9 100644 #define PAM0 0x80 #define PAM1 0x81 -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch b/config/coreboot/default/patches/0035-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch index 9f074e17..29bdec9f 100644 --- a/config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch +++ b/config/coreboot/default/patches/0035-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch @@ -1,7 +1,7 @@ -From eb8150a07c472078ad37887de13a166e6cf8bdad Mon Sep 17 00:00:00 2001 +From db2b383a8ee5a4fc45c9ce0003ae45f25ed51f86 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 21:49:40 +0200 -Subject: [PATCH 06/17] haswell NRI: Add DDR3 JEDEC reset and init +Subject: [PATCH 35/51] haswell NRI: Add DDR3 JEDEC reset and init Implement JEDEC reset and init sequence for DDR3. The MRS commands are issued through the REUT (Robust Electrical Unified Testing) hardware. @@ -1032,5 +1032,5 @@ index 07f4b9dc16..5b3696347c 100644 #define PMSYNC_CONFIG2 0x33cc /* 32bit */ #define SOFT_RESET_CTRL 0x38f4 -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0049-haswell-NRI-Add-pre-training-steps.patch b/config/coreboot/default/patches/0036-haswell-NRI-Add-pre-training-steps.patch index c6beea66..1b58a1f1 100644 --- a/config/coreboot/default/patches/0049-haswell-NRI-Add-pre-training-steps.patch +++ b/config/coreboot/default/patches/0036-haswell-NRI-Add-pre-training-steps.patch @@ -1,7 +1,7 @@ -From 19890277e3a0d411b016efbe1b54e511d4f36c0d Mon Sep 17 00:00:00 2001 +From 19bc8d27c8f52b205df218d5917ae67ac4646024 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 23:12:18 +0200 -Subject: [PATCH 07/17] haswell NRI: Add pre-training steps +Subject: [PATCH 36/51] haswell NRI: Add pre-training steps Implement pre-training steps, which consist of enabling ECC I/O and filling the WDB (Write Data Buffer, stores test patterns) through a @@ -388,5 +388,5 @@ index 4fc78a7f43..f8408e51a0 100644 #define REUT_ch_SEQ_CFG(ch) (0x48a8 + 8 * (ch)) -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0050-haswell-NRI-Add-REUT-I-O-test-library.patch b/config/coreboot/default/patches/0037-haswell-NRI-Add-REUT-I-O-test-library.patch index 6588c376..eaafcde3 100644 --- a/config/coreboot/default/patches/0050-haswell-NRI-Add-REUT-I-O-test-library.patch +++ b/config/coreboot/default/patches/0037-haswell-NRI-Add-REUT-I-O-test-library.patch @@ -1,7 +1,7 @@ -From 5ea55ac3f02a8a10f05e84ab9fbace424194869f Mon Sep 17 00:00:00 2001 +From 460a092b22c9800c5ee9d8c4198e8b241664693f Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 00:11:29 +0200 -Subject: [PATCH 08/17] haswell NRI: Add REUT I/O test library +Subject: [PATCH 37/51] haswell NRI: Add REUT I/O test library Implement a library to run I/O tests using the REUT hardware. @@ -1126,5 +1126,5 @@ index f8408e51a0..817a9f8bf8 100644 #define MCSCHEDS_CBIT 0x4c20 -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0051-haswell-NRI-Add-range-tracking-library.patch b/config/coreboot/default/patches/0038-haswell-NRI-Add-range-tracking-library.patch index 3b78012f..45fdc951 100644 --- a/config/coreboot/default/patches/0051-haswell-NRI-Add-range-tracking-library.patch +++ b/config/coreboot/default/patches/0038-haswell-NRI-Add-range-tracking-library.patch @@ -1,7 +1,7 @@ -From 07970f6dc64e5563c26013d842a929734e2bf8ed Mon Sep 17 00:00:00 2001 +From 36b206a88281796458e6ebc30fe34a7c51c86548 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 00:56:00 +0200 -Subject: [PATCH 09/17] haswell NRI: Add range tracking library +Subject: [PATCH 38/51] haswell NRI: Add range tracking library Implement a small library used to keep track of passing ranges. This will be used by 1D training algorithms when margining some parameter. @@ -218,5 +218,5 @@ index 0000000000..235392df96 + +#endif -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0038-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch b/config/coreboot/default/patches/0038-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch deleted file mode 100644 index 8da97601..00000000 --- a/config/coreboot/default/patches/0038-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 53bddae0fc8436fe262ca7fc2e19049afa7a38f8 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 38/39] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes - -This should fix S3 suspend on these systems - -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c - -diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c -new file mode 100644 -index 0000000000..334d7b1a5f ---- /dev/null -+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <cpu/x86/smm.h> -+#include <ec/dell/mec5035/mec5035.h> -+ -+void mainboard_smi_sleep(u8 slp_typ) -+{ -+ mec5035_sleep(slp_typ); -+} --- -2.39.2 - diff --git a/config/coreboot/default/patches/0052-haswell-NRI-Add-library-to-change-margins.patch b/config/coreboot/default/patches/0039-haswell-NRI-Add-library-to-change-margins.patch index ac096936..401433ac 100644 --- a/config/coreboot/default/patches/0052-haswell-NRI-Add-library-to-change-margins.patch +++ b/config/coreboot/default/patches/0039-haswell-NRI-Add-library-to-change-margins.patch @@ -1,7 +1,7 @@ -From 66db8447d6cf724c4b25618c94d5a53d501f214e Mon Sep 17 00:00:00 2001 +From 926b1af1033c26ad231587fd3a4506efb4b0d8a3 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 01:11:03 +0200 -Subject: [PATCH 10/17] haswell NRI: Add library to change margins +Subject: [PATCH 39/51] haswell NRI: Add library to change margins Implement a library to change Rx/Tx margins. It will be expanded later. @@ -290,5 +290,5 @@ index 817a9f8bf8..a81559bb1e 100644 #define REUT_ch_SEQ_ADDR_INC_CTL(ch) (0x4910 + 8 * (ch)) -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0053-haswell-NRI-Add-RcvEn-training.patch b/config/coreboot/default/patches/0040-haswell-NRI-Add-RcvEn-training.patch index a9821796..a40ffa69 100644 --- a/config/coreboot/default/patches/0053-haswell-NRI-Add-RcvEn-training.patch +++ b/config/coreboot/default/patches/0040-haswell-NRI-Add-RcvEn-training.patch @@ -1,7 +1,7 @@ -From 0826d1e9ba50daad13c3d5adccba4b180c82296b Mon Sep 17 00:00:00 2001 +From 61435822eb1d65b919bec45076737ce4ea91e1b1 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 00:05:41 +0200 -Subject: [PATCH 11/17] haswell NRI: Add RcvEn training +Subject: [PATCH 40/51] haswell NRI: Add RcvEn training Implement the RcvEn (Receive Enable) calibration procedure. @@ -704,5 +704,5 @@ index a81559bb1e..9172d4f2b0 100644 #define REUT_ch_PAT_WDB_CL_MUX_CFG(ch) _MCMAIN_C(0x4040, ch) -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0054-haswell-NRI-Add-function-to-change-margins.patch b/config/coreboot/default/patches/0041-haswell-NRI-Add-function-to-change-margins.patch index 881b81d6..296dbed6 100644 --- a/config/coreboot/default/patches/0054-haswell-NRI-Add-function-to-change-margins.patch +++ b/config/coreboot/default/patches/0041-haswell-NRI-Add-function-to-change-margins.patch @@ -1,7 +1,7 @@ -From 36ec2cfa730ba720ef7ded21cc3e84c47f4e2623 Mon Sep 17 00:00:00 2001 +From fc6c3edf561dd11eeb2ebe7f4cb93542e664935a Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 11:58:59 +0200 -Subject: [PATCH 12/17] haswell NRI: Add function to change margins +Subject: [PATCH 41/51] haswell NRI: Add function to change margins Implement a function to change margin parameters. Haswell provides a register to apply an offset to margin parameters during training, so @@ -268,5 +268,5 @@ index 9172d4f2b0..0acafbc826 100644 /* DDR CKE per-channel */ -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0055-haswell-NRI-Add-read-MPR-training.patch b/config/coreboot/default/patches/0042-haswell-NRI-Add-read-MPR-training.patch index 8a9a3daa..f2ccb7ad 100644 --- a/config/coreboot/default/patches/0055-haswell-NRI-Add-read-MPR-training.patch +++ b/config/coreboot/default/patches/0042-haswell-NRI-Add-read-MPR-training.patch @@ -1,7 +1,7 @@ -From 87015f060aa208f37481deef460b3545ce2d757f Mon Sep 17 00:00:00 2001 +From 8f07ea076572dd3371dca7b3dbd5ff9c9b332c55 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 11:35:49 +0200 -Subject: [PATCH 13/17] haswell NRI: Add read MPR training +Subject: [PATCH 42/51] haswell NRI: Add read MPR training Implement read training using DDR3 MPR (Multi-Purpose Register). @@ -328,5 +328,5 @@ index 0acafbc826..6a31d3a32c 100644 #define REUT_ch_PAT_CADB_MRS(ch) _MCMAIN_C(0x419c, ch) #define REUT_ch_PAT_CADB_MUX_CTRL(ch) _MCMAIN_C(0x41a0, ch) -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0056-haswell-NRI-Add-write-leveling.patch b/config/coreboot/default/patches/0043-haswell-NRI-Add-write-leveling.patch index a3f3e839..0202ed1b 100644 --- a/config/coreboot/default/patches/0056-haswell-NRI-Add-write-leveling.patch +++ b/config/coreboot/default/patches/0043-haswell-NRI-Add-write-leveling.patch @@ -1,7 +1,7 @@ -From ce0ed94f993506e75b711c214b49ba480037e7d3 Mon Sep 17 00:00:00 2001 +From 6df4b7eb0512c24a5f53bc92e81ad6cf42cd28a7 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 12:56:04 +0200 -Subject: [PATCH 14/17] haswell NRI: Add write leveling +Subject: [PATCH 43/51] haswell NRI: Add write leveling Implement JEDEC write leveling, which is done in two steps. The first step uses the JEDEC procedure to do "fine" write leveling, i.e. align @@ -685,5 +685,5 @@ index 6a31d3a32c..7c0b5a49de 100644 #define REUT_ch_MISC_ODT_CTRL(ch) _MCMAIN_C(0x4194, ch) #define REUT_ch_MISC_PAT_CADB_CTRL(ch) _MCMAIN_C(0x4198, ch) -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0057-haswell-NRI-Add-final-raminit-steps.patch b/config/coreboot/default/patches/0044-haswell-NRI-Add-final-raminit-steps.patch index db111ee1..62cae936 100644 --- a/config/coreboot/default/patches/0057-haswell-NRI-Add-final-raminit-steps.patch +++ b/config/coreboot/default/patches/0044-haswell-NRI-Add-final-raminit-steps.patch @@ -1,7 +1,7 @@ -From e30c9c431ef11d87c6f46071ec43cc34391b8349 Mon Sep 17 00:00:00 2001 +From 9d1b945702006db5678c5dc81699699bf6e6741a Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 14:29:05 +0200 -Subject: [PATCH 15/17] haswell NRI: Add final raminit steps +Subject: [PATCH 44/51] haswell NRI: Add final raminit steps Implement the remaining raminit steps. Although many training steps are missing, this is enough to boot on the Asrock B85M Pro4. @@ -566,5 +566,5 @@ index 7c0b5a49de..49a215aa71 100644 #define RCOMP_TIMER 0x5084 -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0058-Haswell-NRI-Implement-fast-boot-path.patch b/config/coreboot/default/patches/0045-Haswell-NRI-Implement-fast-boot-path.patch index 40e86a7a..af614a5f 100644 --- a/config/coreboot/default/patches/0058-Haswell-NRI-Implement-fast-boot-path.patch +++ b/config/coreboot/default/patches/0045-Haswell-NRI-Implement-fast-boot-path.patch @@ -1,7 +1,7 @@ -From 50c9d184cc89cd718c1cb95e1a3cabed24e09e1e Mon Sep 17 00:00:00 2001 +From b6b89013630d535b68a005cede9e2540f273f4e7 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 13 Apr 2024 01:16:30 +0200 -Subject: [PATCH 16/17] Haswell NRI: Implement fast boot path +Subject: [PATCH 45/51] Haswell NRI: Implement fast boot path When the memory configuration hasn't changed, there is no need to do full memory training. Instead, boot firmware can use saved training @@ -718,5 +718,5 @@ index 0000000000..f1f50e3ff8 + return RAMINIT_STATUS_SUCCESS; +} -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0059-haswell-NRI-Do-sense-amplifier-offset-training.patch b/config/coreboot/default/patches/0046-haswell-NRI-Do-sense-amplifier-offset-training.patch index c51560c7..c0945df9 100644 --- a/config/coreboot/default/patches/0059-haswell-NRI-Do-sense-amplifier-offset-training.patch +++ b/config/coreboot/default/patches/0046-haswell-NRI-Do-sense-amplifier-offset-training.patch @@ -1,7 +1,7 @@ -From 8528c7aa2a3cfcf0fe494a515a2e531ff0f1dab8 Mon Sep 17 00:00:00 2001 +From 02aa0c5612388e35f5dd1ff9c5f7a7b5b48fb9c0 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Wed, 17 Apr 2024 13:20:32 +0200 -Subject: [PATCH 17/17] haswell NRI: Do sense amplifier offset training +Subject: [PATCH 46/51] haswell NRI: Do sense amplifier offset training Quoting Wikipedia: @@ -472,5 +472,5 @@ index 49a215aa71..1a168a3fc8 100644 #define DQ_CONTROL_1(ch, byte) _DDRIO_C_R_B(0x0060, ch, 0, byte) -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0060-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0047-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch index 21b0d40c..988ae4e6 100644 --- a/config/coreboot/default/patches/0060-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ b/config/coreboot/default/patches/0047-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -1,7 +1,7 @@ -From f52188b46ce60383b67aeea2bda7ec52d631c822 Mon Sep 17 00:00:00 2001 +From 53f2d47ee6ebaa8d47b076a6c2a1514c91247b95 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 1/1] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ +Subject: [PATCH 47/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ set it to 96MHz. fixes the following build error when building for x4x boards e.g. gigabyte ga-g41m-es2l: @@ -48,5 +48,5 @@ index 9af063819b..93ba575b95 100644 default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX -- -2.39.2 +2.39.5 diff --git a/config/coreboot/default/patches/0048-mb-dell-Convert-E6400-into-a-variant.patch b/config/coreboot/default/patches/0048-mb-dell-Convert-E6400-into-a-variant.patch new file mode 100644 index 00000000..156d5c8d --- /dev/null +++ b/config/coreboot/default/patches/0048-mb-dell-Convert-E6400-into-a-variant.patch @@ -0,0 +1,243 @@ +From 92556743e92cc02524296b653de5241160876218 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Thu, 26 Sep 2024 19:48:26 -0600 +Subject: [PATCH 48/51] mb/dell: Convert E6400 into a variant + +All the GM45 Dell Latitudes should be nearly identical, so convert the +E6400 port into a variant so that future ports for the other systems can +share code with each other. + +Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/e6400/Makefile.mk | 10 -------- + .../dell/{e6400 => gm45_latitude}/Kconfig | 22 +++++++++++++----- + .../{e6400 => gm45_latitude}/Kconfig.name | 0 + src/mainboard/dell/gm45_latitude/Makefile.mk | 11 +++++++++ + .../dell/{e6400 => gm45_latitude}/acpi/ec.asl | 0 + .../acpi/ich9_pci_irqs.asl | 0 + .../{e6400 => gm45_latitude}/acpi/superio.asl | 0 + .../dell/{e6400 => gm45_latitude}/blc.c | 0 + .../{e6400 => gm45_latitude}/board_info.txt | 0 + .../dell/{e6400 => gm45_latitude}/bootblock.c | 0 + .../{e6400 => gm45_latitude}/cmos.default | 0 + .../dell/{e6400 => gm45_latitude}/cmos.layout | 0 + .../dell/{e6400 => gm45_latitude}/cstates.c | 0 + .../{e6400 => gm45_latitude}/devicetree.cb | 1 - + .../dell/{e6400 => gm45_latitude}/dsdt.asl | 0 + .../dell/{e6400 => gm45_latitude}/mainboard.c | 0 + .../dell/{e6400 => gm45_latitude}/romstage.c | 0 + .../variants}/e6400/data.vbt | Bin + .../variants}/e6400/gma-mainboard.ads | 0 + .../{ => gm45_latitude/variants}/e6400/gpio.c | 0 + .../variants}/e6400/hda_verb.c | 0 + .../variants/e6400/overridetree.cb | 7 ++++++ + 22 files changed, 34 insertions(+), 17 deletions(-) + delete mode 100644 src/mainboard/dell/e6400/Makefile.mk + rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig (64%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig.name (100%) + create mode 100644 src/mainboard/dell/gm45_latitude/Makefile.mk + rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ec.asl (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ich9_pci_irqs.asl (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/superio.asl (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/blc.c (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/board_info.txt (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/bootblock.c (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.default (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.layout (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/cstates.c (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/devicetree.cb (98%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/dsdt.asl (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/mainboard.c (100%) + rename src/mainboard/dell/{e6400 => gm45_latitude}/romstage.c (100%) + rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/data.vbt (100%) + rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gma-mainboard.ads (100%) + rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gpio.c (100%) + rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/hda_verb.c (100%) + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb + +diff --git a/src/mainboard/dell/e6400/Makefile.mk b/src/mainboard/dell/e6400/Makefile.mk +deleted file mode 100644 +index ca3a82db48..0000000000 +--- a/src/mainboard/dell/e6400/Makefile.mk ++++ /dev/null +@@ -1,10 +0,0 @@ +-## SPDX-License-Identifier: GPL-2.0-only +- +-bootblock-y += bootblock.c +- +-romstage-y += gpio.c +- +-ramstage-y += cstates.c +-ramstage-y += blc.c +- +-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig +similarity index 64% +rename from src/mainboard/dell/e6400/Kconfig +rename to src/mainboard/dell/gm45_latitude/Kconfig +index 6fe1b1c456..ba76fb6e8c 100644 +--- a/src/mainboard/dell/e6400/Kconfig ++++ b/src/mainboard/dell/gm45_latitude/Kconfig +@@ -1,9 +1,7 @@ + ## SPDX-License-Identifier: GPL-2.0-only + +-if BOARD_DELL_E6400 +- +-config BOARD_SPECIFIC_OPTIONS +- def_bool y ++config BOARD_DELL_GM45_LATITUDE_COMMON ++ def_bool n + select SYSTEM_TYPE_LAPTOP + select CPU_INTEL_SOCKET_P + select NORTHBRIDGE_INTEL_GM45 +@@ -19,19 +17,31 @@ config BOARD_SPECIFIC_OPTIONS + select INTEL_GMA_HAVE_VBT + select EC_DELL_MEC5035 + ++ ++config BOARD_DELL_E6400 ++ select BOARD_DELL_GM45_LATITUDE_COMMON ++ ++if BOARD_DELL_GM45_LATITUDE_COMMON ++ + config INTEL_GMA_DPLL_REF_FREQ + default 100000000 + + config MAINBOARD_DIR +- default "dell/e6400" ++ default "dell/gm45_latitude" + + config MAINBOARD_PART_NUMBER + default "Latitude E6400" if BOARD_DELL_E6400 + ++config OVERRIDE_DEVICETREE ++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" ++ ++config VARIANT_DIR ++ default "e6400" if BOARD_DELL_E6400 ++ + config USBDEBUG_HCD_INDEX + default 1 + + config CBFS_SIZE + default 0x1A0000 + +-endif # BOARD_DELL_E6400 ++endif # BOARD_DELL_GM45_LATITUDE_COMMON +diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name +similarity index 100% +rename from src/mainboard/dell/e6400/Kconfig.name +rename to src/mainboard/dell/gm45_latitude/Kconfig.name +diff --git a/src/mainboard/dell/gm45_latitude/Makefile.mk b/src/mainboard/dell/gm45_latitude/Makefile.mk +new file mode 100644 +index 0000000000..5295d5be22 +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/Makefile.mk +@@ -0,0 +1,11 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++bootblock-y += bootblock.c ++ ++romstage-y += variants/$(VARIANT_DIR)/gpio.c ++ ++ramstage-y += cstates.c ++ramstage-y += blc.c ++ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads +diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/gm45_latitude/acpi/ec.asl +similarity index 100% +rename from src/mainboard/dell/e6400/acpi/ec.asl +rename to src/mainboard/dell/gm45_latitude/acpi/ec.asl +diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl +similarity index 100% +rename from src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl +rename to src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl +diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/gm45_latitude/acpi/superio.asl +similarity index 100% +rename from src/mainboard/dell/e6400/acpi/superio.asl +rename to src/mainboard/dell/gm45_latitude/acpi/superio.asl +diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/gm45_latitude/blc.c +similarity index 100% +rename from src/mainboard/dell/e6400/blc.c +rename to src/mainboard/dell/gm45_latitude/blc.c +diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/gm45_latitude/board_info.txt +similarity index 100% +rename from src/mainboard/dell/e6400/board_info.txt +rename to src/mainboard/dell/gm45_latitude/board_info.txt +diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/gm45_latitude/bootblock.c +similarity index 100% +rename from src/mainboard/dell/e6400/bootblock.c +rename to src/mainboard/dell/gm45_latitude/bootblock.c +diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/gm45_latitude/cmos.default +similarity index 100% +rename from src/mainboard/dell/e6400/cmos.default +rename to src/mainboard/dell/gm45_latitude/cmos.default +diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/gm45_latitude/cmos.layout +similarity index 100% +rename from src/mainboard/dell/e6400/cmos.layout +rename to src/mainboard/dell/gm45_latitude/cmos.layout +diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/gm45_latitude/cstates.c +similarity index 100% +rename from src/mainboard/dell/e6400/cstates.c +rename to src/mainboard/dell/gm45_latitude/cstates.c +diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb +similarity index 98% +rename from src/mainboard/dell/e6400/devicetree.cb +rename to src/mainboard/dell/gm45_latitude/devicetree.cb +index e9f3915d17..76dae87153 100644 +--- a/src/mainboard/dell/e6400/devicetree.cb ++++ b/src/mainboard/dell/gm45_latitude/devicetree.cb +@@ -15,7 +15,6 @@ chip northbridge/intel/gm45 + register "pci_mmio_size" = "2048" + + device domain 0 on +- subsystemid 0x1028 0x0233 inherit + ops gm45_pci_domain_ops + + device pci 00.0 on end # host bridge +diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/gm45_latitude/dsdt.asl +similarity index 100% +rename from src/mainboard/dell/e6400/dsdt.asl +rename to src/mainboard/dell/gm45_latitude/dsdt.asl +diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/gm45_latitude/mainboard.c +similarity index 100% +rename from src/mainboard/dell/e6400/mainboard.c +rename to src/mainboard/dell/gm45_latitude/mainboard.c +diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/gm45_latitude/romstage.c +similarity index 100% +rename from src/mainboard/dell/e6400/romstage.c +rename to src/mainboard/dell/gm45_latitude/romstage.c +diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt +similarity index 100% +rename from src/mainboard/dell/e6400/data.vbt +rename to src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt +diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads +similarity index 100% +rename from src/mainboard/dell/e6400/gma-mainboard.ads +rename to src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads +diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c +similarity index 100% +rename from src/mainboard/dell/e6400/gpio.c +rename to src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c +diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c +similarity index 100% +rename from src/mainboard/dell/e6400/hda_verb.c +rename to src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c +diff --git a/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb +new file mode 100644 +index 0000000000..acc34a2252 +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb +@@ -0,0 +1,7 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/gm45 ++ device domain 0 on ++ subsystemid 0x1028 0x0233 inherit ++ end ++end +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0049-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0049-mb-dell-gm45_latitudes-Add-E4300-variant.patch new file mode 100644 index 00000000..2cdcd499 --- /dev/null +++ b/config/coreboot/default/patches/0049-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -0,0 +1,332 @@ +From ac8ac2543e3ebbc05f79f37d1460cde532a7ee1c Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Thu, 26 Sep 2024 19:51:25 -0600 +Subject: [PATCH 49/51] mb/dell/gm45_latitudes: Add E4300 variant + +Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/gm45_latitude/Kconfig | 5 + + src/mainboard/dell/gm45_latitude/Kconfig.name | 3 + + .../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes + .../variants/e4300/gma-mainboard.ads | 17 +++ + .../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++ + .../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++ + .../variants/e4300/overridetree.cb | 10 ++ + 7 files changed, 210 insertions(+) + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c + create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb + +diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig +index ba76fb6e8c..144f9bcdf0 100644 +--- a/src/mainboard/dell/gm45_latitude/Kconfig ++++ b/src/mainboard/dell/gm45_latitude/Kconfig +@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON + config BOARD_DELL_E6400 + select BOARD_DELL_GM45_LATITUDE_COMMON + ++config BOARD_DELL_E4300 ++ select BOARD_DELL_GM45_LATITUDE_COMMON ++ + if BOARD_DELL_GM45_LATITUDE_COMMON + + config INTEL_GMA_DPLL_REF_FREQ +@@ -31,12 +34,14 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "Latitude E6400" if BOARD_DELL_E6400 ++ default "Latitude E4300" if BOARD_DELL_E4300 + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + + config VARIANT_DIR + default "e6400" if BOARD_DELL_E6400 ++ default "e4300" if BOARD_DELL_E4300 + + config USBDEBUG_HCD_INDEX + default 1 +diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name +index aefe777109..4dc95f46be 100644 +--- a/src/mainboard/dell/gm45_latitude/Kconfig.name ++++ b/src/mainboard/dell/gm45_latitude/Kconfig.name +@@ -1,4 +1,7 @@ + ## SPDX-License-Identifier: GPL-2.0-only + ++config BOARD_DELL_E4300 ++ bool "Latitude E4300" ++ + config BOARD_DELL_E6400 + bool "Latitude E6400" +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3 +GIT binary patch +literal 3881 +zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+ +zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5a<biIGGii6#d8gP4#QmGpeGyBx))(i;53 +zx0(69nR)Nco0&Inc1d4HFVD7b?CrX@org342aOf$sh&<9U7NP<Sl8a$zN4diQ+5M? +z9rN*fa`GZDAW257d6jcVwtw%wp<VsFPss9IbIT6VyT7@GKQuhTyNCDm-+uql-l6R9 +zaA9y{CEr#U=-)Ruz;_Pq?H?H$9GyPr&Fjey7akuO+O>Nhx3i7B*>RjEs#<v0-hG36 +zcy@TCu#&g$*~7O8nNhxFaCC5F|KPw%gBc7st!SzQND;)Ih9pfkBd$T$U~A~qu#ltO +zMczfDhAs`eH4JHpsJLH4lZIP4`dyfi4M|pkg+SayZ(n(7kunGFvl<qe=w81$=+A#a +zN=hgb2&njUcPLB!=P$(o-$={^mxQGIHvtVGBS4IU%YyNVhd3krw*m^es@B12UftTZ +zHsf}zTi<zK_vS6VeYx!qdQTpH>PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC +zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpD<v6uK&w=s5=N^P +zn1nKYZrHyr#A-t5vRX$dPN$Pl=yivfA{67CP>h$)OQqAIh6jOwCxuw)qvS0N+Nk!? +zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E +z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u +z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L<DD#SV;6@`cGC4?jgJ8YLq>~qi^ +z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I<Q#e&+8Yy!=BeKi&0@sfte<K0& +zMgsgs0(vE~6cP&098SWEom4ZZF%<l!OeEuw4n?=)Y_tg#&wy^{e@5{s`F9qRm`5m; +zi_|4iQq@4&R8mD)tJIvCw3$`@-B9JV=`1}s_;B_rjtcVXpQ!o`MAJ$M5w65C7t<Ku +z%xfIo$p$+0N}Qe(C7MY#!0SQ1({^-qFj5ylEHjhwn>8}OhGtOw#1e$Fn9w<r1Zp}l +zPz$#mOP$ow*1(UHvmCGVz;T^IRnSxa*6jz+_oSD)xmT|Cbl&YcJ5M&d?&+&NDI2Y0 +zO0ai&>sUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6 +z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e% +zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D +z!+P0Z#|`^S!}`Hs7Yw^5X*DKUOVaL7TBAv}d|dV9^O8rYn%=4o&5GjdSWeb`yeyf7 +zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG* +zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg +zI{c?gKNv~R$<jgIlQvzm9GD`y{Dh<T(H)!WlUUWvtFvzDqaVV>&eHj<So5w}UG%+7 +zt=J~1YHpT3TjRY{XlrmCz6QBZ$WqGr>8!uus22Br_GkCD$Q)pf!<P$30Ez;o=qDzr +z7@f;LJ+ZPlo=?}4PvMm&OKLGLZ0h1&n7U8@9GP~;8!wz(OqQ<s6e;@8hfYU0ht*9> +zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K<j&AXad#XeO8mgw(v +z_Gj1VBJZIpZ<>`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692<oYlGx5_cte6LX +JE5(FU=`RLB=-&VU + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads +new file mode 100644 +index 0000000000..89b81b3d69 +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads +@@ -0,0 +1,17 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP2, -- dock DP ++ Analog, -- mainboard VGA ++ LVDS, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c +new file mode 100644 +index 0000000000..b50f8da0b5 +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c +@@ -0,0 +1,138 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_GPIO, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_NATIVE, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_NATIVE, ++ .gpio30 = GPIO_MODE_NATIVE, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio1 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio1 = GPIO_INVERT, ++ .gpio7 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_NATIVE, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_GPIO, ++ .gpio54 = GPIO_MODE_NATIVE, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_INPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio53 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++}; +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c +new file mode 100644 +index 0000000000..a9948a93dd +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c +@@ -0,0 +1,37 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x111d76b2, /* IDT 92HD71B7X */ ++ 0x1028024d, /* Subsystem ID */ ++ 13, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f), ++ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021), ++ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2), ++ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0), ++ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4), ++ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5), ++ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6), ++ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7), ++ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0), ++}; ++ ++const u32 pc_beep_verbs[] = { ++ 0x00170500, /* power up codec */ ++ 0x00d70500, /* power up speakers */ ++ 0x00d70102, /* select mixer (input 0x2) for speakers */ ++ 0x00d70740, /* enable speakers output */ ++ 0x02770720, /* enable beep input */ ++ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */ ++ 0x00d37000, /* unmute speakers */ ++}; ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb +new file mode 100644 +index 0000000000..20dfa245fb +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/gm45 ++ device domain 0 on ++ subsystemid 0x1028 0x024d inherit ++ chip southbridge/intel/i82801ix ++ device pci 1c.2 off end # PCIe Port #3 ++ end ++ end ++end +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0050-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0050-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch new file mode 100644 index 00000000..71cc67c1 --- /dev/null +++ b/config/coreboot/default/patches/0050-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -0,0 +1,70 @@ +From 5e8b899654c31fe771e4b1e96c74c93d4509c3b2 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Fri, 3 May 2024 16:31:12 -0600 +Subject: [PATCH 50/51] mb/dell: Add S3 SMI handler for Dell Latitudes + +Integrate the previously added mec5035_smi_sleep() function into +mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. +The E6400 does not require the EC command to sucessfully suspend and +resume from S3, though sending it does enable the breathing effect on +the power LED while in S3. Without it, all LEDs turn off during S3. + +Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/e7240/smihandler.c | 9 +++++++++ + src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++ + src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++ + 3 files changed, 27 insertions(+) + create mode 100644 src/mainboard/dell/e7240/smihandler.c + create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c + create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c + +diff --git a/src/mainboard/dell/e7240/smihandler.c b/src/mainboard/dell/e7240/smihandler.c +new file mode 100644 +index 0000000000..00e55b51db +--- /dev/null ++++ b/src/mainboard/dell/e7240/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <cpu/x86/smm.h> ++#include <ec/dell/mec5035/mec5035.h> ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_smi_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c +new file mode 100644 +index 0000000000..00e55b51db +--- /dev/null ++++ b/src/mainboard/dell/gm45_latitude/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <cpu/x86/smm.h> ++#include <ec/dell/mec5035/mec5035.h> ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_smi_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c +new file mode 100644 +index 0000000000..00e55b51db +--- /dev/null ++++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <cpu/x86/smm.h> ++#include <ec/dell/mec5035/mec5035.h> ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_smi_sleep(slp_typ); ++} +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0051-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0051-ec-dell-mec5035-Route-power-button-event-to-host.patch new file mode 100644 index 00000000..65f90e2c --- /dev/null +++ b/config/coreboot/default/patches/0051-ec-dell-mec5035-Route-power-button-event-to-host.patch @@ -0,0 +1,92 @@ +From 1a342c20b8705bbea02d27a73e383ee2808f2558 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Tue, 18 Jun 2024 21:31:08 -0600 +Subject: [PATCH 51/51] ec/dell/mec5035: Route power button event to host + +If command 0x3e with an argument of 1 isn't sent to the EC, pressing the +power button results in the EC powering off the system without letting +the OS cleanly shutting itself down. This command and argument tells the +EC to route power button events to the host so that it can determine +what to do. + +The EC command was identified from the ec/google/wilco code, which is +used for Dell's Latitude Chromebooks. According to the EC_GOOGLE_WILCO +Kconfig help text, those ECs run a modified version of Dell's typical +Latitude EC firmware, so it is likely that the two firmware +implementations use similar commands. Examining LPC traffic between the +host and the EC on the Latitude E6400 did reveal that the same command +was being sent by the vendor firmware to the EC, but this does not +confirm that it has the same meaning as the command from the Wilco code. +Sending the command using inb/outb calls in a userspace C program while +running coreboot without this patch did allow subsequent power button +events to be handled by the host, confirming that the command was indeed +the same. + +Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/ec/dell/mec5035/mec5035.c | 8 ++++++++ + src/ec/dell/mec5035/mec5035.h | 7 +++++++ + 2 files changed, 15 insertions(+) + +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index 85c2ab0140..bdae929a27 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state) + ec_command(CMD_RADIO_CTRL); + } + ++void mec5035_power_button_route(enum ec_power_button_route target) ++{ ++ u8 buf = (u8)target; ++ write_mailbox_regs(&buf, 2, 1); ++ ec_command(CMD_POWER_BUTTON_TO_HOST); ++} ++ + void mec5035_change_wake(u8 source, enum ec_wake_change change) + { + u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40}; +@@ -121,6 +128,7 @@ static void mec5035_init(struct device *dev) + /* Unconditionally use this argument for now as this setting + is probably the most sensible default out of the 3 choices. */ + mec5035_mouse_touchpad(TP_PS2_MOUSE); ++ mec5035_power_button_route(HOST); + + pc_keyboard_init(NO_AUX_DEVICE); + +diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h +index 8d4fded28b..51422598c4 100644 +--- a/src/ec/dell/mec5035/mec5035.h ++++ b/src/ec/dell/mec5035/mec5035.h +@@ -11,6 +11,7 @@ + enum mec5035_cmd { + CMD_MOUSE_TP = 0x1a, + CMD_RADIO_CTRL = 0x2b, ++ CMD_POWER_BUTTON_TO_HOST = 0x3e, + CMD_ACPI_WAKEUP_CHANGE = 0x4a, + CMD_SLEEP_ENABLE = 0x64, + CMD_CPU_OK = 0xc2, +@@ -36,6 +37,11 @@ enum ec_radio_state { + RADIO_ON + }; + ++enum ec_power_button_route { ++ EC = 0, ++ HOST ++}; ++ + #define ACPI_WAKEUP_NUM_ARGS 4 + enum ec_wake_change { + WAKE_OFF = 0, +@@ -55,6 +61,7 @@ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting); + void mec5035_cpu_ok(void); + void mec5035_early_init(void); + void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state); ++void mec5035_power_button_route(enum ec_power_button_route target); + void mec5035_change_wake(u8 source, enum ec_wake_change change); + void mec5035_sleep_enable(void); + +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch b/config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch deleted file mode 100644 index b09dac46..00000000 --- a/config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch +++ /dev/null @@ -1,932 +0,0 @@ -From 76a22c32d673f7e9afe66424512035586433a78c Mon Sep 17 00:00:00 2001 -From: Mate Kukri <kukri.mate@gmail.com> -Date: Sun, 14 Jul 2024 14:24:12 +0100 -Subject: [PATCH 1/1] [WIP] OptiPlex 3050 Micro port - -- Boots Linux -- SMSC SCH5553 SIO/EC - + Early EC init + HWM init implemented - + Console on serial port tested - + TODO: late HWM init for fan control (fan runs at low speed now) -- Realtek Gigabit LAN works -- WiFi slot works -- NVMe SSD slot works -- Extra: LPSS UART0 - + Stock FW sets undocumented power gating bit, RTC battery needs to - be pulled for it to work. - + Signals exposed on test points on the back of the board. - FIXME: add documentation about this -- Needs 'deguard' to bypass BootGuard - + See https://review.coreboot.org/plugins/gitiles/deguard -- TODO: HDA verbs -- TODO: USB ports -- TODO: Add VBT -- Currently limited to the Micro form factor, but others are very - similar - -Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 -Signed-off-by: Mate Kukri <kukri.mate@gmail.com> ---- - src/mainboard/dell/optiplex_3050/Kconfig | 34 +++ - src/mainboard/dell/optiplex_3050/Kconfig.name | 4 + - src/mainboard/dell/optiplex_3050/Makefile.mk | 9 + - src/mainboard/dell/optiplex_3050/acpi/ec.asl | 3 + - .../dell/optiplex_3050/acpi/superio.asl | 3 + - .../dell/optiplex_3050/board_info.txt | 7 + - src/mainboard/dell/optiplex_3050/bootblock.c | 107 ++++++++ - src/mainboard/dell/optiplex_3050/cmos.default | 5 + - src/mainboard/dell/optiplex_3050/cmos.layout | 54 ++++ - .../dell/optiplex_3050/devicetree.cb | 123 +++++++++ - src/mainboard/dell/optiplex_3050/dsdt.asl | 27 ++ - .../dell/optiplex_3050/gma-mainboard.ads | 19 ++ - .../dell/optiplex_3050/include/early_gpio.h | 11 + - .../dell/optiplex_3050/include/gpio.h | 241 ++++++++++++++++++ - src/mainboard/dell/optiplex_3050/ramstage.c | 17 ++ - src/mainboard/dell/optiplex_3050/romstage.c | 26 ++ - src/mainboard/dell/optiplex_3050/sch5555_ec.c | 54 ++++ - src/mainboard/dell/optiplex_3050/sch5555_ec.h | 10 + - 18 files changed, 754 insertions(+) - create mode 100644 src/mainboard/dell/optiplex_3050/Kconfig - create mode 100644 src/mainboard/dell/optiplex_3050/Kconfig.name - create mode 100644 src/mainboard/dell/optiplex_3050/Makefile.mk - create mode 100644 src/mainboard/dell/optiplex_3050/acpi/ec.asl - create mode 100644 src/mainboard/dell/optiplex_3050/acpi/superio.asl - create mode 100644 src/mainboard/dell/optiplex_3050/board_info.txt - create mode 100644 src/mainboard/dell/optiplex_3050/bootblock.c - create mode 100644 src/mainboard/dell/optiplex_3050/cmos.default - create mode 100644 src/mainboard/dell/optiplex_3050/cmos.layout - create mode 100644 src/mainboard/dell/optiplex_3050/devicetree.cb - create mode 100644 src/mainboard/dell/optiplex_3050/dsdt.asl - create mode 100644 src/mainboard/dell/optiplex_3050/gma-mainboard.ads - create mode 100644 src/mainboard/dell/optiplex_3050/include/early_gpio.h - create mode 100644 src/mainboard/dell/optiplex_3050/include/gpio.h - create mode 100644 src/mainboard/dell/optiplex_3050/ramstage.c - create mode 100644 src/mainboard/dell/optiplex_3050/romstage.c - create mode 100644 src/mainboard/dell/optiplex_3050/sch5555_ec.c - create mode 100644 src/mainboard/dell/optiplex_3050/sch5555_ec.h - -diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig -new file mode 100644 -index 0000000000..763acda0b2 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/Kconfig -@@ -0,0 +1,34 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+if BOARD_DELL_OPTIPLEX_3050 -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ select BOARD_ROMSIZE_KB_16384 -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select HAVE_CMOS_DEFAULT -+ select HAVE_OPTION_TABLE -+ # select INTEL_GMA_HAVE_VBT -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_HAS_TPM2 -+ select MAINBOARD_SUPPORTS_KABYLAKE_CPU -+ select MAINBOARD_SUPPORTS_SKYLAKE_CPU -+ select MEMORY_MAPPED_TPM -+ select SKYLAKE_SOC_PCH_H -+ select SOC_INTEL_KABYLAKE -+ select SUPERIO_SMSC_SCH555x -+ -+config CBFS_SIZE -+ default 0x900000 -+ -+config MAINBOARD_DIR -+ default "dell/optiplex_3050" -+ -+config MAINBOARD_PART_NUMBER -+ default "OptiPlex 3050 Micro" -+ -+config DIMM_SPD_SIZE -+ default 512 # DDR4 -+ -+endif -diff --git a/src/mainboard/dell/optiplex_3050/Kconfig.name b/src/mainboard/dell/optiplex_3050/Kconfig.name -new file mode 100644 -index 0000000000..14eab7f52c ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/Kconfig.name -@@ -0,0 +1,4 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_DELL_OPTIPLEX_3050 -+ bool "OptiPlex 3050 Micro" -diff --git a/src/mainboard/dell/optiplex_3050/Makefile.mk b/src/mainboard/dell/optiplex_3050/Makefile.mk -new file mode 100644 -index 0000000000..c078124332 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/Makefile.mk -@@ -0,0 +1,9 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+bootblock-y += bootblock.c -+bootblock-y += sch5555_ec.c -+ -+romstage-y += romstage.c -+ -+ramstage-y += ramstage.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/optiplex_3050/acpi/ec.asl b/src/mainboard/dell/optiplex_3050/acpi/ec.asl -new file mode 100644 -index 0000000000..16990d45f4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/acpi/ec.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -diff --git a/src/mainboard/dell/optiplex_3050/acpi/superio.asl b/src/mainboard/dell/optiplex_3050/acpi/superio.asl -new file mode 100644 -index 0000000000..16990d45f4 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: CC-PDDC */ -+ -+/* Please update the license if adding licensable material. */ -diff --git a/src/mainboard/dell/optiplex_3050/board_info.txt b/src/mainboard/dell/optiplex_3050/board_info.txt -new file mode 100644 -index 0000000000..47a4a3a4f3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/board_info.txt -@@ -0,0 +1,7 @@ -+Category: desktop -+Board URL: https://www.dell.com/support/kbdoc/en-uk/000124265/dell-optiplex-3050-system-guide -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2017 -diff --git a/src/mainboard/dell/optiplex_3050/bootblock.c b/src/mainboard/dell/optiplex_3050/bootblock.c -new file mode 100644 -index 0000000000..10689c42a1 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/bootblock.c -@@ -0,0 +1,107 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <bootblock_common.h> -+#include <device/pnp_ops.h> -+#include <soc/gpio.h> -+#include <superio/smsc/sch555x/sch555x.h> -+#include "include/early_gpio.h" -+#include "sch5555_ec.h" -+ -+struct ec_init_entry { -+ uint16_t addr; -+ uint8_t val; -+}; -+ -+static void bootblock_ec_init(void) -+{ -+ /* -+ * Early EC init -+ */ -+ -+ static const struct ec_init_entry init_table1[] = { -+ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, -+ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, -+ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, -+ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, -+ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, -+ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) -+ sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val); -+ -+ static const struct ec_init_entry init_table2[] = { -+ {0x0040, 0x00}, {0x00f8, 0x10}, {0x00f9, 0x00}, {0x00f0, 0x30}, -+ {0x00fa, 0x00}, {0x00fb, 0x00}, {0x00ea, 0x00}, {0x00eb, 0x00}, -+ {0x00ef, 0x7c}, {0x0005, 0x0f}, {0x0014, 0x01}, {0x0018, 0x2f}, -+ {0x0019, 0x2f}, {0x001a, 0x2f}, {0x001b, 0x2f}, {0x01d8, 0x01}, -+ {0x0040, 0x11}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) -+ sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val); -+ -+ sch5555_mbox_write(1, 0x000b, 0x01); -+ sch5555_mbox_write(4, 0x001a, 0x04); -+ sch5555_mbox_write(4, 0x0028, 0x18); -+ sch5555_mbox_write(4, 0x001a, 0x00); -+ sch5555_mbox_write(1, 0x000b, 0x03); -+ -+ /* -+ * Early HWM init -+ */ -+ -+ sch5555_mbox_read(1, 0xcb); -+ sch5555_mbox_read(1, 0xb8); -+ -+ static const struct ec_init_entry hwm_init_table[] = { -+ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, -+ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, -+ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, -+ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, -+ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, -+ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, -+ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, -+ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, -+ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, -+ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, -+ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, -+ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, -+ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, -+ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, -+ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, -+ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, -+ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, -+ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, -+ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, {0x0015, 0x33}, -+ {0x018b, 0x00}, {0x018c, 0x00}, {0x02f8, 0x5e}, {0x02f9, 0x01}, -+ }; -+ -+ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) -+ sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); -+} -+ -+ -+#define SCH555x_IOBASE 0x2e -+#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) -+#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) -+ -+void bootblock_mainboard_early_init(void) -+{ -+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -+ -+ // Super I/O early init will map Runtime and EMI registers -+ sch555x_early_init(GLOBAL_DEV); -+ -+ // Changes LED color among a few other things -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); -+ outb(0xf, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); -+ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); -+ -+ // Perform bootblock EC initialization -+ bootblock_ec_init(); -+ -+ // Bootblock EC initialization is required for UART1 to work -+ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -+} -diff --git a/src/mainboard/dell/optiplex_3050/cmos.default b/src/mainboard/dell/optiplex_3050/cmos.default -new file mode 100644 -index 0000000000..79961f43d8 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/cmos.default -@@ -0,0 +1,5 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+boot_option=Fallback -+debug_level=Debug -+power_on_after_fail=Disable -diff --git a/src/mainboard/dell/optiplex_3050/cmos.layout b/src/mainboard/dell/optiplex_3050/cmos.layout -new file mode 100644 -index 0000000000..54a5147b7d ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/cmos.layout -@@ -0,0 +1,54 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+# ----------------------------------------------------------------- -+entries -+ -+#start-bit length config config-ID name -+ -+# ----------------------------------------------------------------- -+0 120 r 0 reserved_memory -+ -+# ----------------------------------------------------------------- -+# RTC_BOOT_BYTE (coreboot hardcoded) -+384 1 e 4 boot_option -+388 4 h 0 reboot_counter -+ -+# ----------------------------------------------------------------- -+# coreboot config options: console -+395 4 e 6 debug_level -+ -+# coreboot config options: southbridge -+409 2 e 7 power_on_after_fail -+ -+# coreboot config options: bootloader -+#Used by ChromeOS: -+416 128 r 0 vbnv -+ -+# coreboot config options: check sums -+984 16 h 0 check_sum -+ -+# ----------------------------------------------------------------- -+ -+enumerations -+ -+#ID value text -+1 0 Disable -+1 1 Enable -+4 0 Fallback -+4 1 Normal -+6 0 Emergency -+6 1 Alert -+6 2 Critical -+6 3 Error -+6 4 Warning -+6 5 Notice -+6 6 Info -+6 7 Debug -+6 8 Spew -+7 0 Disable -+7 1 Enable -+7 2 Keep -+# ----------------------------------------------------------------- -+checksums -+ -+checksum 392 415 984 -diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb -new file mode 100644 -index 0000000000..49b2d7f603 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/devicetree.cb -@@ -0,0 +1,123 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN" -+ -+ # Enable Enhanced Intel SpeedStep -+ register "eist_enable" = "1" -+ -+ device cpu_cluster 0 on end -+ -+ device domain 0 on -+ device ref igpu on -+ register "PrimaryDisplay" = "Display_iGFX" -+ end -+ -+ device ref south_xhci on -+ register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC0), -+ [1] = USB2_PORT_MID(OC0), -+ [2] = USB2_PORT_MID(OC4), -+ [3] = USB2_PORT_MID(OC4), -+ [4] = USB2_PORT_MID(OC2), -+ [5] = USB2_PORT_MID(OC2), -+ [6] = USB2_PORT_MID(OC0), -+ [7] = USB2_PORT_MID(OC0), -+ [8] = USB2_PORT_MID(OC0), -+ [9] = USB2_PORT_MID(OC0), -+ [10] = USB2_PORT_MID(OC1), -+ [11] = USB2_PORT_MID(OC1), -+ [12] = USB2_PORT_MID(OC_SKIP), -+ [13] = USB2_PORT_MID(OC_SKIP), -+ }" -+ register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC0), -+ [1] = USB3_PORT_DEFAULT(OC0), -+ [2] = USB3_PORT_DEFAULT(OC3), -+ [3] = USB3_PORT_DEFAULT(OC3), -+ [4] = USB3_PORT_DEFAULT(OC1), -+ [5] = USB3_PORT_DEFAULT(OC1), -+ [6] = USB3_PORT_DEFAULT(OC_SKIP), -+ [7] = USB3_PORT_DEFAULT(OC_SKIP), -+ [8] = USB3_PORT_DEFAULT(OC_SKIP), -+ [9] = USB3_PORT_DEFAULT(OC_SKIP), -+ }" -+ end -+ -+ # ME interface is 'off' to avoid HECI reset delay due to HAP -+ device ref heci1 off end -+ -+ device ref sata on -+ register "SataSalpSupport" = "1" -+ register "SataPortsEnable[0]" = "1" -+ end -+ -+ device ref pcie_rp21 on -+ register "PcieRpEnable[20]" = "1" -+ register "PcieRpClkReqSupport[20]" = "1" -+ register "PcieRpClkReqNumber[20]" = "3" -+ register "PcieRpAdvancedErrorReporting[20]" = "1" -+ register "PcieRpLtrEnable[20]" = "1" -+ register "PcieRpClkSrcNumber[20]" = "3" -+ register "PcieRpHotPlug[20]" = "1" -+ end -+ -+ # Realtek LAN -+ device ref pcie_rp5 on -+ register "PcieRpEnable[4]" = "1" -+ register "PcieRpClkReqSupport[4]" = "0" -+ register "PcieRpHotPlug[4]" = "0" -+ end -+ -+ # M.2 WiFi -+ device ref pcie_rp8 on -+ register "PcieRpEnable[7]" = "1" -+ register "PcieRpClkReqSupport[7]" = "0" -+ register "PcieRpHotPlug[7]" = "1" -+ end -+ -+ # UART0 is exposed on test points on the bottom of the board -+ device ref uart0 on -+ register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci" -+ end -+ -+ device ref lpc_espi on -+ register "serirq_mode" = "SERIRQ_CONTINUOUS" -+ -+ # I/O decode for EMI/Runtime registers -+ register "gen1_dec" = "0x007c0a01" -+ -+ # SCH5553 -+ chip superio/smsc/sch555x -+ device pnp 2e.0 on # EMI -+ io 0x60 = 0xa00 -+ end -+ device pnp 2e.1 off end # 8042 -+ device pnp 2e.7 on # UART1 -+ io 0x60 = 0x3f8 -+ irq 0x0f = 2 -+ irq 0x70 = 4 -+ end -+ device pnp 2e.8 off end # UART2 -+ device pnp 2e.c on # LPC interface -+ io 0x60 = 0x2e -+ end -+ device pnp 2e.a on # Runtime registers -+ io 0x60 = 0xa40 -+ end -+ device pnp 2e.b off end # Floppy Controller -+ device pnp 2e.11 off end # Parallel Port -+ end -+ -+ chip drivers/pc80/tpm -+ device pnp 0c31.0 on end -+ end -+ end -+ -+ device ref hda on -+ register "PchHdaVcType" = "Vc1" -+ end -+ -+ device ref smbus on end -+ end -+end -diff --git a/src/mainboard/dell/optiplex_3050/dsdt.asl b/src/mainboard/dell/optiplex_3050/dsdt.asl -new file mode 100644 -index 0000000000..9762f6ff74 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/dsdt.asl -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpi.h> -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20110725 -+) -+{ -+ #include <acpi/dsdt_top.asl> -+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> -+ #include <cpu/intel/common/acpi/cpu.asl> -+ -+ Scope (\_SB) -+ { -+ Device (PCI0) -+ { -+ #include <soc/intel/skylake/acpi/systemagent.asl> -+ #include <soc/intel/skylake/acpi/pch.asl> -+ } -+ } -+ -+ #include <southbridge/intel/common/acpi/sleepstates.asl> -+} -diff --git a/src/mainboard/dell/optiplex_3050/gma-mainboard.ads b/src/mainboard/dell/optiplex_3050/gma-mainboard.ads -new file mode 100644 -index 0000000000..cb4c22f285 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/gma-mainboard.ads -@@ -0,0 +1,19 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (HDMI1, -- External HDMI -+ DP2, -- External DP (native) -+ HDMI2, -- External DP (DP++) -+ DP3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) -+ HDMI3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/dell/optiplex_3050/include/early_gpio.h b/src/mainboard/dell/optiplex_3050/include/early_gpio.h -new file mode 100644 -index 0000000000..17a16371e3 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/include/early_gpio.h -@@ -0,0 +1,11 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __OPTIPLEX_3050_EARLY_GPIO_H__ -+#define __OPTIPLEX_3050_EARLY_GPIO_H__ -+ -+static const struct pad_config early_gpio_table[] = { -+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ -+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ -+}; -+ -+#endif -diff --git a/src/mainboard/dell/optiplex_3050/include/gpio.h b/src/mainboard/dell/optiplex_3050/include/gpio.h -new file mode 100644 -index 0000000000..83293c32a9 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/include/gpio.h -@@ -0,0 +1,241 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __OPTIPLEX_3050_GPIO_H__ -+#define __OPTIPLEX_3050_GPIO_H__ -+ -+static const struct pad_config gpio_table[] = { -+ -+ /* ------- GPIO Community 0 ------- */ -+ -+ /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, UP_20K, PLTRST, NF1), /* RCIN# */ -+ PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* LAD0 */ -+ PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* LAD1 */ -+ PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* LAD2 */ -+ PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* LAD3 */ -+ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ -+ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# */ -+ PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */ -+ PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */ -+ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* PME# */ -+ PAD_CFG_GPO(GPP_A12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), /* SUSWARN#/SUSPWRDNACK */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_A15, UP_20K, PLTRST, NF1), /* SUS_ACK# */ -+ PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_B ------- */ -+ PAD_CFG_GPO(GPP_B0, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B1, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B2, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_B3, 1, RSMRST), /* GPIO (ME_CNTL, B3 -> LOW => HDA_SDO -> HIGH) */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_B5, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B6, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_B9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ -+ PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), /* PLTRST# */ -+ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ -+ PAD_CFG_GPO(GPP_B15, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* GSPIO_MOSI */ -+ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* GPIO */ -+ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GSPI1_MOSI */ -+ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* PCHHOT# */ -+ -+ /* ------- GPIO Community 1 ------- */ -+ -+ /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_C2, DN_20K, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_C3, NONE, PLTRST, NF1), /* SML0CLK */ -+ PAD_CFG_NF(GPP_C4, NONE, PLTRST, NF1), /* SML0DATA */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ -+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ -+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ -+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ -+ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ -+ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ -+ PAD_CFG_GPO(GPP_C18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_C22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_D ------- */ -+ PAD_CFG_GPO(GPP_D0, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D1, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D2, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D3, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_D7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_D23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_E ------- */ -+ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ -+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ -+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 */ -+ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ -+ PAD_CFG_NF(GPP_E9, UP_20K, PLTRST, NF1), /* USB_OC0# */ -+ PAD_CFG_NF(GPP_E10, UP_20K, PLTRST, NF1), /* USB_OC1# */ -+ PAD_CFG_NF(GPP_E11, UP_20K, PLTRST, NF1), /* USB_OC2# */ -+ PAD_CFG_NF(GPP_E12, UP_20K, PLTRST, NF1), /* USB_OC3# */ -+ -+ /* ------- GPIO Group GPP_F ------- */ -+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ -+ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* SATAXPCIE4 */ -+ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ -+ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ -+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), /* SATA_DEVSLP4 */ -+ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_F9, 0, RSMRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_F13, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), /* USB_OC4# */ -+ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), /* USB_OC5# */ -+ PAD_CFG_NF(GPP_F17, UP_20K, PLTRST, NF1), /* USB_OC6# */ -+ PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_F21, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F22, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_F23, 1, RSMRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_G ------- */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G9, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G12, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, ACPI), /* GPIO */ -+ PAD_CFG_GPO(GPP_G14, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G16, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G17, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_G19, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G20, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_G21, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G22, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_G23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Group GPP_H ------- */ -+ PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H3, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H4, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H5, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H6, 1, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H7, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H8, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H9, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H10, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H11, 0, PLTRST), /* GPIO */ -+ PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), /* GPIO */ -+ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H16, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H17, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H19, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H20, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H21, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H22, 0, PLTRST), /* GPIO */ -+ PAD_CFG_GPO(GPP_H23, 0, PLTRST), /* GPIO */ -+ -+ /* ------- GPIO Community 2 ------- */ -+ -+ /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ -+ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ -+ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */ -+ PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PWRBTN# */ -+ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ -+ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ -+ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ -+ PAD_CFG_GPO(GPD7, 1, RSMRST), /* GPIO */ -+ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ -+ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ -+ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ -+ PAD_CFG_GPO(GPD11, 1, RSMRST), /* GPIO */ -+ -+ /* ------- GPIO Community 3 ------- */ -+ -+ /* ------- GPIO Group GPP_I ------- */ -+ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ -+ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ -+ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ -+ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ -+ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */ -+ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ -+ PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* DDPB_CTRLDATA */ -+ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ -+ PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* DDPC_CTRLDATA */ -+ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ -+ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */ -+}; -+ -+#endif -diff --git a/src/mainboard/dell/optiplex_3050/ramstage.c b/src/mainboard/dell/optiplex_3050/ramstage.c -new file mode 100644 -index 0000000000..0badd89620 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/ramstage.c -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <soc/ramstage.h> -+#include "include/gpio.h" -+ -+void mainboard_silicon_init_params(FSP_SIL_UPD *params) -+{ -+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -+} -+ -+static void init_mainboard(void *chip_info) -+{ -+} -+ -+struct chip_operations mainboard_ops = { -+ .init = init_mainboard, -+}; -diff --git a/src/mainboard/dell/optiplex_3050/romstage.c b/src/mainboard/dell/optiplex_3050/romstage.c -new file mode 100644 -index 0000000000..a4734e5d61 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/romstage.c -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <assert.h> -+#include <soc/romstage.h> -+#include <stdint.h> -+#include <string.h> -+#include <spd_bin.h> -+#include <cbfs.h> -+ -+void mainboard_memory_init_params(FSPM_UPD *mupd) -+{ -+ struct spd_block blk = { .addr_map = { 0x50, 0x52, } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ mem_cfg->DqPinsInterleaved = true; -+ mem_cfg->CaVrefConfig = 2; -+ mem_cfg->MemorySpdDataLen = blk.len; -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; -+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; -+ -+ /* use virtual channel 1 for the dmi interface of the PCH -+ * FIXME: do we need this? */ -+ mupd->FspmTestConfig.DmiVc1 = 1; -+} -diff --git a/src/mainboard/dell/optiplex_3050/sch5555_ec.c b/src/mainboard/dell/optiplex_3050/sch5555_ec.c -new file mode 100644 -index 0000000000..1df5026531 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/sch5555_ec.c -@@ -0,0 +1,54 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <arch/io.h> -+#include <device/pnp_ops.h> -+#include <superio/smsc/sch555x/sch555x.h> -+#include "sch5555_ec.h" -+ -+uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+ -+ // read result -+ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); -+ return inb(SCH555x_EMI_IOBASE + 4); -+} -+ -+void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address and value -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+} -diff --git a/src/mainboard/dell/optiplex_3050/sch5555_ec.h b/src/mainboard/dell/optiplex_3050/sch5555_ec.h -new file mode 100644 -index 0000000000..9d262d5787 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_3050/sch5555_ec.h -@@ -0,0 +1,10 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __SCH5555_EC_H__ -+#define __SCH5555_EC_H__ -+ -+uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2); -+ -+void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val); -+ -+#endif --- -2.39.5 - |