diff options
Diffstat (limited to 'config/coreboot/default')
49 files changed, 164 insertions, 631 deletions
diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index 3a050d3b..25e7bfce 100644 --- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From 4e350ac1b7d5f27ae0887bb016d748b0987ad14d Mon Sep 17 00:00:00 2001 +From 7a5010bedeaf420af47d06fe33b7f78b354567ef Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 01/41] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/45] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch index 228eb57d..14edd10f 100644 --- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 0322228c25be7d95e7dbcc905dec81960905152b Mon Sep 17 00:00:00 2001 +From 6c04d0ed7ffcbb4f15ab5c8b588665068bfd2842 Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 02/41] lenovo/t400: Enable all SATA ports +Subject: [PATCH 02/45] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index ec891ccf..7b402be9 100644 --- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From 4714f4388bf90fc7ff3d25dd62feec07de5f4c7e Mon Sep 17 00:00:00 2001 +From e12e2fecc3ef8cf06f78ae9d6e48a28ad372dac0 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 03/41] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 03/45] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch index e55f8847..af583721 100644 --- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From 0d8c12b68060ebfe4df4cf0d7cb1abd4c2b2243b Mon Sep 17 00:00:00 2001 +From 5f2607b24f00849aef189179ac245da69f9193ae Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 04/41] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 04/45] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default diff --git a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 1a300e11..2b3a5a04 100644 --- a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From a3bc9753261ebd534df6c6752169b3edbb588a97 Mon Sep 17 00:00:00 2001 +From f56c11820745dceffdfb52caaa45f64942200fb7 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 05/41] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 05/45] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). @@ -20,7 +20,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 84 insertions(+), 32 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 75238c73b2..ea8dfc788d 100644 +index 0592785bf6..cab934c3a5 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -2240,6 +2240,7 @@ static void print_usage(const char *name) diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index bcf15cf0..815e917f 100644 --- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From c3f93c58ddeb1e44daf76db9d67e33bcd2c54a62 Mon Sep 17 00:00:00 2001 +From 96f0538d3b8b40fe1505da2955c53860411294ec Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 06/41] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 06/45] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch index b27e013f..25ea4f8d 100644 --- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From 9c0234bac4d37670da6831e3ff9545a0c6119237 Mon Sep 17 00:00:00 2001 +From 05f2193910c2cc8f7dbd0e3b840e9708ec1d08c8 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 07/41] Remove warning for coreboot images built without a +Subject: [PATCH 07/45] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch index e392d1f7..c78c63b9 100644 --- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From 495eab54f7c2224a0ad3da3dc79905182eca6eee Mon Sep 17 00:00:00 2001 +From 8a50c79dc5ee65f1bc7f60a68354a3733354ce51 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 08/41] HACK: Disable coreboot related BL31 features +Subject: [PATCH 08/45] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. @@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation. 1 file changed, 3 deletions(-) diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk -index 279d31fb47..3d436179fe 100644 +index efd628fee7..6c4f3d702e 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk -@@ -162,9 +162,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 +@@ -156,9 +156,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 # Always enable crash reporting, even on a release build BL31_MAKEARGS += CRASH_REPORTING=1 diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch index f71badef..feb95dc9 100644 --- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From bf464f17367c0dfa7f2c667d699800f3c6e60040 Mon Sep 17 00:00:00 2001 +From f8527c5b1ef6537689427b1ca7bc67a96754c295 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 09/41] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 09/45] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. diff --git a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index a03102e0..3cbf5235 100644 --- a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From 5c27543224963e7fa17ad18dea27d186685e9f13 Mon Sep 17 00:00:00 2001 +From 41f33b00302cae8dcbb2c4c9404dc91f3a7f6dc8 Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 10/41] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 10/45] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. diff --git a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index abd27757..a4439a4d 100644 --- a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From 062b28da685d1c9f7cbe8333e98257a83ce4ca82 Mon Sep 17 00:00:00 2001 +From 253e0316eeddeacd78aba7d3a6fa71a75632febc Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 11/41] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 11/45] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless diff --git a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch index efe5f358..38d69d19 100644 --- a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From 5bd5bc755af744b51e0577970dc6f5214bd0cfee Mon Sep 17 00:00:00 2001 +From fcdb498f9fa13cdf25f9630d5fa24ea5f0bcd09a Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 12/41] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 12/45] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off diff --git a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index 84d83c77..2b9ab519 100644 --- a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From 78da1e003a69a4cc6bd5e71e4bc43a4844d05f16 Mon Sep 17 00:00:00 2001 +From ef705b02719d12b2a92b9abc3663db24f22d4486 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 13/41] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 13/45] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I diff --git a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index 1340effa..c4296394 100644 --- a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,7 +1,7 @@ -From 0a982ec4b606b6c236f71478350b69f532f30719 Mon Sep 17 00:00:00 2001 +From a1270456f4908f1a4e86d4f1a0b51d4553127cda Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 14/41] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 14/45] ec/dell/mec5035: Add S3 suspend SMI handler This is necessary for S3 resume to work on SNB and newer Dell Latitude laptops. If a command isn't sent, the EC cuts power to the DIMMs, diff --git a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index 47b32744..a6189c63 100644 --- a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From 9ca5c919339049518e842980041f528d48d79124 Mon Sep 17 00:00:00 2001 +From c276f783816f44b445853d7db2ca4845dad053de Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 15/41] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 15/45] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch index 84f3899e..005a7ab3 100644 --- a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From e74c4ee6a62ef9f91a8efb257658f627498b91fa Mon Sep 17 00:00:00 2001 +From f1d4736f87a35181d1da3e3941a87461b78c0579 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 16/41] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 16/45] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch index 87894700..afd0e05f 100644 --- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -1,7 +1,7 @@ -From da433a5d9a7d1d7856b55761b8392864343de5a8 Mon Sep 17 00:00:00 2001 +From 2fdbd8a9f05a6bdca83fa4691d037690f0727a8a Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 17/41] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards +Subject: [PATCH 17/45] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards We add this patch: diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index 4b67f8c0..0899b7e0 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From b4443cfe4b63a49b8170bdfb6dacbc8d52110eff Mon Sep 17 00:00:00 2001 +From 760ea1634b4b3bcf3dc0aef9b058d383f2c230ab Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 18/41] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 18/45] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch index 061731e3..46565344 100644 --- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -1,7 +1,7 @@ -From d3d97fccab40cfe50eac92796bb7f16bd245b189 Mon Sep 17 00:00:00 2001 +From 87255c381b1aa3806ca076b11e45b09bfbffca86 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 19/41] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ +Subject: [PATCH 19/45] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ set it to 96MHz. fixes the following build error when building for x4x boards e.g. gigabyte ga-g41m-es2l: diff --git a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch index b5247da2..45429f2d 100644 --- a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -1,7 +1,7 @@ -From c2a05f102ca378d8e23f0485d680845584efa290 Mon Sep 17 00:00:00 2001 +From 15998b0267bb698dc3737b1319f5358bac8a8c7b Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 20/41] mb/dell/gm45_latitudes: Add E4300 variant +Subject: [PATCH 20/45] mb/dell/gm45_latitudes: Add E4300 variant Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch index 4db5b691..97b7b29f 100644 --- a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -1,7 +1,7 @@ -From 2305cfb93110003613caa1dec8c5f574b5e400bd Mon Sep 17 00:00:00 2001 +From 2afe5d44af5a70409cca8c5868c5c022c0cec404 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 21/41] mb/dell: Add S3 SMI handler for Dell Latitudes +Subject: [PATCH 21/45] mb/dell: Add S3 SMI handler for Dell Latitudes Integrate the previously added mec5035_smi_sleep() function into mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. diff --git a/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch index 766b51a3..5d4d3ce8 100644 --- a/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch +++ b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch @@ -1,7 +1,7 @@ -From aafddebf91f185d9c72fa1492af9128ee4803239 Mon Sep 17 00:00:00 2001 +From 1a03117366dd2348143a89f204c9f4e0e84e35f4 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 22/41] Disable compression on refcode insertion +Subject: [PATCH 22/45] Disable compression on refcode insertion Compression is not reliably reproducible. In an lbmk release context, this means we cannot rely on vendorfile insertion. @@ -14,10 +14,10 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.mk b/Makefile.mk -index 75787b32d4..3616f4fe68 100644 +index 5fccb4a52d..c40e06c453 100644 --- a/Makefile.mk +++ b/Makefile.mk -@@ -1422,7 +1422,7 @@ endif +@@ -1414,7 +1414,7 @@ endif cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) $(CONFIG_CBFS_PREFIX)/refcode-type := stage diff --git a/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch index 8746df0d..15c61787 100644 --- a/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch +++ b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch @@ -1,7 +1,7 @@ -From 09febfb85eb176c8bf0e416412ed0b971dc2cefc Mon Sep 17 00:00:00 2001 +From 179f677ab55f05b8cfcaf5539d1bdec93ba710a0 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 23/41] nb/intel/*: Disable stack overflow debug options +Subject: [PATCH 23/45] nb/intel/*: Disable stack overflow debug options Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch index 4fa676fc..29f8ebc1 100644 --- a/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -1,7 +1,7 @@ -From 70f588b7cc66af2e427d9045d36ac2f5f4835dae Mon Sep 17 00:00:00 2001 +From 416a573898cae4b5222eb58dd3dbc0b3d106e8bb Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 24/41] mb/dell: Add Optiplex 780 MT (x4x/ICH10) +Subject: [PATCH 24/45] mb/dell: Add Optiplex 780 MT (x4x/ICH10) Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch index f5a9ce7e..a37a2e6e 100644 --- a/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch +++ b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -1,7 +1,7 @@ -From 463148c9773f3dd44f60c2cf2ac17900c3e68619 Mon Sep 17 00:00:00 2001 +From 66608982981cd8774e44f4918dac03a4027e3287 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 25/41] mb/dell/optiplex_780: Add USFF variant +Subject: [PATCH 25/45] mb/dell/optiplex_780: Add USFF variant Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch index 9769c7e9..150fa808 100644 --- a/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch +++ b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -1,7 +1,7 @@ -From bf3c3df864cae045c82d1c032ced834a60239401 Mon Sep 17 00:00:00 2001 +From 353610638fdb6ad8cf7ea5883368aa1375cff5b6 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:53:53 +0000 -Subject: [PATCH 26/41] src/intel/x4x: Disable stack overflow debug +Subject: [PATCH 26/45] src/intel/x4x: Disable stack overflow debug Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch index d91857a9..4a73984d 100644 --- a/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch +++ b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -1,7 +1,7 @@ -From 0ad074869ec2a25508b1d6fc97c6ce61a9982fbd Mon Sep 17 00:00:00 2001 +From 9ae48676a157c37036b78a2b20a1ff743ec3963e Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 22 Apr 2025 10:21:59 +0100 -Subject: [PATCH 27/41] hp/8300cmt: remove xhci_overcurrent_mapping +Subject: [PATCH 27/45] hp/8300cmt: remove xhci_overcurrent_mapping No longer needed, as per the following commit: diff --git a/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch index b634e107..255b11cf 100644 --- a/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch +++ b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch @@ -1,7 +1,7 @@ -From 4739f197ee3d4c95809ba48671bc5c409766b9c7 Mon Sep 17 00:00:00 2001 +From 79b2b300d32a55d641fd542196f2644dc8e7aacf Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 11 Dec 2024 01:06:01 +0000 -Subject: [PATCH 28/41] dell/3050micro: disable nvme hotplug +Subject: [PATCH 28/45] dell/3050micro: disable nvme hotplug in my testing, when running my 3050micro for a few days, the nvme would sometimes randomly rename. diff --git a/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch index f3864a23..9c736a35 100644 --- a/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -1,7 +1,7 @@ -From a6fdf61bb4779775fa330fc3f9b79be651c6854a Mon Sep 17 00:00:00 2001 +From 554e275c59e8a800c097b7edf5bcdcefc70a3b6c Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 29/41] src/intel/skylake: Disable stack overflow debug options +Subject: [PATCH 29/45] src/intel/skylake: Disable stack overflow debug options The option was appearing in T480/3050micro configs of lbmk, after updating on the coreboot/next uprev for 20241206 rev8: diff --git a/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch index b886e90e..2d999eb8 100644 --- a/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch +++ b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From 287a6d09ac6f5cdfc8255c2020e37441ddb870c7 Mon Sep 17 00:00:00 2001 +From 5a3cced53e209d3ca1b48fc34f126cb4d21bc867 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Thu, 26 Dec 2024 19:45:20 +0000 -Subject: [PATCH 30/41] soc/intel/skylake: Don't compress FSP-S +Subject: [PATCH 30/45] soc/intel/skylake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. diff --git a/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch index bf878964..3fa87ec3 100644 --- a/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch +++ b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -1,7 +1,7 @@ -From c0bb0e62f169e07ab11c434fbd79a6a26b4e7690 Mon Sep 17 00:00:00 2001 +From 61d81f24ae70514f71796c6d3fd1d2d08127cce5 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 18 Dec 2024 02:06:18 +0000 -Subject: [PATCH 31/41] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN +Subject: [PATCH 31/45] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN This is used by lbmk to know where a tb.bin file goes, when extracting and padding TBT.bin from Lenovo ThunderBolt diff --git a/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch index ec1bce88..27788caf 100644 --- a/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch +++ b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch @@ -1,7 +1,7 @@ -From c25cf16fb0d278354c7e2c19f534a04e27ac46dd Mon Sep 17 00:00:00 2001 +From 0ed0d9a18742655ca26466cade80e6fb406606fc Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 05:14:45 +0100 -Subject: [PATCH 32/41] Conditional TBFW setting for kabylake thinkpads +Subject: [PATCH 32/45] Conditional TBFW setting for kabylake thinkpads Otherwise, other boards will define it, which might trigger the vendor download script, and diff --git a/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch index fa279613..38bad2b6 100644 --- a/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch +++ b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch @@ -1,7 +1,7 @@ -From 2c3a31547a14eb1b1145a5d153289b2eef6d71d8 Mon Sep 17 00:00:00 2001 +From 54ae502b30884fa64fafd87c04a09f17e0e1345f Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 27 Sep 2025 23:30:46 +0300 -Subject: [PATCH 33/41] soc/intel/alderlake: Disable +Subject: [PATCH 33/45] soc/intel/alderlake: Disable MRC_CACHE_USING_MRC_VERSION There's some issue with building against the FSP headers in src/vendorcode. @@ -14,7 +14,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 97c2ecca70..a2074fe05a 100644 +index 34c9baf544..e0ab6b10fd 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE diff --git a/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch index f02f2f71..68bd5306 100644 --- a/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch +++ b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch @@ -1,7 +1,7 @@ -From 8eeb1de057b19938f1221b85e00699c58de90069 Mon Sep 17 00:00:00 2001 +From c0625b4e2f9df53e774fe8b8200210b29c52b468 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 28 Sep 2025 03:17:50 +0100 -Subject: [PATCH 34/41] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) +Subject: [PATCH 34/45] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) if you pass -k (keep fptr modules), don't use -r, don't use -t, you can essentially just use me_cleaner to diff --git a/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch index e9b35cc7..0e8b22a4 100644 --- a/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch +++ b/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From be79f8b72a098dcd51639210935ba02d2f5ff808 Mon Sep 17 00:00:00 2001 +From 964cd5ff3d0ac07d625b7c40a46a1ee8d51fb7e6 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 4 Oct 2025 21:57:43 +0100 -Subject: [PATCH 35/41] soc/intel/alderlake: Don't compress FSP-S +Subject: [PATCH 35/45] soc/intel/alderlake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. @@ -18,7 +18,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index a2074fe05a..08137d2706 100644 +index e0ab6b10fd..a2e7cff6f6 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE diff --git a/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch index 638620a9..b655080c 100644 --- a/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch +++ b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch @@ -1,7 +1,7 @@ -From 226df168b34467ca8555e953b6d793f273c0b82c Mon Sep 17 00:00:00 2001 +From 18b6f0d1b15e84f9cc3a2eeb86ed6ac7ae4a7886 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 4 Oct 2025 22:20:11 +0100 -Subject: [PATCH 36/41] alderlake: don't require full fsp repo for fd path +Subject: [PATCH 36/45] alderlake: don't require full fsp repo for fd path Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 08137d2706..67e47c2e36 100644 +index a2e7cff6f6..3402c1e3d5 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig -@@ -417,7 +417,14 @@ config FSP_HEADER_PATH +@@ -430,7 +430,14 @@ config FSP_HEADER_PATH config FSP_FD_PATH string diff --git a/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch index 4f296fbd..ea1a73e1 100644 --- a/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch +++ b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch @@ -1,7 +1,7 @@ -From 30366be45e5b7521b93475f68c7143bd683b25f3 Mon Sep 17 00:00:00 2001 +From 9bd0b15f26681f4d74f5ca7c7f6cbeb1465b7416 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Oct 2025 04:47:06 +0100 -Subject: [PATCH 37/41] soc/alderlake: disable stack overflow debug option +Subject: [PATCH 37/45] soc/alderlake: disable stack overflow debug option same as on other boards. based on this commit: @@ -22,7 +22,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 67e47c2e36..e9c56fc6b9 100644 +index 3402c1e3d5..06b9199e84 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -331,6 +331,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ diff --git a/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch index cd6d5f02..0d8b49c0 100644 --- a/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch +++ b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch @@ -1,7 +1,7 @@ -From 90332fe96aca0de4d99d58d1593048c77e1bdecf Mon Sep 17 00:00:00 2001 +From 357872d4b9c5fdc559d10596b0f21d7065c8fdc5 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 11 May 2025 15:41:22 -0600 -Subject: [PATCH 38/41] ec/dell/mec5035: Add command to disable EC-initiated +Subject: [PATCH 38/45] ec/dell/mec5035: Add command to disable EC-initiated thermal shutdown If command 0xBF isn't sent, the EC shuts down the system without warning diff --git a/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch index ccf93fd7..5aa6d6ff 100644 --- a/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch +++ b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch @@ -1,7 +1,7 @@ -From 68048f4afe369ece02143f9a4a7da2104ff2d10b Mon Sep 17 00:00:00 2001 +From 91a9327e0a2aecfd14be7878b327f5360b658efd Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 11 May 2025 16:28:23 -0600 -Subject: [PATCH 39/41] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown +Subject: [PATCH 39/45] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown at 87 degrees If command 0xBF isn't sent, the EC will shut down the system without diff --git a/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch b/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch deleted file mode 100644 index 9fe5d3da..00000000 --- a/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch +++ /dev/null @@ -1,358 +0,0 @@ -From 0792e39c1684216860b228e6c0935066be1a21b6 Mon Sep 17 00:00:00 2001 -From: Jeremy Soller <jeremy@system76.com> -Date: Fri, 31 May 2024 13:58:00 -0600 -Subject: [PATCH 40/41] drivers/intel/dtbt: Add discrete Thunderbolt driver - -Add a new driver which enables basic TBT support for the Alpine Ridge, -Titan Ridge, and Maple Ridge discrete Thunderbolt controllers. - -This driver will initially be used on the Lenovo T480/T480s and -System76 RPL-HX platform boards. It currently only supports a single -dTBT controller. - -Ref: edk2-platforms KabylakeOpenBoardPkg reference implementation -Ref: Titan Ridge BIOS Implementation Guide v1.4 -Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472) - -Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 -Signed-off-by: Jeremy Soller <jeremy@system76.com> -Signed-off-by: Tim Crawford <tcrawford@system76.com> -Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> ---- - src/drivers/intel/dtbt/Kconfig | 6 + - src/drivers/intel/dtbt/Makefile.mk | 3 + - src/drivers/intel/dtbt/chip.h | 8 ++ - src/drivers/intel/dtbt/dtbt.c | 202 +++++++++++++++++++++++++++++ - src/drivers/intel/dtbt/dtbt.h | 73 +++++++++++ - 5 files changed, 292 insertions(+) - create mode 100644 src/drivers/intel/dtbt/Kconfig - create mode 100644 src/drivers/intel/dtbt/Makefile.mk - create mode 100644 src/drivers/intel/dtbt/chip.h - create mode 100644 src/drivers/intel/dtbt/dtbt.c - create mode 100644 src/drivers/intel/dtbt/dtbt.h - -diff --git a/src/drivers/intel/dtbt/Kconfig b/src/drivers/intel/dtbt/Kconfig -new file mode 100644 -index 0000000000..d895dbd288 ---- /dev/null -+++ b/src/drivers/intel/dtbt/Kconfig -@@ -0,0 +1,6 @@ -+config DRIVERS_INTEL_DTBT -+ def_bool n -+ help -+ Support for discrete Thunderbolt controllers. -+ Currently only supports a single dTBT controller from the -+ Alpine Ridge, Titan Ridge, and Maple Ridge families. -diff --git a/src/drivers/intel/dtbt/Makefile.mk b/src/drivers/intel/dtbt/Makefile.mk -new file mode 100644 -index 0000000000..1b5252dda0 ---- /dev/null -+++ b/src/drivers/intel/dtbt/Makefile.mk -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c -diff --git a/src/drivers/intel/dtbt/chip.h b/src/drivers/intel/dtbt/chip.h -new file mode 100644 -index 0000000000..2b1dfa70a5 ---- /dev/null -+++ b/src/drivers/intel/dtbt/chip.h -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_ -+#define _DRIVERS_INTEL_DTBT_CHIP_H_ -+ -+struct drivers_intel_dtbt_config {}; -+ -+#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */ -diff --git a/src/drivers/intel/dtbt/dtbt.c b/src/drivers/intel/dtbt/dtbt.c -new file mode 100644 -index 0000000000..8613eee5e0 ---- /dev/null -+++ b/src/drivers/intel/dtbt/dtbt.c -@@ -0,0 +1,202 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpigen.h> -+#include <console/console.h> -+#include <delay.h> -+#include <device/device.h> -+#include <device/pci.h> -+#include <device/pciexp.h> -+#include <device/pci_ids.h> -+#include <timer.h> -+#include "chip.h" -+#include "dtbt.h" -+ -+ -+/* -+ * We only want to enable the first/primary bridge device, -+ * as sending mailbox commands to secondary ones will fail, -+ * and we only want to create a single ACPI device in the SSDT. -+ */ -+static bool enable_done; -+static bool ssdt_done; -+ -+static void dtbt_cmd(struct device *dev, u32 command, u32 data, u32 timeout) -+{ -+ u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID; -+ u32 status; -+ -+ printk(BIOS_SPEW, "dTBT send command 0x%x\n", command); -+ /* Send command */ -+ pci_write_config32(dev, PCIE2TBT, reg); -+ /* Wait for done bit to be cleared */ -+ if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) -+ printk(BIOS_ERR, "dTBT command 0x%x send timeout, status 0x%x\n", command, status); -+ /* Clear valid bit */ -+ pci_write_config32(dev, PCIE2TBT, 0); -+ /* Wait for done bit to be cleared */ -+ if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) -+ printk(BIOS_ERR, "dTBT command 0x%x clear valid bit timeout, status 0x%x\n", command, status); -+} -+ -+static void dtbt_write_dsd(void) -+{ -+ struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); -+ -+ acpi_device_add_hotplug_support_in_d3(dsd); -+ acpi_device_add_external_facing_port(dsd); -+ acpi_dp_write(dsd); -+} -+ -+static void dtbt_write_opregion(const struct bus *bus) -+{ -+ uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS -+ + (((uintptr_t)(bus->secondary)) << 20); -+ const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000); -+ const struct fieldlist fieldlist[] = { -+ FIELDLIST_OFFSET(TBT2PCIE), -+ FIELDLIST_NAMESTR("TB2P", 32), -+ FIELDLIST_OFFSET(PCIE2TBT), -+ FIELDLIST_NAMESTR("P2TB", 32), -+ }; -+ -+ acpigen_write_opregion(&opregion); -+ acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), -+ FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); -+} -+ -+static void dtbt_fill_ssdt(const struct device *dev) -+{ -+ struct bus *bus; -+ struct device *parent; -+ const char *parent_scope; -+ const char *dev_name = acpi_device_name(dev); -+ -+ if (ssdt_done) -+ return; -+ -+ bus = dev->upstream; -+ if (!bus) { -+ printk(BIOS_ERR, "dTBT bus invalid\n"); -+ return; -+ } -+ -+ parent = bus->dev; -+ if (!parent || !is_pci(parent)) { -+ printk(BIOS_ERR, "dTBT parent invalid\n"); -+ return; -+ } -+ -+ parent_scope = acpi_device_path(parent); -+ if (!parent_scope) { -+ printk(BIOS_ERR, "dTBT parent scope not valid\n"); -+ return; -+ } -+ -+ /* Scope */ -+ acpigen_write_scope(parent_scope); -+ dtbt_write_dsd(); -+ -+ /* Device */ -+ acpigen_write_device(dev_name); -+ acpigen_write_name_integer("_ADR", 0); -+ dtbt_write_opregion(bus); -+ -+ /* PTS Method */ -+ acpigen_write_method_serialized("PTS", 0); -+ -+ acpigen_write_debug_string("dTBT prepare to sleep"); -+ acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB"); -+ acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1); -+ -+ acpigen_write_debug_namestr("TB2P"); -+ acpigen_write_store_int_to_namestr(0, "P2TB"); -+ acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0); -+ acpigen_write_debug_namestr("TB2P"); -+ -+ acpigen_write_method_end(); -+ acpigen_write_device_end(); -+ acpigen_write_scope_end(); -+ -+ // \.TBTS Method -+ acpigen_write_scope("\\"); -+ acpigen_write_method("TBTS", 0); -+ acpigen_emit_namestring(acpi_device_path_join(dev, "PTS")); -+ acpigen_write_method_end(); -+ acpigen_write_scope_end(); -+ -+ printk(BIOS_INFO, "%s.%s %s\n", parent_scope, dev_name, dev_path(dev)); -+ ssdt_done = true; -+} -+ -+static const char *dtbt_acpi_name(const struct device *dev) -+{ -+ return "DTBT"; -+} -+ -+static void dtbt_enable(struct device *dev) -+{ -+ if (!is_dev_enabled(dev) || enable_done) -+ return; -+ -+ printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev)); -+ -+ // XXX: Recommendation is to set SL1 ("User Authorization") -+ printk(BIOS_DEBUG, "dTBT set security level SL0\n"); -+ /* Set security level */ -+ dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, SEC_LEVEL_NONE, MBOX_TIMEOUT_MS); -+ -+ if (acpi_is_wakeup_s3()) { -+ printk(BIOS_DEBUG, "dTBT SX exit\n"); -+ dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, MBOX_TIMEOUT_MS); -+ /* Read TBT2PCIE register, verify not invalid */ -+ if (pci_read_config32(dev, TBT2PCIE) == 0xffffffff) -+ printk(BIOS_ERR, "dTBT S3 resume failure.\n"); -+ } else { -+ printk(BIOS_DEBUG, "dTBT set boot on\n"); -+ dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, MBOX_TIMEOUT_MS); -+ printk(BIOS_DEBUG, "dTBT set USB on\n"); -+ dtbt_cmd(dev, PCIE2TBT_USB_ON, 0, MBOX_TIMEOUT_MS); -+ } -+ enable_done = true; -+} -+ -+static struct pci_operations dtbt_device_ops_pci = { -+ .set_subsystem = 0, -+}; -+ -+static struct device_operations dtbt_device_ops = { -+ .read_resources = pci_bus_read_resources, -+ .set_resources = pci_dev_set_resources, -+ .enable_resources = pci_bus_enable_resources, -+ .acpi_fill_ssdt = dtbt_fill_ssdt, -+ .acpi_name = dtbt_acpi_name, -+ .scan_bus = pciexp_scan_bridge, -+ .reset_bus = pci_bus_reset, -+ .ops_pci = &dtbt_device_ops_pci, -+ .enable = dtbt_enable -+}; -+ -+/* We only want to match the (first) bridge device */ -+static const unsigned short pci_device_ids[] = { -+ AR_2C_BRG, -+ AR_4C_BRG, -+ AR_LP_BRG, -+ AR_4C_C0_BRG, -+ AR_2C_C0_BRG, -+ TR_2C_BRG, -+ TR_4C_BRG, -+ TR_DD_BRG, -+ MR_2C_BRG, -+ MR_4C_BRG, -+ 0 -+}; -+ -+static const struct pci_driver intel_dtbt_driver __pci_driver = { -+ .ops = &dtbt_device_ops, -+ .vendor = PCI_VID_INTEL, -+ .devices = pci_device_ids, -+}; -+ -+struct chip_operations drivers_intel_dtbt_ops = { -+ .name = "Intel Discrete Thunderbolt", -+}; -diff --git a/src/drivers/intel/dtbt/dtbt.h b/src/drivers/intel/dtbt/dtbt.h -new file mode 100644 -index 0000000000..d01d3a35ef ---- /dev/null -+++ b/src/drivers/intel/dtbt/dtbt.h -@@ -0,0 +1,73 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _DRIVERS_INTEL_DTBT_H_ -+#define _DRIVERS_INTEL_DTBT_H_ -+ -+/* Alpine Ridge device IDs */ -+#define AR_2C_NHI 0x1575 -+#define AR_2C_BRG 0x1576 -+#define AR_2C_USB 0x15B5 -+#define AR_4C_NHI 0x1577 -+#define AR_4C_BRG 0x1578 -+#define AR_4C_USB 0x15B6 -+#define AR_LP_NHI 0x15BF -+#define AR_LP_BRG 0x15C0 -+#define AR_LP_USB 0x15C1 -+#define AR_4C_C0_NHI 0x15D2 -+#define AR_4C_C0_BRG 0x15D3 -+#define AR_4C_C0_USB 0x15D4 -+#define AR_2C_C0_NHI 0x15D9 -+#define AR_2C_C0_BRG 0x15DA -+#define AR_2C_C0_USB 0x15DB -+ -+/* Titan Ridge device IDs */ -+#define TR_2C_BRG 0x15E7 -+#define TR_2C_NHI 0x15E8 -+#define TR_2C_USB 0x15E9 -+#define TR_4C_BRG 0x15EA -+#define TR_4C_NHI 0x15EB -+#define TR_4C_USB 0x15EC -+#define TR_DD_BRG 0x15EF -+#define TR_DD_USB 0x15F0 -+ -+/* Maple Ridge device IDs */ -+#define MR_2C_BRG 0x1133 -+#define MR_2C_NHI 0x1134 -+#define MR_2C_USB 0x1135 -+#define MR_4C_BRG 0x1136 -+#define MR_4C_NHI 0x1137 -+#define MR_4C_USB 0x1138 -+ -+/* Security Levels */ -+#define SEC_LEVEL_NONE 0 -+#define SEC_LEVEL_USER 1 -+#define SEC_LEVEL_AUTH 2 -+#define SEC_LEVEL_DP_ONLY 3 -+ -+#define PCIE2TBT 0x54C -+#define PCIE2TBT_VALID BIT(0) -+#define PCIE2TBT_GO2SX 2 -+#define PCIE2TBT_GO2SX_NO_WAKE 3 -+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED 4 -+#define PCIE2TBT_OS_UP 6 -+#define PCIE2TBT_SET_SECURITY_LEVEL 8 -+#define PCIE2TBT_GET_SECURITY_LEVEL 9 -+#define PCIE2TBT_BOOT_ON 24 -+#define PCIE2TBT_USB_ON 25 -+#define PCIE2TBT_GET_ENUMERATION_METHOD 26 -+#define PCIE2TBT_SET_ENUMERATION_METHOD 27 -+#define PCIE2TBT_POWER_CYCLE 28 -+#define PCIE2TBT_SX_START 29 -+#define PCIE2TBT_ACL_BOOT 30 -+#define PCIE2TBT_CONNECT_TOPOLOGY 31 -+ -+#define TBT2PCIE 0x548 -+#define TBT2PCIE_DONE BIT(0) -+ -+// Timeout for mailbox commands unless otherwise specified. -+#define MBOX_TIMEOUT_MS 5000 -+ -+// Timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command. -+#define GO2SX_TIMEOUT_MS 600 -+ -+#endif /* _DRIVERS_INTEL_DTBT_H_ */ --- -2.47.3 - diff --git a/config/coreboot/default/patches/0042-fix-ifdtool-build.patch b/config/coreboot/default/patches/0040-fix-ifdtool-build.patch index 863ba121..17fc0353 100644 --- a/config/coreboot/default/patches/0042-fix-ifdtool-build.patch +++ b/config/coreboot/default/patches/0040-fix-ifdtool-build.patch @@ -1,7 +1,7 @@ -From 6e084398d4e6847b0f64325dadd4cfee0b43d7ea Mon Sep 17 00:00:00 2001 +From ee295fa8156560526ea9821f6140b84f36d5a92c Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 20 Dec 2025 20:12:48 +0100 -Subject: [PATCH 1/1] fix ifdtool build +Subject: [PATCH 40/45] fix ifdtool build not my mistake. someone messed up. @@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index ea8dfc788d..33f00436bc 100644 +index cab934c3a5..d181888e0f 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -2598,7 +2598,7 @@ int main(int argc, char *argv[]) diff --git a/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch b/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch deleted file mode 100644 index 77edba57..00000000 --- a/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 890eafaa914317b2a67a4b0df9c3a5ea04d88f05 Mon Sep 17 00:00:00 2001 -From: Matt DeVillier <matt.devillier@gmail.com> -Date: Fri, 18 Jul 2025 14:24:05 -0500 -Subject: [PATCH 41/41] mb/lenovo/t480(s): Enable TBT support - -Select the discrete TBT controller driver, and configure the necessary -GPIOs for the Alpine Ridge TBT controller to be fully functional. -Update the documentation w/r/t TBT functionality. - -TEST=build/boot Lenovo T480, boot Linux, verify all TBT-related PCI -devices populated, lower USB-C port works for USB data and PCIe. - -Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4 -Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> ---- - Documentation/mainboard/lenovo/skylake.md | 3 +-- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 2 ++ - src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c | 8 ++++---- - .../lenovo/sklkbl_thinkpad/variants/t480s/gpio.c | 8 ++++---- - 4 files changed, 11 insertions(+), 10 deletions(-) - -diff --git a/Documentation/mainboard/lenovo/skylake.md b/Documentation/mainboard/lenovo/skylake.md -index 64e075e2cd..352d91b3ef 100644 ---- a/Documentation/mainboard/lenovo/skylake.md -+++ b/Documentation/mainboard/lenovo/skylake.md -@@ -193,8 +193,6 @@ binaries if only flashing the `bios` region. - - ## Known Issues - --- Alpine Ridge Thunderbolt 3 controller does not work -- - Lower (right) USB-C port only works for charging/DP alt mode, not USB/PCIe data - - Some Fn+F{1-12} keys aren't handled correctly - - Nvidia dGPU is finicky - - Needs option ROM -@@ -206,6 +204,7 @@ binaries if only flashing the `bios` region. - - ## Verified Working - -+- Alpine Ridge Thunderbolt 3 controller - - Integrated graphics init with libgfxinit - - video output: internal (eDP), miniDP - - ACPI support -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index d69d94f638..c60b85af08 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -33,6 +33,7 @@ config BOARD_LENOVO_T480 - bool - select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - select SOC_INTEL_KABYLAKE -+ select DRIVERS_INTEL_DTBT - select MEC1653_HAS_DEBUG_UNLOCK - select VARIANT_HAS_DGPU - -@@ -40,6 +41,7 @@ config BOARD_LENOVO_T480S - bool - select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - select SOC_INTEL_KABYLAKE -+ select DRIVERS_INTEL_DTBT - select VARIANT_HAS_DGPU - - config BOARD_LENOVO_T580 -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -index f337843fd9..ffd2841e49 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */ - PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ - -@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_G1, NONE), - PAD_NC(GPP_G2, NONE), - PAD_NC(GPP_G3, NONE), -- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */ - PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ - }; - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -index 4f1c57390d..c24c1abb07 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */ - PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ - -@@ -187,9 +187,9 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_G1, NONE), - PAD_NC(GPP_G2, NONE), - PAD_NC(GPP_G3, NONE), -- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */ - PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ - }; - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0044-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch b/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch index afa6017b..92476a67 100644 --- a/config/coreboot/default/patches/0044-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch +++ b/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch @@ -1,7 +1,7 @@ -From ca27517cb5752d078a3f8328ff6b220f652b0849 Mon Sep 17 00:00:00 2001 +From d0f6949cd4ef3e1d88d4fb2f9cc8ffacc02c7879 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 20 Dec 2025 22:36:18 +0100 -Subject: [PATCH 1/1] tests/Makefile.mk: use 3rdparty/cmocka by default +Subject: [PATCH 41/45] tests/Makefile.mk: use 3rdparty/cmocka by default (tests) @@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/Makefile.mk b/tests/Makefile.mk -index f3f122dd38..33bb2a2d07 100644 +index 9e3f86a138..a5a518cd35 100644 --- a/tests/Makefile.mk +++ b/tests/Makefile.mk @@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage diff --git a/config/coreboot/default/patches/0046-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch b/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch index a3258943..e39bb30c 100644 --- a/config/coreboot/default/patches/0046-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch +++ b/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch @@ -1,7 +1,7 @@ -From 22076426d1de6d2e49b8728b3cf206bfcfc6742d Mon Sep 17 00:00:00 2001 +From 75715c75777fbf24c08f2c95b9fcda767f6782dd Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 23 Dec 2025 18:41:27 +0100 -Subject: [PATCH 1/2] mb/dell/optiplex_780: use legacy HDA verb table +Subject: [PATCH 42/45] mb/dell/optiplex_780: use legacy HDA verb table See: diff --git a/config/coreboot/default/patches/0047-hp8300cmt-use-legacy-verb-table.patch b/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch index c7161fc6..3b1a88a4 100644 --- a/config/coreboot/default/patches/0047-hp8300cmt-use-legacy-verb-table.patch +++ b/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch @@ -1,7 +1,7 @@ -From 6cea443cf12eb94b3eafcbba4ce6370b31f716cc Mon Sep 17 00:00:00 2001 +From b6d7b6b5e9b032a81304f5889c7cc3c506a7b0d1 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 23 Dec 2025 18:46:45 +0100 -Subject: [PATCH 2/2] hp8300cmt: use legacy verb table +Subject: [PATCH 43/45] hp8300cmt: use legacy verb table same as for the 780 optiplex patch diff --git a/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch b/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch new file mode 100644 index 00000000..9ef39e5c --- /dev/null +++ b/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch @@ -0,0 +1,34 @@ +From 0f761363172f0d561cf7ef7aa5fb8d1ed4ae50a2 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Tue, 6 Jan 2026 21:42:21 +0000 +Subject: [PATCH 44/45] topton x2e n150: use old fsp + +i added the old fsp back, so that we didn't have to +mess around with vendor files in lbmk, because coreboot +upstream updated the fsp repo, which modified this +fsp file. + +we know the old fsp worked. there's no point testing +the new one yet, unless someone can tell me about +real bugs that got fixed. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/soc/intel/alderlake/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 06b9199e84..f260d10285 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -451,6 +451,7 @@ config FSP_FD_PATH + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S ++ default "3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if BOARD_TOPTON_X2E_N150 + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N + default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0045-mb-lenovo-t580-Enable-TBT-support.patch b/config/coreboot/default/patches/0045-mb-lenovo-t580-Enable-TBT-support.patch deleted file mode 100644 index eafa934f..00000000 --- a/config/coreboot/default/patches/0045-mb-lenovo-t580-Enable-TBT-support.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 2a9e31b0f0bc22d41dfbc5813aa73176619bff9c Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Mon, 22 Dec 2025 11:08:46 +0000 -Subject: [PATCH 1/1] mb/lenovo/t580: Enable TBT support - -This is based on the same change made to the ThinkPad T480 -by Matt DeVillier. - -I simply applied the same changes myself, on the T580. - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 1 + - src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c | 8 ++++---- - 2 files changed, 5 insertions(+), 4 deletions(-) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index c60b85af08..bad6c500d3 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -48,6 +48,7 @@ config BOARD_LENOVO_T580 - bool - select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - select SOC_INTEL_KABYLAKE -+ select DRIVERS_INTEL_DTBT - select MEC1653_HAS_DEBUG_UNLOCK - select VARIANT_HAS_DGPU - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c -index 9c0da3c37e..35ec83152e 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c -@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* TBT_FORCE_PWR */ - PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ - -@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_G1, NONE), - PAD_NC(GPP_G2, NONE), - PAD_NC(GPP_G3, NONE), -- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPO(GPP_G4, 0, PLTRST), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 0, PLTRST), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 0, PLTRST), /* -TBT_PERST */ - PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ - }; - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch b/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch new file mode 100644 index 00000000..c43a2721 --- /dev/null +++ b/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch @@ -0,0 +1,31 @@ +From 015b268510b2d665be21eec1f5e5f9ac41a31eb2 Mon Sep 17 00:00:00 2001 +From: Ron Nazarov <ron@noisytoot.org> +Date: Sat, 14 Feb 2026 20:13:01 +0000 +Subject: [PATCH 45/45] mb/supermicro/x11-lga1151-series: Disable ME HECI in + devicetree + +Since we always use me_cleaner, this speeds up boot time by preventing +coreboot from wasting a few seconds waiting for HECI. + +Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350 +Signed-off-by: Ron Nazarov <ron@noisytoot.org> +--- + src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +index fbf896c6ae..aa09a41f2f 100644 +--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb ++++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +@@ -15,7 +15,7 @@ chip soc/intel/skylake + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end +- device ref heci1 on end ++ device ref heci1 off end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ +-- +2.47.3 + diff --git a/config/coreboot/default/target.cfg b/config/coreboot/default/target.cfg index 3c8ffee2..3cd3e96e 100644 --- a/config/coreboot/default/target.cfg +++ b/config/coreboot/default/target.cfg @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-3.0-or-later tree="default" -rev="def7aa7094122147aed5d36b8f50c56496ee7ab5" +rev="ed5a993f0f98a47d5e780e375e5861860019b183" |