diff options
Diffstat (limited to 'config/coreboot/default')
48 files changed, 187 insertions, 834 deletions
diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index 04e896d9..3a050d3b 100644 --- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From 7436b357fbe12233f3fbc5d360f296e6e15d3c2d Mon Sep 17 00:00:00 2001 +From 4e350ac1b7d5f27ae0887bb016d748b0987ad14d Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 01/40] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/41] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch index 2040cbc2..228eb57d 100644 --- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 7d2e54028f5558f0ccea5ecd8f5f812e28597a47 Mon Sep 17 00:00:00 2001 +From 0322228c25be7d95e7dbcc905dec81960905152b Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 02/40] lenovo/t400: Enable all SATA ports +Subject: [PATCH 02/41] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index 89294d6f..ec891ccf 100644 --- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From 61051fbf9f1da48932930b512527626d1cf5bfbd Mon Sep 17 00:00:00 2001 +From 4714f4388bf90fc7ff3d25dd62feec07de5f4c7e Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 03/40] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 03/41] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch index 7b2ceabd..e55f8847 100644 --- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From be0124d69fef77370eff57cfdfb2d6eae4b0cec3 Mon Sep 17 00:00:00 2001 +From 0d8c12b68060ebfe4df4cf0d7cb1abd4c2b2243b Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 04/40] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 04/41] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default diff --git a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 314c6932..1a300e11 100644 --- a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From d97018fc490daf106582b0b7885a497cc2daba5a Mon Sep 17 00:00:00 2001 +From a3bc9753261ebd534df6c6752169b3edbb588a97 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 05/40] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 05/41] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). @@ -16,22 +16,22 @@ Rebased since the last revision update in lbmk. Signed-off-by: Leah Rowe <leah@libreboot.org> --- - util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++----------- - 1 file changed, 83 insertions(+), 31 deletions(-) + util/ifdtool/ifdtool.c | 116 +++++++++++++++++++++++++++++------------ + 1 file changed, 84 insertions(+), 32 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index b21a89c0e1..fc91d4c239 100644 +index 75238c73b2..ea8dfc788d 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c -@@ -2230,6 +2230,7 @@ static void print_usage(const char *name) +@@ -2240,6 +2240,7 @@ static void print_usage(const char *name) " tgl - Tiger Lake\n" " wbg - Wellsburg\n" " -S | --setpchstrap Write a PCH strap\n" + " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n" " -V | --newvalue The new value to write into PCH strap specified by -S\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" -@@ -2238,6 +2239,60 @@ static void print_usage(const char *name) + " -T | --topswapsize Set the Top Swap Block Size PCH strap value\n" + " Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n" +@@ -2251,6 +2252,60 @@ static void print_usage(const char *name) "\n"); } @@ -92,23 +92,23 @@ index b21a89c0e1..fc91d4c239 100644 int main(int argc, char *argv[]) { int opt, option_index = 0; -@@ -2245,6 +2300,7 @@ int main(int argc, char *argv[]) +@@ -2258,6 +2313,7 @@ int main(int argc, char *argv[]) int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; + int mode_nuke = 0; int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0; + int mode_settopswapsize = 0; char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL; - char *new_filename = NULL; -@@ -2279,6 +2335,7 @@ int main(int argc, char *argv[]) - {"validate", 0, NULL, 't'}, +@@ -2294,6 +2350,7 @@ int main(int argc, char *argv[]) {"setpchstrap", 1, NULL, 'S'}, {"newvalue", 1, NULL, 'V'}, + {"topswapsize", 1, NULL, 'T'}, + {"nuke", 1, NULL, 'N'}, {0, 0, 0, 0} }; -@@ -2328,35 +2385,8 @@ int main(int argc, char *argv[]) +@@ -2343,35 +2400,8 @@ int main(int argc, char *argv[]) region_fname++; // Descriptor, BIOS, ME, GbE, Platform // valid type? @@ -146,10 +146,11 @@ index b21a89c0e1..fc91d4c239 100644 fprintf(stderr, "No such region type: '%s'\n\n", region_type_string); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); -@@ -2533,6 +2563,22 @@ int main(int argc, char *argv[]) - case 't': - mode_validate = 1; +@@ -2552,7 +2582,23 @@ int main(int argc, char *argv[]) + mode_settopswapsize = 1; + top_swap_size_arg = optarg; break; +- case 'v': + case 'N': + region_type_string = strdup(optarg); + if (!region_type_string) { @@ -166,12 +167,13 @@ index b21a89c0e1..fc91d4c239 100644 + } + mode_nuke = 1; + break; - case 'v': ++ Case 'v': print_version(); exit(EXIT_SUCCESS); -@@ -2552,7 +2598,8 @@ int main(int argc, char *argv[]) + break; +@@ -2571,7 +2617,8 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | + mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + - (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) { + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + @@ -179,9 +181,9 @@ index b21a89c0e1..fc91d4c239 100644 fprintf(stderr, "You may not specify more than one mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); -@@ -2561,7 +2608,8 @@ int main(int argc, char *argv[]) +@@ -2580,7 +2627,8 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + + mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 + mode_locked + mode_unlocked + mode_density + mode_altmedisable + - mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) { + mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + @@ -189,7 +191,7 @@ index b21a89c0e1..fc91d4c239 100644 fprintf(stderr, "You need to specify a mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); -@@ -2674,6 +2722,10 @@ int main(int argc, char *argv[]) +@@ -2746,6 +2794,10 @@ int main(int argc, char *argv[]) write_image(new_filename, image, size); } diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index 104df923..bcf15cf0 100644 --- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From 1acdf1d0ff0c7a7ab5f2a0d7e5b57e21bdfaa1ae Mon Sep 17 00:00:00 2001 +From c3f93c58ddeb1e44daf76db9d67e33bcd2c54a62 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 06/40] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 06/41] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch index e8c0f449..b27e013f 100644 --- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From aab9296997bd88a86bbb40079a9caf504db81cea Mon Sep 17 00:00:00 2001 +From 9c0234bac4d37670da6831e3ff9545a0c6119237 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 07/40] Remove warning for coreboot images built without a +Subject: [PATCH 07/41] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch index 66043dc3..e392d1f7 100644 --- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From 319a77d9eeaaf1e344a380b1b449e6a56b3dc92c Mon Sep 17 00:00:00 2001 +From 495eab54f7c2224a0ad3da3dc79905182eca6eee Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 08/40] HACK: Disable coreboot related BL31 features +Subject: [PATCH 08/41] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. @@ -10,7 +10,7 @@ power off properly when shut down from Linux. Needs investigation. 1 file changed, 3 deletions(-) diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk -index f54c6d22fc..b075abfd42 100644 +index 279d31fb47..3d436179fe 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk @@ -162,9 +162,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch index 5ffd4431..f71badef 100644 --- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From d9066d7f51d5742ae8ed1c7ab096ee857358cc48 Mon Sep 17 00:00:00 2001 +From bf464f17367c0dfa7f2c667d699800f3c6e60040 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 09/40] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 09/41] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. diff --git a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index f093db5c..a03102e0 100644 --- a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From 922357b7d5b0b5304b0d4296b2f03961a17288a6 Mon Sep 17 00:00:00 2001 +From 5c27543224963e7fa17ad18dea27d186685e9f13 Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 10/40] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 10/41] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. diff --git a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index 4c773248..abd27757 100644 --- a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From 41256272a7637426c9e68fd633ceb1c108f183c9 Mon Sep 17 00:00:00 2001 +From 062b28da685d1c9f7cbe8333e98257a83ce4ca82 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 11/40] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 11/41] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless diff --git a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch index 24b769cd..efe5f358 100644 --- a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From b243452bf1ed7c9aee1e6685091e98f52d7229c7 Mon Sep 17 00:00:00 2001 +From 5bd5bc755af744b51e0577970dc6f5214bd0cfee Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 12/40] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 12/41] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off diff --git a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index 447693aa..84d83c77 100644 --- a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From 215661dbe631c21a2533cc93bdd1e9f82aa9601e Mon Sep 17 00:00:00 2001 +From 78da1e003a69a4cc6bd5e71e4bc43a4844d05f16 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 13/40] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 13/41] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I diff --git a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index bfbddae1..1340effa 100644 --- a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,7 +1,7 @@ -From aadef041f002b9f0504fcc67df39654680d67bdd Mon Sep 17 00:00:00 2001 +From 0a982ec4b606b6c236f71478350b69f532f30719 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 14/40] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 14/41] ec/dell/mec5035: Add S3 suspend SMI handler This is necessary for S3 resume to work on SNB and newer Dell Latitude laptops. If a command isn't sent, the EC cuts power to the DIMMs, @@ -28,10 +28,10 @@ Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> --- src/ec/dell/mec5035/Makefile.mk | 1 + - src/ec/dell/mec5035/mec5035.c | 14 ++++++++++++++ + src/ec/dell/mec5035/mec5035.c | 13 +++++++++++++ src/ec/dell/mec5035/mec5035.h | 22 ++++++++++++++++++++++ src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++ - 4 files changed, 54 insertions(+) + 4 files changed, 53 insertions(+) create mode 100644 src/ec/dell/mec5035/smihandler.c diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk @@ -46,13 +46,13 @@ index 4ebdd811f9..be557e4599 100644 endif diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index dffbb7960c..85c2ab0140 100644 +index 17ac2c1dab..c5067c16f6 100644 --- a/src/ec/dell/mec5035/mec5035.c +++ b/src/ec/dell/mec5035/mec5035.c -@@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state) - ec_command(CMD_RADIO_CTRL); +@@ -100,6 +100,19 @@ static void mec5035_power_button_route(enum ec_power_button_route target) + write_mailbox_regs(&buf, 2, 1); + ec_command(CMD_POWER_BUTTON_TO_HOST); } - +void mec5035_change_wake(u8 source, enum ec_wake_change change) +{ + u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40}; @@ -66,15 +66,14 @@ index dffbb7960c..85c2ab0140 100644 + write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS); + ec_command(CMD_SLEEP_ENABLE); +} -+ + void mec5035_early_init(void) { - /* If this isn't sent the EC shuts down the system after about 15 diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 32f791cb01..8d4fded28b 100644 +index 5fdf56631b..5cd907bf71 100644 --- a/src/ec/dell/mec5035/mec5035.h +++ b/src/ec/dell/mec5035/mec5035.h -@@ -4,12 +4,15 @@ +@@ -4,6 +4,7 @@ #define _EC_DELL_MEC5035_H_ #include <stdint.h> @@ -82,16 +81,17 @@ index 32f791cb01..8d4fded28b 100644 #define NUM_REGISTERS 32 - enum mec5035_cmd { +@@ -11,6 +12,8 @@ enum mec5035_cmd { CMD_MOUSE_TP = 0x1a, CMD_RADIO_CTRL = 0x2b, + CMD_POWER_BUTTON_TO_HOST = 0x3e, + CMD_ACPI_WAKEUP_CHANGE = 0x4a, + CMD_SLEEP_ENABLE = 0x64, CMD_CPU_OK = 0xc2, }; -@@ -33,9 +36,28 @@ enum ec_radio_state { - RADIO_ON +@@ -39,9 +42,28 @@ enum ec_power_button_route { + HOST }; +#define ACPI_WAKEUP_NUM_ARGS 4 diff --git a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index c1ae05be..47b32744 100644 --- a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From 4a24221fc735117e521cbd7e08d71b6e6a061517 Mon Sep 17 00:00:00 2001 +From 9ca5c919339049518e842980041f528d48d79124 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 15/40] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 15/41] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch index 7537c1a6..84f3899e 100644 --- a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From 20921eb7165b23e7b78e4c4126ff5bab8725404b Mon Sep 17 00:00:00 2001 +From e74c4ee6a62ef9f91a8efb257658f627498b91fa Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 16/40] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 16/41] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values @@ -20,7 +20,7 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> 3 files changed, 106 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h -index 5d9ac56606..338260ea7a 100644 +index f68bfdee7a..b76117bc3a 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); @@ -31,9 +31,9 @@ index 5d9ac56606..338260ea7a 100644 +void raminit_rcomp_calibration(int ddr_type, stepping_t stepping); void raminit_reset_readwrite_pointers(void); void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); - void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume); + void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index b7e013959a..df8f46fbbc 100644 +index def9e1e331..7b091cc567 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping, @@ -70,7 +70,7 @@ index b7e013959a..df8f46fbbc 100644 } mchbar_write32(CxODT_HIGH(ch), reg); -@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) +@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) raminit_write_training(timings->mem_clock, dimms, s3resume); } diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch index 808d90d6..87894700 100644 --- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -1,7 +1,7 @@ -From b5fe5366a03f934df87c5537b12f006ccee0d695 Mon Sep 17 00:00:00 2001 +From da433a5d9a7d1d7856b55761b8392864343de5a8 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 17/40] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards +Subject: [PATCH 17/41] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards We add this patch: @@ -32,7 +32,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 2 files changed, 88 insertions(+), 82 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index df8f46fbbc..433db3a68c 100644 +index 7b091cc567..478898564a 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi @@ -47,7 +47,7 @@ index df8f46fbbc..433db3a68c 100644 } else if (timings->mem_clock != MEM_CLOCK_1067MT) { reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); -@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) +@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume) raminit_write_training(timings->mem_clock, dimms, s3resume); } diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index b537346e..4b67f8c0 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From c075c12d5549cc6cfaa4fbb6bb3abd5e17503b04 Mon Sep 17 00:00:00 2001 +From b4443cfe4b63a49b8170bdfb6dacbc8d52110eff Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 18/40] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 18/41] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For @@ -19,10 +19,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> 2 files changed, 6 insertions(+) diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index 98ad18849c..4b026be2ba 100644 +index edc79b0d43..5020744990 100644 --- a/src/mainboard/dell/gm45_latitude/Kconfig +++ b/src/mainboard/dell/gm45_latitude/Kconfig -@@ -21,6 +21,8 @@ config BOARD_DELL_E6400 +@@ -22,6 +22,8 @@ config BOARD_DELL_E6400 select BOARD_DELL_GM45_LATITUDE_COMMON if BOARD_DELL_GM45_LATITUDE_COMMON @@ -32,7 +32,7 @@ index 98ad18849c..4b026be2ba 100644 config MAINBOARD_DIR default "dell/gm45_latitude" diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index fef0d735b3..fc5df8b11a 100644 +index a776217475..35e89b0c88 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45 diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch index cd1c919f..061731e3 100644 --- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -1,7 +1,7 @@ -From 5833266cabd5dd38596b20d3353eb7b105ffd235 Mon Sep 17 00:00:00 2001 +From d3d97fccab40cfe50eac92796bb7f16bd245b189 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 19/40] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ +Subject: [PATCH 19/41] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ set it to 96MHz. fixes the following build error when building for x4x boards e.g. gigabyte ga-g41m-es2l: @@ -33,7 +33,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 4 insertions(+) diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 097e11126c..6430319f6a 100644 +index 6fa4551957..646af3510b 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X diff --git a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch index 3b2d59ce..b5247da2 100644 --- a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -1,7 +1,7 @@ -From 75620139fe2bd6898d51dd7bd02e1031369feeec Mon Sep 17 00:00:00 2001 +From c2a05f102ca378d8e23f0485d680845584efa290 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 20/40] mb/dell/gm45_latitudes: Add E4300 variant +Subject: [PATCH 20/41] mb/dell/gm45_latitudes: Add E4300 variant Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> @@ -21,10 +21,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index 4b026be2ba..9f0f56e304 100644 +index 5020744990..d27d5728a8 100644 --- a/src/mainboard/dell/gm45_latitude/Kconfig +++ b/src/mainboard/dell/gm45_latitude/Kconfig -@@ -20,6 +20,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON +@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON config BOARD_DELL_E6400 select BOARD_DELL_GM45_LATITUDE_COMMON @@ -34,7 +34,7 @@ index 4b026be2ba..9f0f56e304 100644 if BOARD_DELL_GM45_LATITUDE_COMMON config INTEL_GMA_DPLL_REF_FREQ default 100000000 -@@ -29,12 +32,14 @@ config MAINBOARD_DIR +@@ -30,12 +33,14 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Latitude E6400" if BOARD_DELL_E6400 diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch index dcd75bb6..4db5b691 100644 --- a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -1,7 +1,7 @@ -From 26862554523e08ea1d1cd18cfd09e3434b12e2a3 Mon Sep 17 00:00:00 2001 +From 2305cfb93110003613caa1dec8c5f574b5e400bd Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 21/40] mb/dell: Add S3 SMI handler for Dell Latitudes +Subject: [PATCH 21/41] mb/dell: Add S3 SMI handler for Dell Latitudes Integrate the previously added mec5035_smi_sleep() function into mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. diff --git a/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch index 17e630e3..766b51a3 100644 --- a/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch +++ b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch @@ -1,7 +1,7 @@ -From 89ecd79ab46f56c65c0b5720d1c84b12698a02b4 Mon Sep 17 00:00:00 2001 +From aafddebf91f185d9c72fa1492af9128ee4803239 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 23/40] Disable compression on refcode insertion +Subject: [PATCH 22/41] Disable compression on refcode insertion Compression is not reliably reproducible. In an lbmk release context, this means we cannot rely on vendorfile insertion. @@ -14,10 +14,10 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.mk b/Makefile.mk -index 218e388bb5..a2163c4644 100644 +index 75787b32d4..3616f4fe68 100644 --- a/Makefile.mk +++ b/Makefile.mk -@@ -1392,7 +1392,7 @@ endif +@@ -1422,7 +1422,7 @@ endif cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) $(CONFIG_CBFS_PREFIX)/refcode-type := stage diff --git a/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch deleted file mode 100644 index ab85a389..00000000 --- a/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 849f0aba544d135e2028092862e5f030813c868e Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Tue, 18 Jun 2024 21:31:08 -0600 -Subject: [PATCH 22/40] ec/dell/mec5035: Route power button event to host - -If command 0x3e with an argument of 1 isn't sent to the EC, pressing the -power button results in the EC powering off the system without letting -the OS cleanly shutting itself down. This command and argument tells the -EC to route power button events to the host so that it can determine -what to do. - -The EC command was identified from the ec/google/wilco code, which is -used for Dell's Latitude Chromebooks. According to the EC_GOOGLE_WILCO -Kconfig help text, those ECs run a modified version of Dell's typical -Latitude EC firmware, so it is likely that the two firmware -implementations use similar commands. Examining LPC traffic between the -host and the EC on the Latitude E6400 did reveal that the same command -was being sent by the vendor firmware to the EC, but this does not -confirm that it has the same meaning as the command from the Wilco code. -Sending the command using inb/outb calls in a userspace C program while -running coreboot without this patch did allow subsequent power button -events to be handled by the host, confirming that the command was indeed -the same. - -Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2 -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/ec/dell/mec5035/mec5035.c | 8 ++++++++ - src/ec/dell/mec5035/mec5035.h | 7 +++++++ - 2 files changed, 15 insertions(+) - -diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index 85c2ab0140..bdae929a27 100644 ---- a/src/ec/dell/mec5035/mec5035.c -+++ b/src/ec/dell/mec5035/mec5035.c -@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state) - ec_command(CMD_RADIO_CTRL); - } - -+void mec5035_power_button_route(enum ec_power_button_route target) -+{ -+ u8 buf = (u8)target; -+ write_mailbox_regs(&buf, 2, 1); -+ ec_command(CMD_POWER_BUTTON_TO_HOST); -+} -+ - void mec5035_change_wake(u8 source, enum ec_wake_change change) - { - u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40}; -@@ -121,6 +128,7 @@ static void mec5035_init(struct device *dev) - /* Unconditionally use this argument for now as this setting - is probably the most sensible default out of the 3 choices. */ - mec5035_mouse_touchpad(TP_PS2_MOUSE); -+ mec5035_power_button_route(HOST); - - pc_keyboard_init(NO_AUX_DEVICE); - -diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 8d4fded28b..51422598c4 100644 ---- a/src/ec/dell/mec5035/mec5035.h -+++ b/src/ec/dell/mec5035/mec5035.h -@@ -11,6 +11,7 @@ - enum mec5035_cmd { - CMD_MOUSE_TP = 0x1a, - CMD_RADIO_CTRL = 0x2b, -+ CMD_POWER_BUTTON_TO_HOST = 0x3e, - CMD_ACPI_WAKEUP_CHANGE = 0x4a, - CMD_SLEEP_ENABLE = 0x64, - CMD_CPU_OK = 0xc2, -@@ -36,6 +37,11 @@ enum ec_radio_state { - RADIO_ON - }; - -+enum ec_power_button_route { -+ EC = 0, -+ HOST -+}; -+ - #define ACPI_WAKEUP_NUM_ARGS 4 - enum ec_wake_change { - WAKE_OFF = 0, -@@ -55,6 +61,7 @@ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting); - void mec5035_cpu_ok(void); - void mec5035_early_init(void); - void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state); -+void mec5035_power_button_route(enum ec_power_button_route target); - void mec5035_change_wake(u8 source, enum ec_wake_change change); - void mec5035_sleep_enable(void); - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch index cc9504e9..8746df0d 100644 --- a/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch +++ b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch @@ -1,7 +1,7 @@ -From df60dac9dbaf0c71008dbead7dc1a8c8881c5e33 Mon Sep 17 00:00:00 2001 +From 09febfb85eb176c8bf0e416412ed0b971dc2cefc Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 24/40] nb/intel/*: Disable stack overflow debug options +Subject: [PATCH 23/41] nb/intel/*: Disable stack overflow debug options Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -34,7 +34,7 @@ index 039a7396f8..ddcb986f10 100644 + bool + default n diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index fc5df8b11a..95e3644b73 100644 +index 35e89b0c88..c5456d0ddf 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE @@ -52,7 +52,7 @@ index fc5df8b11a..95e3644b73 100644 + endif diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig -index 6191cb6ccf..0f5b5c7241 100644 +index c57f1ec380..0a5181b183 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL @@ -93,7 +93,7 @@ index dbb2d7436b..5e9418b6a9 100644 + +endif diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig -index 32eff1a611..9479d75c07 100644 +index c4e17f90bf..b12f5be091 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE @@ -111,7 +111,7 @@ index 32eff1a611..9479d75c07 100644 + endif diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig -index 2bafebf92e..16b81705bb 100644 +index 39566a6e5f..f46acf6937 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE @@ -129,7 +129,7 @@ index 2bafebf92e..16b81705bb 100644 + endif diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig -index 59cfcd5e0a..a3ad8d3425 100644 +index a05b866dad..50e3a7cdb9 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE @@ -147,7 +147,7 @@ index 59cfcd5e0a..a3ad8d3425 100644 + endif diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig -index 973eed8bbd..6387cf926d 100644 +index 9972a43da0..fe4ac5106c 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX @@ -165,7 +165,7 @@ index 973eed8bbd..6387cf926d 100644 + endif diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 6430319f6a..1803ef5733 100644 +index 646af3510b..069fa0244d 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE diff --git a/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch index 70bb9ae9..4fa676fc 100644 --- a/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -1,7 +1,7 @@ -From c3af549f5b6431475f3d180eb3b3041d9bfc5d81 Mon Sep 17 00:00:00 2001 +From 70f588b7cc66af2e427d9045d36ac2f5f4835dae Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 25/40] mb/dell: Add Optiplex 780 MT (x4x/ICH10) +Subject: [PATCH 24/41] mb/dell: Add Optiplex 780 MT (x4x/ICH10) Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch index 231e303e..f5a9ce7e 100644 --- a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch +++ b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -1,7 +1,7 @@ -From bb14741af8e4a16d3d098d79fb8df0c3a45e6ccb Mon Sep 17 00:00:00 2001 +From 463148c9773f3dd44f60c2cf2ac17900c3e68619 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 26/40] mb/dell/optiplex_780: Add USFF variant +Subject: [PATCH 25/41] mb/dell/optiplex_780: Add USFF variant Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch index 94186a30..9769c7e9 100644 --- a/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch +++ b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -1,7 +1,7 @@ -From 1685de1beee49456e9f6f578ca6e37219fe7dfff Mon Sep 17 00:00:00 2001 +From bf3c3df864cae045c82d1c032ced834a60239401 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:53:53 +0000 -Subject: [PATCH 27/40] src/intel/x4x: Disable stack overflow debug +Subject: [PATCH 26/41] src/intel/x4x: Disable stack overflow debug Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,7 +9,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 1803ef5733..7129aabf72 100644 +index 069fa0244d..8c70344846 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER diff --git a/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch index c42b3cf0..d91857a9 100644 --- a/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch +++ b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -1,7 +1,7 @@ -From 6f54ed4b0622c7772561760ea4b435bd236ac834 Mon Sep 17 00:00:00 2001 +From 0ad074869ec2a25508b1d6fc97c6ce61a9982fbd Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 22 Apr 2025 10:21:59 +0100 -Subject: [PATCH 28/40] hp/8300cmt: remove xhci_overcurrent_mapping +Subject: [PATCH 27/41] hp/8300cmt: remove xhci_overcurrent_mapping No longer needed, as per the following commit: diff --git a/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch index 4b036e02..b634e107 100644 --- a/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch +++ b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch @@ -1,7 +1,7 @@ -From 17c67799604e0e29192415e97293d71deb457cb2 Mon Sep 17 00:00:00 2001 +From 4739f197ee3d4c95809ba48671bc5c409766b9c7 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 11 Dec 2024 01:06:01 +0000 -Subject: [PATCH 29/40] dell/3050micro: disable nvme hotplug +Subject: [PATCH 28/41] dell/3050micro: disable nvme hotplug in my testing, when running my 3050micro for a few days, the nvme would sometimes randomly rename. @@ -26,24 +26,22 @@ for the nvme, so apply the same fix here for 3050 micro Signed-off-by: Leah Rowe <leah@libreboot.org> --- - src/mainboard/dell/optiplex_3050/devicetree.cb | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb -index 0d2adff74a..829acacab3 100644 ---- a/src/mainboard/dell/optiplex_3050/devicetree.cb -+++ b/src/mainboard/dell/optiplex_3050/devicetree.cb -@@ -44,7 +44,9 @@ chip soc/intel/skylake + .../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb +index c5f1749b2c..ff48a8121a 100644 +--- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb +@@ -46,7 +46,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[20]" = "1" register "PcieRpLtrEnable[20]" = "true" register "PcieRpClkSrcNumber[20]" = "3" - register "PcieRpHotPlug[20]" = "1" -+# disable hotplug on nvme to prevent renaming e.g. nvme0n1 rename to nvme0n2, -+# which could cause crashes in linux if booting from nvme + register "PcieRpHotPlug[20]" = "0" end - # Realtek LAN + end -- 2.47.3 diff --git a/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch index 916e54dc..f3864a23 100644 --- a/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -1,7 +1,7 @@ -From 7194444fbddcf6567d0c82f0986e5deeacaea680 Mon Sep 17 00:00:00 2001 +From a6fdf61bb4779775fa330fc3f9b79be651c6854a Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 31/40] src/intel/skylake: Disable stack overflow debug options +Subject: [PATCH 29/41] src/intel/skylake: Disable stack overflow debug options The option was appearing in T480/3050micro configs of lbmk, after updating on the coreboot/next uprev for 20241206 rev8: @@ -37,10 +37,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 9191ed0ff8..493a2d835a 100644 +index 7c530f2c75..70c2a7643c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig -@@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE +@@ -131,6 +131,15 @@ config DCACHE_RAM_SIZE The size of the cache-as-ram region required during bootblock and/or romstage. diff --git a/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch index cd1ed452..b886e90e 100644 --- a/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch +++ b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From 81360b8c28293856e964934d1f356b1312b39ff2 Mon Sep 17 00:00:00 2001 +From 287a6d09ac6f5cdfc8255c2020e37441ddb870c7 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Thu, 26 Dec 2024 19:45:20 +0000 -Subject: [PATCH 32/40] soc/intel/skylake: Don't compress FSP-S +Subject: [PATCH 30/41] soc/intel/skylake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. @@ -19,11 +19,11 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 493a2d835a..42af82a5d8 100644 +index 70c2a7643c..a2854923e7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig -@@ -12,7 +12,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE - select CPU_SUPPORTS_PM_TIMER_EMULATION +@@ -14,7 +14,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE + select DRAM_SUPPORT_DDR4 select DRIVERS_USB_ACPI select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 - select FSP_COMPRESS_FSP_S_LZ4 diff --git a/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch deleted file mode 100644 index 8a328251..00000000 --- a/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 819fe0e89e426d3d875cf8ab4d2de439ba716848 Mon Sep 17 00:00:00 2001 -From: Felix Singer <felixsinger@posteo.net> -Date: Wed, 26 Jun 2024 04:24:31 +0200 -Subject: [PATCH 30/40] soc/intel/skylake: configure usb acpi - -Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d -Signed-off-by: Felix Singer <felixsinger@posteo.net> ---- - src/soc/intel/skylake/Kconfig | 1 + - src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++- - 2 files changed, 56 insertions(+), 1 deletion(-) - -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 4ad33496b2..9191ed0ff8 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select CPU_SUPPORTS_PM_TIMER_EMULATION -+ select DRIVERS_USB_ACPI - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 - select FSP_COMPRESS_FSP_S_LZ4 - select FSP_M_XIP -diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb -index 6538a1475b..dfb81d496e 100644 ---- a/src/soc/intel/skylake/chipset.cb -+++ b/src/soc/intel/skylake/chipset.cb -@@ -13,7 +13,61 @@ chip soc/intel/skylake - device pci 07.0 alias chap off end - device pci 08.0 alias gmm off end # Gaussian Mixture Model - device pci 13.0 alias ish off end # SensorHub -- device pci 14.0 alias south_xhci off ops usb_xhci_ops end -+ device pci 14.0 alias south_xhci off ops usb_xhci_ops -+ chip drivers/usb/acpi -+ register "type" = "UPC_TYPE_HUB" -+ device usb 0.0 alias xhci_root_hub off -+ chip drivers/usb/acpi -+ device usb 2.0 alias usb2_port1 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.1 alias usb2_port2 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.2 alias usb2_port3 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.3 alias usb2_port4 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.4 alias usb2_port5 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.5 alias usb2_port6 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.6 alias usb2_port7 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.7 alias usb2_port8 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.8 alias usb2_port9 off end -+ end -+ chip drivers/usb/acpi -+ device usb 2.9 alias usb2_port10 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.0 alias usb3_port1 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.1 alias usb3_port2 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.2 alias usb3_port3 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.3 alias usb3_port4 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.4 alias usb3_port5 off end -+ end -+ chip drivers/usb/acpi -+ device usb 3.5 alias usb3_port6 off end -+ end -+ end -+ end -+ end - device pci 14.1 alias south_xdci off ops usb_xdci_ops end - device pci 14.2 alias thermal off end - device pci 14.3 alias cio off end --- -2.47.3 - diff --git a/config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch index 487b32a2..bf878964 100644 --- a/config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch +++ b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -1,7 +1,7 @@ -From 25ff99ff021312387734a10836232a5f3a2d2a12 Mon Sep 17 00:00:00 2001 +From c0bb0e62f169e07ab11c434fbd79a6a26b4e7690 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 18 Dec 2024 02:06:18 +0000 -Subject: [PATCH 33/40] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN +Subject: [PATCH 31/41] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN This is used by lbmk to know where a tb.bin file goes, when extracting and padding TBT.bin from Lenovo ThunderBolt diff --git a/config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch index 1aeae433..ec1bce88 100644 --- a/config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch +++ b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch @@ -1,7 +1,7 @@ -From 57630265c7ba2429a8215757330348733c087db3 Mon Sep 17 00:00:00 2001 +From c25cf16fb0d278354c7e2c19f534a04e27ac46dd Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 05:14:45 +0100 -Subject: [PATCH 34/40] Conditional TBFW setting for T480/T480S +Subject: [PATCH 32/41] Conditional TBFW setting for kabylake thinkpads Otherwise, other boards will define it, which might trigger the vendor download script, and @@ -13,14 +13,14 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 512b326381..3d3490b35d 100644 +index 512b326381..b2c7763198 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -18,6 +18,8 @@ config MAINBOARD_FAMILY string default MAINBOARD_PART_NUMBER -+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S ++if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 + config LENOVO_TBFW_BIN string "Lenovo ThunderBolt firmware bin file" @@ -29,7 +29,7 @@ index 512b326381..3d3490b35d 100644 Just leave this blank if you don't care about this option. It's not useful for every ThinkPad, only certain models. -+endif # BOARD LENOVO_T480 || BOARD_LENOVO_T480S ++endif # BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580 + endif # VENDOR_LENOVO -- diff --git a/config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch index 565be85a..fa279613 100644 --- a/config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch +++ b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch @@ -1,7 +1,7 @@ -From 8e191c71f11de4cb3d08fe585537f15043cacb1b Mon Sep 17 00:00:00 2001 +From 2c3a31547a14eb1b1145a5d153289b2eef6d71d8 Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 27 Sep 2025 23:30:46 +0300 -Subject: [PATCH 36/40] soc/intel/alderlake: Disable +Subject: [PATCH 33/41] soc/intel/alderlake: Disable MRC_CACHE_USING_MRC_VERSION There's some issue with building against the FSP headers in src/vendorcode. @@ -14,10 +14,10 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 51bdf98b9d..739faa3808 100644 +index 97c2ecca70..a2074fe05a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig -@@ -34,7 +34,6 @@ config SOC_INTEL_ALDERLAKE +@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE select INTEL_GMA_VERSION_2 select INTEL_TXT_LIB select MP_SERVICES_PPI_V2 diff --git a/config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch index 8cff0c56..f02f2f71 100644 --- a/config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch +++ b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch @@ -1,7 +1,7 @@ -From 8ab86ffd25fc013790c260e564c8b770c13a5342 Mon Sep 17 00:00:00 2001 +From 8eeb1de057b19938f1221b85e00699c58de90069 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 28 Sep 2025 03:17:50 +0100 -Subject: [PATCH 37/40] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) +Subject: [PATCH 34/41] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) if you pass -k (keep fptr modules), don't use -r, don't use -t, you can essentially just use me_cleaner to diff --git a/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch b/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch deleted file mode 100644 index 1edd0d27..00000000 --- a/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 0a98ff0cbd20484ced53b15f16f8b77d881ffb9e Mon Sep 17 00:00:00 2001 -From: Riku Viitanen <riku.viitanen@protonmail.com> -Date: Thu, 25 Sep 2025 22:45:37 +0300 -Subject: [PATCH 35/40] mb/topton/adl: Add TWL variant (X2E_N150) - -Seems to be the same board but with a Twin Lake processor. -VBT extracted from vendor firmware. This makes HDMI and -DisplayPort work. - -Change-Id: I1018042802cbb8010888847226a2117fd9dfaeb0 -Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> ---- - src/mainboard/topton/adl/Kconfig | 12 +++++++++--- - src/mainboard/topton/adl/Kconfig.name | 3 +++ - src/mainboard/topton/adl/data_twl.vbt | Bin 0 -> 9216 bytes - 3 files changed, 12 insertions(+), 3 deletions(-) - create mode 100644 src/mainboard/topton/adl/data_twl.vbt - -diff --git a/src/mainboard/topton/adl/Kconfig b/src/mainboard/topton/adl/Kconfig -index ffdfae1eee..331e1d624d 100644 ---- a/src/mainboard/topton/adl/Kconfig -+++ b/src/mainboard/topton/adl/Kconfig -@@ -1,6 +1,6 @@ - ## SPDX-License-Identifier: GPL-2.0-or-later - --if BOARD_TOPTON_X2F_N100 -+if BOARD_TOPTON_X2F_N100 || BOARD_TOPTON_X2E_N150 - - config BOARD_SPECIFIC_OPTIONS - def_bool y -@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS - select SUPERIO_ITE_IT8625E - select DRIVERS_UART_8250IO - select SOC_INTEL_ALDERLAKE_PCH_N -+ select SOC_INTEL_TWINLAKE if BOARD_TOPTON_X2E_N150 - select INTEL_GMA_HAVE_VBT - select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select HAVE_INTEL_PTT -@@ -20,7 +21,12 @@ config BOARD_SPECIFIC_OPTIONS - config MAINBOARD_DIR - default "topton/adl" - -+config INTEL_GMA_VBT_FILE -+ default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if BOARD_TOPTON_X2F_N100 -+ default "src/mainboard/\$(MAINBOARDDIR)/data_twl.vbt" if BOARD_TOPTON_X2E_N150 -+ - config MAINBOARD_PART_NUMBER -- default "X2F_N100" -+ default "X2F_N100" if BOARD_TOPTON_X2F_N100 -+ default "X2E_N150" if BOARD_TOPTON_X2E_N150 - --endif # BOARD_TOPTON_X2F_N100 -+endif # BOARD_TOPTON_X2F_N100 || BOARD_TOPTON_X2E_N150 -diff --git a/src/mainboard/topton/adl/Kconfig.name b/src/mainboard/topton/adl/Kconfig.name -index 5b8b5ff602..db0eef29be 100644 ---- a/src/mainboard/topton/adl/Kconfig.name -+++ b/src/mainboard/topton/adl/Kconfig.name -@@ -2,3 +2,6 @@ - - config BOARD_TOPTON_X2F_N100 - bool "X2F_N100" -+ -+config BOARD_TOPTON_X2E_N150 -+ bool "X2E_N150" -diff --git a/src/mainboard/topton/adl/data_twl.vbt b/src/mainboard/topton/adl/data_twl.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..05fbd5807365b3343e55ecedbd12fabb8a3199e9 -GIT binary patch -literal 9216 -zcmeHML2MgE6#cVnZ(QS$EeWj~+AvA0;DjbwJ8eiKOI^oKsN1BmoiuVKP~6mpM!1bh -zQ<Ng4E+U6qkoHnYD<ljO5(<}a;EYcw2q9TTAPykqMyWV})EjNgpV_rtrwuVJg{InX -z{oV2WH*f#{GdnZ8yKlUIj0T261F@mNv4M^VMM;7J%`Is>-Yxy%k<p1zU@S1vKQt0N -zMuF^r-<#KN03-?7<?<?uH+*h3mG;Ei=<xL9R65laN}Ydgb~-~N!7vS+KAlRZW=_qf -zl5}+Z#Q<e|wa)$vQ|Tl<e&Ot7YNn4OiGpbAJ<!>GfKuNJT}pSCPw^f^OP{x=@8F?Y -zXJ{ZeG8_pH1;)Z7$LUCnhQgzP(b0k7{-KjJ5*s-Z?hlU*gle4?Aq1y07iXqkJu^!^ -z!8Yo{>vV8l?lKKd&ty7jAf2W$hB;4Tsq?9sH&V&YS|=mQfx|`sh!g5^fCVPE`#}a9 -zsHlL)`xD_Z5wN|-v938@Q^cwq64R22!kSk4V-#wPQx09BB@^Ooa4i9{41s33Sk2r< -zK0;0ZS^b&{U!7sNmrWe<2^=R^;wVES?xKmSE&7)*aR%uczZ&8$o4D-&c5Imgt&)#j -zgz<fD;_3k;j?*h~oECB4nmE=BB?lQ3$FhWR@J>P8uj_HJ4#(k}A8x&g7&B1>2or#( -ziF#Md@5Pn7>QZ(mOru^zeFybj)b~+8Lj4T&3)C-BzefEI^=H&yQ2#*v6Lnh>DFxmU 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-z4KBA`zl{K!O5Cu3Z?s$S#hJuI(eSwX3BIqkFA@bZh*7W|KFgxyP?>GcPKk`RMw?t= -z(|=;NRT76qw6#{)@^b>Hk|L<cvTXBJ*lrCI7`HExLD12cCbSuE88y7#k9h*Rlm!JS -zayFIx%%M#`DS%dE*p_X3F?QoqB(vGF1hV!#iNF<@7h90ic*bTn7K19SfE%J{OENU7 -z5#L66$)SB;Ez3(5AL-E>aVNGa=cOUUd~sv!9nfp*sPOaZ+xVs0fuGXx2U0!y!oLUb -SeEwbkJq|WZn<bBL2L1wR4t_2G - -literal 0 -HcmV?d00001 - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch index 545f2076..e9b35cc7 100644 --- a/config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch +++ b/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From c36ed52f7573563a9eaeeedd6e6c0ee75973a39d Mon Sep 17 00:00:00 2001 +From be79f8b72a098dcd51639210935ba02d2f5ff808 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 4 Oct 2025 21:57:43 +0100 -Subject: [PATCH 38/40] soc/intel/alderlake: Don't compress FSP-S +Subject: [PATCH 35/41] soc/intel/alderlake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. @@ -18,11 +18,11 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 739faa3808..1f6a1dca7d 100644 +index a2074fe05a..08137d2706 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig -@@ -14,7 +14,7 @@ config SOC_INTEL_ALDERLAKE - select DISPLAY_FSP_VERSION_INFO +@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE + select DRAM_SUPPORT_DDR5 select DRIVERS_USB_ACPI select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 - select FSP_COMPRESS_FSP_S_LZ4 diff --git a/config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch index ed7d98e0..638620a9 100644 --- a/config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch +++ b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch @@ -1,7 +1,7 @@ -From e564490781b0b829da43534c6c2a1b26aeb3282f Mon Sep 17 00:00:00 2001 +From 226df168b34467ca8555e953b6d793f273c0b82c Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 4 Oct 2025 22:20:11 +0100 -Subject: [PATCH 39/40] alderlake: don't require full fsp repo for fd path +Subject: [PATCH 36/41] alderlake: don't require full fsp repo for fd path Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 1f6a1dca7d..3979d9e162 100644 +index 08137d2706..67e47c2e36 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig -@@ -415,7 +415,14 @@ config FSP_HEADER_PATH +@@ -417,7 +417,14 @@ config FSP_HEADER_PATH config FSP_FD_PATH string diff --git a/config/coreboot/default/patches/0041-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch index 979eff9b..4f296fbd 100644 --- a/config/coreboot/default/patches/0041-soc-alderlake-disable-stack-overflow-debug-option.patch +++ b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch @@ -1,7 +1,7 @@ -From 9936228e74ef8bccbf6adb8640040901d395cda0 Mon Sep 17 00:00:00 2001 +From 30366be45e5b7521b93475f68c7143bd683b25f3 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Oct 2025 04:47:06 +0100 -Subject: [PATCH 1/1] soc/alderlake: disable stack overflow debug option +Subject: [PATCH 37/41] soc/alderlake: disable stack overflow debug option same as on other boards. based on this commit: @@ -22,10 +22,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 3979d9e162..a47a27dfaf 100644 +index 67e47c2e36..e9c56fc6b9 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig -@@ -329,6 +329,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ +@@ -331,6 +331,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ int default 19200000 diff --git a/config/coreboot/default/patches/0042-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch index b4ebd870..cd6d5f02 100644 --- a/config/coreboot/default/patches/0042-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch +++ b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch @@ -1,7 +1,7 @@ -From 732819a85ea6cca637350192fbab9d459dc68439 Mon Sep 17 00:00:00 2001 +From 90332fe96aca0de4d99d58d1593048c77e1bdecf Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 11 May 2025 15:41:22 -0600 -Subject: [PATCH 1/2] ec/dell/mec5035: Add command to disable EC-initiated +Subject: [PATCH 38/41] ec/dell/mec5035: Add command to disable EC-initiated thermal shutdown If command 0xBF isn't sent, the EC shuts down the system without warning @@ -39,10 +39,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> 2 files changed, 21 insertions(+) diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index bdae929a27..b3574611a7 100644 +index c5067c16f6..b316fa4989 100644 --- a/src/ec/dell/mec5035/mec5035.c +++ b/src/ec/dell/mec5035/mec5035.c -@@ -115,6 +115,25 @@ void mec5035_sleep_enable(void) +@@ -114,6 +114,25 @@ void mec5035_sleep_enable(void) ec_command(CMD_SLEEP_ENABLE); } @@ -69,7 +69,7 @@ index bdae929a27..b3574611a7 100644 { /* If this isn't sent the EC shuts down the system after about 15 diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 51422598c4..f1d8c43051 100644 +index 5cd907bf71..71d1a71075 100644 --- a/src/ec/dell/mec5035/mec5035.h +++ b/src/ec/dell/mec5035/mec5035.h @@ -14,6 +14,7 @@ enum mec5035_cmd { @@ -80,7 +80,7 @@ index 51422598c4..f1d8c43051 100644 CMD_CPU_OK = 0xc2, }; -@@ -66,5 +67,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change); +@@ -65,5 +66,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change); void mec5035_sleep_enable(void); void mec5035_smi_sleep(int slp_type); diff --git a/config/coreboot/default/patches/0043-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch index 25074d11..ccf93fd7 100644 --- a/config/coreboot/default/patches/0043-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch +++ b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch @@ -1,7 +1,7 @@ -From b93835414970c3b3e5a3f9ccaa82e2ae80756f82 Mon Sep 17 00:00:00 2001 +From 68048f4afe369ece02143f9a4a7da2104ff2d10b Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 11 May 2025 16:28:23 -0600 -Subject: [PATCH 2/2] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown +Subject: [PATCH 39/41] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown at 87 degrees If command 0xBF isn't sent, the EC will shut down the system without diff --git a/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch b/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch deleted file mode 100644 index 4fdf2476..00000000 --- a/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 0fdb23e899e31b17a774ae9151410b11ccf13022 Mon Sep 17 00:00:00 2001 -From: Ron Nazarov <ron@noisytoot.org> -Date: Tue, 30 Sep 2025 22:36:53 +0100 -Subject: [PATCH 40/40] Haswell NRI: Implement SMBIOS type 16/17 - -Based on the implementation from Ivy/Sandy Bridge NRI. - -Tested on a Dell OptiPlex 9020 SFF with libreboot. - -Change-Id: I5e153258f9f88726f54c98baac0b1788a839f934 -Signed-off-by: Ron Nazarov <ron@noisytoot.org> ---- - .../haswell/native_raminit/raminit_main.c | 6 +- - .../haswell/native_raminit/raminit_native.c | 83 +++++++++++++++++-- - .../haswell/native_raminit/raminit_native.h | 2 +- - 3 files changed, 81 insertions(+), 10 deletions(-) - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 84db33ebdf..328f777ee1 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -245,7 +245,7 @@ static enum raminit_status try_raminit( - return status; - } - --void raminit_main(const enum raminit_boot_mode bootmode) -+const struct sysinfo *raminit_main(const enum raminit_boot_mode bootmode) - { - /* - * The mighty_ctrl struct. Will happily nuke the pre-RAM stack -@@ -261,7 +261,7 @@ void raminit_main(const enum raminit_boot_mode bootmode) - if (bootmode != BOOTMODE_COLD) { - status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot)); - if (status == RAMINIT_STATUS_SUCCESS) -- return; -+ return &mighty_ctrl; - } - - /** TODO: Try more than once **/ -@@ -269,4 +269,6 @@ void raminit_main(const enum raminit_boot_mode bootmode) - - if (status != RAMINIT_STATUS_SUCCESS) - die("Memory initialization was met with utmost failure and misery\n"); -+ -+ return &mighty_ctrl; - } -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index 3ad8ce29e7..73532592e8 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -16,6 +16,73 @@ - - #include "raminit_native.h" - -+static uint8_t nb_get_ecc_type(const uint32_t capid0_a) -+{ -+ return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; -+} -+ -+static uint16_t nb_slots_per_channel(const uint32_t capid0_a) -+{ -+ return !(capid0_a & CAPID_DDPCD) + 1; -+} -+ -+static uint16_t nb_number_of_channels(const uint32_t capid0_a) -+{ -+ return !(capid0_a & CAPID_PDCD) + 1; -+} -+ -+static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) -+{ -+ uint32_t ddrsz; -+ -+ /* Values from documentation, which assume two DIMMs per channel */ -+ switch (CAPID_DDRSZ(capid0_a)) { -+ case 1: -+ ddrsz = 8192; -+ break; -+ case 2: -+ ddrsz = 2048; -+ break; -+ case 3: -+ ddrsz = 512; -+ break; -+ default: -+ ddrsz = 16384; -+ break; -+ } -+ -+ /* Account for the maximum number of DIMMs per channel */ -+ return (ddrsz / 2) * nb_slots_per_channel(capid0_a); -+} -+ -+/* Fill cbmem with information for SMBIOS type 16 and type 17 */ -+static void setup_sdram_meminfo(const struct sysinfo *ctrl) -+{ -+ const u16 ddr_freq = (1000 << 8) / ctrl->tCK; -+ -+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { -+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { -+ enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, -+ &ctrl->dimms[channel][slot].data); -+ if (ret != CB_SUCCESS) -+ printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); -+ } -+ } -+ -+ /* The 'spd_add_smbios17' function allocates this CBMEM area */ -+ struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO); -+ if (!m) -+ return; -+ -+ const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); -+ -+ const uint16_t channels = nb_number_of_channels(capid0_a); -+ -+ m->ecc_type = nb_get_ecc_type(capid0_a); -+ m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); -+ m->number_of_devices = channels * nb_slots_per_channel(capid0_a); -+} -+ - static void wait_txt_clear(void) - { - const struct cpuid_result cpuid = cpuid_ext(1, 0); -@@ -90,7 +157,8 @@ static void raminit_reset(void) - static enum raminit_boot_mode do_actual_raminit( - const bool s3resume, - const bool cpu_replaced, -- const enum raminit_boot_mode orig_bootmode) -+ const enum raminit_boot_mode orig_bootmode, -+ const struct sysinfo **ctrl) - { - struct mrc_data md = prepare_mrc_cache(); - -@@ -158,7 +226,7 @@ static enum raminit_boot_mode do_actual_raminit( - * And now, the actual memory initialization thing. - */ - printk(RAM_DEBUG, "\nStarting native raminit\n"); -- raminit_main(bootmode); -+ *ctrl = raminit_main(bootmode); - - return bootmode; - } -@@ -176,8 +244,9 @@ void perform_raminit(const int s3resume) - wait_txt_clear(); - wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); - -+ const struct sysinfo *ctrl; - const enum raminit_boot_mode bootmode = -- do_actual_raminit(s3resume, cpu_replaced, orig_bootmode); -+ do_actual_raminit(s3resume, cpu_replaced, orig_bootmode, &ctrl); - - /** TODO: report_memory_config **/ - -@@ -204,9 +273,9 @@ void perform_raminit(const int s3resume) - system_reset(); - } - -- /* Save training data on non-S3 resumes */ -- if (!s3resume) -+ /* Save training data and set up SMBIOS type 16/17 on non-S3 resumes */ -+ if (!s3resume) { - save_mrc_data(); -- -- /** TODO: setup_sdram_meminfo **/ -+ setup_sdram_meminfo(ctrl); -+ } - } -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index b9e84a11df..1401feedc5 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -476,7 +476,7 @@ static inline void mchbar_write64(const uintptr_t x, const uint64_t v) - "m"(mmxsave)); - } - --void raminit_main(enum raminit_boot_mode bootmode); -+const struct sysinfo *raminit_main(enum raminit_boot_mode bootmode); - - enum raminit_status collect_spd_info(struct sysinfo *ctrl); - enum raminit_status initialise_mpll(struct sysinfo *ctrl); --- -2.47.3 - diff --git a/config/coreboot/default/patches/0046-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch b/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch index c7042f94..9fe5d3da 100644 --- a/config/coreboot/default/patches/0046-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch +++ b/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch @@ -1,7 +1,7 @@ -From a656a385e2c5b3945ff29a45b4129a2516f4b168 Mon Sep 17 00:00:00 2001 +From 0792e39c1684216860b228e6c0935066be1a21b6 Mon Sep 17 00:00:00 2001 From: Jeremy Soller <jeremy@system76.com> Date: Fri, 31 May 2024 13:58:00 -0600 -Subject: [PATCH 1/2] drivers/intel/dtbt: Add discrete Thunderbolt driver +Subject: [PATCH 40/41] drivers/intel/dtbt: Add discrete Thunderbolt driver Add a new driver which enables basic TBT support for the Alpine Ridge, Titan Ridge, and Maple Ridge discrete Thunderbolt controllers. diff --git a/config/coreboot/default/patches/0047-mb-lenovo-t480-s-Enable-TBT-support.patch b/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch index 02d73f79..77edba57 100644 --- a/config/coreboot/default/patches/0047-mb-lenovo-t480-s-Enable-TBT-support.patch +++ b/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch @@ -1,7 +1,7 @@ -From 5249bfd28ffcdab2d54c3c111ec6d3dc567ad090 Mon Sep 17 00:00:00 2001 +From 890eafaa914317b2a67a4b0df9c3a5ea04d88f05 Mon Sep 17 00:00:00 2001 From: Matt DeVillier <matt.devillier@gmail.com> Date: Fri, 18 Jul 2025 14:24:05 -0500 -Subject: [PATCH 2/2] mb/lenovo/t480(s): Enable TBT support +Subject: [PATCH 41/41] mb/lenovo/t480(s): Enable TBT support Select the discrete TBT controller driver, and configure the necessary GPIOs for the Alpine Ridge TBT controller to be fully functional. @@ -13,17 +13,17 @@ devices populated, lower USB-C port works for USB data and PCIe. Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> --- - Documentation/mainboard/lenovo/t480.md | 5 ++--- + Documentation/mainboard/lenovo/skylake.md | 3 +-- src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 2 ++ src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c | 8 ++++---- .../lenovo/sklkbl_thinkpad/variants/t480s/gpio.c | 8 ++++---- - 4 files changed, 12 insertions(+), 11 deletions(-) + 4 files changed, 11 insertions(+), 10 deletions(-) -diff --git a/Documentation/mainboard/lenovo/t480.md b/Documentation/mainboard/lenovo/t480.md -index 9ebce8ff7d..4c3408c4aa 100644 ---- a/Documentation/mainboard/lenovo/t480.md -+++ b/Documentation/mainboard/lenovo/t480.md -@@ -162,8 +162,6 @@ binaries if only flashing the `bios` region. +diff --git a/Documentation/mainboard/lenovo/skylake.md b/Documentation/mainboard/lenovo/skylake.md +index 64e075e2cd..352d91b3ef 100644 +--- a/Documentation/mainboard/lenovo/skylake.md ++++ b/Documentation/mainboard/lenovo/skylake.md +@@ -193,8 +193,6 @@ binaries if only flashing the `bios` region. ## Known Issues @@ -32,7 +32,7 @@ index 9ebce8ff7d..4c3408c4aa 100644 - Some Fn+F{1-12} keys aren't handled correctly - Nvidia dGPU is finicky - Needs option ROM -@@ -175,6 +173,7 @@ binaries if only flashing the `bios` region. +@@ -206,6 +204,7 @@ binaries if only flashing the `bios` region. ## Verified Working @@ -40,32 +40,26 @@ index 9ebce8ff7d..4c3408c4aa 100644 - Integrated graphics init with libgfxinit - video output: internal (eDP), miniDP - ACPI support -@@ -196,4 +195,4 @@ binaries if only flashing the `bios` region. - [from Lenovo's site]: https://pcsupport.lenovo.com/gb/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480s-type-20l7-20l8/solutions/ht508988-critical-intel-thunderbolt-software-and-firmware-updates-thinkpad - [how to externally flash the TB3 firmware]: https://libreboot.org/docs/install/t480.html#thunderbolt-issue-read-this-before-flashing - [Dell firmware updater]: https://web.archive.org/web/20241110222323/https://dl.dell.com/FOLDER04573471M/1/Inspiron_5468_1.3.0.exe --[Dell_PFS_Extract.py]: https://github.com/vuquangtrong/Dell-PFS-BIOS-Assembler/blob/master/Dell_PFS_Extract.py -\ No newline at end of file -+[Dell_PFS_Extract.py]: https://github.com/vuquangtrong/Dell-PFS-BIOS-Assembler/blob/master/Dell_PFS_Extract.py diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index 6036ceb06d..e6fb950d66 100644 +index d69d94f638..c60b85af08 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -26,12 +26,14 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - config BOARD_LENOVO_T480 +@@ -33,6 +33,7 @@ config BOARD_LENOVO_T480 bool select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + select SOC_INTEL_KABYLAKE + select DRIVERS_INTEL_DTBT select MEC1653_HAS_DEBUG_UNLOCK select VARIANT_HAS_DGPU - config BOARD_LENOVO_T480S +@@ -40,6 +41,7 @@ config BOARD_LENOVO_T480S bool select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + select SOC_INTEL_KABYLAKE + select DRIVERS_INTEL_DTBT select VARIANT_HAS_DGPU - if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + config BOARD_LENOVO_T580 diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c index f337843fd9..ffd2841e49 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c diff --git a/config/coreboot/default/patches/0044-mb-lenovo-t480-Fix-headphone-jack.patch b/config/coreboot/default/patches/0044-mb-lenovo-t480-Fix-headphone-jack.patch deleted file mode 100644 index 92e18e57..00000000 --- a/config/coreboot/default/patches/0044-mb-lenovo-t480-Fix-headphone-jack.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 5d463e5e0c33f1788d329ba07ebc20dad552c49e Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 13 Nov 2025 15:45:46 +0100 -Subject: [PATCH] mb/lenovo/t480: Fix headphone jack - -Add additional register configuration for the Realtek ALC257 audio -codec on the Lenovo ThinkPad T480. This includes: - -- Hidden register SW reset sequence -- ClassD 2W amplifier configuration -- Jack detection (JD1) setup for headphone port -- Silence data mode threshold setting at -84dB - -Shamelessly taken from google/brya/variants/pujjolo/hda_verb.c - -Change-Id: Ib77138d782ceb9feeaef82935bc1c0d5c3066183 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> -Reviewed-on: https://review.coreboot.org/c/coreboot/+/90023 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Paul Menzel <paulepanter@mailbox.org> -Reviewed-by: Elyes Haouas <ehaouas@noos.fr> ---- - .../sklkbl_thinkpad/variants/t480/hda_verb.c | 37 ++++++++++++++++++- - 1 file changed, 36 insertions(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -index 3a951ce0da..fc8cac8680 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -@@ -5,7 +5,7 @@ - const u32 cim_verb_data[] = { - 0x10ec0257, // Vendor/Device ID: Realtek ALC257 - 0x17aa225d, // Subsystem ID -- 11, -+ 18, - AZALIA_SUBVENDOR(0, 0x17aa225d), - - AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( -@@ -51,6 +51,41 @@ const u32 cim_verb_data[] = { - 1, 15 - )), - -+ //==========Widget node 0x20 - 0 :Hidden register SW reset -+ 0x0205001A, -+ 0x0204C003, -+ 0x0205001A, -+ 0x0204C003, -+ 0x05850000, -+ 0x0584F880, -+ 0x05850000, -+ 0x0584F880, -+ //==========Widget node 0x20 - 1 : ClassD 2W -+ 0x02050038, -+ 0x02048981, -+ 0x0205001B, -+ 0x02040A4B, -+ //==========Widget node 0x20 - 2 -+ 0x0205003C, -+ 0x02043154, -+ 0x0205003C, -+ 0x02043114, -+ //==========Widget node 0x20 - 3 : -+ 0x02050046, -+ 0x02040004, -+ 0x05750003, -+ 0x057409A3, -+ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD -+ 0x02050009, -+ 0x02046003, -+ 0x0205000A, -+ 0x02047770, -+ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) -+ 0x02050037, -+ 0x0204FE15, -+ 0x02050030, -+ 0x02049004, -+ - 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI - 0x80860101, // Subsystem ID - 4, --- -2.52.0 - diff --git a/config/coreboot/default/patches/0045-mb-lenovo-t480s-Fix-headphone-jack.patch b/config/coreboot/default/patches/0045-mb-lenovo-t480s-Fix-headphone-jack.patch deleted file mode 100644 index aa75f0ad..00000000 --- a/config/coreboot/default/patches/0045-mb-lenovo-t480s-Fix-headphone-jack.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 8a9e9a2c66e90f916c891a80ffe2db0767bd0ae8 Mon Sep 17 00:00:00 2001 -From: Matt DeVillier <matt.devillier@gmail.com> -Date: Wed, 10 Dec 2025 11:02:30 -0600 -Subject: [PATCH 1/1] mb/lenovo/t480s: Fix headphone jack - -Add additional register configuration for the Realtek ALC257 audio -codec on the Lenovo ThinkPad T480s. This includes: - -- Hidden register SW reset sequence -- ClassD 2W amplifier configuration -- Jack detection (JD1) setup for headphone port -- Silence data mode threshold setting at -84dB - -Copied from the T480, originally sourced from -mb/google/brya/variants/pujjolo/hda_verb.c - -Addresses issue #619 - -Change-Id: I0ddea39b40566d6966e89c77352c0904b3c60da9 -Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> ---- - .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 37 ++++++++++++++++++- - 1 file changed, 36 insertions(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -index b1d96c5a76..9eb9287f9b 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -@@ -5,7 +5,7 @@ - const u32 cim_verb_data[] = { - 0x10ec0257, // Vendor/Device ID: Realtek ALC257 - 0x17aa2258, // Subsystem ID -- 11, -+ 18, - AZALIA_SUBVENDOR(0, 0x17aa2258), - - AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( -@@ -51,6 +51,41 @@ const u32 cim_verb_data[] = { - 1, 15 - )), - -+ //==========Widget node 0x20 - 0 :Hidden register SW reset -+ 0x0205001A, -+ 0x0204C003, -+ 0x0205001A, -+ 0x0204C003, -+ 0x05850000, -+ 0x0584F880, -+ 0x05850000, -+ 0x0584F880, -+ //==========Widget node 0x20 - 1 : ClassD 2W -+ 0x02050038, -+ 0x02048981, -+ 0x0205001B, -+ 0x02040A4B, -+ //==========Widget node 0x20 - 2 -+ 0x0205003C, -+ 0x02043154, -+ 0x0205003C, -+ 0x02043114, -+ //==========Widget node 0x20 - 3 : -+ 0x02050046, -+ 0x02040004, -+ 0x05750003, -+ 0x057409A3, -+ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD -+ 0x02050009, -+ 0x02046003, -+ 0x0205000A, -+ 0x02047770, -+ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) -+ 0x02050037, -+ 0x0204FE15, -+ 0x02050030, -+ 0x02049004, -+ - 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI - 0x80860101, // Subsystem ID - 4, --- -2.47.3 - diff --git a/config/coreboot/default/target.cfg b/config/coreboot/default/target.cfg index 80c86778..3c8ffee2 100644 --- a/config/coreboot/default/target.cfg +++ b/config/coreboot/default/target.cfg @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-3.0-or-later tree="default" -rev="9e41c7cec791d84b079251065add7dba66662913" +rev="def7aa7094122147aed5d36b8f50c56496ee7ab5" |