diff options
Diffstat (limited to 'config/coreboot/default/patches')
46 files changed, 2369 insertions, 346 deletions
diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index c908a185..04e896d9 100644 --- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From 857f80c0f41908c2672bd71e161b421676c1f22b Mon Sep 17 00:00:00 2001 +From 7436b357fbe12233f3fbc5d360f296e6e15d3c2d Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 01/24] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/40] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + @@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644 end end -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch index e48d1d77..2040cbc2 100644 --- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 055da4d70c9857b6e301a1fca61e7bf39b8ed788 Mon Sep 17 00:00:00 2001 +From 7d2e54028f5558f0ccea5ecd8f5f812e28597a47 Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 02/24] lenovo/t400: Enable all SATA ports +Subject: [PATCH 02/40] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its @@ -15,7 +15,7 @@ This patch unmasked all SATA ports found within t400s with factory firmware. 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb -index 259c3e1b21..3d007533a4 100644 +index 9e056772e9..9361f330d2 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -46,8 +46,8 @@ chip northbridge/intel/gm45 @@ -30,5 +30,5 @@ index 259c3e1b21..3d007533a4 100644 register "sata_traffic_monitor" = "0" -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index 3a4916ba..89294d6f 100644 --- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From c0246706b784309729194a8e7dd12e130eb74130 Mon Sep 17 00:00:00 2001 +From 61051fbf9f1da48932930b512527626d1cf5bfbd Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 03/24] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 03/40] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do @@ -33,5 +33,5 @@ index 732e214b32..8454f0eac0 100644 -me_state=Normal +me_state=Disabled -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch index d3eaa5a8..7b2ceabd 100644 --- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From b84b1d40d5fef3278d9ea218e92576c095d8814c Mon Sep 17 00:00:00 2001 +From be0124d69fef77370eff57cfdfb2d6eae4b0cec3 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 04/24] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 04/40] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default @@ -120,5 +120,5 @@ index d61046df6b..8c793fd1c3 100644 -me_state=Enable +me_state=Disabled -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 0938b9f2..314c6932 100644 --- a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From f6593dd2146657ee39e2ac3f4b4bac5e7569df67 Mon Sep 17 00:00:00 2001 +From d97018fc490daf106582b0b7885a497cc2daba5a Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 05/24] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 05/40] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). @@ -201,5 +201,5 @@ index b21a89c0e1..fc91d4c239 100644 struct fpsba *fpsba = find_fpsba(image, size); struct fmsba *fmsba = find_fmsba(image, size); -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index b6f44a1a..104df923 100644 --- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,20 +1,20 @@ -From c730bc21c276376baa36956548af1e8412325a9e Mon Sep 17 00:00:00 2001 +From 1acdf1d0ff0c7a7ab5f2a0d7e5b57e21bdfaa1ae Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 06/24] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 06/40] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> --- - src/mainboard/dell/e6400/devicetree.cb | 2 +- + src/mainboard/dell/gm45_latitude/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb -index bb954cbd7b..e9f3915d17 100644 ---- a/src/mainboard/dell/e6400/devicetree.cb -+++ b/src/mainboard/dell/e6400/devicetree.cb -@@ -19,7 +19,7 @@ chip northbridge/intel/gm45 +diff --git a/src/mainboard/dell/gm45_latitude/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb +index 5919803be2..76dae87153 100644 +--- a/src/mainboard/dell/gm45_latitude/devicetree.cb ++++ b/src/mainboard/dell/gm45_latitude/devicetree.cb +@@ -18,7 +18,7 @@ chip northbridge/intel/gm45 ops gm45_pci_domain_ops device pci 00.0 on end # host bridge @@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644 device pci 02.1 on end # Display device pci 03.0 on end # ME -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch index 793abd91..e8c0f449 100644 --- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From b109338522d997dd1b1f705891f000c2f8bfe457 Mon Sep 17 00:00:00 2001 +From aab9296997bd88a86bbb40079a9caf504db81cea Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 07/24] Remove warning for coreboot images built without a +Subject: [PATCH 07/40] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing @@ -35,5 +35,5 @@ index 5f988dac1b..516133880f 100644 -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch index e4fc4f35..66043dc3 100644 --- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From 243d3b1892d33b4eccc9c48333fbc137c4294a73 Mon Sep 17 00:00:00 2001 +From 319a77d9eeaaf1e344a380b1b449e6a56b3dc92c Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 08/24] HACK: Disable coreboot related BL31 features +Subject: [PATCH 08/40] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. @@ -24,5 +24,5 @@ index f54c6d22fc..b075abfd42 100644 BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)" -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch index afada4b5..5ffd4431 100644 --- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From ef4f92299f18c5f28bfe8392cbc0e27d48c03415 Mon Sep 17 00:00:00 2001 +From d9066d7f51d5742ae8ed1c7ab096ee857358cc48 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 09/24] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 09/40] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. @@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644 -me_state=Normal +me_state=Disabled -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index 96a1881c..f093db5c 100644 --- a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From 0cf8b5be9187a6d54e100483943c72f550bc2690 Mon Sep 17 00:00:00 2001 +From 922357b7d5b0b5304b0d4296b2f03961a17288a6 Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 10/24] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 10/40] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. @@ -868,5 +868,5 @@ index 0000000000..8dbd95ef96 + .enable_dev = mainboard_enable, +}; -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index 564cb74c..4c773248 100644 --- a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From a4ffe8da011550fdeacae85ebf642ff57ffb08cc Mon Sep 17 00:00:00 2001 +From 41256272a7637426c9e68fd633ceb1c108f183c9 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 11/24] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 11/40] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless @@ -288,5 +288,5 @@ index e47deb5da6..1a7e0b1076 100644 if (capid0_a & VTD_DISABLE) return; -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch index 06316010..24b769cd 100644 --- a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From bcb2017f4c583742bc60179e6f7c7381e1fa0a39 Mon Sep 17 00:00:00 2001 +From b243452bf1ed7c9aee1e6685091e98f52d7229c7 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 12/24] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 12/40] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off @@ -25,5 +25,5 @@ index 8000eea8c0..0700f971ee 100644 -iommu=Enable +iommu=Disable -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index 1b4f7327..447693aa 100644 --- a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From 1515f6f416a75ecf6de0615f30fc1c5c6696e4d8 Mon Sep 17 00:00:00 2001 +From 215661dbe631c21a2533cc93bdd1e9f82aa9601e Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 13/24] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 13/40] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I @@ -47,5 +47,5 @@ index f7fad3183d..1b188e92e1 100644 static struct device_operations gma_func0_ops = { -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index fe9c4731..bfbddae1 100644 --- a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,7 +1,7 @@ -From 7eb31625fc82a8f697a2f7972b24a4dd19effe5b Mon Sep 17 00:00:00 2001 +From aadef041f002b9f0504fcc67df39654680d67bdd Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 14/24] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 14/40] ec/dell/mec5035: Add S3 suspend SMI handler This is necessary for S3 resume to work on SNB and newer Dell Latitude laptops. If a command isn't sent, the EC cuts power to the DIMMs, @@ -143,5 +143,5 @@ index 0000000000..958733bf97 + } +} -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index 7bc6b3a1..c1ae05be 100644 --- a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From 961814da316a7bd760cd4aa3acd8e176a9ff2cf1 Mon Sep 17 00:00:00 2001 +From 4a24221fc735117e521cbd7e08d71b6e6a061517 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 15/24] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 15/40] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 @@ -51,5 +51,5 @@ index 1a7e0b1076..e9506ee830 100644 /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ u32 reg32; -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch index d024045f..7537c1a6 100644 --- a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From 24e8c088fbe14b598e588383d331f06f21d87190 Mon Sep 17 00:00:00 2001 +From 20921eb7165b23e7b78e4c4126ff5bab8725404b Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 16/24] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 16/40] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values @@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644 + mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); } -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch index 8b85564d..808d90d6 100644 --- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -1,7 +1,7 @@ -From b0ff2cc0470a44078e87bff6226d34b7ac652508 Mon Sep 17 00:00:00 2001 +From b5fe5366a03f934df87c5537b12f006ccee0d695 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 17/24] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards +Subject: [PATCH 17/40] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards We add this patch: @@ -236,5 +236,5 @@ index b74765fd9c..5d4505e063 100644 + } } -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index 2ef3bd9d..b537346e 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From 8926fcba34f6d6ea59bcddbbebf1830df38106d2 Mon Sep 17 00:00:00 2001 +From c075c12d5549cc6cfaa4fbb6bb3abd5e17503b04 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 18/24] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 18/40] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For @@ -14,24 +14,23 @@ display in the pre-OS graphics environment provided by libgfxinit. Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> --- - src/mainboard/dell/e6400/Kconfig | 3 +++ - src/northbridge/intel/gm45/Kconfig | 4 ++++ - 2 files changed, 7 insertions(+) + src/mainboard/dell/gm45_latitude/Kconfig | 2 ++ + src/northbridge/intel/gm45/Kconfig | 4 ++++ + 2 files changed, 6 insertions(+) -diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig -index 417d95fd5d..6fe1b1c456 100644 ---- a/src/mainboard/dell/e6400/Kconfig -+++ b/src/mainboard/dell/e6400/Kconfig -@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS - select INTEL_GMA_HAVE_VBT - select EC_DELL_MEC5035 +diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig +index 98ad18849c..4b026be2ba 100644 +--- a/src/mainboard/dell/gm45_latitude/Kconfig ++++ b/src/mainboard/dell/gm45_latitude/Kconfig +@@ -21,6 +21,8 @@ config BOARD_DELL_E6400 + select BOARD_DELL_GM45_LATITUDE_COMMON + if BOARD_DELL_GM45_LATITUDE_COMMON +config INTEL_GMA_DPLL_REF_FREQ + default 100000000 -+ - config MAINBOARD_DIR - default "dell/e6400" + config MAINBOARD_DIR + default "dell/gm45_latitude" diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index fef0d735b3..fc5df8b11a 100644 --- a/src/northbridge/intel/gm45/Kconfig @@ -48,5 +47,5 @@ index fef0d735b3..fc5df8b11a 100644 select VBOOT_STARTS_IN_BOOTBLOCK -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch index 63a7487a..cd1c919f 100644 --- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -1,7 +1,7 @@ -From a80e71ba4cd7dc7c131c9649de1424899fddddb1 Mon Sep 17 00:00:00 2001 +From 5833266cabd5dd38596b20d3353eb7b105ffd235 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 19/24] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ +Subject: [PATCH 19/40] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ set it to 96MHz. fixes the following build error when building for x4x boards e.g. gigabyte ga-g41m-es2l: @@ -48,5 +48,5 @@ index 097e11126c..6430319f6a 100644 default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch b/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch deleted file mode 100644 index f187c108..00000000 --- a/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch +++ /dev/null @@ -1,243 +0,0 @@ -From 1d62741f0f069241c2d1497c7faf0b31249e706d Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Thu, 26 Sep 2024 19:48:26 -0600 -Subject: [PATCH 20/24] mb/dell: Convert E6400 into a variant - -All the GM45 Dell Latitudes should be nearly identical, so convert the -E6400 port into a variant so that future ports for the other systems can -share code with each other. - -Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95 -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/mainboard/dell/e6400/Makefile.mk | 10 -------- - .../dell/{e6400 => gm45_latitude}/Kconfig | 22 +++++++++++++----- - .../{e6400 => gm45_latitude}/Kconfig.name | 0 - src/mainboard/dell/gm45_latitude/Makefile.mk | 11 +++++++++ - .../dell/{e6400 => gm45_latitude}/acpi/ec.asl | 0 - .../acpi/ich9_pci_irqs.asl | 0 - .../{e6400 => gm45_latitude}/acpi/superio.asl | 0 - .../dell/{e6400 => gm45_latitude}/blc.c | 0 - .../{e6400 => gm45_latitude}/board_info.txt | 0 - .../dell/{e6400 => gm45_latitude}/bootblock.c | 0 - .../{e6400 => gm45_latitude}/cmos.default | 0 - .../dell/{e6400 => gm45_latitude}/cmos.layout | 0 - .../dell/{e6400 => gm45_latitude}/cstates.c | 0 - .../{e6400 => gm45_latitude}/devicetree.cb | 1 - - .../dell/{e6400 => gm45_latitude}/dsdt.asl | 0 - .../dell/{e6400 => gm45_latitude}/mainboard.c | 0 - .../dell/{e6400 => gm45_latitude}/romstage.c | 0 - .../variants}/e6400/data.vbt | Bin - .../variants}/e6400/gma-mainboard.ads | 0 - .../{ => gm45_latitude/variants}/e6400/gpio.c | 0 - .../variants}/e6400/hda_verb.c | 0 - .../variants/e6400/overridetree.cb | 7 ++++++ - 22 files changed, 34 insertions(+), 17 deletions(-) - delete mode 100644 src/mainboard/dell/e6400/Makefile.mk - rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig (64%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig.name (100%) - create mode 100644 src/mainboard/dell/gm45_latitude/Makefile.mk - rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ec.asl (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ich9_pci_irqs.asl (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/superio.asl (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/blc.c (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/board_info.txt (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/bootblock.c (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.default (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.layout (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/cstates.c (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/devicetree.cb (98%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/dsdt.asl (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/mainboard.c (100%) - rename src/mainboard/dell/{e6400 => gm45_latitude}/romstage.c (100%) - rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/data.vbt (100%) - rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gma-mainboard.ads (100%) - rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gpio.c (100%) - rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/hda_verb.c (100%) - create mode 100644 src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb - -diff --git a/src/mainboard/dell/e6400/Makefile.mk b/src/mainboard/dell/e6400/Makefile.mk -deleted file mode 100644 -index ca3a82db48..0000000000 ---- a/src/mainboard/dell/e6400/Makefile.mk -+++ /dev/null -@@ -1,10 +0,0 @@ --## SPDX-License-Identifier: GPL-2.0-only -- --bootblock-y += bootblock.c -- --romstage-y += gpio.c -- --ramstage-y += cstates.c --ramstage-y += blc.c -- --ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -similarity index 64% -rename from src/mainboard/dell/e6400/Kconfig -rename to src/mainboard/dell/gm45_latitude/Kconfig -index 6fe1b1c456..ba76fb6e8c 100644 ---- a/src/mainboard/dell/e6400/Kconfig -+++ b/src/mainboard/dell/gm45_latitude/Kconfig -@@ -1,9 +1,7 @@ - ## SPDX-License-Identifier: GPL-2.0-only - --if BOARD_DELL_E6400 -- --config BOARD_SPECIFIC_OPTIONS -- def_bool y -+config BOARD_DELL_GM45_LATITUDE_COMMON -+ def_bool n - select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_P - select NORTHBRIDGE_INTEL_GM45 -@@ -19,19 +17,31 @@ config BOARD_SPECIFIC_OPTIONS - select INTEL_GMA_HAVE_VBT - select EC_DELL_MEC5035 - -+ -+config BOARD_DELL_E6400 -+ select BOARD_DELL_GM45_LATITUDE_COMMON -+ -+if BOARD_DELL_GM45_LATITUDE_COMMON -+ - config INTEL_GMA_DPLL_REF_FREQ - default 100000000 - - config MAINBOARD_DIR -- default "dell/e6400" -+ default "dell/gm45_latitude" - - config MAINBOARD_PART_NUMBER - default "Latitude E6400" if BOARD_DELL_E6400 - -+config OVERRIDE_DEVICETREE -+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -+ -+config VARIANT_DIR -+ default "e6400" if BOARD_DELL_E6400 -+ - config USBDEBUG_HCD_INDEX - default 1 - - config CBFS_SIZE - default 0x1A0000 - --endif # BOARD_DELL_E6400 -+endif # BOARD_DELL_GM45_LATITUDE_COMMON -diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name -similarity index 100% -rename from src/mainboard/dell/e6400/Kconfig.name -rename to src/mainboard/dell/gm45_latitude/Kconfig.name -diff --git a/src/mainboard/dell/gm45_latitude/Makefile.mk b/src/mainboard/dell/gm45_latitude/Makefile.mk -new file mode 100644 -index 0000000000..5295d5be22 ---- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/Makefile.mk -@@ -0,0 +1,11 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+bootblock-y += bootblock.c -+ -+romstage-y += variants/$(VARIANT_DIR)/gpio.c -+ -+ramstage-y += cstates.c -+ramstage-y += blc.c -+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -+ -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads -diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/gm45_latitude/acpi/ec.asl -similarity index 100% -rename from src/mainboard/dell/e6400/acpi/ec.asl -rename to src/mainboard/dell/gm45_latitude/acpi/ec.asl -diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl -similarity index 100% -rename from src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl -rename to src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl -diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/gm45_latitude/acpi/superio.asl -similarity index 100% -rename from src/mainboard/dell/e6400/acpi/superio.asl -rename to src/mainboard/dell/gm45_latitude/acpi/superio.asl -diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/gm45_latitude/blc.c -similarity index 100% -rename from src/mainboard/dell/e6400/blc.c -rename to src/mainboard/dell/gm45_latitude/blc.c -diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/gm45_latitude/board_info.txt -similarity index 100% -rename from src/mainboard/dell/e6400/board_info.txt -rename to src/mainboard/dell/gm45_latitude/board_info.txt -diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/gm45_latitude/bootblock.c -similarity index 100% -rename from src/mainboard/dell/e6400/bootblock.c -rename to src/mainboard/dell/gm45_latitude/bootblock.c -diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/gm45_latitude/cmos.default -similarity index 100% -rename from src/mainboard/dell/e6400/cmos.default -rename to src/mainboard/dell/gm45_latitude/cmos.default -diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/gm45_latitude/cmos.layout -similarity index 100% -rename from src/mainboard/dell/e6400/cmos.layout -rename to src/mainboard/dell/gm45_latitude/cmos.layout -diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/gm45_latitude/cstates.c -similarity index 100% -rename from src/mainboard/dell/e6400/cstates.c -rename to src/mainboard/dell/gm45_latitude/cstates.c -diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb -similarity index 98% -rename from src/mainboard/dell/e6400/devicetree.cb -rename to src/mainboard/dell/gm45_latitude/devicetree.cb -index e9f3915d17..76dae87153 100644 ---- a/src/mainboard/dell/e6400/devicetree.cb -+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb -@@ -15,7 +15,6 @@ chip northbridge/intel/gm45 - register "pci_mmio_size" = "2048" - - device domain 0 on -- subsystemid 0x1028 0x0233 inherit - ops gm45_pci_domain_ops - - device pci 00.0 on end # host bridge -diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/gm45_latitude/dsdt.asl -similarity index 100% -rename from src/mainboard/dell/e6400/dsdt.asl -rename to src/mainboard/dell/gm45_latitude/dsdt.asl -diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/gm45_latitude/mainboard.c -similarity index 100% -rename from src/mainboard/dell/e6400/mainboard.c -rename to src/mainboard/dell/gm45_latitude/mainboard.c -diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/gm45_latitude/romstage.c -similarity index 100% -rename from src/mainboard/dell/e6400/romstage.c -rename to src/mainboard/dell/gm45_latitude/romstage.c -diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt -similarity index 100% -rename from src/mainboard/dell/e6400/data.vbt -rename to src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt -diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads -similarity index 100% -rename from src/mainboard/dell/e6400/gma-mainboard.ads -rename to src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads -diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c -similarity index 100% -rename from src/mainboard/dell/e6400/gpio.c -rename to src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c -diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c -similarity index 100% -rename from src/mainboard/dell/e6400/hda_verb.c -rename to src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c -diff --git a/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb -new file mode 100644 -index 0000000000..acc34a2252 ---- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb -@@ -0,0 +1,7 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+chip northbridge/intel/gm45 -+ device domain 0 on -+ subsystemid 0x1028 0x0233 inherit -+ end -+end --- -2.39.5 - diff --git a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch index 17fa6aff..3b2d59ce 100644 --- a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -1,7 +1,7 @@ -From 031aca7160b8258bd16d5c5a3481c6ee900111e1 Mon Sep 17 00:00:00 2001 +From 75620139fe2bd6898d51dd7bd02e1031369feeec Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 21/24] mb/dell/gm45_latitudes: Add E4300 variant +Subject: [PATCH 20/40] mb/dell/gm45_latitudes: Add E4300 variant Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> @@ -21,10 +21,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index ba76fb6e8c..144f9bcdf0 100644 +index 4b026be2ba..9f0f56e304 100644 --- a/src/mainboard/dell/gm45_latitude/Kconfig +++ b/src/mainboard/dell/gm45_latitude/Kconfig -@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON +@@ -20,6 +20,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON config BOARD_DELL_E6400 select BOARD_DELL_GM45_LATITUDE_COMMON @@ -32,9 +32,9 @@ index ba76fb6e8c..144f9bcdf0 100644 + select BOARD_DELL_GM45_LATITUDE_COMMON + if BOARD_DELL_GM45_LATITUDE_COMMON - config INTEL_GMA_DPLL_REF_FREQ -@@ -31,12 +34,14 @@ config MAINBOARD_DIR + default 100000000 +@@ -29,12 +32,14 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Latitude E6400" if BOARD_DELL_E6400 @@ -328,5 +328,5 @@ index 0000000000..20dfa245fb + end +end -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch index ddcaadb3..dcd75bb6 100644 --- a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -1,7 +1,7 @@ -From e6a153dbaf95b034f75dd6717c6d250d1cc21635 Mon Sep 17 00:00:00 2001 +From 26862554523e08ea1d1cd18cfd09e3434b12e2a3 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 22/24] mb/dell: Add S3 SMI handler for Dell Latitudes +Subject: [PATCH 21/40] mb/dell: Add S3 SMI handler for Dell Latitudes Integrate the previously added mec5035_smi_sleep() function into mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. @@ -12,19 +12,19 @@ the power LED while in S3. Without it, all LEDs turn off during S3. Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> --- - src/mainboard/dell/e7240/smihandler.c | 9 +++++++++ src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++ + src/mainboard/dell/haswell_latitude/smihandler.c | 9 +++++++++ src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++ 3 files changed, 27 insertions(+) - create mode 100644 src/mainboard/dell/e7240/smihandler.c create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c + create mode 100644 src/mainboard/dell/haswell_latitude/smihandler.c create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c -diff --git a/src/mainboard/dell/e7240/smihandler.c b/src/mainboard/dell/e7240/smihandler.c +diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c new file mode 100644 index 0000000000..00e55b51db --- /dev/null -+++ b/src/mainboard/dell/e7240/smihandler.c ++++ b/src/mainboard/dell/gm45_latitude/smihandler.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + @@ -35,11 +35,11 @@ index 0000000000..00e55b51db +{ + mec5035_smi_sleep(slp_typ); +} -diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c +diff --git a/src/mainboard/dell/haswell_latitude/smihandler.c b/src/mainboard/dell/haswell_latitude/smihandler.c new file mode 100644 index 0000000000..00e55b51db --- /dev/null -+++ b/src/mainboard/dell/gm45_latitude/smihandler.c ++++ b/src/mainboard/dell/haswell_latitude/smihandler.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + @@ -66,5 +66,5 @@ index 0000000000..00e55b51db + mec5035_smi_sleep(slp_typ); +} -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch index 0351d503..ab85a389 100644 --- a/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch +++ b/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch @@ -1,7 +1,7 @@ -From 41fab69e70eb78b93e1998396bf85a5afbaa61ef Mon Sep 17 00:00:00 2001 +From 849f0aba544d135e2028092862e5f030813c868e Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Tue, 18 Jun 2024 21:31:08 -0600 -Subject: [PATCH 23/24] ec/dell/mec5035: Route power button event to host +Subject: [PATCH 22/40] ec/dell/mec5035: Route power button event to host If command 0x3e with an argument of 1 isn't sent to the EC, pressing the power button results in the EC powering off the system without letting @@ -88,5 +88,5 @@ index 8d4fded28b..51422598c4 100644 void mec5035_sleep_enable(void); -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch index 51928bd6..17e630e3 100644 --- a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch +++ b/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch @@ -1,7 +1,7 @@ -From 1380f0f6f3c73bbd994228acdbcbbc06da7c6cb2 Mon Sep 17 00:00:00 2001 +From 89ecd79ab46f56c65c0b5720d1c84b12698a02b4 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 24/24] Disable compression on refcode insertion +Subject: [PATCH 23/40] Disable compression on refcode insertion Compression is not reliably reproducible. In an lbmk release context, this means we cannot rely on vendorfile insertion. @@ -14,7 +14,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.mk b/Makefile.mk -index 3969bfbd05..15346569f8 100644 +index 218e388bb5..a2163c4644 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -1392,7 +1392,7 @@ endif @@ -27,5 +27,5 @@ index 3969bfbd05..15346569f8 100644 cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch index c9e243f4..cc9504e9 100644 --- a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch +++ b/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch @@ -1,7 +1,7 @@ -From 3400b3e7c31e45506bb060db0164fa9390366d27 Mon Sep 17 00:00:00 2001 +From df60dac9dbaf0c71008dbead7dc1a8c8881c5e33 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 1/1] nb/intel/*: Disable stack overflow debug options +Subject: [PATCH 24/40] nb/intel/*: Disable stack overflow debug options Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -183,5 +183,5 @@ index 6430319f6a..1803ef5733 100644 + endif -- -2.39.5 +2.47.3 diff --git a/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch new file mode 100644 index 00000000..70bb9ae9 --- /dev/null +++ b/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -0,0 +1,708 @@ +From c3af549f5b6431475f3d180eb3b3041d9bfc5d81 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Mon, 30 Sep 2024 20:44:38 -0400 +Subject: [PATCH 25/40] mb/dell: Add Optiplex 780 MT (x4x/ICH10) + +Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/optiplex_780/Kconfig | 40 ++++ + src/mainboard/dell/optiplex_780/Kconfig.name | 4 + + src/mainboard/dell/optiplex_780/Makefile.mk | 10 + + src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 + + .../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++ + .../dell/optiplex_780/acpi/superio.asl | 18 ++ + .../dell/optiplex_780/board_info.txt | 6 + + src/mainboard/dell/optiplex_780/cmos.default | 8 + + src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++ + src/mainboard/dell/optiplex_780/cstates.c | 8 + + src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++ + src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++ + .../dell/optiplex_780/gma-mainboard.ads | 16 ++ + .../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes + .../optiplex_780/variants/780_mt/early_init.c | 12 ++ + .../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++ + .../optiplex_780/variants/780_mt/hda_verb.c | 26 +++ + .../variants/780_mt/overridetree.cb | 10 + + 18 files changed, 530 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/Kconfig + create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name + create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk + create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl + create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl + create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl + create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt + create mode 100644 src/mainboard/dell/optiplex_780/cmos.default + create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout + create mode 100644 src/mainboard/dell/optiplex_780/cstates.c + create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb + create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl + create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +new file mode 100644 +index 0000000000..2d06c75c9a +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -0,0 +1,40 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_780_COMMON ++ def_bool n ++ select BOARD_ROMSIZE_KB_8192 ++ select CPU_INTEL_SOCKET_LGA775 ++ select DRIVERS_I2C_CK505 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select NORTHBRIDGE_INTEL_X4X ++ select PCIEXP_ASPM ++ select PCIEXP_CLK_PM ++ select SOUTHBRIDGE_INTEL_I82801JX ++ ++config BOARD_DELL_OPTIPLEX_780_MT ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ ++if BOARD_DELL_OPTIPLEX_780_COMMON ++ ++config VGA_BIOS_ID ++ default "8086,2e22" ++ ++config MAINBOARD_DIR ++ default "dell/optiplex_780" ++ ++config MAINBOARD_PART_NUMBER ++ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ ++config OVERRIDE_DEVICETREE ++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" ++ ++config VARIANT_DIR ++ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ ++endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +new file mode 100644 +index 0000000000..db7f2e8fe3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_780_MT ++ bool "OptiPlex 780 MT" +diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk +new file mode 100644 +index 0000000000..d462995d75 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/Makefile.mk +@@ -0,0 +1,10 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++ramstage-y += cstates.c ++romstage-y += variants/$(VARIANT_DIR)/gpio.c ++ ++bootblock-y += variants/$(VARIANT_DIR)/early_init.c ++romstage-y += variants/$(VARIANT_DIR)/early_init.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads ++ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl +new file mode 100644 +index 0000000000..479296cb76 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl +@@ -0,0 +1,5 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ ++ ++/* dummy */ +diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl +new file mode 100644 +index 0000000000..b7588dcc41 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* This is board specific information: ++ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 ++ */ ++ ++If (PICM) { ++ Return (Package() { ++ /* PCI slot */ ++ Package() { 0x0001ffff, 0, 0, 0x14}, ++ Package() { 0x0001ffff, 1, 0, 0x15}, ++ Package() { 0x0001ffff, 2, 0, 0x16}, ++ Package() { 0x0001ffff, 3, 0, 0x17}, ++ ++ Package() { 0x0002ffff, 0, 0, 0x15}, ++ Package() { 0x0002ffff, 1, 0, 0x16}, ++ Package() { 0x0002ffff, 2, 0, 0x17}, ++ Package() { 0x0002ffff, 3, 0, 0x14}, ++ }) ++} Else { ++ Return (Package() { ++ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, ++ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, ++ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, ++ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, ++ ++ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, ++ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, ++ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, ++ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, ++ }) ++} +diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl +new file mode 100644 +index 0000000000..9f3900b86c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl +@@ -0,0 +1,18 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#undef SUPERIO_DEV ++#undef SUPERIO_PNP_BASE ++#undef IT8720F_SHOW_SP1 ++#undef IT8720F_SHOW_SP2 ++#undef IT8720F_SHOW_EC ++#undef IT8720F_SHOW_KBCK ++#undef IT8720F_SHOW_KBCM ++#undef IT8720F_SHOW_GPIO ++#undef IT8720F_SHOW_CIR ++#define SUPERIO_DEV SIO0 ++#define SUPERIO_PNP_BASE 0x2e ++#define IT8720F_SHOW_EC 1 ++#define IT8720F_SHOW_KBCK 1 ++#define IT8720F_SHOW_KBCM 1 ++#define IT8720F_SHOW_GPIO 1 ++#include <superio/ite/it8720f/acpi/superio.asl> +diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt +new file mode 100644 +index 0000000000..aaf657b583 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/board_info.txt +@@ -0,0 +1,6 @@ ++Category: desktop ++Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y +diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default +new file mode 100644 +index 0000000000..23f0e55f3e +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cmos.default +@@ -0,0 +1,8 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++sata_mode=AHCI ++gfx_uma_size=64M +diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout +new file mode 100644 +index 0000000000..9f5012adb4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cmos.layout +@@ -0,0 +1,72 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++# coreboot config options: southbridge ++408 1 e 10 sata_mode ++409 2 e 7 power_on_after_fail ++411 1 e 1 nmi ++ ++# coreboot config options: cpu ++ ++# coreboot config options: northbridge ++432 4 e 11 gfx_uma_size ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++10 0 AHCI ++10 1 Compatible ++11 1 4M ++11 2 8M ++11 3 16M ++11 4 32M ++11 5 48M ++11 6 64M ++11 7 128M ++11 8 256M ++11 9 96M ++11 10 160M ++11 11 224M ++11 12 352M ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 983 984 +diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c +new file mode 100644 +index 0000000000..4adf0edc63 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/cstates.c +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <acpi/acpigen.h> ++ ++int get_cst_entries(const acpi_cstate_t **entries) ++{ ++ return 0; ++} +diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb +new file mode 100644 +index 0000000000..95e3bd517c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/devicetree.cb +@@ -0,0 +1,63 @@ ++# SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster ++ device domain 0 on ++ ops x4x_pci_domain_ops # PCI domain ++ subsystemid 0x8086 0x0028 inherit ++ device pci 0.0 on end # Host Bridge ++ device pci 1.0 on end # PCIe x16 2.0 slot ++ device pci 2.0 on end # Integrated graphics controller ++ device pci 2.1 on end # Integrated graphics controller 2 ++ device pci 3.0 off end # ME ++ device pci 3.1 off end # ME ++ chip southbridge/intel/i82801jx # ICH10 ++ register "gpe0_en" = "0x40" ++ ++ # Set AHCI mode. ++ register "sata_port_map" = "0x3f" ++ register "sata_clock_request" = "1" ++ ++ # Enable PCIe ports 0,1 as slots. ++ register "pcie_slot_implemented" = "0x3" ++ ++ device pci 19.0 on end # GBE ++ device pci 1a.0 on end # USB ++ device pci 1a.1 on end # USB ++ device pci 1a.2 on end # USB ++ device pci 1a.7 on end # USB ++ device pci 1b.0 on end # Audio ++ device pci 1c.0 off end # PCIe 1 ++ device pci 1c.1 off end # PCIe 2 ++ device pci 1c.2 off end # PCIe 3 ++ device pci 1c.3 off end # PCIe 4 ++ device pci 1c.4 off end # PCIe 5 ++ device pci 1c.5 off end # PCIe 6 ++ device pci 1d.0 on end # USB ++ device pci 1d.1 on end # USB ++ device pci 1d.2 on end # USB ++ device pci 1d.7 on end # USB ++ device pci 1e.0 on end # PCI bridge ++ device pci 1f.0 on end # LPC bridge ++ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) ++ device pci 1f.3 on # SMBus ++ chip drivers/i2c/ck505 # IDT CV194 ++ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff }" ++ register "regs" = "{ 0x15, 0x82, 0xff, 0xff, ++ 0xff, 0x00, 0x00, 0x95, ++ 0x00, 0x65, 0x7d, 0x56, ++ 0x13, 0xc0, 0x00, 0x07, ++ 0x01, 0x0a, 0x64 }" ++ device i2c 69 on end ++ end ++ end ++ device pci 1f.4 off end ++ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) ++ device pci 1f.6 off end # Thermal Subsystem ++ end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl +new file mode 100644 +index 0000000000..9ad70469de +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/dsdt.asl +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <acpi/acpi.h> ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20090811 // OEM revision ++) ++{ ++ #include <acpi/dsdt_top.asl> ++ ++ OSYS = 2002 ++ // global NVS and variables ++ #include <southbridge/intel/common/acpi/platform.asl> ++ ++ Device (\_SB.PCI0) ++ { ++ #include <northbridge/intel/x4x/acpi/x4x.asl> ++ #include <southbridge/intel/i82801jx/acpi/ich10.asl> ++ } ++ ++ #include <southbridge/intel/common/acpi/sleepstates.asl> ++} +diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads +new file mode 100644 +index 0000000000..bc81cf4a40 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads +@@ -0,0 +1,16 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (DP2, ++ Analog, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb +zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX +zznS;`v-5V=o<pVaS;}Q53%NpOI!8{cz{K0eVfK65_|*A}SF)Me%$4!N`H5-z90%~a +zvGog3fe5LjnM&o#3$<#k{6>{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E +znI_A1T57efS5MG<y}m-_+CrVKE#0VADDft%nb#Y<<ao9;Mf?!XvM)_$Xla>NN5_ut +zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh +z0Pae^5`gfb?<R!YN+PQ)U7<%H;73qF3iyQT71$?W2s|f{69_4sRY(x>7Q)c(LsP)8 +zQy)2gw<F#IP`I}U>gG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa<Jq(M +zbA{r}Z0XY6<@U{Y-d!KWR>9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n +z>oEf8XCt;_Y-iYBWz#<re{?il1^f{S#nht`VW!62^5R*KQ6_?#8e&Qw=9%`og2x!s +z&J)wlZ=a<yoJkutfwu4%aVXlu?i^8v?R77IyGvKcD|M`CFG$6FUmK8q<|o>3T9EmJ +z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<<Gei4)FzWqGEt6P8D +zA9m}s>;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH` +zawsKv^FvHqm+<DDPT)%}_kZ8^eT88YGmG-#)X3=RRB|L^Uj_{yd%JeO<1HRZVz=Fz +z+aqUCWdF3_={#Q&&k)eF1i=WV`AbSlzo*bP?x?ir5BVVO`R34f89jWL{Z}or^BwmG +z-E;A_iWVUUWnWQl3L|~0xA@rHJRA-;7V)Y6B5=@E8R@?(?5{Eh23RefpSOGX_F{8A +z1PtU+iNng^h#C7J<vufJ9>c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E +xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO(<xf!`#Pk3F + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c +new file mode 100644 +index 0000000000..e2fa05cd8f +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include <northbridge/intel/x4x/x4x.h> ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ // BTX form factor ++ spd_map[0] = 0x53; ++ spd_map[1] = 0x52; ++ spd_map[2] = 0x51; ++ spd_map[3] = 0x50; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c +new file mode 100644 +index 0000000000..9993f17c55 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c +@@ -0,0 +1,174 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_NATIVE, ++ .gpio69 = GPIO_MODE_NATIVE, ++ .gpio70 = GPIO_MODE_NATIVE, ++ .gpio71 = GPIO_MODE_NATIVE, ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c +new file mode 100644 +index 0000000000..4158bcf899 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0xbfd40000, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x032140f0), ++ AZALIA_PIN_CFG(0, 0x12, 0x21214010), ++ AZALIA_PIN_CFG(0, 0x13, 0x901701f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0), ++ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121), ++ AZALIA_PIN_CFG(0, 0x16, 0x9933012e), ++ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch new file mode 100644 index 00000000..231e303e --- /dev/null +++ b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -0,0 +1,326 @@ +From bb14741af8e4a16d3d098d79fb8df0c3a45e6ccb Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Wed, 30 Oct 2024 20:55:25 -0600 +Subject: [PATCH 26/40] mb/dell/optiplex_780: Add USFF variant + +Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/optiplex_780/Kconfig | 5 + + src/mainboard/dell/optiplex_780/Kconfig.name | 3 + + .../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes + .../variants/780_usff/early_init.c | 9 + + .../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++ + .../optiplex_780/variants/780_usff/hda_verb.c | 26 +++ + .../variants/780_usff/overridetree.cb | 10 ++ + 7 files changed, 219 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +index 2d06c75c9a..fc649e35d5 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON + config BOARD_DELL_OPTIPLEX_780_MT + select BOARD_DELL_OPTIPLEX_780_COMMON + ++config BOARD_DELL_OPTIPLEX_780_USFF ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ + if BOARD_DELL_OPTIPLEX_780_COMMON + + config VGA_BIOS_ID +@@ -30,11 +33,13 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + + config VARIANT_DIR + default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF + + endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +index db7f2e8fe3..bc84c82a79 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig.name ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -2,3 +2,6 @@ + + config BOARD_DELL_OPTIPLEX_780_MT + bool "OptiPlex 780 MT" ++ ++config BOARD_DELL_OPTIPLEX_780_USFF ++ bool "OptiPlex 780 USFF" +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7 +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@i<uQKf!)+gO;| +zveT#>P+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G +z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX +zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv +zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB +zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU<Iv53Rb6YTgMPOY8;~P1Yglh^6Fgt1^ +zCTz|SVPcSpZ44F@&oNPUMO@&BE3y(57YP_Y!4SZhE?GXYa7k+b0(X|s7u3GDRf^1# +zOd2ZCCPO|I&sHEt;p8UshhHtYQ>7!7x2m<d`Gu2<r+Qc4|6pwd8&zFboH_W7XE7uU +zWW-@Cim&mdY2!O{JANR)OTJG2z>LBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T +z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`<pE+J?KFZ=&_JVP1YL=#z<-Q*24K4 +zn+$YxrHNJJc`k?_8N=Kres26_#E8GLn2{jfW5P%ge`kL(Btkt=>xo)V)Ow=U6P12c +z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8 +zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE +zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb +zV99s{>`r76L#Hr6XW6r|<iq#4Jr?XsxKyeJKEj7;e4SZ^1B12u&iV_9M0*Kem@fmn +z1C>>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq<Gj{q2D( +z>&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a= +T#w3FFBiyj<XAh$hb(enud`r7S + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c +new file mode 100644 +index 0000000000..2a55fc3a6e +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include <northbridge/intel/x4x/x4x.h> ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ spd_map[0] = 0x50; ++ spd_map[2] = 0x52; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +new file mode 100644 +index 0000000000..389f4077d7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +@@ -0,0 +1,166 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +new file mode 100644 +index 0000000000..c94e06b156 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0x10280420, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x02214040), ++ AZALIA_PIN_CFG(0, 0x12, 0x01014010), ++ AZALIA_PIN_CFG(0, 0x13, 0x991301f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x02a19020), ++ AZALIA_PIN_CFG(0, 0x15, 0x01813030), ++ AZALIA_PIN_CFG(0, 0x16, 0x413301f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch new file mode 100644 index 00000000..94186a30 --- /dev/null +++ b/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -0,0 +1,33 @@ +From 1685de1beee49456e9f6f578ca6e37219fe7dfff Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Mon, 6 Jan 2025 01:53:53 +0000 +Subject: [PATCH 27/40] src/intel/x4x: Disable stack overflow debug + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/northbridge/intel/x4x/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig +index 1803ef5733..7129aabf72 100644 +--- a/src/northbridge/intel/x4x/Kconfig ++++ b/src/northbridge/intel/x4x/Kconfig +@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER + int + default 256 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + # This number must be equal or lower than what's reported in ACPI PCI _CRS + config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xfec00000 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch new file mode 100644 index 00000000..c42b3cf0 --- /dev/null +++ b/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -0,0 +1,42 @@ +From 6f54ed4b0622c7772561760ea4b435bd236ac834 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Tue, 22 Apr 2025 10:21:59 +0100 +Subject: [PATCH 28/40] hp/8300cmt: remove xhci_overcurrent_mapping + +No longer needed, as per the following commit: + +commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1 +Author: Keith Hui <buurin@gmail.com> +Date: Tue Dec 31 18:19:31 2024 -0500 + + sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping + +Removing this from the devicetree also allows the +board to compile, otherwise an error is thrown: + +build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping' + 147 | .xhci_overcurrent_mapping = 0x00000c03, + | ^~~~~~~~~~~~~~~~~~~~~~~~ +build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror] + 147 | .xhci_overcurrent_mapping = 0x00000c03, + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +index 3d21739b72..3a0b6d5c59 100644 +--- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" +- register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch new file mode 100644 index 00000000..4b036e02 --- /dev/null +++ b/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch @@ -0,0 +1,49 @@ +From 17c67799604e0e29192415e97293d71deb457cb2 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Wed, 11 Dec 2024 01:06:01 +0000 +Subject: [PATCH 29/40] dell/3050micro: disable nvme hotplug + +in my testing, when running my 3050micro for a few days, +the nvme would sometimes randomly rename. + +e.g. nvme0n1 renamed to nvme0n2 + +this might cause crashes in linux, if booting only from the +nvme. in my case, i was booting from mdraid (sata+nvme) and +every few days, the nvme would rename at least once, causing +my RAID to become unsynced. since i'm using RAID1, this was +OK and I could simply re-sync the array, but this is quite +precarious indeed. if you're using raid0, that will potentially +corrupt your RAID array indefinitely. + +this same issue manifested on the T480/T480 thinkpads, and +S3 resume would break because of that, when booting from nvme, +because the nvme would be "unplugged" and appear to linux as a +new device (the one that you booted from). + +the fix there was to disable hotplugging on that pci-e slot +for the nvme, so apply the same fix here for 3050 micro + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/mainboard/dell/optiplex_3050/devicetree.cb | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb +index 0d2adff74a..829acacab3 100644 +--- a/src/mainboard/dell/optiplex_3050/devicetree.cb ++++ b/src/mainboard/dell/optiplex_3050/devicetree.cb +@@ -44,7 +44,9 @@ chip soc/intel/skylake + register "PcieRpAdvancedErrorReporting[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" + register "PcieRpClkSrcNumber[20]" = "3" +- register "PcieRpHotPlug[20]" = "1" ++# disable hotplug on nvme to prevent renaming e.g. nvme0n1 rename to nvme0n2, ++# which could cause crashes in linux if booting from nvme ++ register "PcieRpHotPlug[20]" = "0" + end + + # Realtek LAN +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch new file mode 100644 index 00000000..8a328251 --- /dev/null +++ b/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch @@ -0,0 +1,94 @@ +From 819fe0e89e426d3d875cf8ab4d2de439ba716848 Mon Sep 17 00:00:00 2001 +From: Felix Singer <felixsinger@posteo.net> +Date: Wed, 26 Jun 2024 04:24:31 +0200 +Subject: [PATCH 30/40] soc/intel/skylake: configure usb acpi + +Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d +Signed-off-by: Felix Singer <felixsinger@posteo.net> +--- + src/soc/intel/skylake/Kconfig | 1 + + src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++- + 2 files changed, 56 insertions(+), 1 deletion(-) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index 4ad33496b2..9191ed0ff8 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE + select CPU_INTEL_COMMON + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION ++ select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 + select FSP_COMPRESS_FSP_S_LZ4 + select FSP_M_XIP +diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb +index 6538a1475b..dfb81d496e 100644 +--- a/src/soc/intel/skylake/chipset.cb ++++ b/src/soc/intel/skylake/chipset.cb +@@ -13,7 +13,61 @@ chip soc/intel/skylake + device pci 07.0 alias chap off end + device pci 08.0 alias gmm off end # Gaussian Mixture Model + device pci 13.0 alias ish off end # SensorHub +- device pci 14.0 alias south_xhci off ops usb_xhci_ops end ++ device pci 14.0 alias south_xhci off ops usb_xhci_ops ++ chip drivers/usb/acpi ++ register "type" = "UPC_TYPE_HUB" ++ device usb 0.0 alias xhci_root_hub off ++ chip drivers/usb/acpi ++ device usb 2.0 alias usb2_port1 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.1 alias usb2_port2 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.2 alias usb2_port3 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.3 alias usb2_port4 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.4 alias usb2_port5 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.5 alias usb2_port6 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.6 alias usb2_port7 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.7 alias usb2_port8 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.8 alias usb2_port9 off end ++ end ++ chip drivers/usb/acpi ++ device usb 2.9 alias usb2_port10 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.0 alias usb3_port1 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.1 alias usb3_port2 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.2 alias usb3_port3 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.3 alias usb3_port4 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.4 alias usb3_port5 off end ++ end ++ chip drivers/usb/acpi ++ device usb 3.5 alias usb3_port6 off end ++ end ++ end ++ end ++ end + device pci 14.1 alias south_xdci off ops usb_xdci_ops end + device pci 14.2 alias thermal off end + device pci 14.3 alias cio off end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch new file mode 100644 index 00000000..916e54dc --- /dev/null +++ b/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -0,0 +1,61 @@ +From 7194444fbddcf6567d0c82f0986e5deeacaea680 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Mon, 6 Jan 2025 01:36:23 +0000 +Subject: [PATCH 31/40] src/intel/skylake: Disable stack overflow debug options + +The option was appearing in T480/3050micro configs of lbmk, +after updating on the coreboot/next uprev for 20241206 rev8: + +CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y + +I did some digging. See coreboot commit: + +commit 51cc2bacb6b07279b97e9934d079060475481fb6 +Author: Subrata Banik <subratabanik@google.com> +Date: Fri Dec 13 13:07:28 2024 +0530 + + soc/intel/pantherlake: Disable stack overflow debug options + +Well now: + +I'm disabling this behaviour on Skylake, for the same +behaviour, because I want as few behaviour changes in general, +as possible, for the rev8 release. + +According to Subrata's patch, which was for Pantherlake, +without this change, stack corruption can occur on verstage +and romstage early on. Please look at that coreboot patch, +referenced above, for clarity. + +I see no harm in disabling this option for Skylake, since +the behaviour that it otherwise enables was not present +before. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/soc/intel/skylake/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index 9191ed0ff8..493a2d835a 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE + The size of the cache-as-ram region required during bootblock + and/or romstage. + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config DCACHE_BSP_STACK_SIZE + hex + default 0x20400 if FSP_USES_CB_STACK +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch new file mode 100644 index 00000000..cd1ed452 --- /dev/null +++ b/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -0,0 +1,36 @@ +From 81360b8c28293856e964934d1f356b1312b39ff2 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Thu, 26 Dec 2024 19:45:20 +0000 +Subject: [PATCH 32/40] soc/intel/skylake: Don't compress FSP-S + +Build systems like lbmk need to reproducibly insert +certain vendor files on release images. + +Compression isn't always reproducible, and making it +so costs a lot more time than simply disabling compression. + +With this change, the FSP-S module will now be inserted +without compression, which means that there will now be +about 40KB of extra space used in the flash. + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/soc/intel/skylake/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index 493a2d835a..42af82a5d8 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -12,7 +12,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE + select CPU_SUPPORTS_PM_TIMER_EMULATION + select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 +- select FSP_COMPRESS_FSP_S_LZ4 ++# select FSP_COMPRESS_FSP_S_LZ4 + select FSP_M_XIP + select GENERIC_GPIO_LIB + select HAVE_FSP_GOP +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch new file mode 100644 index 00000000..487b32a2 --- /dev/null +++ b/config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -0,0 +1,78 @@ +From 25ff99ff021312387734a10836232a5f3a2d2a12 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Wed, 18 Dec 2024 02:06:18 +0000 +Subject: [PATCH 33/40] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN + +This is used by lbmk to know where a tb.bin file goes, +when extracting and padding TBT.bin from Lenovo ThunderBolt +firmware updates on T480/T480s and other machines, grabbing +Lenovo update files. + +Not used in any builds, so it's not relevant for ./mk inject + +However, the ThunderBolt firmware is now auto-downloaded on +T480/T480s. This is not inserted, because it doesn't go in +the main flash, but the resulting ROM image can be flashed +on the TB controller's separate flash chip. + +Locations are as follows: + +vendorfiles/t480s/tb.bin +vendorfiles/t480/tb.bin + +This can be used for other affected ThinkPads when they're +added to Libreboot, but note that Lenovo provides different +TB firmware files for each machine. + +Since I assume it's the same TB controller on all of those +machines, I have to wonder: what difference is there between +the various TBT.bin files provided by Lenovo, and how do they +differ in terms of actual flashed configuration? + +We simply flash the padded TBT.bin when updating the firmware, +flashing externally. That's what this patch is for, so that +lbmk can auto-download them. + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig +index 2ffbaab85f..512b326381 100644 +--- a/src/mainboard/lenovo/Kconfig ++++ b/src/mainboard/lenovo/Kconfig +@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + ++config LENOVO_TBFW_BIN ++ string "Lenovo ThunderBolt firmware bin file" ++ default "" ++ help ++ ThunderBolt firmware for certain ThinkPad models e.g. T480. ++ Not used in the actual build. Libreboot's build system uses this ++ along with config/vendor/*/pkg.cfg entries defining a URL to the ++ Lenovo download link and hash. The resulting file when processed by ++ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device. ++ Earlier versions of this firmware had debug commands enabled that ++ sent logs to said flash IC, and it would quickly fill up, bricking ++ the ThunderBolt controller. With these updates, flashed externally, ++ you can fix the issue if present or otherwise prevent it. The benefit ++ here is that you then don't need to use Windows or a boot disk. You ++ can flash the TB firmware while flashing Libreboot firmware. Easy! ++ Look for these variables in lbmk: ++ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and ++ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file. ++ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting ++ the firmware, putting it at that desired location. In this way, lbmk ++ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb ++ and it appears at vendorfiles/t480/tb.bin fully padded and everything! ++ ++ Just leave this blank if you don't care about this option. It's not ++ useful for every ThinkPad, only certain models. ++ + endif # VENDOR_LENOVO +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch b/config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch new file mode 100644 index 00000000..1aeae433 --- /dev/null +++ b/config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch @@ -0,0 +1,37 @@ +From 57630265c7ba2429a8215757330348733c087db3 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Mon, 21 Apr 2025 05:14:45 +0100 +Subject: [PATCH 34/40] Conditional TBFW setting for T480/T480S + +Otherwise, other boards will define it, which +might trigger the vendor download script, and +lead to a non-zero exit. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/mainboard/lenovo/Kconfig | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig +index 512b326381..3d3490b35d 100644 +--- a/src/mainboard/lenovo/Kconfig ++++ b/src/mainboard/lenovo/Kconfig +@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + ++if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S ++ + config LENOVO_TBFW_BIN + string "Lenovo ThunderBolt firmware bin file" + default "" +@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN + Just leave this blank if you don't care about this option. It's not + useful for every ThinkPad, only certain models. + ++endif # BOARD LENOVO_T480 || BOARD_LENOVO_T480S ++ + endif # VENDOR_LENOVO +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch b/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch new file mode 100644 index 00000000..1edd0d27 --- /dev/null +++ b/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch @@ -0,0 +1,106 @@ +From 0a98ff0cbd20484ced53b15f16f8b77d881ffb9e Mon Sep 17 00:00:00 2001 +From: Riku Viitanen <riku.viitanen@protonmail.com> +Date: Thu, 25 Sep 2025 22:45:37 +0300 +Subject: [PATCH 35/40] mb/topton/adl: Add TWL variant (X2E_N150) + +Seems to be the same board but with a Twin Lake processor. +VBT extracted from vendor firmware. This makes HDMI and +DisplayPort work. + +Change-Id: I1018042802cbb8010888847226a2117fd9dfaeb0 +Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> +--- + src/mainboard/topton/adl/Kconfig | 12 +++++++++--- + src/mainboard/topton/adl/Kconfig.name | 3 +++ + src/mainboard/topton/adl/data_twl.vbt | Bin 0 -> 9216 bytes + 3 files changed, 12 insertions(+), 3 deletions(-) + create mode 100644 src/mainboard/topton/adl/data_twl.vbt + +diff --git a/src/mainboard/topton/adl/Kconfig b/src/mainboard/topton/adl/Kconfig +index ffdfae1eee..331e1d624d 100644 +--- a/src/mainboard/topton/adl/Kconfig ++++ b/src/mainboard/topton/adl/Kconfig +@@ -1,6 +1,6 @@ + ## SPDX-License-Identifier: GPL-2.0-or-later + +-if BOARD_TOPTON_X2F_N100 ++if BOARD_TOPTON_X2F_N100 || BOARD_TOPTON_X2E_N150 + + config BOARD_SPECIFIC_OPTIONS + def_bool y +@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS + select SUPERIO_ITE_IT8625E + select DRIVERS_UART_8250IO + select SOC_INTEL_ALDERLAKE_PCH_N ++ select SOC_INTEL_TWINLAKE if BOARD_TOPTON_X2E_N150 + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select HAVE_INTEL_PTT +@@ -20,7 +21,12 @@ config BOARD_SPECIFIC_OPTIONS + config MAINBOARD_DIR + default "topton/adl" + ++config INTEL_GMA_VBT_FILE ++ default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if BOARD_TOPTON_X2F_N100 ++ default "src/mainboard/\$(MAINBOARDDIR)/data_twl.vbt" if BOARD_TOPTON_X2E_N150 ++ + config MAINBOARD_PART_NUMBER +- default "X2F_N100" ++ default "X2F_N100" if BOARD_TOPTON_X2F_N100 ++ default "X2E_N150" if BOARD_TOPTON_X2E_N150 + +-endif # BOARD_TOPTON_X2F_N100 ++endif # BOARD_TOPTON_X2F_N100 || BOARD_TOPTON_X2E_N150 +diff --git a/src/mainboard/topton/adl/Kconfig.name b/src/mainboard/topton/adl/Kconfig.name +index 5b8b5ff602..db0eef29be 100644 +--- a/src/mainboard/topton/adl/Kconfig.name ++++ b/src/mainboard/topton/adl/Kconfig.name +@@ -2,3 +2,6 @@ + + config BOARD_TOPTON_X2F_N100 + bool "X2F_N100" ++ ++config BOARD_TOPTON_X2E_N150 ++ bool "X2E_N150" +diff --git a/src/mainboard/topton/adl/data_twl.vbt b/src/mainboard/topton/adl/data_twl.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..05fbd5807365b3343e55ecedbd12fabb8a3199e9 +GIT binary patch +literal 9216 +zcmeHML2MgE6#cVnZ(QS$EeWj~+AvA0;DjbwJ8eiKOI^oKsN1BmoiuVKP~6mpM!1bh +zQ<Ng4E+U6qkoHnYD<ljO5(<}a;EYcw2q9TTAPykqMyWV})EjNgpV_rtrwuVJg{InX +z{oV2WH*f#{GdnZ8yKlUIj0T261F@mNv4M^VMM;7J%`Is>-Yxy%k<p1zU@S1vKQt0N +zMuF^r-<#KN03-?7<?<?uH+*h3mG;Ei=<xL9R65laN}Ydgb~-~N!7vS+KAlRZW=_qf +zl5}+Z#Q<e|wa)$vQ|Tl<e&Ot7YNn4OiGpbAJ<!>GfKuNJT}pSCPw^f^OP{x=@8F?Y +zXJ{ZeG8_pH1;)Z7$LUCnhQgzP(b0k7{-KjJ5*s-Z?hlU*gle4?Aq1y07iXqkJu^!^ +z!8Yo{>vV8l?lKKd&ty7jAf2W$hB;4Tsq?9sH&V&YS|=mQfx|`sh!g5^fCVPE`#}a9 +zsHlL)`xD_Z5wN|-v938@Q^cwq64R22!kSk4V-#wPQx09BB@^Ooa4i9{41s33Sk2r< +zK0;0ZS^b&{U!7sNmrWe<2^=R^;wVES?xKmSE&7)*aR%uczZ&8$o4D-&c5Imgt&)#j +zgz<fD;_3k;j?*h~oECB4nmE=BB?lQ3$FhWR@J>P8uj_HJ4#(k}A8x&g7&B1>2or#( +ziF#Md@5Pn7>QZ(mOru^zeFybj)b~+8Lj4T&3)C-BzefEI^=H&yQ2#*v6Lnh>DFxmU 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+z4KBA`zl{K!O5Cu3Z?s$S#hJuI(eSwX3BIqkFA@bZh*7W|KFgxyP?>GcPKk`RMw?t= +z(|=;NRT76qw6#{)@^b>Hk|L<cvTXBJ*lrCI7`HExLD12cCbSuE88y7#k9h*Rlm!JS +zayFIx%%M#`DS%dE*p_X3F?QoqB(vGF1hV!#iNF<@7h90ic*bTn7K19SfE%J{OENU7 +z5#L66$)SB;Ez3(5AL-E>aVNGa=cOUUd~sv!9nfp*sPOaZ+xVs0fuGXx2U0!y!oLUb +SeEwbkJq|WZn<bBL2L1wR4t_2G + +literal 0 +HcmV?d00001 + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch new file mode 100644 index 00000000..565be85a --- /dev/null +++ b/config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch @@ -0,0 +1,30 @@ +From 8e191c71f11de4cb3d08fe585537f15043cacb1b Mon Sep 17 00:00:00 2001 +From: Riku Viitanen <riku.viitanen@protonmail.com> +Date: Sat, 27 Sep 2025 23:30:46 +0300 +Subject: [PATCH 36/40] soc/intel/alderlake: Disable + MRC_CACHE_USING_MRC_VERSION + +There's some issue with building against the FSP headers in src/vendorcode. +Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing +from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force. + +Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> +--- + src/soc/intel/alderlake/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 51bdf98b9d..739faa3808 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -34,7 +34,6 @@ config SOC_INTEL_ALDERLAKE + select INTEL_GMA_VERSION_2 + select INTEL_TXT_LIB + select MP_SERVICES_PPI_V2 +- select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO + select MRC_SETTINGS_PROTECT + select PARALLEL_MP_AP_WORK + select PLATFORM_USES_FSP2_2 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch new file mode 100644 index 00000000..8cff0c56 --- /dev/null +++ b/config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch @@ -0,0 +1,76 @@ +From 8ab86ffd25fc013790c260e564c8b770c13a5342 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Sun, 28 Sep 2025 03:17:50 +0100 +Subject: [PATCH 37/40] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) + +if you pass -k (keep fptr modules), don't use -r, don't +use -t, you can essentially just use me_cleaner to +extract a ME image without changing it. this is useful +when for example, you just want to set the HAP bit. + +however, me_cleaner still performs a FPTR check. + +on some newer ME versions, it's always invalid according +to me_cleaner, because for example it doesn't handle +ME16 very well yet. + +this patch adds an option to override the FPTR check + +either pass -p or --pass-fptr + +NOTE: we probably won't use this on coreboot's me_cleaner, +which is the corna version. we only need it on the newer +me_cleaner versions for e.g. ME16, on certain setups. +still, it's best to have the patch here too, just in case. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + util/me_cleaner/me_cleaner.py | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py +index fae5e56732..228bac899f 100755 +--- a/util/me_cleaner/me_cleaner.py ++++ b/util/me_cleaner/me_cleaner.py +@@ -246,8 +246,10 @@ def check_partition_signature(f, offset): + return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME + + +-def print_check_partition_signature(f, offset): +- if check_partition_signature(f, offset): ++def print_check_partition_signature(f, offset, pass_fptr): ++ if pass_fptr: ++ print("Skipping FPTR checks because the user told us to") ++ elif check_partition_signature(f, offset): + print("VALID") + else: + print("INVALID!!") +@@ -486,6 +488,8 @@ if __name__ == "__main__": + "--extract-me)", action="store_true") + parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR " + "modules, even when possible", action="store_true") ++ parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks" ++ "regardless of other operations", action="store_true") + bw_list.add_argument("-w", "--whitelist", metavar="whitelist", + help="Comma separated list of additional partitions " + "to keep in the final image. This can be used to " +@@ -871,12 +875,14 @@ if __name__ == "__main__": + print("Checking the FTPR RSA signature of the extracted ME " + "image... ", end="") + print_check_partition_signature(mef_copy, +- ftpr_offset + ftpr_mn2_offset) ++ ftpr_offset + ftpr_mn2_offset, ++ args.pass_fptr) + mef_copy.close() + + if not me6_ignition: + print("Checking the FTPR RSA signature... ", end="") +- print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset) ++ print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset, ++ args.pass_fptr) + + f.close() + +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch new file mode 100644 index 00000000..545f2076 --- /dev/null +++ b/config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch @@ -0,0 +1,35 @@ +From c36ed52f7573563a9eaeeedd6e6c0ee75973a39d Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Sat, 4 Oct 2025 21:57:43 +0100 +Subject: [PATCH 38/40] soc/intel/alderlake: Don't compress FSP-S + +Build systems like lbmk need to reproducibly insert +certain vendor files on release images. + +Compression isn't always reproducible, and making it +so costs a lot more time than simply disabling compression. + +With this change, FSP-S uses slightly more space inside +the flash, but it's not that much. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/soc/intel/alderlake/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 739faa3808..1f6a1dca7d 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -14,7 +14,7 @@ config SOC_INTEL_ALDERLAKE + select DISPLAY_FSP_VERSION_INFO + select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 +- select FSP_COMPRESS_FSP_S_LZ4 ++# select FSP_COMPRESS_FSP_S_LZ4 + select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW + select FSP_M_XIP + select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch new file mode 100644 index 00000000..ed7d98e0 --- /dev/null +++ b/config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch @@ -0,0 +1,33 @@ +From e564490781b0b829da43534c6c2a1b26aeb3282f Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Sat, 4 Oct 2025 22:20:11 +0100 +Subject: [PATCH 39/40] alderlake: don't require full fsp repo for fd path + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/soc/intel/alderlake/Kconfig | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 1f6a1dca7d..3979d9e162 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -415,7 +415,14 @@ config FSP_HEADER_PATH + + config FSP_FD_PATH + string +- depends on FSP_USE_REPO ++# dependency removed for lbmk purposes, so that the path is present ++# in the config regardless of whether it's used. this is for ./mk -d ++# on alderlake boards, which is used by lbmk to manually split fsp, ++# even though the result is identical to what coreboot produces, because ++# this enables lbmk to strip the fsp in release archives, and re-insert ++# for compliance reasons (due to technicalities in intel's licensing), ++# and to enable lbmk's advanced checksum verification of vendor files ++# depends on FSP_USE_REPO + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch b/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch new file mode 100644 index 00000000..4fdf2476 --- /dev/null +++ b/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch @@ -0,0 +1,184 @@ +From 0fdb23e899e31b17a774ae9151410b11ccf13022 Mon Sep 17 00:00:00 2001 +From: Ron Nazarov <ron@noisytoot.org> +Date: Tue, 30 Sep 2025 22:36:53 +0100 +Subject: [PATCH 40/40] Haswell NRI: Implement SMBIOS type 16/17 + +Based on the implementation from Ivy/Sandy Bridge NRI. + +Tested on a Dell OptiPlex 9020 SFF with libreboot. + +Change-Id: I5e153258f9f88726f54c98baac0b1788a839f934 +Signed-off-by: Ron Nazarov <ron@noisytoot.org> +--- + .../haswell/native_raminit/raminit_main.c | 6 +- + .../haswell/native_raminit/raminit_native.c | 83 +++++++++++++++++-- + .../haswell/native_raminit/raminit_native.h | 2 +- + 3 files changed, 81 insertions(+), 10 deletions(-) + +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c +index 84db33ebdf..328f777ee1 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c +@@ -245,7 +245,7 @@ static enum raminit_status try_raminit( + return status; + } + +-void raminit_main(const enum raminit_boot_mode bootmode) ++const struct sysinfo *raminit_main(const enum raminit_boot_mode bootmode) + { + /* + * The mighty_ctrl struct. Will happily nuke the pre-RAM stack +@@ -261,7 +261,7 @@ void raminit_main(const enum raminit_boot_mode bootmode) + if (bootmode != BOOTMODE_COLD) { + status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot)); + if (status == RAMINIT_STATUS_SUCCESS) +- return; ++ return &mighty_ctrl; + } + + /** TODO: Try more than once **/ +@@ -269,4 +269,6 @@ void raminit_main(const enum raminit_boot_mode bootmode) + + if (status != RAMINIT_STATUS_SUCCESS) + die("Memory initialization was met with utmost failure and misery\n"); ++ ++ return &mighty_ctrl; + } +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c +index 3ad8ce29e7..73532592e8 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c +@@ -16,6 +16,73 @@ + + #include "raminit_native.h" + ++static uint8_t nb_get_ecc_type(const uint32_t capid0_a) ++{ ++ return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; ++} ++ ++static uint16_t nb_slots_per_channel(const uint32_t capid0_a) ++{ ++ return !(capid0_a & CAPID_DDPCD) + 1; ++} ++ ++static uint16_t nb_number_of_channels(const uint32_t capid0_a) ++{ ++ return !(capid0_a & CAPID_PDCD) + 1; ++} ++ ++static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) ++{ ++ uint32_t ddrsz; ++ ++ /* Values from documentation, which assume two DIMMs per channel */ ++ switch (CAPID_DDRSZ(capid0_a)) { ++ case 1: ++ ddrsz = 8192; ++ break; ++ case 2: ++ ddrsz = 2048; ++ break; ++ case 3: ++ ddrsz = 512; ++ break; ++ default: ++ ddrsz = 16384; ++ break; ++ } ++ ++ /* Account for the maximum number of DIMMs per channel */ ++ return (ddrsz / 2) * nb_slots_per_channel(capid0_a); ++} ++ ++/* Fill cbmem with information for SMBIOS type 16 and type 17 */ ++static void setup_sdram_meminfo(const struct sysinfo *ctrl) ++{ ++ const u16 ddr_freq = (1000 << 8) / ctrl->tCK; ++ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { ++ enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, ++ &ctrl->dimms[channel][slot].data); ++ if (ret != CB_SUCCESS) ++ printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); ++ } ++ } ++ ++ /* The 'spd_add_smbios17' function allocates this CBMEM area */ ++ struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO); ++ if (!m) ++ return; ++ ++ const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); ++ ++ const uint16_t channels = nb_number_of_channels(capid0_a); ++ ++ m->ecc_type = nb_get_ecc_type(capid0_a); ++ m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); ++ m->number_of_devices = channels * nb_slots_per_channel(capid0_a); ++} ++ + static void wait_txt_clear(void) + { + const struct cpuid_result cpuid = cpuid_ext(1, 0); +@@ -90,7 +157,8 @@ static void raminit_reset(void) + static enum raminit_boot_mode do_actual_raminit( + const bool s3resume, + const bool cpu_replaced, +- const enum raminit_boot_mode orig_bootmode) ++ const enum raminit_boot_mode orig_bootmode, ++ const struct sysinfo **ctrl) + { + struct mrc_data md = prepare_mrc_cache(); + +@@ -158,7 +226,7 @@ static enum raminit_boot_mode do_actual_raminit( + * And now, the actual memory initialization thing. + */ + printk(RAM_DEBUG, "\nStarting native raminit\n"); +- raminit_main(bootmode); ++ *ctrl = raminit_main(bootmode); + + return bootmode; + } +@@ -176,8 +244,9 @@ void perform_raminit(const int s3resume) + wait_txt_clear(); + wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); + ++ const struct sysinfo *ctrl; + const enum raminit_boot_mode bootmode = +- do_actual_raminit(s3resume, cpu_replaced, orig_bootmode); ++ do_actual_raminit(s3resume, cpu_replaced, orig_bootmode, &ctrl); + + /** TODO: report_memory_config **/ + +@@ -204,9 +273,9 @@ void perform_raminit(const int s3resume) + system_reset(); + } + +- /* Save training data on non-S3 resumes */ +- if (!s3resume) ++ /* Save training data and set up SMBIOS type 16/17 on non-S3 resumes */ ++ if (!s3resume) { + save_mrc_data(); +- +- /** TODO: setup_sdram_meminfo **/ ++ setup_sdram_meminfo(ctrl); ++ } + } +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +index b9e84a11df..1401feedc5 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +@@ -476,7 +476,7 @@ static inline void mchbar_write64(const uintptr_t x, const uint64_t v) + "m"(mmxsave)); + } + +-void raminit_main(enum raminit_boot_mode bootmode); ++const struct sysinfo *raminit_main(enum raminit_boot_mode bootmode); + + enum raminit_status collect_spd_info(struct sysinfo *ctrl); + enum raminit_status initialise_mpll(struct sysinfo *ctrl); +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0041-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0041-soc-alderlake-disable-stack-overflow-debug-option.patch new file mode 100644 index 00000000..979eff9b --- /dev/null +++ b/config/coreboot/default/patches/0041-soc-alderlake-disable-stack-overflow-debug-option.patch @@ -0,0 +1,46 @@ +From 9936228e74ef8bccbf6adb8640040901d395cda0 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Mon, 6 Oct 2025 04:47:06 +0100 +Subject: [PATCH 1/1] soc/alderlake: disable stack overflow debug option + +same as on other boards. based on this commit: + +commit 51cc2bacb6b07279b97e9934d079060475481fb6 +Author: Subrata Banik <subratabanik@google.com> +Author: Subrata Banik <subratabanik@google.com> +Date: Fri Dec 13 13:07:28 2024 +0530 + + soc/intel/pantherlake: Disable stack overflow debug options + +yeah, i've been replicating this change per platform. + +we do alderlake now in libreboot, so let's set that here too. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/soc/intel/alderlake/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 3979d9e162..a47a27dfaf 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -329,6 +329,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ + int + default 19200000 + ++# Override DEBUG Kconfig to avoid false alarm about stack overflow. ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS ++ bool ++ default n ++ ++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES ++ bool ++ default n ++ + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0042-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0042-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch new file mode 100644 index 00000000..b4ebd870 --- /dev/null +++ b/config/coreboot/default/patches/0042-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch @@ -0,0 +1,92 @@ +From 732819a85ea6cca637350192fbab9d459dc68439 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Sun, 11 May 2025 15:41:22 -0600 +Subject: [PATCH 1/2] ec/dell/mec5035: Add command to disable EC-initiated + thermal shutdown + +If command 0xBF isn't sent, the EC shuts down the system without warning +as soon as the CPU temperature reaches about 87 degrees, without letting +the CPU thermal throttle to try and reduce the temperature. With vendor +firmware, the CPU is able to reach around 100 degrees before thermal +throttling. + +This command was found by collecting EC commands by logging the LPC bus +while running with vendor firmware and then replaying observed commands +from coreboot. By systematically replaying subsets of commands in a +binary search pattern and then stress testing the system, the command to +disable the shutdown was isolated. + +The exact meaning of the parameters for this command are unknown at this +time, but do seem to differ between different generations of these +laptops. Due to this, the commmand should be called by mainboard +specific code which passes the specific parameter value used. + +The Google Wilco EC code, which runs on Latitude Chromebooks and shares +many commands with the standard Latitude ECs, suggests that command 0xBF +tells the EC about the processors CPUID. However, the values observed in +LPC bus logs do not seem to correspond with any CPUID values on the +non-Chromebook systems I tested. + +Observed command parameter values (sent on mailbox registers 2-4): +- E6430 (Ivy Bridge): 0x07, 0x00, 0x00 +- M6800 (Haswell): 0x14, 0x00, 0x00 + +Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++ + src/ec/dell/mec5035/mec5035.h | 2 ++ + 2 files changed, 21 insertions(+) + +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index bdae929a27..b3574611a7 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -115,6 +115,25 @@ void mec5035_sleep_enable(void) + ec_command(CMD_SLEEP_ENABLE); + } + ++void mec5035_cmd_bf(u8 i) ++{ ++ /* ++ * If this command isn't sent, the EC shuts down the system as soon as ++ * the CPU temperature reaches about 87 degrees. It is unknown exactly ++ * what the parameters represent. The Google Wilco EC code, which runs ++ * on Latitude Chromebooks and shares some commands with the standard ++ * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but ++ * the values observed in LPC bus logs don't seem to match any CPUID ++ * values of the normal Latitudes this was tested with. ++ * Observed i values: ++ * - E6430 (Ivy Bridge): 0x7 ++ * - M6800 (Haswell): 0x14 ++ */ ++ u8 buf[3] = {i, 0, 0}; ++ write_mailbox_regs(buf, 2, 3); ++ ec_command(CMD_BF); ++} ++ + void mec5035_early_init(void) + { + /* If this isn't sent the EC shuts down the system after about 15 +diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h +index 51422598c4..f1d8c43051 100644 +--- a/src/ec/dell/mec5035/mec5035.h ++++ b/src/ec/dell/mec5035/mec5035.h +@@ -14,6 +14,7 @@ enum mec5035_cmd { + CMD_POWER_BUTTON_TO_HOST = 0x3e, + CMD_ACPI_WAKEUP_CHANGE = 0x4a, + CMD_SLEEP_ENABLE = 0x64, ++ CMD_BF = 0xbf, + CMD_CPU_OK = 0xc2, + }; + +@@ -66,5 +67,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change); + void mec5035_sleep_enable(void); + + void mec5035_smi_sleep(int slp_type); ++void mec5035_cmd_bf(u8 i); + + #endif /* _EC_DELL_MEC5035_H_ */ +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0043-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0043-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch new file mode 100644 index 00000000..25074d11 --- /dev/null +++ b/config/coreboot/default/patches/0043-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch @@ -0,0 +1,36 @@ +From b93835414970c3b3e5a3f9ccaa82e2ae80756f82 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Sun, 11 May 2025 16:28:23 -0600 +Subject: [PATCH 2/2] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown + at 87 degrees + +If command 0xBF isn't sent, the EC will shut down the system without +warning once the CPU reaches approximately 87 degrees, without the +system thermal throttling first. Call the newly added function from the +MEC5035 code to send this command and disable this behavior. + +Tested on the Latitude E6430. + +Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c +index ff83db095b..ef385a0a70 100644 +--- a/src/mainboard/dell/snb_ivb_latitude/early_init.c ++++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c +@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void) + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); ++ ++ /* Observed from LPC logs with vendor firmware. Seems to disable ++ * EC-initiated shutdown when the CPU reaches approximately 87 degrees. ++ * The exact meaning of the parameter is currently unknown. */ ++ mec5035_cmd_bf(0x07); + } +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0044-mb-lenovo-t480-Fix-headphone-jack.patch b/config/coreboot/default/patches/0044-mb-lenovo-t480-Fix-headphone-jack.patch new file mode 100644 index 00000000..92e18e57 --- /dev/null +++ b/config/coreboot/default/patches/0044-mb-lenovo-t480-Fix-headphone-jack.patch @@ -0,0 +1,83 @@ +From 5d463e5e0c33f1788d329ba07ebc20dad552c49e Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 13 Nov 2025 15:45:46 +0100 +Subject: [PATCH] mb/lenovo/t480: Fix headphone jack + +Add additional register configuration for the Realtek ALC257 audio +codec on the Lenovo ThinkPad T480. This includes: + +- Hidden register SW reset sequence +- ClassD 2W amplifier configuration +- Jack detection (JD1) setup for headphone port +- Silence data mode threshold setting at -84dB + +Shamelessly taken from google/brya/variants/pujjolo/hda_verb.c + +Change-Id: Ib77138d782ceb9feeaef82935bc1c0d5c3066183 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +Reviewed-on: https://review.coreboot.org/c/coreboot/+/90023 +Tested-by: build bot (Jenkins) <no-reply@coreboot.org> +Reviewed-by: Paul Menzel <paulepanter@mailbox.org> +Reviewed-by: Elyes Haouas <ehaouas@noos.fr> +--- + .../sklkbl_thinkpad/variants/t480/hda_verb.c | 37 ++++++++++++++++++- + 1 file changed, 36 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c +index 3a951ce0da..fc8cac8680 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c +@@ -5,7 +5,7 @@ + const u32 cim_verb_data[] = { + 0x10ec0257, // Vendor/Device ID: Realtek ALC257 + 0x17aa225d, // Subsystem ID +- 11, ++ 18, + AZALIA_SUBVENDOR(0, 0x17aa225d), + + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( +@@ -51,6 +51,41 @@ const u32 cim_verb_data[] = { + 1, 15 + )), + ++ //==========Widget node 0x20 - 0 :Hidden register SW reset ++ 0x0205001A, ++ 0x0204C003, ++ 0x0205001A, ++ 0x0204C003, ++ 0x05850000, ++ 0x0584F880, ++ 0x05850000, ++ 0x0584F880, ++ //==========Widget node 0x20 - 1 : ClassD 2W ++ 0x02050038, ++ 0x02048981, ++ 0x0205001B, ++ 0x02040A4B, ++ //==========Widget node 0x20 - 2 ++ 0x0205003C, ++ 0x02043154, ++ 0x0205003C, ++ 0x02043114, ++ //==========Widget node 0x20 - 3 : ++ 0x02050046, ++ 0x02040004, ++ 0x05750003, ++ 0x057409A3, ++ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD ++ 0x02050009, ++ 0x02046003, ++ 0x0205000A, ++ 0x02047770, ++ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) ++ 0x02050037, ++ 0x0204FE15, ++ 0x02050030, ++ 0x02049004, ++ + 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI + 0x80860101, // Subsystem ID + 4, +-- +2.52.0 + diff --git a/config/coreboot/default/patches/0045-mb-lenovo-t480s-Fix-headphone-jack.patch b/config/coreboot/default/patches/0045-mb-lenovo-t480s-Fix-headphone-jack.patch new file mode 100644 index 00000000..aa75f0ad --- /dev/null +++ b/config/coreboot/default/patches/0045-mb-lenovo-t480s-Fix-headphone-jack.patch @@ -0,0 +1,82 @@ +From 8a9e9a2c66e90f916c891a80ffe2db0767bd0ae8 Mon Sep 17 00:00:00 2001 +From: Matt DeVillier <matt.devillier@gmail.com> +Date: Wed, 10 Dec 2025 11:02:30 -0600 +Subject: [PATCH 1/1] mb/lenovo/t480s: Fix headphone jack + +Add additional register configuration for the Realtek ALC257 audio +codec on the Lenovo ThinkPad T480s. This includes: + +- Hidden register SW reset sequence +- ClassD 2W amplifier configuration +- Jack detection (JD1) setup for headphone port +- Silence data mode threshold setting at -84dB + +Copied from the T480, originally sourced from +mb/google/brya/variants/pujjolo/hda_verb.c + +Addresses issue #619 + +Change-Id: I0ddea39b40566d6966e89c77352c0904b3c60da9 +Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> +--- + .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 37 ++++++++++++++++++- + 1 file changed, 36 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c +index b1d96c5a76..9eb9287f9b 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c +@@ -5,7 +5,7 @@ + const u32 cim_verb_data[] = { + 0x10ec0257, // Vendor/Device ID: Realtek ALC257 + 0x17aa2258, // Subsystem ID +- 11, ++ 18, + AZALIA_SUBVENDOR(0, 0x17aa2258), + + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( +@@ -51,6 +51,41 @@ const u32 cim_verb_data[] = { + 1, 15 + )), + ++ //==========Widget node 0x20 - 0 :Hidden register SW reset ++ 0x0205001A, ++ 0x0204C003, ++ 0x0205001A, ++ 0x0204C003, ++ 0x05850000, ++ 0x0584F880, ++ 0x05850000, ++ 0x0584F880, ++ //==========Widget node 0x20 - 1 : ClassD 2W ++ 0x02050038, ++ 0x02048981, ++ 0x0205001B, ++ 0x02040A4B, ++ //==========Widget node 0x20 - 2 ++ 0x0205003C, ++ 0x02043154, ++ 0x0205003C, ++ 0x02043114, ++ //==========Widget node 0x20 - 3 : ++ 0x02050046, ++ 0x02040004, ++ 0x05750003, ++ 0x057409A3, ++ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD ++ 0x02050009, ++ 0x02046003, ++ 0x0205000A, ++ 0x02047770, ++ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) ++ 0x02050037, ++ 0x0204FE15, ++ 0x02050030, ++ 0x02049004, ++ + 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI + 0x80860101, // Subsystem ID + 4, +-- +2.47.3 + |