diff options
Diffstat (limited to 'config/coreboot/default/patches')
52 files changed, 1076 insertions, 626 deletions
diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index 3a050d3b..b654b32c 100644 --- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From 4e350ac1b7d5f27ae0887bb016d748b0987ad14d Mon Sep 17 00:00:00 2001 +From 03e8f5f33723fd291e30c5305fa2f5eb22bdf656 Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 01/41] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/48] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch index 228eb57d..20fff9eb 100644 --- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 0322228c25be7d95e7dbcc905dec81960905152b Mon Sep 17 00:00:00 2001 +From da742084f51bb7e97472605d6eff0726fd7a5863 Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 02/41] lenovo/t400: Enable all SATA ports +Subject: [PATCH 02/48] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index ec891ccf..8e814be3 100644 --- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From 4714f4388bf90fc7ff3d25dd62feec07de5f4c7e Mon Sep 17 00:00:00 2001 +From 278c2a989c025c1b3a097966968c8d253c973a3e Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 03/41] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 03/48] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch index e55f8847..43830448 100644 --- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From 0d8c12b68060ebfe4df4cf0d7cb1abd4c2b2243b Mon Sep 17 00:00:00 2001 +From 63357b7f8c9da3a8d644542c70f50fc9bc77a8fc Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 04/41] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 04/48] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default diff --git a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 1a300e11..8490157a 100644 --- a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From a3bc9753261ebd534df6c6752169b3edbb588a97 Mon Sep 17 00:00:00 2001 +From 434136e0aca4839e449e3841a5e993688b4586f0 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 05/41] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 05/48] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). @@ -20,7 +20,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 84 insertions(+), 32 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 75238c73b2..ea8dfc788d 100644 +index 0592785bf6..cab934c3a5 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -2240,6 +2240,7 @@ static void print_usage(const char *name) diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index bcf15cf0..725c6380 100644 --- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From c3f93c58ddeb1e44daf76db9d67e33bcd2c54a62 Mon Sep 17 00:00:00 2001 +From 91e4334541da6522d5a0bf5277ac478c891e7117 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 06/41] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 06/48] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch index b27e013f..e583accc 100644 --- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From 9c0234bac4d37670da6831e3ff9545a0c6119237 Mon Sep 17 00:00:00 2001 +From 3ebe9e03ec563e5adb43337340fe973aa66a984a Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 07/41] Remove warning for coreboot images built without a +Subject: [PATCH 07/48] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch index e392d1f7..a450cb4e 100644 --- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From 495eab54f7c2224a0ad3da3dc79905182eca6eee Mon Sep 17 00:00:00 2001 +From 0e2fa472354b2e68ffbfc01d5bb225ca9d8973f0 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 08/41] HACK: Disable coreboot related BL31 features +Subject: [PATCH 08/48] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. @@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation. 1 file changed, 3 deletions(-) diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk -index 279d31fb47..3d436179fe 100644 +index efd628fee7..6c4f3d702e 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk -@@ -162,9 +162,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 +@@ -156,9 +156,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 # Always enable crash reporting, even on a release build BL31_MAKEARGS += CRASH_REPORTING=1 diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch index f71badef..d67bdf03 100644 --- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From bf464f17367c0dfa7f2c667d699800f3c6e60040 Mon Sep 17 00:00:00 2001 +From f692cd96a4484b8e60bd112454d1bdbc3c689017 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 09/41] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 09/48] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. diff --git a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index a03102e0..e01800af 100644 --- a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From 5c27543224963e7fa17ad18dea27d186685e9f13 Mon Sep 17 00:00:00 2001 +From 78db6c595ff816ad4344d541688605ae720a83c4 Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 10/41] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 10/48] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. diff --git a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index abd27757..235ee880 100644 --- a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From 062b28da685d1c9f7cbe8333e98257a83ce4ca82 Mon Sep 17 00:00:00 2001 +From beb9b1650fb3aec96544b683fbe53ee16584f3d8 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 11/41] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 11/48] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless diff --git a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch index efe5f358..3e6b8085 100644 --- a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From 5bd5bc755af744b51e0577970dc6f5214bd0cfee Mon Sep 17 00:00:00 2001 +From 0f76a919522c9624c2b5df2a9c17525ab21bd6b9 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 12/41] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 12/48] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off diff --git a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index 84d83c77..56b61882 100644 --- a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From 78da1e003a69a4cc6bd5e71e4bc43a4844d05f16 Mon Sep 17 00:00:00 2001 +From df64f2825157226b98e002e746114e25b0047438 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 13/41] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 13/48] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I diff --git a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index 1340effa..722e895d 100644 --- a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,7 +1,7 @@ -From 0a982ec4b606b6c236f71478350b69f532f30719 Mon Sep 17 00:00:00 2001 +From fdf4774a6e80b1f94079abb346049113dfbf5241 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 14/41] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 14/48] ec/dell/mec5035: Add S3 suspend SMI handler This is necessary for S3 resume to work on SNB and newer Dell Latitude laptops. If a command isn't sent, the EC cuts power to the DIMMs, diff --git a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index 47b32744..ac672295 100644 --- a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From 9ca5c919339049518e842980041f528d48d79124 Mon Sep 17 00:00:00 2001 +From 18216387e5c40ec3c80c63ec25e9b0c55a009cff Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 15/41] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 15/48] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch index 84f3899e..e7c8d0a9 100644 --- a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From e74c4ee6a62ef9f91a8efb257658f627498b91fa Mon Sep 17 00:00:00 2001 +From d797b9d19c6bc3224897000756caef29e98dd266 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 16/41] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 16/48] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch index 87894700..51ba3ae7 100644 --- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -1,7 +1,7 @@ -From da433a5d9a7d1d7856b55761b8392864343de5a8 Mon Sep 17 00:00:00 2001 +From e573065ac900d4decfd4dbd0a1464d82501ac3c5 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 17/41] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards +Subject: [PATCH 17/48] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards We add this patch: diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index 4b67f8c0..fdb225e8 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From b4443cfe4b63a49b8170bdfb6dacbc8d52110eff Mon Sep 17 00:00:00 2001 +From 130a5ca25fbedb58e49b613e4a7cece715b545ae Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 18/41] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 18/48] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch index 061731e3..b7af55b4 100644 --- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -1,7 +1,7 @@ -From d3d97fccab40cfe50eac92796bb7f16bd245b189 Mon Sep 17 00:00:00 2001 +From 7641a4b9b91c385223026cd566e0ffc2a2aa0d8f Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 19/41] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ +Subject: [PATCH 19/48] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ set it to 96MHz. fixes the following build error when building for x4x boards e.g. gigabyte ga-g41m-es2l: diff --git a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch index b5247da2..c9603f71 100644 --- a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -1,7 +1,7 @@ -From c2a05f102ca378d8e23f0485d680845584efa290 Mon Sep 17 00:00:00 2001 +From 36126c093a9b9e01d41f0a68977cd09070c3c276 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 20/41] mb/dell/gm45_latitudes: Add E4300 variant +Subject: [PATCH 20/48] mb/dell/gm45_latitudes: Add E4300 variant Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch index 4db5b691..238e4799 100644 --- a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -1,7 +1,7 @@ -From 2305cfb93110003613caa1dec8c5f574b5e400bd Mon Sep 17 00:00:00 2001 +From 4caca6e6e349fa1913df622081025ea53bfd136f Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 21/41] mb/dell: Add S3 SMI handler for Dell Latitudes +Subject: [PATCH 21/48] mb/dell: Add S3 SMI handler for Dell Latitudes Integrate the previously added mec5035_smi_sleep() function into mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. diff --git a/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch index 766b51a3..deaefbfd 100644 --- a/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch +++ b/config/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch @@ -1,7 +1,7 @@ -From aafddebf91f185d9c72fa1492af9128ee4803239 Mon Sep 17 00:00:00 2001 +From 669ef0d2c72326134f64a4fe70f67220ec690c5e Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 22/41] Disable compression on refcode insertion +Subject: [PATCH 22/48] Disable compression on refcode insertion Compression is not reliably reproducible. In an lbmk release context, this means we cannot rely on vendorfile insertion. @@ -14,10 +14,10 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.mk b/Makefile.mk -index 75787b32d4..3616f4fe68 100644 +index 5fccb4a52d..c40e06c453 100644 --- a/Makefile.mk +++ b/Makefile.mk -@@ -1422,7 +1422,7 @@ endif +@@ -1414,7 +1414,7 @@ endif cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) $(CONFIG_CBFS_PREFIX)/refcode-type := stage diff --git a/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch index 8746df0d..3bb55c37 100644 --- a/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch +++ b/config/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch @@ -1,7 +1,7 @@ -From 09febfb85eb176c8bf0e416412ed0b971dc2cefc Mon Sep 17 00:00:00 2001 +From c7b136f1f4fa2bc1a783711b5a1ee82c5d9ce69f Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 23/41] nb/intel/*: Disable stack overflow debug options +Subject: [PATCH 23/48] nb/intel/*: Disable stack overflow debug options Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch index 4fa676fc..22061393 100644 --- a/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ b/config/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -1,7 +1,7 @@ -From 70f588b7cc66af2e427d9045d36ac2f5f4835dae Mon Sep 17 00:00:00 2001 +From c15a0ef9b964e9df9a5578ed271af4f1c0419f38 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 24/41] mb/dell: Add Optiplex 780 MT (x4x/ICH10) +Subject: [PATCH 24/48] mb/dell: Add Optiplex 780 MT (x4x/ICH10) Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch index f5a9ce7e..c126ee58 100644 --- a/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch +++ b/config/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -1,7 +1,7 @@ -From 463148c9773f3dd44f60c2cf2ac17900c3e68619 Mon Sep 17 00:00:00 2001 +From bfd5f6628a69d8704a84b30c4027149fe1b21efa Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 25/41] mb/dell/optiplex_780: Add USFF variant +Subject: [PATCH 25/48] mb/dell/optiplex_780: Add USFF variant Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch index 9769c7e9..4c693f65 100644 --- a/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch +++ b/config/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -1,7 +1,7 @@ -From bf3c3df864cae045c82d1c032ced834a60239401 Mon Sep 17 00:00:00 2001 +From 82f47133c20abc720f5d5fa8a54be465ebd95f28 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:53:53 +0000 -Subject: [PATCH 26/41] src/intel/x4x: Disable stack overflow debug +Subject: [PATCH 26/48] src/intel/x4x: Disable stack overflow debug Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch index d91857a9..da5ae94d 100644 --- a/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch +++ b/config/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -1,7 +1,7 @@ -From 0ad074869ec2a25508b1d6fc97c6ce61a9982fbd Mon Sep 17 00:00:00 2001 +From 5c4439fb513c315ef3effff19146b331c492fa9b Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 22 Apr 2025 10:21:59 +0100 -Subject: [PATCH 27/41] hp/8300cmt: remove xhci_overcurrent_mapping +Subject: [PATCH 27/48] hp/8300cmt: remove xhci_overcurrent_mapping No longer needed, as per the following commit: diff --git a/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch index b634e107..52b49b36 100644 --- a/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch +++ b/config/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch @@ -1,7 +1,7 @@ -From 4739f197ee3d4c95809ba48671bc5c409766b9c7 Mon Sep 17 00:00:00 2001 +From 71ec1f7a6480e72b77a567f8cc0c2673a5e7905f Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 11 Dec 2024 01:06:01 +0000 -Subject: [PATCH 28/41] dell/3050micro: disable nvme hotplug +Subject: [PATCH 28/48] dell/3050micro: disable nvme hotplug in my testing, when running my 3050micro for a few days, the nvme would sometimes randomly rename. diff --git a/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch index f3864a23..78ccf785 100644 --- a/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ b/config/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -1,7 +1,7 @@ -From a6fdf61bb4779775fa330fc3f9b79be651c6854a Mon Sep 17 00:00:00 2001 +From 95a0af0eea56e1bddcb243ed135835448b90fa56 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 29/41] src/intel/skylake: Disable stack overflow debug options +Subject: [PATCH 29/48] src/intel/skylake: Disable stack overflow debug options The option was appearing in T480/3050micro configs of lbmk, after updating on the coreboot/next uprev for 20241206 rev8: diff --git a/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch index b886e90e..e5f4987b 100644 --- a/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch +++ b/config/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From 287a6d09ac6f5cdfc8255c2020e37441ddb870c7 Mon Sep 17 00:00:00 2001 +From 7d94457ba0e2be10d781c5fd0659d895c9b558b1 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Thu, 26 Dec 2024 19:45:20 +0000 -Subject: [PATCH 30/41] soc/intel/skylake: Don't compress FSP-S +Subject: [PATCH 30/48] soc/intel/skylake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. diff --git a/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch index bf878964..d1d47338 100644 --- a/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch +++ b/config/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -1,7 +1,7 @@ -From c0bb0e62f169e07ab11c434fbd79a6a26b4e7690 Mon Sep 17 00:00:00 2001 +From 8768e53f3b2ceb00ec0c8abf0fc0af03993820b1 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 18 Dec 2024 02:06:18 +0000 -Subject: [PATCH 31/41] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN +Subject: [PATCH 31/48] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN This is used by lbmk to know where a tb.bin file goes, when extracting and padding TBT.bin from Lenovo ThunderBolt diff --git a/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch index ec1bce88..6ed150e7 100644 --- a/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch +++ b/config/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch @@ -1,7 +1,7 @@ -From c25cf16fb0d278354c7e2c19f534a04e27ac46dd Mon Sep 17 00:00:00 2001 +From 579c60fd77517497eb18dfeca8d73cdca94c15da Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 05:14:45 +0100 -Subject: [PATCH 32/41] Conditional TBFW setting for kabylake thinkpads +Subject: [PATCH 32/48] Conditional TBFW setting for kabylake thinkpads Otherwise, other boards will define it, which might trigger the vendor download script, and diff --git a/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch index fa279613..64f257e4 100644 --- a/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch +++ b/config/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch @@ -1,7 +1,7 @@ -From 2c3a31547a14eb1b1145a5d153289b2eef6d71d8 Mon Sep 17 00:00:00 2001 +From 23d8a97ff213f744b4e6333d92fc90e9ea97e879 Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 27 Sep 2025 23:30:46 +0300 -Subject: [PATCH 33/41] soc/intel/alderlake: Disable +Subject: [PATCH 33/48] soc/intel/alderlake: Disable MRC_CACHE_USING_MRC_VERSION There's some issue with building against the FSP headers in src/vendorcode. @@ -14,7 +14,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 97c2ecca70..a2074fe05a 100644 +index 34c9baf544..e0ab6b10fd 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE diff --git a/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch index f02f2f71..bb6e39c0 100644 --- a/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch +++ b/config/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch @@ -1,7 +1,7 @@ -From 8eeb1de057b19938f1221b85e00699c58de90069 Mon Sep 17 00:00:00 2001 +From e2e070ab1f080c0ae59c43131faa57f3499fd813 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 28 Sep 2025 03:17:50 +0100 -Subject: [PATCH 34/41] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) +Subject: [PATCH 34/48] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) if you pass -k (keep fptr modules), don't use -r, don't use -t, you can essentially just use me_cleaner to diff --git a/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch index e9b35cc7..2292605e 100644 --- a/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch +++ b/config/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From be79f8b72a098dcd51639210935ba02d2f5ff808 Mon Sep 17 00:00:00 2001 +From fee89a6c872ec26c2ea128ecdce62d6c3abe53f1 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 4 Oct 2025 21:57:43 +0100 -Subject: [PATCH 35/41] soc/intel/alderlake: Don't compress FSP-S +Subject: [PATCH 35/48] soc/intel/alderlake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. @@ -18,7 +18,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index a2074fe05a..08137d2706 100644 +index e0ab6b10fd..a2e7cff6f6 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE diff --git a/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch index 638620a9..a4f9068d 100644 --- a/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch +++ b/config/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch @@ -1,7 +1,7 @@ -From 226df168b34467ca8555e953b6d793f273c0b82c Mon Sep 17 00:00:00 2001 +From abd26006eff71c9570bc90fdbce3a76f8f559cea Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 4 Oct 2025 22:20:11 +0100 -Subject: [PATCH 36/41] alderlake: don't require full fsp repo for fd path +Subject: [PATCH 36/48] alderlake: don't require full fsp repo for fd path Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 08137d2706..67e47c2e36 100644 +index a2e7cff6f6..3402c1e3d5 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig -@@ -417,7 +417,14 @@ config FSP_HEADER_PATH +@@ -430,7 +430,14 @@ config FSP_HEADER_PATH config FSP_FD_PATH string diff --git a/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch index 4f296fbd..d740f7a7 100644 --- a/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch +++ b/config/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch @@ -1,7 +1,7 @@ -From 30366be45e5b7521b93475f68c7143bd683b25f3 Mon Sep 17 00:00:00 2001 +From 6a4a79d82df982c2fca859101040e407623f519c Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Oct 2025 04:47:06 +0100 -Subject: [PATCH 37/41] soc/alderlake: disable stack overflow debug option +Subject: [PATCH 37/48] soc/alderlake: disable stack overflow debug option same as on other boards. based on this commit: @@ -22,7 +22,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 67e47c2e36..e9c56fc6b9 100644 +index 3402c1e3d5..06b9199e84 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -331,6 +331,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ diff --git a/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch index cd6d5f02..dd5412a2 100644 --- a/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch +++ b/config/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch @@ -1,7 +1,7 @@ -From 90332fe96aca0de4d99d58d1593048c77e1bdecf Mon Sep 17 00:00:00 2001 +From bb286d13cb7702e9396deab04023cc58dcc01a15 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 11 May 2025 15:41:22 -0600 -Subject: [PATCH 38/41] ec/dell/mec5035: Add command to disable EC-initiated +Subject: [PATCH 38/48] ec/dell/mec5035: Add command to disable EC-initiated thermal shutdown If command 0xBF isn't sent, the EC shuts down the system without warning diff --git a/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch index ccf93fd7..1814806f 100644 --- a/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch +++ b/config/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch @@ -1,7 +1,7 @@ -From 68048f4afe369ece02143f9a4a7da2104ff2d10b Mon Sep 17 00:00:00 2001 +From a93c01173c2f88b4a09286740c030314040c39fc Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 11 May 2025 16:28:23 -0600 -Subject: [PATCH 39/41] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown +Subject: [PATCH 39/48] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown at 87 degrees If command 0xBF isn't sent, the EC will shut down the system without diff --git a/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch b/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch deleted file mode 100644 index 9fe5d3da..00000000 --- a/config/coreboot/default/patches/0040-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch +++ /dev/null @@ -1,358 +0,0 @@ -From 0792e39c1684216860b228e6c0935066be1a21b6 Mon Sep 17 00:00:00 2001 -From: Jeremy Soller <jeremy@system76.com> -Date: Fri, 31 May 2024 13:58:00 -0600 -Subject: [PATCH 40/41] drivers/intel/dtbt: Add discrete Thunderbolt driver - -Add a new driver which enables basic TBT support for the Alpine Ridge, -Titan Ridge, and Maple Ridge discrete Thunderbolt controllers. - -This driver will initially be used on the Lenovo T480/T480s and -System76 RPL-HX platform boards. It currently only supports a single -dTBT controller. - -Ref: edk2-platforms KabylakeOpenBoardPkg reference implementation -Ref: Titan Ridge BIOS Implementation Guide v1.4 -Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472) - -Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 -Signed-off-by: Jeremy Soller <jeremy@system76.com> -Signed-off-by: Tim Crawford <tcrawford@system76.com> -Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> ---- - src/drivers/intel/dtbt/Kconfig | 6 + - src/drivers/intel/dtbt/Makefile.mk | 3 + - src/drivers/intel/dtbt/chip.h | 8 ++ - src/drivers/intel/dtbt/dtbt.c | 202 +++++++++++++++++++++++++++++ - src/drivers/intel/dtbt/dtbt.h | 73 +++++++++++ - 5 files changed, 292 insertions(+) - create mode 100644 src/drivers/intel/dtbt/Kconfig - create mode 100644 src/drivers/intel/dtbt/Makefile.mk - create mode 100644 src/drivers/intel/dtbt/chip.h - create mode 100644 src/drivers/intel/dtbt/dtbt.c - create mode 100644 src/drivers/intel/dtbt/dtbt.h - -diff --git a/src/drivers/intel/dtbt/Kconfig b/src/drivers/intel/dtbt/Kconfig -new file mode 100644 -index 0000000000..d895dbd288 ---- /dev/null -+++ b/src/drivers/intel/dtbt/Kconfig -@@ -0,0 +1,6 @@ -+config DRIVERS_INTEL_DTBT -+ def_bool n -+ help -+ Support for discrete Thunderbolt controllers. -+ Currently only supports a single dTBT controller from the -+ Alpine Ridge, Titan Ridge, and Maple Ridge families. -diff --git a/src/drivers/intel/dtbt/Makefile.mk b/src/drivers/intel/dtbt/Makefile.mk -new file mode 100644 -index 0000000000..1b5252dda0 ---- /dev/null -+++ b/src/drivers/intel/dtbt/Makefile.mk -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c -diff --git a/src/drivers/intel/dtbt/chip.h b/src/drivers/intel/dtbt/chip.h -new file mode 100644 -index 0000000000..2b1dfa70a5 ---- /dev/null -+++ b/src/drivers/intel/dtbt/chip.h -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_ -+#define _DRIVERS_INTEL_DTBT_CHIP_H_ -+ -+struct drivers_intel_dtbt_config {}; -+ -+#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */ -diff --git a/src/drivers/intel/dtbt/dtbt.c b/src/drivers/intel/dtbt/dtbt.c -new file mode 100644 -index 0000000000..8613eee5e0 ---- /dev/null -+++ b/src/drivers/intel/dtbt/dtbt.c -@@ -0,0 +1,202 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpigen.h> -+#include <console/console.h> -+#include <delay.h> -+#include <device/device.h> -+#include <device/pci.h> -+#include <device/pciexp.h> -+#include <device/pci_ids.h> -+#include <timer.h> -+#include "chip.h" -+#include "dtbt.h" -+ -+ -+/* -+ * We only want to enable the first/primary bridge device, -+ * as sending mailbox commands to secondary ones will fail, -+ * and we only want to create a single ACPI device in the SSDT. -+ */ -+static bool enable_done; -+static bool ssdt_done; -+ -+static void dtbt_cmd(struct device *dev, u32 command, u32 data, u32 timeout) -+{ -+ u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID; -+ u32 status; -+ -+ printk(BIOS_SPEW, "dTBT send command 0x%x\n", command); -+ /* Send command */ -+ pci_write_config32(dev, PCIE2TBT, reg); -+ /* Wait for done bit to be cleared */ -+ if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) -+ printk(BIOS_ERR, "dTBT command 0x%x send timeout, status 0x%x\n", command, status); -+ /* Clear valid bit */ -+ pci_write_config32(dev, PCIE2TBT, 0); -+ /* Wait for done bit to be cleared */ -+ if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) -+ printk(BIOS_ERR, "dTBT command 0x%x clear valid bit timeout, status 0x%x\n", command, status); -+} -+ -+static void dtbt_write_dsd(void) -+{ -+ struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); -+ -+ acpi_device_add_hotplug_support_in_d3(dsd); -+ acpi_device_add_external_facing_port(dsd); -+ acpi_dp_write(dsd); -+} -+ -+static void dtbt_write_opregion(const struct bus *bus) -+{ -+ uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS -+ + (((uintptr_t)(bus->secondary)) << 20); -+ const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000); -+ const struct fieldlist fieldlist[] = { -+ FIELDLIST_OFFSET(TBT2PCIE), -+ FIELDLIST_NAMESTR("TB2P", 32), -+ FIELDLIST_OFFSET(PCIE2TBT), -+ FIELDLIST_NAMESTR("P2TB", 32), -+ }; -+ -+ acpigen_write_opregion(&opregion); -+ acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), -+ FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); -+} -+ -+static void dtbt_fill_ssdt(const struct device *dev) -+{ -+ struct bus *bus; -+ struct device *parent; -+ const char *parent_scope; -+ const char *dev_name = acpi_device_name(dev); -+ -+ if (ssdt_done) -+ return; -+ -+ bus = dev->upstream; -+ if (!bus) { -+ printk(BIOS_ERR, "dTBT bus invalid\n"); -+ return; -+ } -+ -+ parent = bus->dev; -+ if (!parent || !is_pci(parent)) { -+ printk(BIOS_ERR, "dTBT parent invalid\n"); -+ return; -+ } -+ -+ parent_scope = acpi_device_path(parent); -+ if (!parent_scope) { -+ printk(BIOS_ERR, "dTBT parent scope not valid\n"); -+ return; -+ } -+ -+ /* Scope */ -+ acpigen_write_scope(parent_scope); -+ dtbt_write_dsd(); -+ -+ /* Device */ -+ acpigen_write_device(dev_name); -+ acpigen_write_name_integer("_ADR", 0); -+ dtbt_write_opregion(bus); -+ -+ /* PTS Method */ -+ acpigen_write_method_serialized("PTS", 0); -+ -+ acpigen_write_debug_string("dTBT prepare to sleep"); -+ acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB"); -+ acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1); -+ -+ acpigen_write_debug_namestr("TB2P"); -+ acpigen_write_store_int_to_namestr(0, "P2TB"); -+ acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0); -+ acpigen_write_debug_namestr("TB2P"); -+ -+ acpigen_write_method_end(); -+ acpigen_write_device_end(); -+ acpigen_write_scope_end(); -+ -+ // \.TBTS Method -+ acpigen_write_scope("\\"); -+ acpigen_write_method("TBTS", 0); -+ acpigen_emit_namestring(acpi_device_path_join(dev, "PTS")); -+ acpigen_write_method_end(); -+ acpigen_write_scope_end(); -+ -+ printk(BIOS_INFO, "%s.%s %s\n", parent_scope, dev_name, dev_path(dev)); -+ ssdt_done = true; -+} -+ -+static const char *dtbt_acpi_name(const struct device *dev) -+{ -+ return "DTBT"; -+} -+ -+static void dtbt_enable(struct device *dev) -+{ -+ if (!is_dev_enabled(dev) || enable_done) -+ return; -+ -+ printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev)); -+ -+ // XXX: Recommendation is to set SL1 ("User Authorization") -+ printk(BIOS_DEBUG, "dTBT set security level SL0\n"); -+ /* Set security level */ -+ dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, SEC_LEVEL_NONE, MBOX_TIMEOUT_MS); -+ -+ if (acpi_is_wakeup_s3()) { -+ printk(BIOS_DEBUG, "dTBT SX exit\n"); -+ dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, MBOX_TIMEOUT_MS); -+ /* Read TBT2PCIE register, verify not invalid */ -+ if (pci_read_config32(dev, TBT2PCIE) == 0xffffffff) -+ printk(BIOS_ERR, "dTBT S3 resume failure.\n"); -+ } else { -+ printk(BIOS_DEBUG, "dTBT set boot on\n"); -+ dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, MBOX_TIMEOUT_MS); -+ printk(BIOS_DEBUG, "dTBT set USB on\n"); -+ dtbt_cmd(dev, PCIE2TBT_USB_ON, 0, MBOX_TIMEOUT_MS); -+ } -+ enable_done = true; -+} -+ -+static struct pci_operations dtbt_device_ops_pci = { -+ .set_subsystem = 0, -+}; -+ -+static struct device_operations dtbt_device_ops = { -+ .read_resources = pci_bus_read_resources, -+ .set_resources = pci_dev_set_resources, -+ .enable_resources = pci_bus_enable_resources, -+ .acpi_fill_ssdt = dtbt_fill_ssdt, -+ .acpi_name = dtbt_acpi_name, -+ .scan_bus = pciexp_scan_bridge, -+ .reset_bus = pci_bus_reset, -+ .ops_pci = &dtbt_device_ops_pci, -+ .enable = dtbt_enable -+}; -+ -+/* We only want to match the (first) bridge device */ -+static const unsigned short pci_device_ids[] = { -+ AR_2C_BRG, -+ AR_4C_BRG, -+ AR_LP_BRG, -+ AR_4C_C0_BRG, -+ AR_2C_C0_BRG, -+ TR_2C_BRG, -+ TR_4C_BRG, -+ TR_DD_BRG, -+ MR_2C_BRG, -+ MR_4C_BRG, -+ 0 -+}; -+ -+static const struct pci_driver intel_dtbt_driver __pci_driver = { -+ .ops = &dtbt_device_ops, -+ .vendor = PCI_VID_INTEL, -+ .devices = pci_device_ids, -+}; -+ -+struct chip_operations drivers_intel_dtbt_ops = { -+ .name = "Intel Discrete Thunderbolt", -+}; -diff --git a/src/drivers/intel/dtbt/dtbt.h b/src/drivers/intel/dtbt/dtbt.h -new file mode 100644 -index 0000000000..d01d3a35ef ---- /dev/null -+++ b/src/drivers/intel/dtbt/dtbt.h -@@ -0,0 +1,73 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _DRIVERS_INTEL_DTBT_H_ -+#define _DRIVERS_INTEL_DTBT_H_ -+ -+/* Alpine Ridge device IDs */ -+#define AR_2C_NHI 0x1575 -+#define AR_2C_BRG 0x1576 -+#define AR_2C_USB 0x15B5 -+#define AR_4C_NHI 0x1577 -+#define AR_4C_BRG 0x1578 -+#define AR_4C_USB 0x15B6 -+#define AR_LP_NHI 0x15BF -+#define AR_LP_BRG 0x15C0 -+#define AR_LP_USB 0x15C1 -+#define AR_4C_C0_NHI 0x15D2 -+#define AR_4C_C0_BRG 0x15D3 -+#define AR_4C_C0_USB 0x15D4 -+#define AR_2C_C0_NHI 0x15D9 -+#define AR_2C_C0_BRG 0x15DA -+#define AR_2C_C0_USB 0x15DB -+ -+/* Titan Ridge device IDs */ -+#define TR_2C_BRG 0x15E7 -+#define TR_2C_NHI 0x15E8 -+#define TR_2C_USB 0x15E9 -+#define TR_4C_BRG 0x15EA -+#define TR_4C_NHI 0x15EB -+#define TR_4C_USB 0x15EC -+#define TR_DD_BRG 0x15EF -+#define TR_DD_USB 0x15F0 -+ -+/* Maple Ridge device IDs */ -+#define MR_2C_BRG 0x1133 -+#define MR_2C_NHI 0x1134 -+#define MR_2C_USB 0x1135 -+#define MR_4C_BRG 0x1136 -+#define MR_4C_NHI 0x1137 -+#define MR_4C_USB 0x1138 -+ -+/* Security Levels */ -+#define SEC_LEVEL_NONE 0 -+#define SEC_LEVEL_USER 1 -+#define SEC_LEVEL_AUTH 2 -+#define SEC_LEVEL_DP_ONLY 3 -+ -+#define PCIE2TBT 0x54C -+#define PCIE2TBT_VALID BIT(0) -+#define PCIE2TBT_GO2SX 2 -+#define PCIE2TBT_GO2SX_NO_WAKE 3 -+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED 4 -+#define PCIE2TBT_OS_UP 6 -+#define PCIE2TBT_SET_SECURITY_LEVEL 8 -+#define PCIE2TBT_GET_SECURITY_LEVEL 9 -+#define PCIE2TBT_BOOT_ON 24 -+#define PCIE2TBT_USB_ON 25 -+#define PCIE2TBT_GET_ENUMERATION_METHOD 26 -+#define PCIE2TBT_SET_ENUMERATION_METHOD 27 -+#define PCIE2TBT_POWER_CYCLE 28 -+#define PCIE2TBT_SX_START 29 -+#define PCIE2TBT_ACL_BOOT 30 -+#define PCIE2TBT_CONNECT_TOPOLOGY 31 -+ -+#define TBT2PCIE 0x548 -+#define TBT2PCIE_DONE BIT(0) -+ -+// Timeout for mailbox commands unless otherwise specified. -+#define MBOX_TIMEOUT_MS 5000 -+ -+// Timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command. -+#define GO2SX_TIMEOUT_MS 600 -+ -+#endif /* _DRIVERS_INTEL_DTBT_H_ */ --- -2.47.3 - diff --git a/config/coreboot/default/patches/0042-fix-ifdtool-build.patch b/config/coreboot/default/patches/0040-fix-ifdtool-build.patch index 863ba121..b39fbc0b 100644 --- a/config/coreboot/default/patches/0042-fix-ifdtool-build.patch +++ b/config/coreboot/default/patches/0040-fix-ifdtool-build.patch @@ -1,7 +1,7 @@ -From 6e084398d4e6847b0f64325dadd4cfee0b43d7ea Mon Sep 17 00:00:00 2001 +From dc4036353483c5fc0c140fc269d9bddb0bb7a967 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 20 Dec 2025 20:12:48 +0100 -Subject: [PATCH 1/1] fix ifdtool build +Subject: [PATCH 40/48] fix ifdtool build not my mistake. someone messed up. @@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index ea8dfc788d..33f00436bc 100644 +index cab934c3a5..d181888e0f 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -2598,7 +2598,7 @@ int main(int argc, char *argv[]) diff --git a/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch b/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch deleted file mode 100644 index 77edba57..00000000 --- a/config/coreboot/default/patches/0041-mb-lenovo-t480-s-Enable-TBT-support.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 890eafaa914317b2a67a4b0df9c3a5ea04d88f05 Mon Sep 17 00:00:00 2001 -From: Matt DeVillier <matt.devillier@gmail.com> -Date: Fri, 18 Jul 2025 14:24:05 -0500 -Subject: [PATCH 41/41] mb/lenovo/t480(s): Enable TBT support - -Select the discrete TBT controller driver, and configure the necessary -GPIOs for the Alpine Ridge TBT controller to be fully functional. -Update the documentation w/r/t TBT functionality. - -TEST=build/boot Lenovo T480, boot Linux, verify all TBT-related PCI -devices populated, lower USB-C port works for USB data and PCIe. - -Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4 -Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> ---- - Documentation/mainboard/lenovo/skylake.md | 3 +-- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 2 ++ - src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c | 8 ++++---- - .../lenovo/sklkbl_thinkpad/variants/t480s/gpio.c | 8 ++++---- - 4 files changed, 11 insertions(+), 10 deletions(-) - -diff --git a/Documentation/mainboard/lenovo/skylake.md b/Documentation/mainboard/lenovo/skylake.md -index 64e075e2cd..352d91b3ef 100644 ---- a/Documentation/mainboard/lenovo/skylake.md -+++ b/Documentation/mainboard/lenovo/skylake.md -@@ -193,8 +193,6 @@ binaries if only flashing the `bios` region. - - ## Known Issues - --- Alpine Ridge Thunderbolt 3 controller does not work -- - Lower (right) USB-C port only works for charging/DP alt mode, not USB/PCIe data - - Some Fn+F{1-12} keys aren't handled correctly - - Nvidia dGPU is finicky - - Needs option ROM -@@ -206,6 +204,7 @@ binaries if only flashing the `bios` region. - - ## Verified Working - -+- Alpine Ridge Thunderbolt 3 controller - - Integrated graphics init with libgfxinit - - video output: internal (eDP), miniDP - - ACPI support -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index d69d94f638..c60b85af08 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -33,6 +33,7 @@ config BOARD_LENOVO_T480 - bool - select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - select SOC_INTEL_KABYLAKE -+ select DRIVERS_INTEL_DTBT - select MEC1653_HAS_DEBUG_UNLOCK - select VARIANT_HAS_DGPU - -@@ -40,6 +41,7 @@ config BOARD_LENOVO_T480S - bool - select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - select SOC_INTEL_KABYLAKE -+ select DRIVERS_INTEL_DTBT - select VARIANT_HAS_DGPU - - config BOARD_LENOVO_T580 -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -index f337843fd9..ffd2841e49 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */ - PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ - -@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_G1, NONE), - PAD_NC(GPP_G2, NONE), - PAD_NC(GPP_G3, NONE), -- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */ - PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ - }; - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -index 4f1c57390d..c24c1abb07 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */ - PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ - -@@ -187,9 +187,9 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_G1, NONE), - PAD_NC(GPP_G2, NONE), - PAD_NC(GPP_G3, NONE), -- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */ - PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ - }; - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0044-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch b/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch index afa6017b..8f61bcd0 100644 --- a/config/coreboot/default/patches/0044-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch +++ b/config/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch @@ -1,7 +1,7 @@ -From ca27517cb5752d078a3f8328ff6b220f652b0849 Mon Sep 17 00:00:00 2001 +From 5b7bbc6fcc6f737f259906f1919c1e28b6628a7e Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 20 Dec 2025 22:36:18 +0100 -Subject: [PATCH 1/1] tests/Makefile.mk: use 3rdparty/cmocka by default +Subject: [PATCH 41/48] tests/Makefile.mk: use 3rdparty/cmocka by default (tests) @@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/Makefile.mk b/tests/Makefile.mk -index f3f122dd38..33bb2a2d07 100644 +index 9e3f86a138..a5a518cd35 100644 --- a/tests/Makefile.mk +++ b/tests/Makefile.mk @@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage diff --git a/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch b/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch new file mode 100644 index 00000000..4ce1241c --- /dev/null +++ b/config/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch @@ -0,0 +1,51 @@ +From ecbf5a133d839b6c8579e384e9db0a036eca939d Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Tue, 23 Dec 2025 18:41:27 +0100 +Subject: [PATCH 42/48] mb/dell/optiplex_780: use legacy HDA verb table + +See: + +commit 31fc5b06a6be62b30739d33eeabe6c2727679bb1 +Author: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> +Date: Thu Aug 7 08:31:24 2025 +0900 + + device: Introduce reworked azalia verb table + +and: + +commit 50a59d4464917503847eeeb2df4320c35cf2f6cc +Author: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> +Date: Mon Sep 15 16:25:21 2025 +0900 + + device: Add Kconfig to prepare for reworked verb table implementation + +Without this change, lbmk gets the following error +when building for Dell OptiPlex 780: + +i386-elf-ld.bfd: build/ramstage/device/azalia_device.o: in function `azalia_codecs_init': +/path/to/corebootclone/src/device/azalia_device.c:318:(.text.azalia_codecs_init+0xa): undefined reference to `mainboard_azalia_codecs' + +This is a temporary fix. Upstream will require that the code +be fully adapted at a future date. Therefore, one could consider +the current functionality to be "deprecated". + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/mainboard/dell/optiplex_780/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +index fc649e35d5..172bb2fa87 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -2,6 +2,7 @@ + + config BOARD_DELL_OPTIPLEX_780_COMMON + def_bool n ++ select AZALIA_USE_LEGACY_VERB_TABLE + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_LGA775 + select DRIVERS_I2C_CK505 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch b/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch new file mode 100644 index 00000000..e5ea4f3c --- /dev/null +++ b/config/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch @@ -0,0 +1,30 @@ +From 962bfe1366598145a93cf6a7ed0f78393e5e9ff7 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Tue, 23 Dec 2025 18:46:45 +0100 +Subject: [PATCH 43/48] hp8300cmt: use legacy verb table + +same as for the 780 optiplex patch + +coreboot is making some changes to the way verbs are +handled. for now, this change is being made to adapt. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/mainboard/hp/compaq_elite_8300_cmt/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig +index d2bfd35dc4..30be7fb3fe 100644 +--- a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig ++++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig +@@ -2,6 +2,7 @@ if BOARD_HP_COMPAQ_ELITE_8300_CMT + + config BOARD_SPECIFIC_OPTIONS + def_bool y ++ select AZALIA_USE_LEGACY_VERB_TABLE + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch b/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch new file mode 100644 index 00000000..ae70996f --- /dev/null +++ b/config/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch @@ -0,0 +1,34 @@ +From 88d29f792de89bb0a138e671432227cb5679b5ae Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Tue, 6 Jan 2026 21:42:21 +0000 +Subject: [PATCH 44/48] topton x2e n150: use old fsp + +i added the old fsp back, so that we didn't have to +mess around with vendor files in lbmk, because coreboot +upstream updated the fsp repo, which modified this +fsp file. + +we know the old fsp worked. there's no point testing +the new one yet, unless someone can tell me about +real bugs that got fixed. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + src/soc/intel/alderlake/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 06b9199e84..f260d10285 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -451,6 +451,7 @@ config FSP_FD_PATH + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S ++ default "3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if BOARD_TOPTON_X2E_N150 + default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N + default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0045-mb-lenovo-t580-Enable-TBT-support.patch b/config/coreboot/default/patches/0045-mb-lenovo-t580-Enable-TBT-support.patch deleted file mode 100644 index eafa934f..00000000 --- a/config/coreboot/default/patches/0045-mb-lenovo-t580-Enable-TBT-support.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 2a9e31b0f0bc22d41dfbc5813aa73176619bff9c Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Mon, 22 Dec 2025 11:08:46 +0000 -Subject: [PATCH 1/1] mb/lenovo/t580: Enable TBT support - -This is based on the same change made to the ThinkPad T480 -by Matt DeVillier. - -I simply applied the same changes myself, on the T580. - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 1 + - src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c | 8 ++++---- - 2 files changed, 5 insertions(+), 4 deletions(-) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index c60b85af08..bad6c500d3 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -48,6 +48,7 @@ config BOARD_LENOVO_T580 - bool - select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON - select SOC_INTEL_KABYLAKE -+ select DRIVERS_INTEL_DTBT - select MEC1653_HAS_DEBUG_UNLOCK - select VARIANT_HAS_DGPU - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c -index 9c0da3c37e..35ec83152e 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c -@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* TBT_FORCE_PWR */ - PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ - -@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = { - PAD_NC(GPP_G1, NONE), - PAD_NC(GPP_G2, NONE), - PAD_NC(GPP_G3, NONE), -- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPO(GPP_G4, 0, PLTRST), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 0, PLTRST), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 0, PLTRST), /* -TBT_PERST */ - PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ - }; - --- -2.47.3 - diff --git a/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch b/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch new file mode 100644 index 00000000..e4622ce4 --- /dev/null +++ b/config/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch @@ -0,0 +1,31 @@ +From 5b52abaa8529f7493f9d4ecf402e9ee130f4f8d2 Mon Sep 17 00:00:00 2001 +From: Ron Nazarov <ron@noisytoot.org> +Date: Sat, 14 Feb 2026 20:13:01 +0000 +Subject: [PATCH 45/48] mb/supermicro/x11-lga1151-series: Disable ME HECI in + devicetree + +Since we always use me_cleaner, this speeds up boot time by preventing +coreboot from wasting a few seconds waiting for HECI. + +Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350 +Signed-off-by: Ron Nazarov <ron@noisytoot.org> +--- + src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +index fbf896c6ae..aa09a41f2f 100644 +--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb ++++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +@@ -15,7 +15,7 @@ chip soc/intel/skylake + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end +- device ref heci1 on end ++ device ref heci1 off end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch b/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch new file mode 100644 index 00000000..45539084 --- /dev/null +++ b/config/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch @@ -0,0 +1,60 @@ +From b9cc1be6f9d591dbc4f73b1448f8fce5ea20a0b4 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Fri, 20 Feb 2026 01:23:32 +0000 +Subject: [PATCH 46/48] util/ifdtool: option to allow region override + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + util/ifdtool/ifdtool.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c +index d181888e0f..dfefe316a9 100644 +--- a/util/ifdtool/ifdtool.c ++++ b/util/ifdtool/ifdtool.c +@@ -78,6 +78,8 @@ static unsigned int max_regions = 0; + static int selected_chip = 0; + static int platform = -1; + ++static int ignore_region_override = 0; ++ + static const struct region_name region_names[MAX_REGIONS] = { + { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" }, + { "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" }, +@@ -2093,7 +2095,9 @@ static void new_layout(const char *filename, char *image, int size, + } + + for (j = i + 1; j < max_regions; j++) { +- if (regions_collide(&new_regions[i], &new_regions[j])) { ++ if (ignore_region_override) { ++ printf("Ignoring region overlap by user's will.\n"); ++ } else if (regions_collide(&new_regions[i], &new_regions[j])) { + fprintf(stderr, "Regions would overlap.\n"); + exit(EXIT_FAILURE); + } +@@ -2351,10 +2355,11 @@ int main(int argc, char *argv[]) + {"newvalue", 1, NULL, 'V'}, + {"topswapsize", 1, NULL, 'T'}, + {"nuke", 1, NULL, 'N'}, ++ {"ignore-region-overlap", 0, NULL, 'I'}, + {0, 0, 0, 0} + }; + +- while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?", ++ while ((opt = getopt_long(argc, argv, "I:S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'd': +@@ -2598,6 +2603,9 @@ int main(int argc, char *argv[]) + } + mode_nuke = 1; + break; ++ case 'I': ++ ignore_region_override = 1; ++ break; + case 'v': + print_version(); + exit(EXIT_SUCCESS); +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch b/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch new file mode 100644 index 00000000..cfd5c6c9 --- /dev/null +++ b/config/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch @@ -0,0 +1,44 @@ +From 1bc6028bf88ca6306ad89fc17fa6f31b9788b248 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Fri, 20 Feb 2026 19:31:19 +0000 +Subject: [PATCH 47/48] me_cleaner: don't modify if -k is used + +don't remove *anything*. in libreboot, we only +ever use -k when we werely want to extract the +ME, but otherwise not modify it. this is because +we rely on bruteforce, detecting when me.bin is +found based on mecleaner validation. + +this way, we can much more reliable get the ME +images. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + util/me_cleaner/me_cleaner.py | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py +index 228bac899f..269aa4ad04 100755 +--- a/util/me_cleaner/me_cleaner.py ++++ b/util/me_cleaner/me_cleaner.py +@@ -677,7 +677,7 @@ if __name__ == "__main__": + # ME 6 Ignition: wipe everything + me6_ignition = False + if not args.check and not args.soft_disable_only and \ +- variant == "ME" and version[0] == 6: ++ variant == "ME" and version[0] == 6 and not args.keep_modules: + mef.seek(ftpr_offset + 0x20) + num_modules = unpack("<I", mef.read(4))[0] + mef.seek(ftpr_offset + 0x290 + (num_modules + 1) * 0x60) +@@ -689,7 +689,7 @@ if __name__ == "__main__": + me6_ignition = True + + if not args.check: +- if not args.soft_disable_only and not me6_ignition: ++ if not args.soft_disable_only and not me6_ignition and not args.keep_modules: + print("Reading partitions list...") + unremovable_part_fpt = b"" + extra_part_end = 0 +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch b/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch new file mode 100644 index 00000000..76fc54e2 --- /dev/null +++ b/config/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch @@ -0,0 +1,600 @@ +From f5f73c2539e05cf85bf5eec795e4f91da50838ba Mon Sep 17 00:00:00 2001 +From: Kat Inskip <kat@inskip.me> +Date: Tue, 17 Feb 2026 16:18:15 -0800 +Subject: [PATCH 48/48] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant + +This machine is somewhat dissimilar from the X280 in the PCIe allocations in the overridetree. It also lacks soldered RAM, having a single SODIMM slot. + +This port was based upon the work done by Johann C Rode for the X280 and the VBT and hda verbs were obtained from that work, not obtained separately. GPIO ports and PCI-e allocations have been checked against schematics after editing. + +Functionality has been validated on a ThinkPad X270 with machine type model 20HMS2WU03 with 16GB onboard RAM and i5-7300U CPU. The laptop has been tested running libreboot, booting Guix via GRUB payload. A check of the hardware shows no issues (video, wifi, wired ethernet, reboot, sleep, NVMe). + +An untested variety allowing for a Skylake CPU (for 20K5 and 20K6) has been included. +--- + src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 14 ++ + .../lenovo/sklkbl_thinkpad/Kconfig.name | 3 + + .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 0 -> 6144 bytes + .../variants/x270/gma-mainboard.ads | 19 ++ + .../sklkbl_thinkpad/variants/x270/gpio.c | 200 ++++++++++++++++++ + .../sklkbl_thinkpad/variants/x270/hda_verb.c | 124 +++++++++++ + .../variants/x270/memory_init_params.c | 19 ++ + .../variants/x270/overridetree.cb | 89 ++++++++ + 8 files changed, 468 insertions(+) + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +index b7cc705699..5945fe7b99 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +@@ -58,6 +58,16 @@ config BOARD_LENOVO_X280 + select SOC_INTEL_KABYLAKE + select HAVE_SPD_IN_CBFS + ++config BOARD_LENOVO_X270_20K6 ++ bool ++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ select SOC_INTEL_SKYLAKE ++ ++config BOARD_LENOVO_X270_20HM ++ bool ++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ select SOC_INTEL_KABYLAKE ++ + if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + + config MAINBOARD_DIR +@@ -69,6 +79,8 @@ config VARIANT_DIR + default "t480s" if BOARD_LENOVO_T480S + default "t580" if BOARD_LENOVO_T580 + default "x280" if BOARD_LENOVO_X280 ++ default "x270" if BOARD_LENOVO_X270_20HM ++ default "x270" if BOARD_LENOVO_X270_20K6 + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" +@@ -79,6 +91,8 @@ config MAINBOARD_PART_NUMBER + default "T480s" if BOARD_LENOVO_T480S + default "T580" if BOARD_LENOVO_T580 + default "X280" if BOARD_LENOVO_X280 ++ default "X270" if BOARD_LENOVO_X270_20HM ++ default "X270" if BOARD_LENOVO_X270_20K6 + + config CBFS_SIZE + default 0x900000 +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +index 1d2888840f..43f9296bc5 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +@@ -14,3 +14,6 @@ config BOARD_LENOVO_T580 + + config BOARD_LENOVO_X280 + bool "ThinkPad X280" ++ ++config BOARD_LENOVO_X270_20HM ++ bool "ThinkPad X270" +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..bfb312850e0ab4ea834c535df35edb45834ed248 +GIT binary patch +literal 6144 +zcmeHKUu;ul6hF83w!Qs&FT30g8FkDf5a<SMw;NO(Gu-~!ShtRLf0!jPp+KunJ2ti< +z!(djDC1OmZCThSK>4S-84?3TW@j;A<!SI4Hfy4)cZ%Ryzkr$&_&%L+X*all8F+}XS +zJ>Pe}bI<wR^PTT+Hw^^)v9IeuG|<(CMM{ANOgTp7QVK?5eFwvV{=mUtG#2W@Z{Q*L +zuHvs704a`JC;2pgbL8lFI^*rFBiLwTS1^j*!-oem>Bew+?D_HG5sZf-7&vkyok@=# +z8c(ONZ(wf#4P2Q8j}K;2xbOJT;q+(=8en9Nz8wwCI}kNrqtD;ir1>5vxw&Phzs2{M +z%))J<Sa&=U4fIE1`!Lpv;YeSgudl5;7(IaT-dIN@80l{d%gpFYXn5r0=-@NYj-xkJ +zhfSKMZ6`b*njvFocyy!z1DOo=8a89tn;uJ#zK~8e$jtD+2%^9NaCUG8frDF3Ac;bU +zsCz}M7L~A|ZxXOdP~y6h)KNnvD(Kq;tPvHG6S|U6bOmfXIhz2mS%j}9X0wZ+T_bqj +zXxnr^s)&$SfU8N+0TPu)Tf622u#*~`3WpR45fbY~tLKVVqTxv7L=J6+U|N}iqKKzV +zE3;KBI5a<PSkaG2QQ)<etxVHdmtteC!a2zj7Ps%Ly}K390sQ$Qc~QN9R&g4<C)O^| +zCHYIxE+Pzy3Y;Q7OYE{Us3cxbyoK0Dyqma<I7WPc_z3Y3@d@J7#IF*+Nqm9Wm84JD +z=$S38FW#=XSD9S~mKBnGp-}j|Pyl<vHY;76)j4&$rPG}wMJemd7bPnq0P-!;{gk9i +z=%jhbi>*^Nkaf-o`vHErAoDN*Y&A{MBB|1XA+35B93JbHvvt;HaeY7Ec#IkF@Xxj@ +zP6k(;H@P#F3nedGs=JfjzpYa!OobkwSsK#P$I2^BlEsV4e37vB4$G)q{*N<I(*ajq +z*&JS9uZYPFRw8QundXtFXdc=`+8A^?Y!r~71H4cTVb}y!kc7B->k!R-c0tBVQz1gd +z3e(o>A@DI1+dL($vl6C>0P5ZV{-g^pxYUnb>@yes;8K5cv0E<O$kd&T?O~W^>Iue9 +zGkl+^pEC9(!=IS?2V-_OZgs0qxY=Ge4!PAyH+#j6AGy^p-0ZR&e|4+8#AFGZCACdr +zF$s@L>dO*)UBXW!^=pZJE8*{w>Xz9W8F$NSx6GcD@g-S3E3@;mT(8=*w(DGW^(yn4 +zAdX73_atnRS>NOos_hk9XyacxDE>*#THX@!3ERpD`3eMIq6WR$s^UQVC#{1Gq^xt7 +zU?8;e8r(gGm_M5z*|kA$YW)zZ-l2VHoqv+IZZ{Mr6cJz<1g##<^?;^pBXkQfsMbG8 +zj)o*n*gYj7Okj_PE?l=Ea5?ktR3gF$jT6^<Je&2zx%n8loWqPkcg&O!L&qLnJ3P~* +z>lfz{96(n%>cxN^_?5@v=|=~qd!SZp&lSg_nlhO)&rS-Zlsuej$mNrsT3tiG@m({M +zLe6DKG@7OK!rMxtIkS-v>J2YzEOK;RC4{_vs)Sy=U6;SoGqpjBpI>WunFu_%4N1}+ +zr66ea`laMlN~`X%R;)1}c-lG)1mlXaawb#jKo7uXt@_M-9(a%~1Ur_1aKi)nIIh(s +zEo69Ey~xpeG&5<f3uBVseO=gEven0SZPydqZ;zqEL;w*S*2-EAp-zWn7Alj9vfA(} +zX3{w6L5jA=55^B2O=tEU8cII^4Wm=b)7I1A=v1~qV!HDZ{Y9GY{GJ!)WJ`0;WudU2 +z?%VTZTSVK|z$@((W&{}Qr^71++qk#jN4{YO;LIHTH^k+$U4C26Ksf{D43sla&OkW> +I4@?IB2821pg#Z8m + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads +new file mode 100644 +index 0000000000..fcfbd75a92 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads +@@ -0,0 +1,19 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (eDP, ++ DP1, ++ DP2, ++ HDMI1, ++ HDMI2, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c +new file mode 100644 +index 0000000000..ec5db9c53c +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c +@@ -0,0 +1,200 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <soc/gpio.h> ++#include "../../variant.h" ++ ++static const struct pad_config gpio_table[] = { ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ ++ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ ++ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ ++ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ ++ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ ++ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ ++ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ ++ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ ++ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ ++ PAD_NC(GPP_A11, NONE), ++ PAD_NC(GPP_A12, NONE), /* BM_BUSY#/ISH_GP6 */ ++ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */ ++ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */ ++ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSACK*/ ++ PAD_NC(GPP_A16, NONE), ++ PAD_NC(GPP_A17, NONE), ++ PAD_NC(GPP_A18, NONE), /* ISH_GP0 */ ++ PAD_NC(GPP_A19, NONE), /* ISH_GP1 */ ++ PAD_NC(GPP_A20, NONE), /* ISH_GP2 */ ++ PAD_NC(GPP_A21, NONE), /* ISH_GP3 */ ++ PAD_NC(GPP_A22, NONE), /* ISH_GP4 */ ++ PAD_NC(GPP_A23, NONE), /* ISH_GP5 */ ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ ++ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ ++ PAD_NC(GPP_B2, NONE), ++ PAD_NC(GPP_B3, NONE), ++ PAD_NC(GPP_B4, NONE), ++ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (Card Reader / SD) */ ++ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE1 (WLAN) */ ++ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE2 (GBE) */ ++ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (NVMe) */ ++ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WWAN) */ ++ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* -EXT_PWR_GATE */ ++ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ ++ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ ++ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */ ++ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ ++ PAD_NC(GPP_B16, NONE), /* GSPIO0_CLK */ ++ PAD_NC(GPP_B17, NONE), ++ PAD_NC(GPP_B18, NONE), ++ PAD_NC(GPP_B19, NONE), ++ PAD_NC(GPP_B20, NONE), ++ PAD_NC(GPP_B21, NONE), ++ PAD_NC(GPP_B22, NONE), ++ PAD_NC(GPP_B23, NONE), ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ ++ PAD_NC(GPP_C2, NONE), /* -SMBALERT */ ++ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ ++ PAD_NC(GPP_C5, NONE), ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ ++ PAD_NC(GPP_C8, NONE), ++ PAD_NC(GPP_C9, NONE), ++ PAD_NC(GPP_C10, NONE), ++ PAD_NC(GPP_C11, NONE), ++ PAD_NC(GPP_C12, NONE), ++ PAD_NC(GPP_C13, NONE), ++ PAD_NC(GPP_C14, NONE), ++ PAD_NC(GPP_C15, NONE), ++ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ ++ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ ++ PAD_NC(GPP_C18, NONE), ++ PAD_NC(GPP_C19, NONE), ++ PAD_NC(GPP_C20, NONE), ++ PAD_NC(GPP_C21, NONE), /* X280: TBT_FORCE_PWR X270: INT#_TYPEC_CPU */ ++ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_NC(GPP_D0, NONE), ++ PAD_NC(GPP_D1, NONE), ++ PAD_NC(GPP_D2, NONE), ++ PAD_NC(GPP_D3, NONE), ++ PAD_NC(GPP_D4, NONE), ++ PAD_NC(GPP_D5, NONE), ++ PAD_NC(GPP_D6, NONE), ++ PAD_NC(GPP_D7, NONE), ++ PAD_NC(GPP_D8, NONE), ++ PAD_NC(GPP_D9, UP_20K), ++ PAD_NC(GPP_D10, NONE), ++ PAD_NC(GPP_D11, UP_20K), ++ PAD_NC(GPP_D12, UP_20K), ++ PAD_NC(GPP_D13, NONE), ++ PAD_NC(GPP_D14, NONE), ++ PAD_NC(GPP_D15, NONE), ++ PAD_NC(GPP_D16, NONE), ++ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ ++ PAD_NC(GPP_D18, NONE), ++ PAD_NC(GPP_D19, NONE), ++ PAD_NC(GPP_D20, NONE), ++ PAD_NC(GPP_D21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ ++ PAD_NC(GPP_D23, NONE), ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ ++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -SATA1_DTCT */ ++ PAD_NC(GPP_E2, NONE), ++ PAD_NC(GPP_E3, NONE), /* X280: -TBT_PLUG_EVENT X270: ? */ ++ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ ++ PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA1_DEVSLP */ ++ PAD_NC(GPP_E6, NONE), ++ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* -WWAN_DISABLE */ ++ PAD_NC(GPP_E8, NONE), ++ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ ++ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ ++ PAD_NC(GPP_E11, NONE), ++ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ ++ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ ++ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ ++ PAD_NC(GPP_E15, NONE), ++ PAD_NC(GPP_E16, NONE), ++ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ ++ PAD_NC(GPP_E18, NONE), ++ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ ++ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ ++ PAD_NC(GPP_E22, NONE), ++ PAD_NC(GPP_E23, NONE), ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ ++ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ ++ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ ++ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ ++ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ ++ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ ++ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ ++ PAD_NC(GPD7, NONE), ++ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ ++ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ ++ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ ++ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_NC(GPP_F0, NONE), /* NFC_ACTIVE */ ++ PAD_NC(GPP_F1, NONE), ++ PAD_NC(GPP_F2, NONE), ++ PAD_NC(GPP_F3, NONE), ++ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ ++ PAD_NC(GPP_F5, UP_20K), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI), /* -INT_MIC_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI), /* PLANARID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI), /* PLANARID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI), /* PLANARID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI), /* PLANARID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID4 */ ++ PAD_NC(GPP_F21, UP_20K), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI), /* -TAMPER_SW_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI), /* -SC_DTCT */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_NC(GPP_G0, NONE), /* SD_CMD */ ++ PAD_NC(GPP_G1, NONE), /* SD_DATA0 */ ++ PAD_NC(GPP_G2, NONE), /* SD_DATA1 */ ++ PAD_NC(GPP_G3, NONE), /* SD_DATA2 */ ++ PAD_NC(GPP_G4, NONE), /* X280: TBT_RTD3_PWR_EN X270: SD_DATA3 */ ++ PAD_NC(GPP_G5, NONE), /* X280: TBT_FORCE_USB_PWR X270: SD_CD# */ ++ PAD_NC(GPP_G6, NONE), /* X280: -TBT_PERST X270: SD_CLK */ ++ PAD_NC(GPP_G7, NONE), /* X280: -TBT_PCIE_WAKE X270: SD_WP */ ++ ++}; ++ ++void variant_config_gpios(void) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +new file mode 100644 +index 0000000000..089e605eaf +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +@@ -0,0 +1,124 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 ++ 0x17aa2256, // Subsystem ID ++ 18, ++ AZALIA_SUBVENDOR(0, 0x17aa2256), ++ ++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_MIC_IN, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_MIC_IN, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 15 ++ )), ++ ++ //==========Widget node 0x20 - 0 :Hidden register SW reset ++ 0x0205001A, ++ 0x0204C003, ++ 0x0205001A, ++ 0x0204C003, ++ 0x05850000, ++ 0x0584F880, ++ 0x05850000, ++ 0x0584F880, ++ //==========Widget node 0x20 - 1 : ClassD 2W ++ 0x02050038, ++ 0x02048981, ++ 0x0205001B, ++ 0x02040A4B, ++ //==========Widget node 0x20 - 2 ++ 0x0205003C, ++ 0x02043154, ++ 0x0205003C, ++ 0x02043114, ++ //==========Widget node 0x20 - 3 : ++ 0x02050046, ++ 0x02040004, ++ 0x05750003, ++ 0x057409A3, ++ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD ++ 0x02050009, ++ 0x02046003, ++ 0x0205000A, ++ 0x02047770, ++ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) ++ 0x02050037, ++ 0x0204FE15, ++ 0x02050030, ++ 0x02049004, ++ ++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI ++ 0x80860101, // Subsystem ID ++ 4, ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c +new file mode 100644 +index 0000000000..a2317c026d +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c +@@ -0,0 +1,19 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <soc/romstage.h> ++#include <spd_bin.h> ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = false; /* DDR_DQ probably not in interleave mode */ ++ mem_cfg->CaVrefConfig = 1; /* VREF_CA to CH_A */ ++ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; ++ ++ /* Get SPD for memory slots */ ++ struct spd_block blk = { .addr_map = { 0x50 } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb +new file mode 100644 +index 0000000000..3191cdfac5 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb +@@ -0,0 +1,89 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ device domain 0 on ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) ++ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) ++ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) ++ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB docking station) ++ [4] = USB2_PORT_MID(OC_SKIP), // JIRCAM (IR camera) ++ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) ++ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) ++ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) ++ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) ++ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) ++ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) ++ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) ++ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSB3 (USB docking station) ++ }" ++ end ++ ++ # PCIe ++ # PCIe Controller 1 - 1x2 + 2x1 ++ # PCIE 1 - RP1 - Media / SD - CLKOUT0 - CLKREQ0 ++ # PCIE 2 - USB3 Port ++ # PCIE 3 - RP3 - WiGig - CLKOUT1 - CLKREQ1 ++ # PCIE 3 - RP3 - WLAN - CLKOUT2 - CLKREQ2 ++ # PCIE 4 - GbE - GbE - CLKOUT3 - CLKREQ3 ++ # PCIe Controller 2 - 1x4 ++ # PCIE 5 - RP5 - NVMe - CLKOUT4 - CLKREQ4 ++ # PCIe Controller 3 - 4x1 ++ # PCIE 7 - RP8 - WWAN - CLKOUT5 - CLKREQ5 ++ # PCIE 8 - Optane ++ ++ # Media / SD - x2 ++ device ref pcie_rp1 on ++ register "PcieRpClkReqSupport[0]" = "true" ++ register "PcieRpClkReqNumber[0]" = "0" ++ register "PcieRpClkSrcNumber[0]" = "0" ++ register "PcieRpAdvancedErrorReporting[0]" = "true" ++ register "PcieRpHotPlug[0]" = "true" ++ end ++ ++ # M.2 WLAN x1 ++ device ref pcie_rp3 on ++ register "PcieRpClkReqSupport[2]" = "true" ++ register "PcieRpClkReqNumber[2]" = "2" ++ register "PcieRpClkSrcNumber[2]" = "2" ++ register "PcieRpAdvancedErrorReporting[2]" = "true" ++ register "PcieRpLtrEnable[2]" = "true" ++ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" ++ end ++ ++ # Ethernet (clobbers RP4) ++ device ref gbe on ++ register "LanClkReqSupported" = "true" ++ register "LanClkReqNumber" = "3" ++ register "PcieRpClkReqNumber[3]" = "3" ++ register "PcieRpClkSrcNumber[3]" = "3" ++ register "EnableLanLtr" = "true" ++ register "EnableLanK1Off" = "true" ++ end ++ ++ # M.2 2280 SSD - x4 (RP9) ++ device ref pcie_rp5 on ++ register "PcieRpClkReqSupport[4]" = "true" ++ register "PcieRpClkReqNumber[4]" = "4" ++ register "PcieRpClkSrcNumber[4]" = "4" ++ register "PcieRpAdvancedErrorReporting[4]" = "true" ++ register "PcieRpLtrEnable[4]" = "true" ++ register "PcieRpHotPlug[4]" = "false" ++ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" ++ end ++ ++ # M.2 WWAN x1 ++ device ref pcie_rp8 on ++ register "PcieRpClkReqSupport[7]" = "true" ++ register "PcieRpClkReqNumber[7]" = "5" ++ register "PcieRpClkSrcNumber[7]" = "5" ++ register "PcieRpAdvancedErrorReporting[7]" = "true" ++ register "PcieRpLtrEnable[7]" = "true" ++ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" ++ end ++ end ++end +-- +2.47.3 + diff --git a/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch b/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch new file mode 100644 index 00000000..df86ee01 --- /dev/null +++ b/config/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch @@ -0,0 +1,132 @@ +From 9d39437b9447ab6e6164440bddf459111bd4903f Mon Sep 17 00:00:00 2001 +From: Kat Inskip <kat@inskip.me> +Date: Sat, 21 Feb 2026 19:48:17 +0000 +Subject: [PATCH] mb/lenovo/x270: Provide correct vbt and hda_verb + +--- + .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 6144 -> 4449 bytes + .../sklkbl_thinkpad/variants/x270/hda_verb.c | 29 +++++++++--------- + 2 files changed, 15 insertions(+), 14 deletions(-) + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt +index bfb312850e0ab4ea834c535df35edb45834ed248..c6561a9c57e4e600bc0adb5f6679f2f5d6b6c640 100644 +GIT binary patch +delta 1043 +zcmZoLc&Ic%f;Calfx%$%L?+>h1_E+-8N?V21pmEaU`SzPl;klqFfjDYD@o1K2+~vt +z_MVtzqhMg55a6s}XrgCqqM%@?Z)B)%WMF8jpkQcVWoTw)YB_PgJ|n}#S5l0olUW%J +zmH8bQ7#aQ=F)(m2Ft9K%I51!UfyozHMC%0@m~0uDSQr@8IT+X^kQH$;FffDp4h#xl +z8bl~CurORpU|?Wi|HJ{}Gcd3-Ft9R!tPx;TV1x)UFbFU>fRs5fu(NPN#30UK;9yW- +zRA7P#ft0y`jTR8#5QD0NNii@mDnP7fU|>*S5CDk_2ry`1Q#Lt(Nn)}ATY5b+BLl;q +zDh37ys6!YT7(sx6fsfIEA&*mz!Jk=!p@x}>p^e#sL5t-Cg8-)jgE6N7gBzy+LnNmF +z!(~=3hP$j>49{7)7(TLcG5lubVqj(CV&G@vVvuCxVo+w|V$fydVlZdpVsK>RV(@0; +zVhCm9Vu)wsV#s9k=3-zgW%%=-sR0x!3=9knjO-wHGc*W7Xa)fmhCWS(hB;92IZ$!V +z4=iAHTu_?(1IuJZHeH|p|Jm6Y{{25E!SMe-hb_othYu_u&oR0{ReC^aA27|#8~~;n +z7(yWG7$Ttj|Nl2@GH+mFWY~O*Rg<|MY#YO>RjXDpFlbI;V0PwG$m9~L=HhDQQdrF; +zw3mzPIG4g(E}{QiT%6nr`rJZ}++5z=3WeN4&D>nQ+zOkyg^qG_o#$5g$}Pms!zIY0 +zV9q1t$-@=Qqfp5s)Xl>+l}BMWkI-2juIoGse|d!XdATHc73_J10(rTjc@?x9d4(qP +za?RycILs?_m6z*2uL3KdkT@TgBA<dgpHL(pS27>3mJn+L(*wrIjyy_}&vV92KFDLv +zD6u(}E1HG>1Or3FDlZ6mhk<$WLq5C7@A-r#%kwKri!pS#F)%QAGH@}3G6XQBFz7H& +kV|c;Lpl851c_M$+Bmr(DBv}6+5)=${r;WiWnGIq+0Ot0jSpWb4 + +delta 808 +zcmaE;)L<|{f|X04kilTGBa`q%0|BLr3}Oto`2W3PU`SzPl;klqFf;bdD@o1K2+~vt +z_V&^DcA6MxqiANV5a6s}XrgCqqM%@4sBdVdZ)9L-si0tBY-MU@WoSNem;S_eVvL59 +zSs4xM*_{{|8U7kE@Nlqra5!jiC`fP!xUe{=uqcSI2n09?BseG-C<yqlIOwn_$Z!Z4 +zC<sJ22t)`t2rw|2GBU9+FsN}b9IIe}0tE(x>s$;B%pfk41A_vHW&l$x4A&AE92giP +zgh70R>+B2+tPBhcP7Le<j0%ikbs*IaP-R(AWgH9)EFejC1x5uX5Cd!&m?0p*Q3Fyn +zS&>OpPyu8rNLWCCp${g?0TZ2U$Rsz}l1X5)C6gG8t_NAi%*ep-r;34r0pbFX0T9f` +zXuz<9Lk_}$k_pTw7~D7%7&18o7-~2K82UK`7&uwE7=&557-U(w7}Qz07z|mt7_3>j +z7+hJo82nke7$RA@7?N4J7;;&;7|L0>7#dl*7`j=x7^bqaaWTwi<zm?UnRx>frvL*3 +zg8+j7gW=>2Y~q^_vvD!kgT2kLYSpS$3=Eo67?>+L73OmaZRF(I&8hH^Q|L1%*I!Nr +zWiBC8E-rg6g;Xw~axSh$E`{Y>LOZ#*4s$8I<P!SL#l_04pv^60%gyD^t&qztRL{-T +z$*r)STj(G+*J*BrkK97cJY2jy3dTG_t~^}+JPM^eLhU?U6L}PrxAO>{<l(x^qwteQ +zh?|#7lvlx;SIC!_E1XxMmRG2smun{P<b19U?gn-XmIgsS1{-FB$p^Tkh5XGL78F=0 +zIT+cjV-T4mz`!86S)V(ag<n9OA!3!+2?h{(kC|oiMt+OQ`}rj%zvNex5@qOgV_;zL +yWZ+^5We8wMVbEcm#_)n!Zv(^RK!MiD2L!|>9}tk){DbW~<0kg^a6CDHNgDv8%8_CK + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +index 089e605eaf..60289355f8 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +@@ -3,10 +3,10 @@ + #include <device/azalia_device.h> + + const u32 cim_verb_data[] = { +- 0x10ec0257, // Vendor/Device ID: Realtek ALC257 +- 0x17aa2256, // Subsystem ID +- 18, +- AZALIA_SUBVENDOR(0, 0x17aa2256), ++ 0x10ec0298, // Vendor/Device ID: Realtek ALC298 ++ 0x17aa5062, // Subsystem ID ++ 19, ++ AZALIA_SUBVENDOR(0, 0x17aa5062), + + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, +@@ -15,7 +15,7 @@ const u32 cim_verb_data[] = { + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, +- 2, 0 ++ 4, 0 + )), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( +@@ -27,28 +27,29 @@ const u32 cim_verb_data[] = { + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), +- AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 3, 0 + )), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), +- AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1d, 0x40648605), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, +- 1, 15 ++ 2, 0 + )), + + //==========Widget node 0x20 - 0 :Hidden register SW reset +@@ -107,7 +108,7 @@ const u32 cim_verb_data[] = { + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, +- 1, 0 ++ 2, 0 + )), + AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( + AZALIA_JACK, +@@ -116,7 +117,7 @@ const u32 cim_verb_data[] = { + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, +- 1, 0 ++ 3, 0 + )), + }; + +-- +2.52.0 + |