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-rw-r--r--config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch113
-rw-r--r--config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb2
-rw-r--r--config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode2
-rw-r--r--config/data/coreboot/mkhelper.cfg2
-rw-r--r--include/rom.sh11
-rw-r--r--include/tree.sh2
6 files changed, 124 insertions, 8 deletions
diff --git a/config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch b/config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch
new file mode 100644
index 00000000..2223ec46
--- /dev/null
+++ b/config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch
@@ -0,0 +1,113 @@
+From eb71b55d2dd7af6f6ddca5e462fc228bdb04af50 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Tue, 8 Jul 2025 17:54:57 +0100
+Subject: [PATCH 1/1] lenovo/t480: Drop redundant PcieRpEnable
+
+This is in line with another change from upstream, in
+the recent revision update:
+
+commit ee30558c49c9c4622277785ee0cd54c32720e489
+Author: Nico Huber <nico.h@gmx.de>
+Date: Fri Jan 12 16:22:19 2024 +0100
+
+ soc/intel/skylake: Drop redundant PcieRpEnable
+
+This change is necessary, to prevent a build error.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ .../lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb | 5 -----
+ .../lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb | 5 -----
+ 2 files changed, 10 deletions(-)
+
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+index bf66bd3a69..316dbcbe8a 100644
+--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+@@ -43,7 +43,6 @@ chip soc/intel/skylake
+
+ # dGPU - x4
+ device ref pcie_rp1 on
+- register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "0"
+ register "PcieRpClkSrcNumber[0]" = "0"
+@@ -61,7 +60,6 @@ chip soc/intel/skylake
+
+ # M.2 WLAN - x1
+ device ref pcie_rp7 on
+- register "PcieRpEnable[6]" = "1"
+ register "PcieRpClkReqSupport[6]" = "1"
+ register "PcieRpClkReqNumber[6]" = "2"
+ register "PcieRpClkSrcNumber[6]" = "2"
+@@ -71,7 +69,6 @@ chip soc/intel/skylake
+
+ # M.2 WWAN - x2
+ device ref pcie_rp5 on
+- register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ register "PcieRpClkReqNumber[4]" = "3"
+ register "PcieRpClkSrcNumber[4]" = "3"
+@@ -81,7 +78,6 @@ chip soc/intel/skylake
+
+ # TB3 (Alpine Ridge LP) - x2
+ device ref pcie_rp9 on
+- register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "4"
+ register "PcieRpClkSrcNumber[8]" = "4"
+@@ -92,7 +88,6 @@ chip soc/intel/skylake
+
+ # M.2 2280 caddy - x2
+ device ref pcie_rp11 on
+- register "PcieRpEnable[10]" = "1"
+ register "PcieRpClkReqSupport[10]" = "1"
+ register "PcieRpClkReqNumber[10]" = "5"
+ register "PcieRpClkSrcNumber[10]" = "5"
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+index d4afca20c4..dcaf15fabf 100644
+--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+@@ -43,7 +43,6 @@ chip soc/intel/skylake
+
+ # dGPU - x2
+ device ref pcie_rp1 on
+- register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "0"
+ register "PcieRpClkSrcNumber[0]" = "0"
+@@ -53,7 +52,6 @@ chip soc/intel/skylake
+
+ # M.2 WWAN - x1
+ device ref pcie_rp4 on
+- register "PcieRpEnable[3]" = "1"
+ register "PcieRpClkReqSupport[3]" = "1"
+ register "PcieRpClkReqNumber[3]" = "1"
+ register "PcieRpClkSrcNumber[3]" = "1"
+@@ -71,7 +69,6 @@ chip soc/intel/skylake
+
+ # M.2 WLAN - x1
+ device ref pcie_rp7 on
+- register "PcieRpEnable[6]" = "1"
+ register "PcieRpClkReqSupport[6]" = "1"
+ register "PcieRpClkReqNumber[6]" = "3"
+ register "PcieRpClkSrcNumber[6]" = "3"
+@@ -81,7 +78,6 @@ chip soc/intel/skylake
+
+ # TB3 (Alpine Ridge LP) - x2
+ device ref pcie_rp5 on
+- register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ register "PcieRpClkReqNumber[4]" = "4"
+ register "PcieRpClkSrcNumber[4]" = "4"
+@@ -92,7 +88,6 @@ chip soc/intel/skylake
+
+ # M.2 2280 SSD - x2
+ device ref pcie_rp9 on
+- register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "5"
+ register "PcieRpClkSrcNumber[8]" = "5"
+--
+2.39.5
+
diff --git a/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb b/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb
index cd847e35..e01a0f5d 100644
--- a/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb
@@ -122,7 +122,7 @@ CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="HP"
-CONFIG_CBFS_SIZE=0x400000
+CONFIG_CBFS_SIZE=0x7E7000
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
CONFIG_MAX_CPUS=8
diff --git a/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode b/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode
index 1165b724..a9358a5e 100644
--- a/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode
@@ -122,7 +122,7 @@ CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="HP"
-CONFIG_CBFS_SIZE=0x400000
+CONFIG_CBFS_SIZE=0x7E7000
CONFIG_MAX_CPUS=8
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
diff --git a/config/data/coreboot/mkhelper.cfg b/config/data/coreboot/mkhelper.cfg
index da9015f1..743d7c5b 100644
--- a/config/data/coreboot/mkhelper.cfg
+++ b/config/data/coreboot/mkhelper.cfg
@@ -3,7 +3,7 @@
makeargs="UPDATED_SUBMODULES=1 CPUS=$XBMK_THREADS"
build_depend="seabios/default grub/default memtest86plus u-boot/amd64coreboot"
-seavgabiosrom="elf/seabios/default/libgfxinit/vgabios.bin"
+seavgabiosrom="elf/seabios/default/default/libgfxinit/vgabios.bin"
pv="payload_seabios payload_memtest payload_grub payload_grubsea"
v="initmode ubootelf grub_scan_disk uboot_config grubtree grubelf pname"
diff --git a/include/rom.sh b/include/rom.sh
index c1b78c75..c88d0c69 100644
--- a/include/rom.sh
+++ b/include/rom.sh
@@ -25,7 +25,7 @@ copyps1bios()
remkdir "bin/playstation"
x_ cp src/pcsx-redux/src/mips/openbios/openbios.bin bin/playstation
- printf "MIT License\n\nCopyright (c) 2019-2024 PCSX-Redux authors\n\n" \
+ printf "MIT License\n\nCopyright (c) 2019-2025 PCSX-Redux authors\n\n" \
> bin/playstation/COPYING.txt || err "!pcsx-redux copyright"
cat config/snippet/mit >>bin/playstation/COPYING.txt || err "!pcsx MIT"
}
@@ -102,7 +102,7 @@ mkcorebootbin()
[ -z "$grub_scan_disk" ] && grub_scan_disk="nvme ahci ata"
[ -n "$grubtree" ] || grubtree="default"
- grubelf="elf/grub/$grubtree/payload/grub.elf"
+ grubelf="elf/grub/$grubtree/$grubtree/payload/grub.elf"
[ "$payload_memtest" = "y" ] || payload_memtest="n"
[ "$(uname -m)" = "x86_64" ] || payload_memtest="n"
@@ -127,7 +127,7 @@ add_seabios()
[ -z "$payload_uboot" ] || [ "$payload_uboot" = "arm64" ] || \
$dry add_uboot
- _seabioself="elf/seabios/default/$initmode/bios.bin.elf"
+ _seabioself="elf/seabios/default/default/$initmode/bios.bin.elf"
_seaname="fallback/payload" && [ "$payload_grubsea" = "y" ] && \
_seaname="seabios.elf"
@@ -191,18 +191,21 @@ add_uboot()
# aarch64 targets:
ubcbfsargs=""
ubpath="fallback/payload"
+ ubtree="default"
ubtarget="$target"
# override for x86/x86_64 targets:
if [ -n "$payload_uboot" ] && [ "$payload_uboot" != "arm64" ]; then
ubcbfsargs="-l 0x1110000 -e 0x1110000" # 64-bit and 32-bit
# on 64-bit, 0x1120000 is the SPL, and stub before that
ubpath="img/u-boot" # 64-bit
+ ubtree="x86_64"
ubtarget="amd64coreboot"
[ "$payload_uboot" = "i386" ] && ubpath="u-boot" # 32-bit
+ [ "$payload_uboot" = "i386" ] && ubtree="x86"
[ "$payload_uboot" = "i386" ] && ubtarget="i386coreboot"; :
fi
- ubdir="elf/u-boot/$ubtarget/$uboot_config"
+ ubdir="elf/u-boot/$ubtree/$ubtarget/$uboot_config"
# aarch64 targets:
ubootelf="$ubdir/u-boot.elf" && [ ! -f "$ubootelf" ] && \
diff --git a/include/tree.sh b/include/tree.sh
index 85f97101..59dd765c 100644
--- a/include/tree.sh
+++ b/include/tree.sh
@@ -264,7 +264,7 @@ gnu_setver()
check_defconfig()
{
[ -f "$defconfig" ] || $dry err "$project/$target: missing defconfig"
- dest_dir="$elfdir/$target/${defconfig#"$target_dir/config/"}"
+ dest_dir="$elfdir/$tree/$target/${defconfig#"$target_dir/config/"}"
$dry elfcheck || return 1; : # skip build if a previous one exists
}
generated by cgit v1.2.1 (git 2.18.0) at 2025-07-08 17:40:49 +0000