diff options
139 files changed, 2251 insertions, 987 deletions
diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index d5a356e4..60d8080d 100644 --- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From 2a1f4af15aa785776498c17abd5d790e1507bd02 Mon Sep 17 00:00:00 2001 +From 7e5ec10bd8a3d95a1d2e12a66e79f180858806c3 Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 01/41] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/43] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch index 95cf7cd9..3a62e972 100644 --- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 089da6f216a8f6c9deec3e6c8d9feb5bf2ff907b Mon Sep 17 00:00:00 2001 +From ded01a8b8f88729c14ddda81c6aa3ceb027cf137 Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 02/41] lenovo/t400: Enable all SATA ports +Subject: [PATCH 02/43] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index 98bd1ebe..ff89ae4a 100644 --- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From ce328f1fa7e7cd90f31728eb1c1215bcb062acd6 Mon Sep 17 00:00:00 2001 +From 2d0fa52a3fccb6e178726db2ae2d0d19cb14f92a Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 03/41] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 03/43] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch index 4595d767..5997b08a 100644 --- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From a7aaa58404cb19e6d89a9c9c5a137f9629d6e140 Mon Sep 17 00:00:00 2001 +From cb0364d9f5814e8bbc853e250eb541b7b040bb08 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 04/41] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 04/43] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default diff --git a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 5c193b84..75c947a5 100644 --- a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From 5a226a91554c70c1c5d56a3184abdea48ea43fbb Mon Sep 17 00:00:00 2001 +From 9a1c993ce23a0c08ed660293143607a8343729b2 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 05/41] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 05/43] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index 0929787d..9c085c55 100644 --- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From 0994cde09852b152039f478937875ada3b3933d8 Mon Sep 17 00:00:00 2001 +From bc9eb4f1d9e39f87498e08880606731775991a4a Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 06/41] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 06/43] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch index 8e38a793..b121ddd2 100644 --- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From b8f173c3ef36873314d4718cf8a8cbe472c0a62b Mon Sep 17 00:00:00 2001 +From 9707d3d8c7e55e2244663983e97b79368565e007 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 07/41] Remove warning for coreboot images built without a +Subject: [PATCH 07/43] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch index 7a66ec5c..aa29df40 100644 --- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From f9ac80501381f464f20b0dfb8b921cfd32267728 Mon Sep 17 00:00:00 2001 +From 0fb47aa25ac0eca68991b16e31c106c48f29df23 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 08/41] HACK: Disable coreboot related BL31 features +Subject: [PATCH 08/43] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch index 2fbd7b3d..33bcaefc 100644 --- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From 8833d84c55c8fc1c49cf320c1825e89984555900 Mon Sep 17 00:00:00 2001 +From 7180330d306c3e66f1868ff38d6c8f34975ce833 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 09/41] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 09/43] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. diff --git a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index dd8c94a4..d27aca56 100644 --- a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From 40b9ffdb09eb40581ae2ea91a653192a6b7507ba Mon Sep 17 00:00:00 2001 +From c5ee5befc6ca5a7bbedfb7b5a594897d66d4fb83 Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 10/41] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 10/43] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. diff --git a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index 41a5c4bb..350122cd 100644 --- a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From 49c11dedc8c12c6868237109c49509729502cc45 Mon Sep 17 00:00:00 2001 +From 73dc0d08dc11f297681123f91754722dac35c293 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 11/41] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 11/43] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless diff --git a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch index 3ebe0c7a..a79e3068 100644 --- a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From 49f11a79d59856b9dc2f81c436933ef22077adc6 Mon Sep 17 00:00:00 2001 +From ceb1fbaadad7c6c814a5e95424c6def7fb8cad40 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 12/41] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 12/43] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off diff --git a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index e28e65c5..92172b25 100644 --- a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From bf2779aa7dc40c8b671d231ca041c3532381b723 Mon Sep 17 00:00:00 2001 +From ba62bbca682e187487eea1709a80dd7f34007bbc Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 13/41] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 13/43] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I diff --git a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index fb00d0b5..65e7b0cd 100644 --- a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,7 +1,7 @@ -From 44ad334748c8c979a42ece4d3425879d3eb9a2b7 Mon Sep 17 00:00:00 2001 +From 892b36c5f5a2004dafcd1af5662eb7f7062ee7b7 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 14/41] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 14/43] ec/dell/mec5035: Add S3 suspend SMI handler This is necessary for S3 resume to work on SNB and newer Dell Latitude laptops. If a command isn't sent, the EC cuts power to the DIMMs, diff --git a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index 6f1792be..95e0360d 100644 --- a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From c9b30b3c93acc42b3c4de4f782dd47d519f81a8d Mon Sep 17 00:00:00 2001 +From 1739b9892390ffda230b1ac8b88aa3e8e7b1527b Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 15/41] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 15/43] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch index 8b75181f..c9c9a450 100644 --- a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From dc5084cfa9526d5ba4a450b4d30f7463d857ba5f Mon Sep 17 00:00:00 2001 +From 2b0d5d00a405d96c59d525305673b18b98ea7e58 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 16/41] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 16/43] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch index 61aa4bff..e745e5eb 100644 --- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -1,7 +1,7 @@ -From 1afeaab1f511e0fac478560d8da2d378858e2ac9 Mon Sep 17 00:00:00 2001 +From 4436acb74d92034f7b6ce73bf7cf2cc542cd4d49 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 17/41] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards +Subject: [PATCH 17/43] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards We add this patch: diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index 863ae505..a03a4b19 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From 12d29915dcd43053b7e3a17e778db3627fbbadfb Mon Sep 17 00:00:00 2001 +From e3d766b05a58ba8db0f19d5a6f124e5a18373562 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 18/41] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 18/43] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch index b75f269c..e6e8ed8d 100644 --- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -1,7 +1,7 @@ -From 25af68c921f62046ea6e939cbe9c7c7936497e96 Mon Sep 17 00:00:00 2001 +From e046f1f9bc7bae66262ea36178a123c8bf2a7387 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 19/41] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ +Subject: [PATCH 19/43] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ set it to 96MHz. fixes the following build error when building for x4x boards e.g. gigabyte ga-g41m-es2l: diff --git a/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch b/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch index 6f45ba44..71d60c71 100644 --- a/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch +++ b/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch @@ -1,7 +1,7 @@ -From 6421e20fe009e981d6bc28cfd79e79ae2097c80d Mon Sep 17 00:00:00 2001 +From 4554a398dab2f1b5e04153103e34378f4ee2f172 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Thu, 26 Sep 2024 19:48:26 -0600 -Subject: [PATCH 20/41] mb/dell: Convert E6400 into a variant +Subject: [PATCH 20/43] mb/dell: Convert E6400 into a variant All the GM45 Dell Latitudes should be nearly identical, so convert the E6400 port into a variant so that future ports for the other systems can diff --git a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch index 557c00f6..6ffa1c0d 100644 --- a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -1,7 +1,7 @@ -From 0b5aa25828b0f91a5345c12dfabdc9a0f9b3765b Mon Sep 17 00:00:00 2001 +From 6fc8dd1d0d4fc369bd98b9305f81f7f1362dad58 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 21/41] mb/dell/gm45_latitudes: Add E4300 variant +Subject: [PATCH 21/43] mb/dell/gm45_latitudes: Add E4300 variant Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch index 16544078..976abf36 100644 --- a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -1,7 +1,7 @@ -From 2f07e367c9c5488722619a6a2efd5aa2fb634a05 Mon Sep 17 00:00:00 2001 +From 9f38902761ca84c873d5f141c318e26c51a482ec Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 22/41] mb/dell: Add S3 SMI handler for Dell Latitudes +Subject: [PATCH 22/43] mb/dell: Add S3 SMI handler for Dell Latitudes Integrate the previously added mec5035_smi_sleep() function into mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. diff --git a/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch index d4d3444a..f8a1883e 100644 --- a/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch +++ b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch @@ -1,7 +1,7 @@ -From ed8e485c5f719fbd0da34d2e883d002945134796 Mon Sep 17 00:00:00 2001 +From 5fc350208fff941734d267d9521c54b7f76cf081 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Tue, 18 Jun 2024 21:31:08 -0600 -Subject: [PATCH 23/41] ec/dell/mec5035: Route power button event to host +Subject: [PATCH 23/43] ec/dell/mec5035: Route power button event to host If command 0x3e with an argument of 1 isn't sent to the EC, pressing the power button results in the EC powering off the system without letting diff --git a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch index 00de7f73..5be3b97f 100644 --- a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch +++ b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch @@ -1,7 +1,7 @@ -From 5d056590dd6f3899422546a16a59bec6402b96f6 Mon Sep 17 00:00:00 2001 +From d7c6ec6e2d336f2e5e489bbfb306f858bcf0d46b Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 24/41] Disable compression on refcode insertion +Subject: [PATCH 24/43] Disable compression on refcode insertion Compression is not reliably reproducible. In an lbmk release context, this means we cannot rely on vendorfile insertion. diff --git a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch index 935ad553..2fcf761a 100644 --- a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch +++ b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch @@ -1,7 +1,7 @@ -From 0b4bce08857e886b15277099cb1a53fe31ddfece Mon Sep 17 00:00:00 2001 +From 5ac7b49b8fcb0ba21af96c72ab8827f2bef9d392 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 25/41] nb/intel/*: Disable stack overflow debug options +Subject: [PATCH 25/43] nb/intel/*: Disable stack overflow debug options Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0026-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch index bb1dc948..92b5532c 100644 --- a/config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ b/config/coreboot/default/patches/0026-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -1,7 +1,7 @@ -From 3505474eebdb54c566dfff79286689f1ba4fbb67 Mon Sep 17 00:00:00 2001 +From 4442c2a69e01c7cf7deececa3ccf2edb06c31b82 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 29/41] mb/dell: Add Optiplex 780 MT (x4x/ICH10) +Subject: [PATCH 26/43] mb/dell: Add Optiplex 780 MT (x4x/ICH10) Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0030-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0027-mb-dell-optiplex_780-Add-USFF-variant.patch index 68bf39e9..26946123 100644 --- a/config/coreboot/default/patches/0030-mb-dell-optiplex_780-Add-USFF-variant.patch +++ b/config/coreboot/default/patches/0027-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -1,7 +1,7 @@ -From 77f7b454580edf756c22b38dd78a855fa5b0977f Mon Sep 17 00:00:00 2001 +From c5b90e39909fc88bec811ab8a24f79a7fce5c4af Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 30/41] mb/dell/optiplex_780: Add USFF variant +Subject: [PATCH 27/43] mb/dell/optiplex_780: Add USFF variant Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch b/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch deleted file mode 100644 index e090016e..00000000 --- a/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 6b623421531a04d0d615889b0710dd82a800c0bd Mon Sep 17 00:00:00 2001 -From: Mate Kukri <km@mkukri.xyz> -Date: Fri, 22 Nov 2024 21:26:48 +0000 -Subject: [PATCH 27/41] soc/intel/skylake: Enable 4E/4F PNP I/O ports in - bootblock - -Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173 -Signed-off-by: Mate Kukri <km@mkukri.xyz> ---- - src/soc/intel/skylake/bootblock/pch.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c -index df00bb85a9..beaece960b 100644 ---- a/src/soc/intel/skylake/bootblock/pch.c -+++ b/src/soc/intel/skylake/bootblock/pch.c -@@ -100,8 +100,8 @@ static void soc_config_pwrmbase(void) - - void pch_early_iorange_init(void) - { -- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | -- LPC_IOE_EC_62_66; -+ uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F | -+ LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66; - - const config_t *config = config_of_soc(); - --- -2.39.5 - diff --git a/config/coreboot/default/patches/0036-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0028-src-intel-x4x-Disable-stack-overflow-debug.patch index 303955a4..dd5f49b1 100644 --- a/config/coreboot/default/patches/0036-src-intel-x4x-Disable-stack-overflow-debug.patch +++ b/config/coreboot/default/patches/0028-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -1,7 +1,7 @@ -From 5f34838af23fd4b6dccbab1f60b931fca7762e01 Mon Sep 17 00:00:00 2001 +From 67b679f676c239ef904cdfdfc11d34f5ffe47b74 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:53:53 +0000 -Subject: [PATCH 36/41] src/intel/x4x: Disable stack overflow debug +Subject: [PATCH 28/43] src/intel/x4x: Disable stack overflow debug Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0039-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0029-hp-8300cmt-remove-xhci_overcurrent_mapping.patch index 4dc78bdc..48255a87 100644 --- a/config/coreboot/default/patches/0039-hp-8300cmt-remove-xhci_overcurrent_mapping.patch +++ b/config/coreboot/default/patches/0029-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -1,7 +1,7 @@ -From 521518c2b9fe32f77937cbd4ff1942f148b1c0f3 Mon Sep 17 00:00:00 2001 +From b738fe8af0132d6d0def055dbe25fa8bb3a797d0 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 22 Apr 2025 10:21:59 +0100 -Subject: [PATCH 39/41] hp/8300cmt: remove xhci_overcurrent_mapping +Subject: [PATCH 29/43] hp/8300cmt: remove xhci_overcurrent_mapping No longer needed, as per the following commit: diff --git a/config/coreboot/default/patches/0031-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0030-dell-3050micro-disable-nvme-hotplug.patch index 66a36d35..6fbfa632 100644 --- a/config/coreboot/default/patches/0031-dell-3050micro-disable-nvme-hotplug.patch +++ b/config/coreboot/default/patches/0030-dell-3050micro-disable-nvme-hotplug.patch @@ -1,7 +1,7 @@ -From cf5f29a8cfed97bb7fb5dee2d7539e57b169661e Mon Sep 17 00:00:00 2001 +From a9a8ed5895dcb3af2bb57ca1492ddc5e9432b2b7 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 11 Dec 2024 01:06:01 +0000 -Subject: [PATCH 31/41] dell/3050micro: disable nvme hotplug +Subject: [PATCH 30/43] dell/3050micro: disable nvme hotplug in my testing, when running my 3050micro for a few days, the nvme would sometimes randomly rename. diff --git a/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0031-soc-intel-skylake-configure-usb-acpi.patch index d77fb756..34db0787 100644 --- a/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch +++ b/config/coreboot/default/patches/0031-soc-intel-skylake-configure-usb-acpi.patch @@ -1,7 +1,7 @@ -From 0287b792fced5752eef4e14d7bc95a21b318e64d Mon Sep 17 00:00:00 2001 +From 17cddce1253e9d71760a2ce066edffd3fc78c844 Mon Sep 17 00:00:00 2001 From: Felix Singer <felixsinger@posteo.net> Date: Wed, 26 Jun 2024 04:24:31 +0200 -Subject: [PATCH 26/41] soc/intel/skylake: configure usb acpi +Subject: [PATCH 31/43] soc/intel/skylake: configure usb acpi Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d Signed-off-by: Felix Singer <felixsinger@posteo.net> diff --git a/config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0032-src-intel-skylake-Disable-stack-overflow-debug-optio.patch index 70ea1b6d..60dda558 100644 --- a/config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ b/config/coreboot/default/patches/0032-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -1,7 +1,7 @@ -From 1f13ade55375d32a65eb5e9cf327f7060353a225 Mon Sep 17 00:00:00 2001 +From 02d0bc457b15874a450d67045f98c869cbf7dd03 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 35/41] src/intel/skylake: Disable stack overflow debug options +Subject: [PATCH 32/43] src/intel/skylake: Disable stack overflow debug options The option was appearing in T480/3050micro configs of lbmk, after updating on the coreboot/next uprev for 20241206 rev8: @@ -37,7 +37,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index d51ffaef7b..42af82a5d8 100644 +index 9191ed0ff8..493a2d835a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE diff --git a/config/coreboot/default/patches/0033-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0033-soc-intel-skylake-Don-t-compress-FSP-S.patch index f1defb5d..0d450229 100644 --- a/config/coreboot/default/patches/0033-soc-intel-skylake-Don-t-compress-FSP-S.patch +++ b/config/coreboot/default/patches/0033-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From 2c1616af49bbc353b0946bcedf077d69d79ba293 Mon Sep 17 00:00:00 2001 +From c52fff995041cc6370e43201873dd1e3dff4e90c Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Thu, 26 Dec 2024 19:45:20 +0000 -Subject: [PATCH 33/41] soc/intel/skylake: Don't compress FSP-S +Subject: [PATCH 33/43] soc/intel/skylake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. @@ -19,7 +19,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 9191ed0ff8..d51ffaef7b 100644 +index 493a2d835a..42af82a5d8 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -12,7 +12,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE diff --git a/config/coreboot/default/patches/0034-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch b/config/coreboot/default/patches/0034-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch index 215a95f1..950b5dec 100644 --- a/config/coreboot/default/patches/0034-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch +++ b/config/coreboot/default/patches/0034-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch @@ -1,7 +1,7 @@ -From 4e269cb66361a5b102f582e41ce8c70a0df3f60f Mon Sep 17 00:00:00 2001 +From c3210c2d3e8a4be7eaf8d005ec3c0595a0d39919 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 31 Dec 2024 01:40:42 +0000 -Subject: [PATCH 34/41] soc/intel/pmc: Hardcoded poweroff after power fail +Subject: [PATCH 34/43] soc/intel/pmc: Hardcoded poweroff after power fail Coreboot can set the power state for power on after previous power failure, based on the option table. On the ThinkPad T480, diff --git a/config/coreboot/default/patches/0035-ec-lenovo-h8-Add-CFR-objects-for-existing-options.patch b/config/coreboot/default/patches/0035-ec-lenovo-h8-Add-CFR-objects-for-existing-options.patch new file mode 100644 index 00000000..b8c9e0fa --- /dev/null +++ b/config/coreboot/default/patches/0035-ec-lenovo-h8-Add-CFR-objects-for-existing-options.patch @@ -0,0 +1,182 @@ +From 9e74101196da1ee94be39e68b37ce7ede665529d Mon Sep 17 00:00:00 2001 +From: Matt DeVillier <matt.devillier@gmail.com> +Date: Fri, 11 Jul 2025 16:07:29 -0500 +Subject: [PATCH 35/43] ec/lenovo/h8: Add CFR objects for existing options + +Add a header with CFR objects for existing configuration options, +so that supported boards can make use of them without duplication. + +TEST=build/boot lenovo/t480 w/edk2 payload + +Change-Id: I198f569e69abd42071df4d5354cd2bb258749257 +Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> +--- + src/ec/lenovo/h8/cfr.h | 156 +++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 156 insertions(+) + create mode 100644 src/ec/lenovo/h8/cfr.h + +diff --git a/src/ec/lenovo/h8/cfr.h b/src/ec/lenovo/h8/cfr.h +new file mode 100644 +index 0000000000..934a3e866b +--- /dev/null ++++ b/src/ec/lenovo/h8/cfr.h +@@ -0,0 +1,156 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * CFR enums and structs for Lenovo H8 EC ++ */ ++ ++#ifndef _LENOVO_H8_CFR_H_ ++#define _LENOVO_H8_CFR_H_ ++ ++#include <drivers/option/cfr_frontend.h> ++ ++/* Bluetooth */ ++static const struct sm_object bluetooth = SM_DECLARE_ENUM({ ++ .opt_name = "bluetooth", ++ .ui_name = "Bluetooth", ++ .ui_helptext = "Enable or disable the bluetooth module", ++ .default_value = 1, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* Keyboard Backlight */ ++static const struct sm_object backlight = SM_DECLARE_ENUM({ ++ .opt_name = "backlight", ++ .ui_name = "Keyboard Backlight", ++ .ui_helptext = "Enable or disable the keyboard backlight", ++ .default_value = 0, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* USB Always-On */ ++static const struct sm_object usb_always_on = SM_DECLARE_ENUM({ ++ .opt_name = "usb_always_on", ++ .ui_name = "USB Always-on", ++ .ui_helptext = "Always keep USB ports powered", ++ .default_value = 0, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* Ultrawideband */ ++static const struct sm_object uwb = SM_DECLARE_ENUM({ ++ .opt_name = "uwb", ++ .ui_name = "Ultrawideband", ++ .ui_helptext = "TBD", ++ .default_value = 1, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* Volume control */ ++static const struct sm_object volume = SM_DECLARE_ENUM({ ++ .opt_name = "volume", ++ .ui_name = "Volume", ++ .ui_helptext = "TBD", ++ .default_value = 0, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* WLAN */ ++static const struct sm_object wlan = SM_DECLARE_ENUM({ ++ .opt_name = "wlan", ++ .ui_name = "WLAN", ++ .ui_helptext = "Enable or disable the WLAN module", ++ .default_value = 1, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* WWAN */ ++static const struct sm_object wwan = SM_DECLARE_ENUM({ ++ .opt_name = "wwan", ++ .ui_name = "WWAN", ++ .ui_helptext = "Enable or disable the WWAN module", ++ .default_value = 1, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* Power Management Beeps */ ++static const struct sm_object pm_beeps = SM_DECLARE_ENUM({ ++ .opt_name = "power_management_beeps", ++ .ui_name = "Power Management Beeps", ++ .ui_helptext = "Enable or disable power management beeps", ++ .default_value = 1, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* Low Battery Beep */ ++static const struct sm_object battery_beep = SM_DECLARE_ENUM({ ++ .opt_name = "low_battery_beep", ++ .ui_name = "Low Battery Beep", ++ .ui_helptext = "Enable or disable low battery beep", ++ .default_value = 1, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* Fn-CTRL Swap */ ++static const struct sm_object fn_ctrl_swap = SM_DECLARE_ENUM({ ++ .opt_name = "fn_ctrl_swap", ++ .ui_name = "Swap Fn and CTRL", ++ .ui_helptext = "Swap the left Fn and CTRL keys", ++ .default_value = CONFIG(H8_FN_CTRL_SWAP), ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* Fn Lock */ ++static const struct sm_object sticky_fn = SM_DECLARE_ENUM({ ++ .opt_name = "sticky_fn", ++ .ui_name = "Sticky Fn key", ++ .ui_helptext = "Function key acts as a toggle", ++ .default_value = 0, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* Function keys primary */ ++static const struct sm_object f1_to_f12_as_primary = SM_DECLARE_ENUM({ ++ .opt_name = "f1_to_f12_as_primary", ++ .ui_name = "Primary Function keys", ++ .ui_helptext = "F1-F12 default act as function keys", ++ .default_value = 1, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++#endif /* _LENOVO_H8_CFR_H_ */ +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0036-ec-lenovo-pmh7-Add-CFR-objects-for-existing-options.patch b/config/coreboot/default/patches/0036-ec-lenovo-pmh7-Add-CFR-objects-for-existing-options.patch new file mode 100644 index 00000000..f010c7ae --- /dev/null +++ b/config/coreboot/default/patches/0036-ec-lenovo-pmh7-Add-CFR-objects-for-existing-options.patch @@ -0,0 +1,62 @@ +From 93e574a0a913b2d982d10aab50f372f59e41ba8c Mon Sep 17 00:00:00 2001 +From: Matt DeVillier <matt.devillier@gmail.com> +Date: Fri, 11 Jul 2025 16:09:08 -0500 +Subject: [PATCH 36/43] ec/lenovo/pmh7: Add CFR objects for existing options + +Add a header with CFR objects for existing configuration options, +so that supported boards can make use of them without duplication. + +TEST=build/boot lenovo/t480 w/edk2 payload + +Change-Id: I8f5c335a8b9d1697b77b3c3542bd96f98583dbf6 +Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> +--- + src/ec/lenovo/pmh7/cfr.h | 36 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + create mode 100644 src/ec/lenovo/pmh7/cfr.h + +diff --git a/src/ec/lenovo/pmh7/cfr.h b/src/ec/lenovo/pmh7/cfr.h +new file mode 100644 +index 0000000000..329fb56a3e +--- /dev/null ++++ b/src/ec/lenovo/pmh7/cfr.h +@@ -0,0 +1,36 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * CFR enums and structs for Lenovo PMH7 EC ++ */ ++ ++#ifndef _LENOVO_PMH7_CFR_H_ ++#define _LENOVO_PMH7_CFR_H_ ++ ++#include <drivers/option/cfr_frontend.h> ++ ++/* Touchpad */ ++static const struct sm_object touchpad = SM_DECLARE_ENUM({ ++ .opt_name = "touchpad", ++ .ui_name = "Touchpad", ++ .ui_helptext = "Enable or disable the touchpad", ++ .default_value = 1, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++/* Trackpoint */ ++static const struct sm_object trackpoint = SM_DECLARE_ENUM({ ++ .opt_name = "trackpoint", ++ .ui_name = "Trackpoint", ++ .ui_helptext = "Enable or disable the trackpoint", ++ .default_value = 1, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}); ++ ++#endif /* _LENOVO_PMH7_CFR_H_ */ +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0037-ec-lenovo-h8-Replace-chip-regs-for-BT-WWAN-detect-wi.patch b/config/coreboot/default/patches/0037-ec-lenovo-h8-Replace-chip-regs-for-BT-WWAN-detect-wi.patch new file mode 100644 index 00000000..401f4d9a --- /dev/null +++ b/config/coreboot/default/patches/0037-ec-lenovo-h8-Replace-chip-regs-for-BT-WWAN-detect-wi.patch @@ -0,0 +1,512 @@ +From 321fa80375cb1050a09ef8ae8e1d9fb7a1590c8b Mon Sep 17 00:00:00 2001 +From: Matt DeVillier <matt.devillier@gmail.com> +Date: Sat, 12 Jul 2025 14:48:33 -0500 +Subject: [PATCH 37/43] ec/lenovo/h8: Replace chip regs for BT/WWAN detect with + Kconfig options + +Using Kconfig options instead of chip registers allows for newer boards +which do not implement BT/WWAN detection to not compile in the GPIO- +related parts, which are only valid for older (pre-FSP) platforms. + +Change-Id: Ibfe738adfc75abfaf078c6b7ff5472a1424909f5 +Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> +--- + src/ec/lenovo/h8/Kconfig | 8 ++++++++ + src/ec/lenovo/h8/bluetooth.c | 2 +- + src/ec/lenovo/h8/chip.h | 2 -- + src/ec/lenovo/h8/wwan.c | 2 +- + src/mainboard/lenovo/t400/Kconfig | 1 + + src/mainboard/lenovo/t400/devicetree.cb | 1 - + src/mainboard/lenovo/t420/Kconfig | 1 + + src/mainboard/lenovo/t420/devicetree.cb | 1 - + src/mainboard/lenovo/t420s/Kconfig | 1 + + src/mainboard/lenovo/t420s/devicetree.cb | 1 - + src/mainboard/lenovo/t430/Kconfig | 2 ++ + src/mainboard/lenovo/t430/devicetree.cb | 2 -- + src/mainboard/lenovo/t430s/Kconfig | 1 + + src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb | 1 - + src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb | 2 -- + src/mainboard/lenovo/t520/Kconfig | 2 ++ + src/mainboard/lenovo/t520/devicetree.cb | 1 - + src/mainboard/lenovo/t520/variants/t520/overridetree.cb | 1 - + src/mainboard/lenovo/t530/Kconfig | 2 ++ + src/mainboard/lenovo/t530/devicetree.cb | 1 - + src/mainboard/lenovo/t530/variants/t530/overridetree.cb | 1 - + src/mainboard/lenovo/t60/Kconfig | 1 + + src/mainboard/lenovo/t60/variants/t60/overridetree.cb | 1 - + src/mainboard/lenovo/x1_carbon_gen1/Kconfig | 2 ++ + src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb | 2 -- + src/mainboard/lenovo/x200/Kconfig | 1 + + src/mainboard/lenovo/x200/devicetree.cb | 1 - + src/mainboard/lenovo/x201/Kconfig | 1 + + src/mainboard/lenovo/x201/devicetree.cb | 1 - + src/mainboard/lenovo/x220/Kconfig | 1 + + src/mainboard/lenovo/x220/devicetree.cb | 2 -- + src/mainboard/lenovo/x230/Kconfig | 1 + + src/mainboard/lenovo/x230/devicetree.cb | 2 -- + src/mainboard/lenovo/x230/variants/x230s/overridetree.cb | 2 -- + src/mainboard/lenovo/x60/Kconfig | 1 + + src/mainboard/lenovo/x60/devicetree.cb | 1 - + 36 files changed, 28 insertions(+), 28 deletions(-) + +diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig +index b15657d21a..fbdca5f94a 100644 +--- a/src/ec/lenovo/h8/Kconfig ++++ b/src/ec/lenovo/h8/Kconfig +@@ -65,4 +65,12 @@ config THINKPADEC_HKEY_EISAID + Motherboards of newer thinkpad models can override the default to match + vendor drivers and quirks. + ++config H8_HAS_BDC_GPIO_DETECTION ++ bool ++ default n ++ ++config H8_HAS_WWAN_GPIO_DETECTION ++ bool ++ default n ++ + endif # EC_LENOVO_H8 +diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c +index 16fc8dce39..aa5fc5814f 100644 +--- a/src/ec/lenovo/h8/bluetooth.c ++++ b/src/ec/lenovo/h8/bluetooth.c +@@ -28,7 +28,7 @@ bool h8_has_bdc(const struct device *dev) + { + struct ec_lenovo_h8_config *conf = dev->chip_info; + +- if (!conf->has_bdc_detection) { ++ if (!CONFIG(H8_HAS_BDC_GPIO_DETECTION)) { + printk(BIOS_INFO, "H8: BDC detection not implemented. " + "Assuming BDC installed\n"); + return true; +diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h +index 440c2fc4dd..0e4b11e753 100644 +--- a/src/ec/lenovo/h8/chip.h ++++ b/src/ec/lenovo/h8/chip.h +@@ -32,8 +32,6 @@ struct ec_lenovo_h8_config { + u8 has_keyboard_backlight; + u8 has_power_management_beeps; + u8 has_uwb; +- u8 has_bdc_detection; +- u8 has_wwan_detection; + + u8 bdc_gpio_num; + u8 bdc_gpio_lvl; +diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c +index 685886fcce..3eea9541ec 100644 +--- a/src/ec/lenovo/h8/wwan.c ++++ b/src/ec/lenovo/h8/wwan.c +@@ -26,7 +26,7 @@ bool h8_has_wwan(const struct device *dev) + { + struct ec_lenovo_h8_config *conf = dev->chip_info; + +- if (!conf->has_wwan_detection) { ++ if (!CONFIG(H8_HAS_WWAN_GPIO_DETECTION)) { + printk(BIOS_INFO, "H8: WWAN detection not implemented. " + "Assuming WWAN installed\n"); + return true; +diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig +index 5afcde8b81..85e580e30e 100644 +--- a/src/mainboard/lenovo/t400/Kconfig ++++ b/src/mainboard/lenovo/t400/Kconfig +@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION if !BOARD_LENOVO_R500 + select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 + select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 + select HAVE_ACPI_TABLES +diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb +index 3d007533a4..9361f330d2 100644 +--- a/src/mainboard/lenovo/t400/devicetree.cb ++++ b/src/mainboard/lenovo/t400/devicetree.cb +@@ -155,7 +155,6 @@ chip northbridge/intel/gm45 + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "48" + register "bdc_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig +index e2137a3379..cbf07efab7 100644 +--- a/src/mainboard/lenovo/t420/Kconfig ++++ b/src/mainboard/lenovo/t420/Kconfig +@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION + select NO_UART_ON_SUPERIO + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES +diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb +index f5272fc701..37ac884eb3 100644 +--- a/src/mainboard/lenovo/t420/devicetree.cb ++++ b/src/mainboard/lenovo/t420/devicetree.cb +@@ -149,7 +149,6 @@ chip northbridge/intel/sandybridge + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "54" + register "bdc_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig +index 5ed1fdefe9..37b3993a1a 100644 +--- a/src/mainboard/lenovo/t420s/Kconfig ++++ b/src/mainboard/lenovo/t420s/Kconfig +@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_PMH7 + select GFX_GMA_PANEL_1_ON_LVDS + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT +diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb +index 840e520fbb..335e025c72 100644 +--- a/src/mainboard/lenovo/t420s/devicetree.cb ++++ b/src/mainboard/lenovo/t420s/devicetree.cb +@@ -141,7 +141,6 @@ chip northbridge/intel/sandybridge + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "54" + register "bdc_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig +index e136871503..1baa94a4c8 100644 +--- a/src/mainboard/lenovo/t430/Kconfig ++++ b/src/mainboard/lenovo/t430/Kconfig +@@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_PMH7 + select GFX_GMA_PANEL_1_ON_LVDS + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION ++ select H8_HAS_WWAN_GPIO_DETECTION + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT +diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb +index 9a0db4dd85..02a4c85344 100644 +--- a/src/mainboard/lenovo/t430/devicetree.cb ++++ b/src/mainboard/lenovo/t430/devicetree.cb +@@ -118,11 +118,9 @@ chip northbridge/intel/sandybridge + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "54" + register "bdc_gpio_lvl" = "0" + +- register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig +index 9a7a91b512..3ab5d340bb 100644 +--- a/src/mainboard/lenovo/t430s/Kconfig ++++ b/src/mainboard/lenovo/t430s/Kconfig +@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_T430S + select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_T431S + select NO_UART_ON_SUPERIO + select BOARD_ROMSIZE_KB_16384 +diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +index a9da730815..bc947af287 100644 +--- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb ++++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +@@ -24,7 +24,6 @@ chip northbridge/intel/sandybridge + device ref lpc on + chip ec/lenovo/h8 + device pnp ff.2 on end # dummy +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "54" + register "bdc_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +index 15712f941d..dae8bc7a2d 100644 +--- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb ++++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +@@ -55,8 +55,6 @@ chip northbridge/intel/sandybridge + register "config1" = "0x09" + register "config3" = "0xc0" + register "evente_enable" = "0x1d" +- # T431s only has BT on wlan card +- register "has_bdc_detection" = "0" + end + end + device ref thermal off end +diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig +index 663113b98f..384927989f 100644 +--- a/src/mainboard/lenovo/t520/Kconfig ++++ b/src/mainboard/lenovo/t520/Kconfig +@@ -9,6 +9,8 @@ config BOARD_LENOVO_BASEBOARD_T520 + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION ++ select H8_HAS_WWAN_GPIO_DETECTION + select NO_UART_ON_SUPERIO + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES +diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb +index 7102df0b9d..74605ca081 100644 +--- a/src/mainboard/lenovo/t520/devicetree.cb ++++ b/src/mainboard/lenovo/t520/devicetree.cb +@@ -137,7 +137,6 @@ chip northbridge/intel/sandybridge + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "54" + register "bdc_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb +index 52946d1b6e..48d8f34e8d 100644 +--- a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb ++++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb +@@ -5,7 +5,6 @@ chip northbridge/intel/sandybridge + device ref lpc on + chip ec/lenovo/h8 + device pnp ff.2 on end # dummy +- register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig +index a797656d71..9450fdddd7 100644 +--- a/src/mainboard/lenovo/t530/Kconfig ++++ b/src/mainboard/lenovo/t530/Kconfig +@@ -9,6 +9,8 @@ config BOARD_LENOVO_BASEBOARD_T530 + select EC_LENOVO_PMH7 + select GFX_GMA_PANEL_1_ON_LVDS + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION ++ select H8_HAS_WWAN_GPIO_DETECTION + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT +diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb +index 362e0a69e9..13c40d91d4 100644 +--- a/src/mainboard/lenovo/t530/devicetree.cb ++++ b/src/mainboard/lenovo/t530/devicetree.cb +@@ -117,7 +117,6 @@ chip northbridge/intel/sandybridge + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "54" + register "bdc_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb +index 3f058e3854..9bd36488f6 100644 +--- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb ++++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb +@@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge + device ref lpc on + chip ec/lenovo/h8 + device pnp ff.2 on end # dummy +- register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig +index ec3a6e01bb..6d095943bd 100644 +--- a/src/mainboard/lenovo/t60/Kconfig ++++ b/src/mainboard/lenovo/t60/Kconfig +@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS + select HAVE_CMOS_DEFAULT + select I945_LVDS + select INTEL_GMA_HAVE_VBT ++ select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_T60 || BOARD_LENOVO_R60 + + config MAINBOARD_DIR + default "lenovo/t60" +diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb +index c58884a4b5..42e07a648c 100644 +--- a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb ++++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb +@@ -26,7 +26,6 @@ chip northbridge/intel/i945 + end + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "7" + register "bdc_gpio_lvl" = "0" + device pnp ff.2 on end +diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +index 4e4c58b246..f0dcb38ab4 100644 +--- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig ++++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +@@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_PMH7 + select GFX_GMA_PANEL_1_ON_LVDS + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION ++ select H8_HAS_WWAN_GPIO_DETECTION + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT +diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +index 84611d0656..6f601e9521 100644 +--- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb ++++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +@@ -127,11 +127,9 @@ chip northbridge/intel/sandybridge + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "54" + register "bdc_gpio_lvl" = "0" + +- register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig +index 29e2f6ca91..4aa1e2ce1e 100644 +--- a/src/mainboard/lenovo/x200/Kconfig ++++ b/src/mainboard/lenovo/x200/Kconfig +@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_X200 + select NO_UART_ON_SUPERIO + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES +diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb +index 7871cfd00d..2d6ea77214 100644 +--- a/src/mainboard/lenovo/x200/devicetree.cb ++++ b/src/mainboard/lenovo/x200/devicetree.cb +@@ -144,7 +144,6 @@ chip northbridge/intel/gm45 + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "7" + register "bdc_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig +index 8517232d20..319f127ab6 100644 +--- a/src/mainboard/lenovo/x201/Kconfig ++++ b/src/mainboard/lenovo/x201/Kconfig +@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS + select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_BDC_GPIO_DETECTION + + config VBOOT + select VBOOT_VBNV_FLASH +diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb +index 0be8a3ba07..5b6746b718 100644 +--- a/src/mainboard/lenovo/x201/devicetree.cb ++++ b/src/mainboard/lenovo/x201/devicetree.cb +@@ -140,7 +140,6 @@ chip northbridge/intel/ironlake + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "48" + register "bdc_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig +index e6a2e66209..a877546bb7 100644 +--- a/src/mainboard/lenovo/x220/Kconfig ++++ b/src/mainboard/lenovo/x220/Kconfig +@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_PMH7 + select GFX_GMA_PANEL_1_ON_LVDS + select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_WWAN_GPIO_DETECTION + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT +diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb +index aaeecc8246..0ca9bcc6a3 100644 +--- a/src/mainboard/lenovo/x220/devicetree.cb ++++ b/src/mainboard/lenovo/x220/devicetree.cb +@@ -141,9 +141,7 @@ chip northbridge/intel/sandybridge + # BDC shorts pin14 and pin1 + # BDC's connector pin14 is left floating + # BDC's connector pin1 is routed to SB GPIO 54 +- register "has_bdc_detection" = "0" + +- register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig +index 1d04af9bff..cb6395beb9 100644 +--- a/src/mainboard/lenovo/x230/Kconfig ++++ b/src/mainboard/lenovo/x230/Kconfig +@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_H8 + select H8_HAS_BAT_THRESHOLDS_IMPL + select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S ++ select H8_HAS_WWAN_GPIO_DETECTION if !BOARD_LENOVO_X230S + select NO_UART_ON_SUPERIO + select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP + select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S +diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb +index 3067096f0d..735ce4d9d9 100644 +--- a/src/mainboard/lenovo/x230/devicetree.cb ++++ b/src/mainboard/lenovo/x230/devicetree.cb +@@ -123,9 +123,7 @@ chip northbridge/intel/sandybridge + # BDC shorts pin14 and pin1 + # BDC's connector pin14 is left floating + # BDC's connector pin1 is routed to SB GPIO 54 +- register "has_bdc_detection" = "0" + +- register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end +diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +index a84b5f3bdd..86c2e16e7d 100644 +--- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb ++++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +@@ -40,8 +40,6 @@ chip northbridge/intel/sandybridge + register "config3" = "0xc4" + register "event5_enable" = "0x3c" + register "evente_enable" = "0x1d" +- # X230s only has BT on wlan card +- register "has_bdc_detection" = "0" + device pnp ff.2 on end + end + end +diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig +index 0f12a9272e..33238ccbd8 100644 +--- a/src/mainboard/lenovo/x60/Kconfig ++++ b/src/mainboard/lenovo/x60/Kconfig +@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_H8 + select DRIVERS_I2C_CK505 + select DRIVER_LENOVO_SERIALS ++ select H8_HAS_BDC_GPIO_DETECTION + select HAVE_OPTION_TABLE + select INTEL_INT15 + select HAVE_CMOS_DEFAULT +diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb +index 0e1e5fced5..7f28bbae49 100644 +--- a/src/mainboard/lenovo/x60/devicetree.cb ++++ b/src/mainboard/lenovo/x60/devicetree.cb +@@ -130,7 +130,6 @@ chip northbridge/intel/i945 + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + +- register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "7" + register "bdc_gpio_lvl" = "0" + end +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0038-do-not-break-building-other-thinkpads-with-the-hacks.patch b/config/coreboot/default/patches/0038-do-not-break-building-other-thinkpads-with-the-hacks.patch deleted file mode 100644 index 8447cfab..00000000 --- a/config/coreboot/default/patches/0038-do-not-break-building-other-thinkpads-with-the-hacks.patch +++ /dev/null @@ -1,153 +0,0 @@ -From 99086eb3298b01aa9b3c68d78c399261866321d5 Mon Sep 17 00:00:00 2001 -From: gaspar-ilom <gasparilom@riseup.net> -Date: Thu, 6 Mar 2025 23:00:00 +0000 -Subject: [PATCH 38/41] do not break building other thinkpads with the hacks - for the t480/s made Mate Kukri - -still not fixing things properly but at least it should now be possible to build older thinkpads without regressions. -prior, some code was just commented or unreachable. now we make this explicit with preprocessor directives. -heads should build all boards on this coreboot version from the same coreboot tree. - -Signed-off-by: gaspar-ilom <gasparilom@riseup.net> ---- - src/device/pci_rom.c | 9 ++++++--- - src/ec/lenovo/h8/acpi/ec.asl | 4 +++- - src/ec/lenovo/h8/bluetooth.c | 14 ++++++++++---- - src/ec/lenovo/h8/wwan.c | 14 ++++++++++---- - 4 files changed, 29 insertions(+), 12 deletions(-) - -diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c -index bba98d9dea..db3dbbe2ce 100644 ---- a/src/device/pci_rom.c -+++ b/src/device/pci_rom.c -@@ -396,16 +396,19 @@ void pci_rom_ssdt(const struct device *device) - rom = cbrom; - } - --#if 0 -+ -+ #if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) -+ const char *scope = "\\_SB.PCI0.RP01.PEGP"; -+ #else - const char *scope = acpi_device_path(device); -+ #endif - if (!scope) { - printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device)); - return; - } --#endif - - /* write _ROM method */ -- acpigen_write_scope("\\_SB.PCI0.RP01.PEGP"); -+ acpigen_write_scope(scope); - acpigen_write_rom((void *)rom, rom->size * 512); - acpigen_pop_len(); /* pop scope */ - } -diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl -index 8f4a8e1986..f80c15106c 100644 ---- a/src/ec/lenovo/h8/acpi/ec.asl -+++ b/src/ec/lenovo/h8/acpi/ec.asl -@@ -331,7 +331,9 @@ Device(EC) - #include "sleepbutton.asl" - #include "lid.asl" - #include "beep.asl" --//#include "thermal.asl" -+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) -+#include "thermal.asl" -+#endif - #include "systemstatus.asl" - #include "thinkpad.asl" - } -diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c -index be71a24ced..e60b6c088c 100644 ---- a/src/ec/lenovo/h8/bluetooth.c -+++ b/src/ec/lenovo/h8/bluetooth.c -@@ -1,6 +1,8 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ - --// #include <southbridge/intel/common/gpio.h> -+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) -+#include <southbridge/intel/common/gpio.h> -+#endif - #include <console/console.h> - #include <device/device.h> - #include <ec/acpi/ec.h> -@@ -26,23 +28,27 @@ void h8_bluetooth_enable(int on) - */ - bool h8_has_bdc(const struct device *dev) - { -+ #if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) -+ printk(BIOS_INFO, "H8: BDC detection not implemented. " -+ "Assuming BDC installed\n"); -+ return true; -+ #else - struct ec_lenovo_h8_config *conf = dev->chip_info; - -- if (1 || !conf->has_bdc_detection) { -+ if (!conf->has_bdc_detection) { - printk(BIOS_INFO, "H8: BDC detection not implemented. " - "Assuming BDC installed\n"); - return true; - } - --#if 0 - if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) { - printk(BIOS_INFO, "H8: BDC installed\n"); - return true; - } --#endif - - printk(BIOS_INFO, "H8: BDC not installed\n"); - return false; -+ #endif - } - - /* -diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c -index 5cdcf77406..b4f5787e01 100644 ---- a/src/ec/lenovo/h8/wwan.c -+++ b/src/ec/lenovo/h8/wwan.c -@@ -1,6 +1,8 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ - --// #include <southbridge/intel/common/gpio.h> -+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) -+#include <southbridge/intel/common/gpio.h> -+#endif - #include <console/console.h> - #include <device/device.h> - #include <ec/acpi/ec.h> -@@ -24,23 +26,27 @@ void h8_wwan_enable(int on) - */ - bool h8_has_wwan(const struct device *dev) - { -+ #if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON) -+ printk(BIOS_INFO, "H8: WWAN detection not implemented. " -+ "Assuming WWAN installed\n"); -+ return true; -+ #else - struct ec_lenovo_h8_config *conf = dev->chip_info; - -- if (1 || !conf->has_wwan_detection) { -+ if (!conf->has_wwan_detection) { - printk(BIOS_INFO, "H8: WWAN detection not implemented. " - "Assuming WWAN installed\n"); - return true; - } - --#if 0 - if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) { - printk(BIOS_INFO, "H8: WWAN installed\n"); - return true; - } --#endif - - printk(BIOS_INFO, "H8: WWAN not installed\n"); - return false; -+ #endif - } - - /* --- -2.39.5 - diff --git a/config/coreboot/default/patches/0038-ec-lenovo-h8-Add-Kconfig-to-select-use-of-Thermal-Zo.patch b/config/coreboot/default/patches/0038-ec-lenovo-h8-Add-Kconfig-to-select-use-of-Thermal-Zo.patch new file mode 100644 index 00000000..d393226c --- /dev/null +++ b/config/coreboot/default/patches/0038-ec-lenovo-h8-Add-Kconfig-to-select-use-of-Thermal-Zo.patch @@ -0,0 +1,137 @@ +From 596f2d915a36ebd3347441d7486e4d11780fc48c Mon Sep 17 00:00:00 2001 +From: Matt DeVillier <matt.devillier@gmail.com> +Date: Sat, 12 Jul 2025 17:17:42 -0500 +Subject: [PATCH 38/43] ec/lenovo/h8: Add Kconfig to select use of Thermal Zone + 1 + +Looking at the ACPI dumps of many older Thinkpads, most do not have a +second thermal zone (zone 1), they only use zone 0. This doesn't seem +to be a problem for most boards in the tree currently, but newer boards +(such as the T480) are reporting critical temperature errors on zone 1, +due to differences in the EC RAM layout (ie, TMP1 is not valid). + +To mitigate this issue with the T480 (and likely other newer boards), +only include the ACPI code for thermal zone 1 for boards which need it. +Explicitly select it for those boards based on ACPI dump analysis and +model similarity. + +Change-Id: Ic022f2e14b2cae74656c0ac85ba8410d50cdc9de +Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> +--- + src/ec/lenovo/h8/Kconfig | 4 ++++ + src/ec/lenovo/h8/acpi/thermal.asl | 3 ++- + src/mainboard/lenovo/t400/Kconfig | 1 + + src/mainboard/lenovo/t410/Kconfig | 1 + + src/mainboard/lenovo/t60/Kconfig | 1 + + src/mainboard/lenovo/x200/Kconfig | 1 + + src/mainboard/lenovo/x201/Kconfig | 1 + + src/mainboard/lenovo/x60/Kconfig | 1 + + 8 files changed, 12 insertions(+), 1 deletion(-) + +diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig +index fbdca5f94a..c8626cc75b 100644 +--- a/src/ec/lenovo/h8/Kconfig ++++ b/src/ec/lenovo/h8/Kconfig +@@ -73,4 +73,8 @@ config H8_HAS_WWAN_GPIO_DETECTION + bool + default n + ++config H8_HAS_2ND_THERMAL_ZONE ++ bool ++ default n ++ + endif # EC_LENOVO_H8 +diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl +index fa5a282f54..bf9b653e12 100644 +--- a/src/ec/lenovo/h8/acpi/thermal.asl ++++ b/src/ec/lenovo/h8/acpi/thermal.asl +@@ -130,7 +130,7 @@ External (\PPKG, MethodObj) + Name (_PR0, Package () { FPWR }) + } + } +- ++#if CONFIG(H8_HAS_2ND_THERMAL_ZONE) + ThermalZone(THM1) + { + /* Thermal zone polling frequency: 10 seconds */ +@@ -168,4 +168,5 @@ External (\PPKG, MethodObj) + Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) + } + } ++#endif + } +diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig +index 85e580e30e..12fbcbdee6 100644 +--- a/src/mainboard/lenovo/t400/Kconfig ++++ b/src/mainboard/lenovo/t400/Kconfig +@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS + select SOUTHBRIDGE_INTEL_I82801IX + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 ++ select H8_HAS_2ND_THERMAL_ZONE + select H8_HAS_BAT_THRESHOLDS_IMPL + select H8_HAS_BDC_GPIO_DETECTION if !BOARD_LENOVO_R500 + select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 +diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig +index 9c78cb1741..6f18528824 100644 +--- a/src/mainboard/lenovo/t410/Kconfig ++++ b/src/mainboard/lenovo/t410/Kconfig +@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS + select DRIVERS_LENOVO_HYBRID_GRAPHICS + select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION ++ select H8_HAS_2ND_THERMAL_ZONE + select H8_HAS_BAT_THRESHOLDS_IMPL + select MAINBOARD_HAS_LIBGFXINIT + select DRIVERS_RICOH_RCE822 +diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig +index 6d095943bd..f1221191da 100644 +--- a/src/mainboard/lenovo/t60/Kconfig ++++ b/src/mainboard/lenovo/t60/Kconfig +@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS + select HAVE_CMOS_DEFAULT + select I945_LVDS + select INTEL_GMA_HAVE_VBT ++ select H8_HAS_2ND_THERMAL_ZONE + select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_T60 || BOARD_LENOVO_R60 + + config MAINBOARD_DIR +diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig +index 4aa1e2ce1e..148584ed5c 100644 +--- a/src/mainboard/lenovo/x200/Kconfig ++++ b/src/mainboard/lenovo/x200/Kconfig +@@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS + select SOUTHBRIDGE_INTEL_I82801IX + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 ++ select H8_HAS_2ND_THERMAL_ZONE if BOARD_LENOVO_X200 + select H8_HAS_BAT_THRESHOLDS_IMPL + select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_X200 + select NO_UART_ON_SUPERIO +diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig +index 319f127ab6..e91ec3e642 100644 +--- a/src/mainboard/lenovo/x201/Kconfig ++++ b/src/mainboard/lenovo/x201/Kconfig +@@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS + select MAINBOARD_HAS_TPM1 + select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION ++ select H8_HAS_2ND_THERMAL_ZONE + select H8_HAS_BAT_THRESHOLDS_IMPL + select H8_HAS_BDC_GPIO_DETECTION + +diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig +index 33238ccbd8..edacdcf234 100644 +--- a/src/mainboard/lenovo/x60/Kconfig ++++ b/src/mainboard/lenovo/x60/Kconfig +@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS + select EC_LENOVO_H8 + select DRIVERS_I2C_CK505 + select DRIVER_LENOVO_SERIALS ++ select H8_HAS_2ND_THERMAL_ZONE + select H8_HAS_BDC_GPIO_DETECTION + select HAVE_OPTION_TABLE + select INTEL_INT15 +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0039-ec-lenovo-h8-Rework-invalid-temperature-reporting.patch b/config/coreboot/default/patches/0039-ec-lenovo-h8-Rework-invalid-temperature-reporting.patch new file mode 100644 index 00000000..3e73a17d --- /dev/null +++ b/config/coreboot/default/patches/0039-ec-lenovo-h8-Rework-invalid-temperature-reporting.patch @@ -0,0 +1,488 @@ +From aedef7382e27d1494768997a18e4d9351cb44cd6 Mon Sep 17 00:00:00 2001 +From: Matt DeVillier <matt.devillier@gmail.com> +Date: Sat, 12 Jul 2025 17:28:13 -0500 +Subject: [PATCH 39/43] ec/lenovo/h8: Rework invalid temperature reporting + +As far back as the x201, Lenovo's EC ACPI has treated 128 as an invalid +value, and returned a corrected value when it is reported/read from EC +RAM. Drop the ME workaround, which most H8-equipped boards select, in +favor of Lenovo's logic, since both accomplish the same result. + +Change-Id: Icdc91e439ec30c8263de5810a13e75f7595472a5 +Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> +--- + src/ec/lenovo/h8/acpi/thermal.asl | 25 ++++++------------- + .../lenovo/haswell/acpi/platform.asl | 3 --- + src/mainboard/lenovo/haswell/dsdt.asl | 1 - + src/mainboard/lenovo/l520/acpi/platform.asl | 4 --- + src/mainboard/lenovo/l520/dsdt.asl | 1 - + src/mainboard/lenovo/s230u/dsdt.asl | 1 - + src/mainboard/lenovo/t400/dsdt.asl | 1 - + src/mainboard/lenovo/t410/dsdt.asl | 1 - + src/mainboard/lenovo/t420/acpi/platform.asl | 4 --- + src/mainboard/lenovo/t420/dsdt.asl | 1 - + src/mainboard/lenovo/t420s/acpi/platform.asl | 4 --- + src/mainboard/lenovo/t420s/dsdt.asl | 1 - + src/mainboard/lenovo/t430/acpi/platform.asl | 4 --- + src/mainboard/lenovo/t430/dsdt.asl | 1 - + src/mainboard/lenovo/t430s/acpi/platform.asl | 4 --- + src/mainboard/lenovo/t430s/dsdt.asl | 1 - + src/mainboard/lenovo/t520/acpi/platform.asl | 4 --- + src/mainboard/lenovo/t520/dsdt.asl | 1 - + src/mainboard/lenovo/t530/acpi/platform.asl | 4 --- + src/mainboard/lenovo/t530/dsdt.asl | 1 - + src/mainboard/lenovo/x131e/acpi/platform.asl | 4 --- + src/mainboard/lenovo/x131e/dsdt.asl | 1 - + .../lenovo/x1_carbon_gen1/acpi/platform.asl | 4 --- + src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | 1 - + src/mainboard/lenovo/x201/acpi/platform.asl | 4 --- + src/mainboard/lenovo/x201/dsdt.asl | 1 - + src/mainboard/lenovo/x220/acpi/platform.asl | 4 --- + src/mainboard/lenovo/x220/dsdt.asl | 1 - + src/mainboard/lenovo/x230/acpi/platform.asl | 4 --- + src/mainboard/lenovo/x230/dsdt.asl | 1 - + 30 files changed, 8 insertions(+), 84 deletions(-) + +diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl +index bf9b653e12..54f4f922bd 100644 +--- a/src/ec/lenovo/h8/acpi/thermal.asl ++++ b/src/ec/lenovo/h8/acpi/thermal.asl +@@ -4,11 +4,6 @@ + + Scope(\_TZ) + { +-#if defined(EC_LENOVO_H8_ME_WORKAROUND) +- Name (MEB1, 0) +- Name (MEB2, 0) +-#endif +- + Method(C2K, 1, NotSerialized) + { + Local0 = Arg0 * 10 +@@ -71,14 +66,12 @@ External (\PPKG, MethodObj) + } + + Method(_TMP) { +-#if defined(EC_LENOVO_H8_ME_WORKAROUND) +- /* Avoid tripping alarm if ME isn't booted at all yet */ +- If (!MEB1 && \_SB.PCI0.LPCB.EC.TMP0 == 128) { ++ Local0 = \_SB.PCI0.LPCB.EC.TMP0 ++ /* Avoid tripping alarm if invalid value reported */ ++ If (Local0 == 128) { + Return (C2K(40)) + } +- MEB1 = 1 +-#endif +- Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) ++ Return (C2K(Local0)) + } + + Method (_AC0) { +@@ -158,14 +151,12 @@ External (\PPKG, MethodObj) + } + + Method(_TMP) { +-#if defined(EC_LENOVO_H8_ME_WORKAROUND) +- /* Avoid tripping alarm if ME isn't booted at all yet */ +- If (!MEB2 && \_SB.PCI0.LPCB.EC.TMP1 == 128) { ++ Local0 = \_SB.PCI0.LPCB.EC.TMP1 ++ /* Avoid tripping alarm if invalid value reported */ ++ If (Local0 == 128) { + Return (C2K(40)) + } +- MEB2 = 1 +-#endif +- Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) ++ Return (C2K(Local0)) + } + } + #endif +diff --git a/src/mainboard/lenovo/haswell/acpi/platform.asl b/src/mainboard/lenovo/haswell/acpi/platform.asl +index f5a4df75f4..42587fd78a 100644 +--- a/src/mainboard/lenovo/haswell/acpi/platform.asl ++++ b/src/mainboard/lenovo/haswell/acpi/platform.asl +@@ -2,9 +2,6 @@ + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 + Return(Package(){0,0}) + } + +diff --git a/src/mainboard/lenovo/haswell/dsdt.asl b/src/mainboard/lenovo/haswell/dsdt.asl +index a7afeee766..708f524b08 100644 +--- a/src/mainboard/lenovo/haswell/dsdt.asl ++++ b/src/mainboard/lenovo/haswell/dsdt.asl +@@ -2,7 +2,6 @@ + + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + #define THINKPAD_EC_GPE 17 + + #include <acpi/acpi.h> +diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/l520/acpi/platform.asl ++++ b/src/mainboard/lenovo/l520/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl +index 06cffcf8a2..18e9f25a9a 100644 +--- a/src/mainboard/lenovo/l520/dsdt.asl ++++ b/src/mainboard/lenovo/l520/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 22 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl +index 861309b8e9..47e91fdb30 100644 +--- a/src/mainboard/lenovo/s230u/dsdt.asl ++++ b/src/mainboard/lenovo/s230u/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 23 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl +index f9c682f9dc..cb824e42da 100644 +--- a/src/mainboard/lenovo/t400/dsdt.asl ++++ b/src/mainboard/lenovo/t400/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl +index 42a10e605c..e2571f60c7 100644 +--- a/src/mainboard/lenovo/t410/dsdt.asl ++++ b/src/mainboard/lenovo/t410/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/t420/acpi/platform.asl b/src/mainboard/lenovo/t420/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/t420/acpi/platform.asl ++++ b/src/mainboard/lenovo/t420/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl +index 33b6f80b17..1134782675 100644 +--- a/src/mainboard/lenovo/t420/dsdt.asl ++++ b/src/mainboard/lenovo/t420/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/t420s/acpi/platform.asl ++++ b/src/mainboard/lenovo/t420s/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl +index 33b6f80b17..1134782675 100644 +--- a/src/mainboard/lenovo/t420s/dsdt.asl ++++ b/src/mainboard/lenovo/t420s/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/t430/acpi/platform.asl ++++ b/src/mainboard/lenovo/t430/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl +index c19e75ee82..795f9a1ee9 100644 +--- a/src/mainboard/lenovo/t430/dsdt.asl ++++ b/src/mainboard/lenovo/t430/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/t430s/acpi/platform.asl ++++ b/src/mainboard/lenovo/t430s/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl +index 33b6f80b17..1134782675 100644 +--- a/src/mainboard/lenovo/t430s/dsdt.asl ++++ b/src/mainboard/lenovo/t430s/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/t520/acpi/platform.asl ++++ b/src/mainboard/lenovo/t520/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl +index 33b6f80b17..1134782675 100644 +--- a/src/mainboard/lenovo/t520/dsdt.asl ++++ b/src/mainboard/lenovo/t520/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/t530/acpi/platform.asl ++++ b/src/mainboard/lenovo/t530/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl +index 33b6f80b17..1134782675 100644 +--- a/src/mainboard/lenovo/t530/dsdt.asl ++++ b/src/mainboard/lenovo/t530/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/x131e/acpi/platform.asl b/src/mainboard/lenovo/x131e/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/x131e/acpi/platform.asl ++++ b/src/mainboard/lenovo/x131e/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl +index 34391416f3..dc9878030e 100644 +--- a/src/mainboard/lenovo/x131e/dsdt.asl ++++ b/src/mainboard/lenovo/x131e/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 22 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl ++++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +index 6838b5e9a6..18a47960f4 100644 +--- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl ++++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + #define EC_LENOVO_H8_ALT_FN_F2F3_LAYOUT 1 + + #include <acpi/acpi.h> +diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl +index f17adafc88..a238248886 100644 +--- a/src/mainboard/lenovo/x201/acpi/platform.asl ++++ b/src/mainboard/lenovo/x201/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl +index 42a10e605c..e2571f60c7 100644 +--- a/src/mainboard/lenovo/x201/dsdt.asl ++++ b/src/mainboard/lenovo/x201/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/x220/acpi/platform.asl ++++ b/src/mainboard/lenovo/x220/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl +index 33b6f80b17..1134782675 100644 +--- a/src/mainboard/lenovo/x220/dsdt.asl ++++ b/src/mainboard/lenovo/x220/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl +index c4becafc2a..9dee90edc3 100644 +--- a/src/mainboard/lenovo/x230/acpi/platform.asl ++++ b/src/mainboard/lenovo/x230/acpi/platform.asl +@@ -15,10 +15,6 @@ Method(_PTS,1) + + Method(_WAK,1) + { +- /* ME may not be up yet. */ +- \_TZ.MEB1 = 0 +- \_TZ.MEB2 = 0 +- + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + +diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl +index 33b6f80b17..1134782675 100644 +--- a/src/mainboard/lenovo/x230/dsdt.asl ++++ b/src/mainboard/lenovo/x230/dsdt.asl +@@ -3,7 +3,6 @@ + #define THINKPAD_EC_GPE 17 + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB + #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +-#define EC_LENOVO_H8_ME_WORKAROUND 1 + + #include <acpi/acpi.h> + DefinitionBlock( +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0040-ec-lenovo-Add-support-for-MEC1653-EC.patch b/config/coreboot/default/patches/0040-ec-lenovo-Add-support-for-MEC1653-EC.patch new file mode 100644 index 00000000..8972e90e --- /dev/null +++ b/config/coreboot/default/patches/0040-ec-lenovo-Add-support-for-MEC1653-EC.patch @@ -0,0 +1,371 @@ +From c88b371cb56046f79710143866562e119a8318ca Mon Sep 17 00:00:00 2001 +From: Matt DeVillier <matt.devillier@gmail.com> +Date: Fri, 11 Jul 2025 16:11:47 -0500 +Subject: [PATCH 40/43] ec/lenovo: Add support for MEC1653 EC + +Add support for the MEC1653 EC as used by the Thinkpad T480/480s. + +Change-Id: If82a7d27eb3163f51565c0c6e60cab60753611a7 +Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> +--- + src/ec/lenovo/mec1653/Kconfig | 11 ++ + src/ec/lenovo/mec1653/Makefile.mk | 8 ++ + src/ec/lenovo/mec1653/mec1653.c | 207 ++++++++++++++++++++++++++++++ + src/ec/lenovo/mec1653/mec1653.h | 98 ++++++++++++++ + 4 files changed, 324 insertions(+) + create mode 100644 src/ec/lenovo/mec1653/Kconfig + create mode 100644 src/ec/lenovo/mec1653/Makefile.mk + create mode 100644 src/ec/lenovo/mec1653/mec1653.c + create mode 100644 src/ec/lenovo/mec1653/mec1653.h + +diff --git a/src/ec/lenovo/mec1653/Kconfig b/src/ec/lenovo/mec1653/Kconfig +new file mode 100644 +index 0000000000..858f13897b +--- /dev/null ++++ b/src/ec/lenovo/mec1653/Kconfig +@@ -0,0 +1,11 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config EC_LENOVO_MEC1653 ++ bool ++ ++if EC_LENOVO_MEC1653 ++ ++config MEC1653_SEND_DEBUG_UNLOCK ++ bool ++ ++endif +diff --git a/src/ec/lenovo/mec1653/Makefile.mk b/src/ec/lenovo/mec1653/Makefile.mk +new file mode 100644 +index 0000000000..4cb4b20cbb +--- /dev/null ++++ b/src/ec/lenovo/mec1653/Makefile.mk +@@ -0,0 +1,8 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++ifeq ($(CONFIG_EC_LENOVO_MEC1653),y) ++ ++bootblock-y += mec1653.c ++ramstage-y += mec1653.c ++ ++endif +diff --git a/src/ec/lenovo/mec1653/mec1653.c b/src/ec/lenovo/mec1653/mec1653.c +new file mode 100644 +index 0000000000..098ae47425 +--- /dev/null ++++ b/src/ec/lenovo/mec1653/mec1653.c +@@ -0,0 +1,207 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <arch/io.h> ++#include "mec1653.h" ++ ++#define MICROCHIP_CONFIGURATION_ENTRY_KEY 0x55 ++#define MICROCHIP_CONFIGURATION_EXIT_KEY 0xaa ++ ++#define UART_PORT 0x3f8 ++#define UART_IRQ 4 ++ ++// RW unlock key for EC version N24HT37W ++const uint8_t debug_rw_key[8] = { 0x7a, 0x41, 0xb1, 0x49, 0xfe, 0x21, 0x01, 0xcf }; ++ ++void microchip_pnp_enter_conf_state(uint16_t port) ++{ ++ outb(MICROCHIP_CONFIGURATION_ENTRY_KEY, port); ++} ++ ++void microchip_pnp_exit_conf_state(uint16_t port) ++{ ++ outb(MICROCHIP_CONFIGURATION_EXIT_KEY, port); ++} ++ ++uint8_t pnp_read(uint16_t port, uint8_t index) ++{ ++ outb(index, port); ++ return inb(port + 1); ++} ++ ++uint32_t pnp_read_le32(uint16_t port, uint8_t index) ++{ ++ return (uint32_t) pnp_read(port, index) | ++ (uint32_t) pnp_read(port, index + 1) << 8 | ++ (uint32_t) pnp_read(port, index + 2) << 16 | ++ (uint32_t) pnp_read(port, index + 3) << 24; ++} ++ ++void pnp_write(uint16_t port, uint8_t index, uint8_t value) ++{ ++ outb(index, port); ++ outb(value, port + 1); ++} ++ ++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value) ++{ ++ pnp_write(port, index, value & 0xff); ++ pnp_write(port, index + 1, value >> 8 & 0xff); ++ pnp_write(port, index + 2, value >> 16 & 0xff); ++ pnp_write(port, index + 3, value >> 24 & 0xff); ++} ++ ++static void ecN_clear_out_queue(uint16_t cmd_port, uint16_t data_port) ++{ ++ while (inb(cmd_port) & EC_OBF) ++ inb(data_port); ++} ++ ++static void ecN_wait_to_send(uint16_t cmd_port, uint16_t data_port) ++{ ++ while (inb(cmd_port) & EC_IBF) ++ ; ++} ++ ++static void ecN_wait_to_recv(uint16_t cmd_port, uint16_t data_port) ++{ ++ while (!(inb(cmd_port) & EC_OBF)) ++ ; ++} ++ ++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr) ++{ ++ ecN_clear_out_queue(cmd_port, data_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(EC_READ, cmd_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(addr, data_port); ++ ecN_wait_to_recv(cmd_port, data_port); ++ return inb(data_port); ++} ++ ++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val) ++{ ++ ecN_clear_out_queue(cmd_port, data_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(EC_WRITE, cmd_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(addr, data_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(val, data_port); ++} ++ ++uint8_t eeprom_read(uint16_t addr) ++{ ++ ecN_clear_out_queue(EC2_CMD, EC2_DATA); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl(1, EC2_CMD); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl(addr, EC2_DATA); ++ ecN_wait_to_recv(EC2_CMD, EC2_DATA); ++ return inl(EC2_DATA); ++} ++ ++void eeprom_write(uint16_t addr, uint8_t val) ++{ ++ ecN_clear_out_queue(EC2_CMD, EC2_DATA); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl(2, EC2_CMD); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl((uint32_t) addr | (uint32_t) val << 16, EC2_DATA); ++ ecN_wait_to_recv(EC2_CMD, EC2_DATA); ++ inl(EC2_DATA); ++} ++ ++uint16_t debug_loaded_keys(void) ++{ ++ return (uint16_t) ec0_read(0x87) << 8 | (uint16_t) ec0_read(0x86); ++} ++ ++static void debug_cmd(uint8_t cmd) ++{ ++ ec0_write(EC_DEBUG_CMD, cmd); ++ while (ec0_read(EC_DEBUG_CMD) & 0x80) ++ ; ++} ++ ++void debug_read_key(uint8_t i, uint8_t *key) ++{ ++ debug_cmd(0x80 | (i & 0xf)); ++ for (int j = 0; j < 8; ++j) ++ key[j] = ec0_read(0x3e + j); ++} ++ ++void debug_write_key(uint8_t i, const uint8_t *key) ++{ ++ for (int j = 0; j < 8; ++j) ++ ec0_write(0x3e + j, key[j]); ++ debug_cmd(0xc0 | (i & 0xf)); ++} ++ ++uint32_t debug_read_dword(uint32_t addr) ++{ ++ ecN_clear_out_queue(EC3_CMD, EC3_DATA); ++ ecN_wait_to_send(EC3_CMD, EC3_DATA); ++ outl(addr << 8 | 0xE2, EC3_DATA); ++ ecN_wait_to_recv(EC3_CMD, EC3_DATA); ++ return inl(EC3_DATA); ++} ++ ++void debug_write_dword(uint32_t addr, uint32_t val) ++{ ++ ecN_clear_out_queue(EC3_CMD, EC3_DATA); ++ ecN_wait_to_send(EC3_CMD, EC3_DATA); ++ outl(addr << 8 | 0xEA, EC3_DATA); ++ ecN_wait_to_send(EC3_CMD, EC3_DATA); ++ outl(val, EC3_DATA); ++} ++ ++static void configure_uart(uint16_t port, uint16_t iobase, uint8_t irqno) ++{ ++ microchip_pnp_enter_conf_state(port); ++ ++ // Select LPC I/F LDN ++ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF); ++ // Write UART BAR ++ pnp_write_le32(port, LPCIF_BAR_UART, (uint32_t) iobase << 16 | 0x8707); ++ // Set SIRQ4 to UART ++ pnp_write(port, LPCIF_SIRQ(irqno), LDN_UART); ++ ++ // Configure UART LDN ++ pnp_write(port, PNP_LDN_SELECT, LDN_UART); ++ pnp_write(port, UART_ACTIVATE, 0x01); ++ pnp_write(port, UART_CONFIG_SELECT, 0x00); ++ ++ microchip_pnp_exit_conf_state(port); ++ ++ if (CONFIG(MEC1653_SEND_DEBUG_UNLOCK)) { ++ // Supply debug unlock key ++ debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key); ++ ++ // Use debug writes to set UART_TX and UART_RX GPIOs ++ debug_write_dword(0xf0c400 + 0x110, 0x00001000); ++ debug_write_dword(0xf0c400 + 0x114, 0x00001000); ++ } ++} ++ ++void bootblock_ec_init(void) ++{ ++ // Tell EC via BIOS Debug Port 1 that the world isn't on fire ++ ++ // Let the EC know that BIOS code is running ++ outb(0x11, 0x86); ++ outb(0x6e, 0x86); ++ ++ // Enable accesses to EC1 interface ++ ec0_write(0, ec0_read(0) | 0x20); ++ ++ // Reset LEDs to power on state ++ // (Without this warm reboot leaves LEDs off) ++ ec0_write(0x0c, 0x80); ++ ec0_write(0x0c, 0x07); ++ ec0_write(0x0c, 0x8a); ++ ++ // Setup debug UART ++ if (CONFIG(CONSOLE_SERIAL)) ++ configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ); ++} +diff --git a/src/ec/lenovo/mec1653/mec1653.h b/src/ec/lenovo/mec1653/mec1653.h +new file mode 100644 +index 0000000000..7dc4c1f635 +--- /dev/null ++++ b/src/ec/lenovo/mec1653/mec1653.h +@@ -0,0 +1,98 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef EC_LENOVO_MEC1653_H ++#define EC_LENOVO_MEC1653_H ++ ++// EC configuration base address ++#define EC_CFG_PORT 0x4e ++ ++// Chip global registers ++#define PNP_LDN_SELECT 0x07 ++# define LDN_UART 0x07 ++# define LDN_LPCIF 0x0c ++#define EC_DEVICE_ID 0x20 ++#define EC_DEVICE_REV 0x21 ++ ++// LPC I/F registers ++#define LPCIF_SIRQ(i) (0x40 + (i)) ++ ++#define LPCIF_BAR_CFG 0x60 ++#define LPCIF_BAR_MAILBOX 0x64 ++#define LPCIF_BAR_8042 0x68 ++#define LPCIF_BAR_ACPI_EC0 0x6c ++#define LPCIF_BAR_ACPI_EC1 0x70 ++#define LPCIF_BAR_ACPI_EC2 0x74 ++#define LPCIF_BAR_ACPI_EC3 0x78 ++#define LPCIF_BAR_ACPI_PM0 0x7c ++#define LPCIF_BAR_UART 0x80 ++#define LPCIF_BAR_FAST_KYBD 0x84 ++#define LPCIF_BAR_EMBED_FLASH 0x88 ++#define LPCIF_BAR_GP_SPI 0x8c ++#define LPCIF_BAR_EMI 0x90 ++#define LPCIF_BAR_PMH7 0x94 ++#define LPCIF_BAR_PORT80_DBG0 0x98 ++#define LPCIF_BAR_PORT80_DBG1 0x9c ++#define LPCIF_BAR_RTC 0xa0 ++ ++// UART registers ++#define UART_ACTIVATE 0x30 ++#define UART_CONFIG_SELECT 0xf0 ++ ++void microchip_pnp_enter_conf_state(uint16_t port); ++void microchip_pnp_exit_conf_state(uint16_t port); ++uint8_t pnp_read(uint16_t port, uint8_t index); ++uint32_t pnp_read_le32(uint16_t port, uint8_t index); ++void pnp_write(uint16_t port, uint8_t index, uint8_t value); ++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value); ++ ++#define EC0_CMD 0x0066 ++#define EC0_DATA 0x0062 ++#define EC1_CMD 0x1604 ++#define EC1_DATA 0x1600 ++#define EC2_CMD 0x1634 ++#define EC2_DATA 0x1630 ++#define EC3_CMD 0x161c ++#define EC3_DATA 0x1618 ++ ++#define EC_OBF (1 << 0) ++#define EC_IBF (1 << 1) ++ ++#define EC_READ 0x80 ++#define EC_WRITE 0x81 ++ ++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr); ++ ++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val); ++ ++// EC0 and EC1 mostly are useful with the READ/WRITE commands ++#define ec0_read(addr) ecN_read(EC0_CMD, EC0_DATA, addr) ++#define ec0_write(addr, val) ecN_write(EC0_CMD, EC0_DATA, addr, val) ++#define ec1_read(addr) ecN_read(EC1_CMD, EC1_DATA, addr) ++#define ec1_write(addr, val) ecN_write(EC1_CMD, EC1_DATA, addr, val) ++ ++// Read from the emulated EEPROM ++uint8_t eeprom_read(uint16_t addr); ++ ++// Write to the emulated EEPROM ++void eeprom_write(uint16_t addr, uint8_t val); ++ ++// Read loaded debug key mask ++uint16_t debug_loaded_keys(void); ++ ++// The following location (via either EC0 or EC1) can be used to interact with the debug interface ++#define EC_DEBUG_CMD 0x3d ++ ++void debug_read_key(uint8_t i, uint8_t *key); ++ ++void debug_write_key(uint8_t i, const uint8_t *key); ++ ++uint32_t debug_read_dword(uint32_t addr); ++ ++void debug_write_dword(uint32_t addr, uint32_t val); ++ ++// RW unlock key index ++#define DEBUG_RW_KEY_IDX 1 ++ ++void bootblock_ec_init(void); ++ ++#endif /* EC_LENOVO_MEC1653_H */ +-- +2.39.5 + diff --git a/config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch b/config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch deleted file mode 100644 index 2223ec46..00000000 --- a/config/coreboot/default/patches/0040-lenovo-t480-Drop-redundant-PcieRpEnable.patch +++ /dev/null @@ -1,113 +0,0 @@ -From eb71b55d2dd7af6f6ddca5e462fc228bdb04af50 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Tue, 8 Jul 2025 17:54:57 +0100 -Subject: [PATCH 1/1] lenovo/t480: Drop redundant PcieRpEnable - -This is in line with another change from upstream, in -the recent revision update: - -commit ee30558c49c9c4622277785ee0cd54c32720e489 -Author: Nico Huber <nico.h@gmx.de> -Date: Fri Jan 12 16:22:19 2024 +0100 - - soc/intel/skylake: Drop redundant PcieRpEnable - -This change is necessary, to prevent a build error. - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - .../lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb | 5 ----- - .../lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb | 5 ----- - 2 files changed, 10 deletions(-) - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb -index bf66bd3a69..316dbcbe8a 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb -@@ -43,7 +43,6 @@ chip soc/intel/skylake - - # dGPU - x4 - device ref pcie_rp1 on -- register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "0" - register "PcieRpClkSrcNumber[0]" = "0" -@@ -61,7 +60,6 @@ chip soc/intel/skylake - - # M.2 WLAN - x1 - device ref pcie_rp7 on -- register "PcieRpEnable[6]" = "1" - register "PcieRpClkReqSupport[6]" = "1" - register "PcieRpClkReqNumber[6]" = "2" - register "PcieRpClkSrcNumber[6]" = "2" -@@ -71,7 +69,6 @@ chip soc/intel/skylake - - # M.2 WWAN - x2 - device ref pcie_rp5 on -- register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "3" - register "PcieRpClkSrcNumber[4]" = "3" -@@ -81,7 +78,6 @@ chip soc/intel/skylake - - # TB3 (Alpine Ridge LP) - x2 - device ref pcie_rp9 on -- register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "4" - register "PcieRpClkSrcNumber[8]" = "4" -@@ -92,7 +88,6 @@ chip soc/intel/skylake - - # M.2 2280 caddy - x2 - device ref pcie_rp11 on -- register "PcieRpEnable[10]" = "1" - register "PcieRpClkReqSupport[10]" = "1" - register "PcieRpClkReqNumber[10]" = "5" - register "PcieRpClkSrcNumber[10]" = "5" -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -index d4afca20c4..dcaf15fabf 100644 ---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -@@ -43,7 +43,6 @@ chip soc/intel/skylake - - # dGPU - x2 - device ref pcie_rp1 on -- register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "0" - register "PcieRpClkSrcNumber[0]" = "0" -@@ -53,7 +52,6 @@ chip soc/intel/skylake - - # M.2 WWAN - x1 - device ref pcie_rp4 on -- register "PcieRpEnable[3]" = "1" - register "PcieRpClkReqSupport[3]" = "1" - register "PcieRpClkReqNumber[3]" = "1" - register "PcieRpClkSrcNumber[3]" = "1" -@@ -71,7 +69,6 @@ chip soc/intel/skylake - - # M.2 WLAN - x1 - device ref pcie_rp7 on -- register "PcieRpEnable[6]" = "1" - register "PcieRpClkReqSupport[6]" = "1" - register "PcieRpClkReqNumber[6]" = "3" - register "PcieRpClkSrcNumber[6]" = "3" -@@ -81,7 +78,6 @@ chip soc/intel/skylake - - # TB3 (Alpine Ridge LP) - x2 - device ref pcie_rp5 on -- register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "4" - register "PcieRpClkSrcNumber[4]" = "4" -@@ -92,7 +88,6 @@ chip soc/intel/skylake - - # M.2 2280 SSD - x2 - device ref pcie_rp9 on -- register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "5" - register "PcieRpClkSrcNumber[8]" = "5" --- -2.39.5 - diff --git a/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch b/config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch index 3b40298f..8f9d1d97 100644 --- a/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch +++ b/config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch @@ -1,7 +1,7 @@ -From a2f4492e8680d96f328846e3eba85d5aebec8d09 Mon Sep 17 00:00:00 2001 -From: Mate Kukri <km@mkukri.xyz> -Date: Tue, 31 Dec 2024 22:49:15 +0000 -Subject: [PATCH 28/41] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s +From 05d402ba24e80a164fc3f7332ef9086a4750d266 Mon Sep 17 00:00:00 2001 +From: Matt DeVillier <matt.devillier@gmail.com> +Date: Wed, 9 Jul 2025 12:28:48 -0500 +Subject: [PATCH 41/43] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s These machine have BootGuard fused and requires deguard to boot coreboot. @@ -17,37 +17,34 @@ Known issues: Thanks to Leah Rowe for helping with the T480s. -Signed-off-by: Mate Kukri <km@mkukri.xyz> Change-Id: I19d421412c771c1f242f6ff39453f824fa866163 +Signed-off-by: Mate Kukri <km@mkukri.xyz> +Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> --- - src/device/pci_rom.c | 4 +- - src/ec/lenovo/h8/acpi/ec.asl | 2 +- - src/ec/lenovo/h8/bluetooth.c | 6 +- - src/ec/lenovo/h8/wwan.c | 6 +- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 57 +++++ + src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 84 ++++++++ .../lenovo/sklkbl_thinkpad/Kconfig.name | 7 + - .../lenovo/sklkbl_thinkpad/Makefile.mk | 73 +++++++ + .../lenovo/sklkbl_thinkpad/Makefile.mk | 21 ++ .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 12 ++ .../lenovo/sklkbl_thinkpad/acpi/superio.asl | 3 + - .../lenovo/sklkbl_thinkpad/bootblock.c | 60 ++++++ - .../lenovo/sklkbl_thinkpad/devicetree.cb | 71 ++++++ + .../lenovo/sklkbl_thinkpad/board_info.txt | 6 + + .../lenovo/sklkbl_thinkpad/bootblock.c | 9 + + src/mainboard/lenovo/sklkbl_thinkpad/cfr.c | 82 +++++++ + .../lenovo/sklkbl_thinkpad/devicetree.cb | 78 +++++++ src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 33 +++ - src/mainboard/lenovo/sklkbl_thinkpad/ec.c | 153 +++++++++++++ - src/mainboard/lenovo/sklkbl_thinkpad/ec.h | 99 +++++++++ src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 + - .../lenovo/sklkbl_thinkpad/ramstage.c | 105 +++++++++ + .../lenovo/sklkbl_thinkpad/ramstage.c | 87 ++++++++ .../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes .../variants/t480/gma-mainboard.ads | 19 ++ .../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++ .../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++ .../variants/t480/memory_init_params.c | 20 ++ - .../variants/t480/overridetree.cb | 103 +++++++++ + .../variants/t480/overridetree.cb | 93 ++++++++ .../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes .../variants/t480s/gma-mainboard.ads | 19 ++ .../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++ .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++ .../variants/t480s/memory_init_params.c | 44 ++++ - .../variants/t480s/overridetree.cb | 103 +++++++++ + .../variants/t480s/overridetree.cb | 93 ++++++++ .../variants/t480s/spd/spd_0.bin | Bin 0 -> 512 bytes .../variants/t480s/spd/spd_1.bin | Bin 0 -> 512 bytes .../variants/t480s/spd/spd_10.bin | Bin 0 -> 512 bytes @@ -69,17 +66,17 @@ Change-Id: I19d421412c771c1f242f6ff39453f824fa866163 .../variants/t480s/spd/spd_7.bin | Bin 0 -> 512 bytes .../variants/t480s/spd/spd_8.bin | Bin 0 -> 512 bytes .../variants/t480s/spd/spd_9.bin | Bin 0 -> 512 bytes - 49 files changed, 1583 insertions(+), 6 deletions(-) + 45 files changed, 1300 insertions(+) create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/cfr.c create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.h create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt @@ -116,125 +113,28 @@ Change-Id: I19d421412c771c1f242f6ff39453f824fa866163 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin -diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c -index dc41ef14ce..bba98d9dea 100644 ---- a/src/device/pci_rom.c -+++ b/src/device/pci_rom.c -@@ -396,14 +396,16 @@ void pci_rom_ssdt(const struct device *device) - rom = cbrom; - } - -+#if 0 - const char *scope = acpi_device_path(device); - if (!scope) { - printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device)); - return; - } -+#endif - - /* write _ROM method */ -- acpigen_write_scope(scope); -+ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP"); - acpigen_write_rom((void *)rom, rom->size * 512); - acpigen_pop_len(); /* pop scope */ - } -diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl -index bc54d3b422..8f4a8e1986 100644 ---- a/src/ec/lenovo/h8/acpi/ec.asl -+++ b/src/ec/lenovo/h8/acpi/ec.asl -@@ -331,7 +331,7 @@ Device(EC) - #include "sleepbutton.asl" - #include "lid.asl" - #include "beep.asl" --#include "thermal.asl" -+//#include "thermal.asl" - #include "systemstatus.asl" - #include "thinkpad.asl" - } -diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c -index 16fc8dce39..be71a24ced 100644 ---- a/src/ec/lenovo/h8/bluetooth.c -+++ b/src/ec/lenovo/h8/bluetooth.c -@@ -1,6 +1,6 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ - --#include <southbridge/intel/common/gpio.h> -+// #include <southbridge/intel/common/gpio.h> - #include <console/console.h> - #include <device/device.h> - #include <ec/acpi/ec.h> -@@ -28,16 +28,18 @@ bool h8_has_bdc(const struct device *dev) - { - struct ec_lenovo_h8_config *conf = dev->chip_info; - -- if (!conf->has_bdc_detection) { -+ if (1 || !conf->has_bdc_detection) { - printk(BIOS_INFO, "H8: BDC detection not implemented. " - "Assuming BDC installed\n"); - return true; - } - -+#if 0 - if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) { - printk(BIOS_INFO, "H8: BDC installed\n"); - return true; - } -+#endif - - printk(BIOS_INFO, "H8: BDC not installed\n"); - return false; -diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c -index 685886fcce..5cdcf77406 100644 ---- a/src/ec/lenovo/h8/wwan.c -+++ b/src/ec/lenovo/h8/wwan.c -@@ -1,6 +1,6 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ - --#include <southbridge/intel/common/gpio.h> -+// #include <southbridge/intel/common/gpio.h> - #include <console/console.h> - #include <device/device.h> - #include <ec/acpi/ec.h> -@@ -26,16 +26,18 @@ bool h8_has_wwan(const struct device *dev) - { - struct ec_lenovo_h8_config *conf = dev->chip_info; - -- if (!conf->has_wwan_detection) { -+ if (1 || !conf->has_wwan_detection) { - printk(BIOS_INFO, "H8: WWAN detection not implemented. " - "Assuming WWAN installed\n"); - return true; - } - -+#if 0 - if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) { - printk(BIOS_INFO, "H8: WWAN installed\n"); - return true; - } -+#endif - - printk(BIOS_INFO, "H8: WWAN not installed\n"); - return false; diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig new file mode 100644 -index 0000000000..4998672943 +index 0000000000..ccf43ea5c0 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -0,0 +1,57 @@ +@@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + bool + select BOARD_ROMSIZE_KB_16384 ++ select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE + select EC_LENOVO_H8 ++ select EC_LENOVO_MEC1653 + select EC_LENOVO_PMH7 + select H8_HAS_BAT_THRESHOLDS_IMPL + select H8_HAS_LEDLOGO + select H8_HAS_PRIMARY_FN_KEYS ++ select H8_SUPPORT_BT_ON_WIFI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT -+ select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_GBE_REGION @@ -247,6 +147,7 @@ index 0000000000..4998672943 +config BOARD_LENOVO_T480 + bool + select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ select MEC1653_SEND_DEBUG_UNLOCK + +config BOARD_LENOVO_T480S + bool @@ -277,6 +178,30 @@ index 0000000000..4998672943 +config DIMM_SPD_SIZE + default 512 # DDR4 + ++config CONSOLE_SERIAL ++ default n ++ ++config NO_POST ++ default y ++ ++config EDK2_BOOT_MANAGER_ESCAPE ++ default y ++ ++config EDK2_FOLLOW_BGRT_SPEC ++ default y ++ ++config EDK2_FULL_SCREEN_SETUP ++ default n ++ ++config PS2K_EISAID ++ default "LEN0071" ++ ++config PS2M_EISAID ++ default "LEN0094" ++ ++config THINKPADEC_HKEY_EISAID ++ default "LEN0268" ++ +endif diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name new file mode 100644 @@ -293,83 +218,31 @@ index 0000000000..abc273f387 + bool "ThinkPad T480s" diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk new file mode 100644 -index 0000000000..c308239177 +index 0000000000..7122a232b4 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk -@@ -0,0 +1,73 @@ +@@ -0,0 +1,21 @@ +## SPDX-License-Identifier: GPL-2.0-only + -+bootblock-y += bootblock.c ec.c ++bootblock-y += bootblock.c + +romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c + -+ramstage-y += ramstage.c ec.c ++ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c ++ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads + -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_0.bin -+spd_0.bin-file := variants/$(VARIANT_DIR)/spd/spd_0.bin -+spd_0.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_1.bin -+spd_1.bin-file := variants/$(VARIANT_DIR)/spd/spd_1.bin -+spd_1.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_2.bin -+spd_2.bin-file := variants/$(VARIANT_DIR)/spd/spd_2.bin -+spd_2.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_3.bin -+spd_3.bin-file := variants/$(VARIANT_DIR)/spd/spd_3.bin -+spd_3.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_4.bin -+spd_4.bin-file := variants/$(VARIANT_DIR)/spd/spd_4.bin -+spd_4.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_5.bin -+spd_5.bin-file := variants/$(VARIANT_DIR)/spd/spd_5.bin -+spd_5.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_6.bin -+spd_6.bin-file := variants/$(VARIANT_DIR)/spd/spd_6.bin -+spd_6.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_7.bin -+spd_7.bin-file := variants/$(VARIANT_DIR)/spd/spd_7.bin -+spd_7.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_8.bin -+spd_8.bin-file := variants/$(VARIANT_DIR)/spd/spd_8.bin -+spd_8.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_9.bin -+spd_9.bin-file := variants/$(VARIANT_DIR)/spd/spd_9.bin -+spd_9.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_10.bin -+spd_10.bin-file := variants/$(VARIANT_DIR)/spd/spd_10.bin -+spd_10.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_11.bin -+spd_11.bin-file := variants/$(VARIANT_DIR)/spd/spd_11.bin -+spd_11.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_12.bin -+spd_12.bin-file := variants/$(VARIANT_DIR)/spd/spd_12.bin -+spd_12.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_13.bin -+spd_13.bin-file := variants/$(VARIANT_DIR)/spd/spd_13.bin -+spd_13.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_14.bin -+spd_14.bin-file := variants/$(VARIANT_DIR)/spd/spd_14.bin -+spd_14.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_15.bin -+spd_15.bin-file := variants/$(VARIANT_DIR)/spd/spd_15.bin -+spd_15.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_16.bin -+spd_16.bin-file := variants/$(VARIANT_DIR)/spd/spd_16.bin -+spd_16.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_17.bin -+spd_17.bin-file := variants/$(VARIANT_DIR)/spd/spd_17.bin -+spd_17.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_18.bin -+spd_18.bin-file := variants/$(VARIANT_DIR)/spd/spd_18.bin -+spd_18.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_19.bin -+spd_19.bin-file := variants/$(VARIANT_DIR)/spd/spd_19.bin -+spd_19.bin-type := raw -+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_20.bin -+spd_20.bin-file := variants/$(VARIANT_DIR)/spd/spd_20.bin -+spd_20.bin-type := raw ++# Add files spd_0.bin to spd_20.bin to the cbfs image ++ifeq ($(CONFIG_BOARD_LENOVO_T480S),y) ++SPD_BINS := $(shell seq 0 20) ++define SPD_template ++cbfs-files-y += spd_$(1).bin ++spd_$(1).bin-file := variants/$(VARIANT_DIR)/spd/spd_$(1).bin ++spd_$(1).bin-type := raw ++endef ++$(foreach n,$(SPD_BINS),$(eval $(call SPD_template,$(n)))) ++endif diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl new file mode 100644 index 0000000000..3a949a2fca @@ -397,92 +270,130 @@ index 0000000000..55b1db5b11 +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt b/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt +new file mode 100644 +index 0000000000..07ab6a3cd0 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt +@@ -0,0 +1,6 @@ ++Category: laptop ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2016 diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c new file mode 100644 -index 0000000000..fb660dbdfa +index 0000000000..e1fdf18add --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c -@@ -0,0 +1,60 @@ +@@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + -+#include <arch/io.h> +#include <bootblock_common.h> -+#include <device/pci.h> -+#include <soc/pci_devs.h> -+#include "ec.h" ++#include <ec/lenovo/mec1653/mec1653.h> + -+static void configure_uart(uint16_t port, uint16_t iobase, uint8_t irqno) ++void bootblock_mainboard_early_init(void) +{ -+ microchip_pnp_enter_conf_state(port); -+ -+ // Select LPC I/F LDN -+ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF); -+ // Write UART BAR -+ pnp_write_le32(port, LPCIF_BAR_UART, (uint32_t) iobase << 16 | 0x8707); -+ // Set SIRQ4 to UART -+ pnp_write(port, LPCIF_SIRQ(irqno), LDN_UART); -+ -+ // Configure UART LDN -+ pnp_write(port, PNP_LDN_SELECT, LDN_UART); -+ pnp_write(port, UART_ACTIVATE, 0x01); -+ pnp_write(port, UART_CONFIG_SELECT, 0x00); -+ -+ microchip_pnp_exit_conf_state(port); -+ -+#ifdef CONFIG_BOARD_LENOVO_T480 -+ // Supply debug unlock key -+ debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key); -+ -+ // Use debug writes to set UART_TX and UART_RX GPIOs -+ debug_write_dword(0xf0c400 + 0x110, 0x00001000); -+ debug_write_dword(0xf0c400 + 0x114, 0x00001000); -+#endif ++ bootblock_ec_init(); +} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c +new file mode 100644 +index 0000000000..45f344b939 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c +@@ -0,0 +1,82 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ + ++#include <boot/coreboot_tables.h> ++#include <drivers/option/cfr_frontend.h> ++#include <ec/lenovo/h8/cfr.h> ++#include <ec/lenovo/pmh7/cfr.h> ++#include <intelblocks/cfr.h> ++#include <soc/cfr.h> ++#include <static.h> + -+#define UART_PORT 0x3f8 -+#define UART_IRQ 4 -+ -+void bootblock_mainboard_early_init(void) ++/* Hide the dGPU CFR entry if dGPU not present */ ++static void update_dgpu(const struct sm_object *obj, struct sm_object *new) +{ -+ // Tell EC via BIOS Debug Port 1 that the world isn't on fire ++ struct device *dgpu = DEV_PTR(dgpu); ++ if (!dgpu || !dgpu->enabled) { ++ new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS; ++ } ++} + -+ // Let the EC know that BIOS code is running -+ outb(0x11, 0x86); -+ outb(0x6e, 0x86); ++/* dGPU */ ++static const struct sm_object dgpu = SM_DECLARE_ENUM({ ++ .opt_name = "dgpu_enable", ++ .ui_name = "dGPU", ++ .ui_helptext = "Enable or disable the dGPU", ++ .default_value = 0, ++ .values = (const struct sm_enum_value[]) { ++ { "Disabled", 0 }, ++ { "Enabled", 1 }, ++ SM_ENUM_VALUE_END }, ++}, WITH_CALLBACK(update_dgpu)); ++ ++static struct sm_obj_form system = { ++ .ui_name = "System", ++ .obj_list = (const struct sm_object *[]) { ++ &dgpu, ++ &hyper_threading, ++ &igd_dvmt, ++ &igd_aperture, ++ &legacy_8254_timer, ++ &me_state, ++ &me_state_counter, ++ &pciexp_aspm, ++ &pciexp_clk_pm, ++ &pciexp_l1ss, ++ &pciexp_speed, ++ &s0ix_enable, ++ &vtd, ++ NULL ++ }, ++}; + -+ // Enable accesses to EC1 interface -+ ec0_write(0, ec0_read(0) | 0x20); ++static struct sm_obj_form ec = { ++ .ui_name = "Embedded Controller", ++ .obj_list = (const struct sm_object *[]) { ++ &bluetooth, ++ &backlight, ++ &uwb, ++ &usb_always_on, ++ &volume, ++ &wlan, ++ &wwan, ++ &pm_beeps, ++ &battery_beep, ++ &fn_ctrl_swap, ++ &sticky_fn, ++ &f1_to_f12_as_primary, ++ &touchpad, ++ &trackpoint, ++ NULL ++ }, ++}; + -+ // Reset LEDs to power on state -+ // (Without this warm reboot leaves LEDs off) -+ ec0_write(0x0c, 0x80); -+ ec0_write(0x0c, 0x07); -+ ec0_write(0x0c, 0x8a); ++static struct sm_obj_form *sm_root[] = { ++ &ec, ++ &system, ++ NULL ++}; + -+ // Setup debug UART -+ configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ); ++void mb_cfr_setup_menu(struct lb_cfr *cfr_root) ++{ ++ cfr_write_setup_menu(cfr_root, sm_root); +} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb new file mode 100644 -index 0000000000..c07d4d53ca +index 0000000000..5ec7750025 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb -@@ -0,0 +1,71 @@ +@@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake -+ # IGD Displays -+ register "gfx" = "GMA_STATIC_DISPLAYS(0)" -+ -+ register "panel_cfg" = "{ -+ .up_delay_ms = 200, -+ .down_delay_ms = 50, -+ .cycle_delay_ms = 600, -+ .backlight_on_delay_ms = 1, -+ .backlight_off_delay_ms = 200, -+ .backlight_pwm_hz = 200, -+ }" + + # Power + register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -491,15 +402,33 @@ index 0000000000..c07d4d53ca + register "PmConfigSlpAMinAssert" = "3" # 2s + + device domain 0 on -+ device ref igpu on end ++ subsystemid 0x17aa 0x225d inherit ++ device ref igpu on ++ register "gfx" = "GMA_STATIC_DISPLAYS(0)" ++ register "panel_cfg" = "{ ++ .up_delay_ms = 200, ++ .down_delay_ms = 50, ++ .cycle_delay_ms = 600, ++ .backlight_on_delay_ms = 1, ++ .backlight_off_delay_ms = 200, ++ .backlight_pwm_hz = 200, ++ }" ++ end + device ref sa_thermal on end + device ref thermal on end + device ref south_xhci on end ++ device ref sata on ++ register "SataPortsEnable[2]" = "1" ++ register "SataPortsDevSlp[2]" = "1" ++ end + device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" ++ register "lpc_ioe" = "LPC_IOE_EC_4E_4F | ++ LPC_IOE_EC_62_66 | ++ LPC_IOE_KBC_60_64" + + chip ec/lenovo/pmh7 + register "backlight_enable" = "true" @@ -579,270 +508,6 @@ index 0000000000..aa4d4de2a6 + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.c b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c -new file mode 100644 -index 0000000000..adb6a60324 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c -@@ -0,0 +1,153 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <arch/io.h> -+#include "ec.h" -+ -+#define MICROCHIP_CONFIGURATION_ENTRY_KEY 0x55 -+#define MICROCHIP_CONFIGURATION_EXIT_KEY 0xaa -+ -+void microchip_pnp_enter_conf_state(uint16_t port) -+{ -+ outb(MICROCHIP_CONFIGURATION_ENTRY_KEY, port); -+} -+ -+void microchip_pnp_exit_conf_state(uint16_t port) -+{ -+ outb(MICROCHIP_CONFIGURATION_EXIT_KEY, port); -+} -+ -+uint8_t pnp_read(uint16_t port, uint8_t index) -+{ -+ outb(index, port); -+ return inb(port + 1); -+} -+ -+uint32_t pnp_read_le32(uint16_t port, uint8_t index) -+{ -+ return (uint32_t) pnp_read(port, index) | -+ (uint32_t) pnp_read(port, index + 1) << 8 | -+ (uint32_t) pnp_read(port, index + 2) << 16 | -+ (uint32_t) pnp_read(port, index + 3) << 24; -+} -+ -+void pnp_write(uint16_t port, uint8_t index, uint8_t value) -+{ -+ outb(index, port); -+ outb(value, port + 1); -+} -+ -+void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value) -+{ -+ pnp_write(port, index, value & 0xff); -+ pnp_write(port, index + 1, value >> 8 & 0xff); -+ pnp_write(port, index + 2, value >> 16 & 0xff); -+ pnp_write(port, index + 3, value >> 24 & 0xff); -+} -+ -+static void ecN_clear_out_queue(uint16_t cmd_port, uint16_t data_port) -+{ -+ while (inb(cmd_port) & EC_OBF) -+ inb(data_port); -+} -+ -+static void ecN_wait_to_send(uint16_t cmd_port, uint16_t data_port) -+{ -+ while (inb(cmd_port) & EC_IBF) -+ ; -+} -+ -+static void ecN_wait_to_recv(uint16_t cmd_port, uint16_t data_port) -+{ -+ while (!(inb(cmd_port) & EC_OBF)) -+ ; -+} -+ -+uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr) -+{ -+ ecN_clear_out_queue(cmd_port, data_port); -+ ecN_wait_to_send(cmd_port, data_port); -+ outb(EC_READ, cmd_port); -+ ecN_wait_to_send(cmd_port, data_port); -+ outb(addr, data_port); -+ ecN_wait_to_recv(cmd_port, data_port); -+ return inb(data_port); -+} -+ -+void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val) -+{ -+ ecN_clear_out_queue(cmd_port, data_port); -+ ecN_wait_to_send(cmd_port, data_port); -+ outb(EC_WRITE, cmd_port); -+ ecN_wait_to_send(cmd_port, data_port); -+ outb(addr, data_port); -+ ecN_wait_to_send(cmd_port, data_port); -+ outb(val, data_port); -+} -+ -+uint8_t eeprom_read(uint16_t addr) -+{ -+ ecN_clear_out_queue(EC2_CMD, EC2_DATA); -+ ecN_wait_to_send(EC2_CMD, EC2_DATA); -+ outl(1, EC2_CMD); -+ ecN_wait_to_send(EC2_CMD, EC2_DATA); -+ outl(addr, EC2_DATA); -+ ecN_wait_to_recv(EC2_CMD, EC2_DATA); -+ return inl(EC2_DATA); -+} -+ -+void eeprom_write(uint16_t addr, uint8_t val) -+{ -+ ecN_clear_out_queue(EC2_CMD, EC2_DATA); -+ ecN_wait_to_send(EC2_CMD, EC2_DATA); -+ outl(2, EC2_CMD); -+ ecN_wait_to_send(EC2_CMD, EC2_DATA); -+ outl((uint32_t) addr | (uint32_t) val << 16, EC2_DATA); -+ ecN_wait_to_recv(EC2_CMD, EC2_DATA); -+ inl(EC2_DATA); -+} -+ -+uint16_t debug_loaded_keys(void) -+{ -+ return (uint16_t) ec0_read(0x87) << 8 | (uint16_t) ec0_read(0x86); -+} -+ -+static void debug_cmd(uint8_t cmd) -+{ -+ ec0_write(EC_DEBUG_CMD, cmd); -+ while (ec0_read(EC_DEBUG_CMD) & 0x80) -+ ; -+} -+ -+void debug_read_key(uint8_t i, uint8_t *key) -+{ -+ debug_cmd(0x80 | (i & 0xf)); -+ for (int j = 0; j < 8; ++j) -+ key[j] = ec0_read(0x3e + j); -+} -+ -+void debug_write_key(uint8_t i, const uint8_t *key) -+{ -+ for (int j = 0; j < 8; ++j) -+ ec0_write(0x3e + j, key[j]); -+ debug_cmd(0xc0 | (i & 0xf)); -+} -+ -+uint32_t debug_read_dword(uint32_t addr) -+{ -+ ecN_clear_out_queue(EC3_CMD, EC3_DATA); -+ ecN_wait_to_send(EC3_CMD, EC3_DATA); -+ outl(addr << 8 | 0xE2, EC3_DATA); -+ ecN_wait_to_recv(EC3_CMD, EC3_DATA); -+ return inl(EC3_DATA); -+} -+ -+void debug_write_dword(uint32_t addr, uint32_t val) -+{ -+ ecN_clear_out_queue(EC3_CMD, EC3_DATA); -+ ecN_wait_to_send(EC3_CMD, EC3_DATA); -+ outl(addr << 8 | 0xEA, EC3_DATA); -+ ecN_wait_to_send(EC3_CMD, EC3_DATA); -+ outl(val, EC3_DATA); -+} -+ -+const uint8_t debug_rw_key[8] = { 0x7a, 0x41, 0xb1, 0x49, 0xfe, 0x21, 0x01, 0xcf }; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.h b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h -new file mode 100644 -index 0000000000..d2963c8962 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h -@@ -0,0 +1,99 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef SKLKBL_THINKPAD_EC_H -+#define SKLKBL_THINKPAD_EC_H -+ -+// EC configuration base address -+#define EC_CFG_PORT 0x4e -+ -+// Chip global registers -+#define PNP_LDN_SELECT 0x07 -+# define LDN_UART 0x07 -+# define LDN_LPCIF 0x0c -+#define EC_DEVICE_ID 0x20 -+#define EC_DEVICE_REV 0x21 -+ -+// LPC I/F registers -+#define LPCIF_SIRQ(i) (0x40 + (i)) -+ -+#define LPCIF_BAR_CFG 0x60 -+#define LPCIF_BAR_MAILBOX 0x64 -+#define LPCIF_BAR_8042 0x68 -+#define LPCIF_BAR_ACPI_EC0 0x6c -+#define LPCIF_BAR_ACPI_EC1 0x70 -+#define LPCIF_BAR_ACPI_EC2 0x74 -+#define LPCIF_BAR_ACPI_EC3 0x78 -+#define LPCIF_BAR_ACPI_PM0 0x7c -+#define LPCIF_BAR_UART 0x80 -+#define LPCIF_BAR_FAST_KYBD 0x84 -+#define LPCIF_BAR_EMBED_FLASH 0x88 -+#define LPCIF_BAR_GP_SPI 0x8c -+#define LPCIF_BAR_EMI 0x90 -+#define LPCIF_BAR_PMH7 0x94 -+#define LPCIF_BAR_PORT80_DBG0 0x98 -+#define LPCIF_BAR_PORT80_DBG1 0x9c -+#define LPCIF_BAR_RTC 0xa0 -+ -+// UART registers -+#define UART_ACTIVATE 0x30 -+#define UART_CONFIG_SELECT 0xf0 -+ -+void microchip_pnp_enter_conf_state(uint16_t port); -+void microchip_pnp_exit_conf_state(uint16_t port); -+uint8_t pnp_read(uint16_t port, uint8_t index); -+uint32_t pnp_read_le32(uint16_t port, uint8_t index); -+void pnp_write(uint16_t port, uint8_t index, uint8_t value); -+void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value); -+ -+#define EC0_CMD 0x0066 -+#define EC0_DATA 0x0062 -+#define EC1_CMD 0x1604 -+#define EC1_DATA 0x1600 -+#define EC2_CMD 0x1634 -+#define EC2_DATA 0x1630 -+#define EC3_CMD 0x161c -+#define EC3_DATA 0x1618 -+ -+#define EC_OBF (1 << 0) -+#define EC_IBF (1 << 1) -+ -+#define EC_READ 0x80 -+#define EC_WRITE 0x81 -+ -+uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr); -+ -+void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val); -+ -+// EC0 and EC1 mostly are useful with the READ/WRITE commands -+#define ec0_read(addr) ecN_read(EC0_CMD, EC0_DATA, addr) -+#define ec0_write(addr, val) ecN_write(EC0_CMD, EC0_DATA, addr, val) -+#define ec1_read(addr) ecN_read(EC1_CMD, EC1_DATA, addr) -+#define ec1_write(addr, val) ecN_write(EC1_CMD, EC1_DATA, addr, val) -+ -+// Read from the emulated EEPROM -+uint8_t eeprom_read(uint16_t addr); -+ -+// Write to the emulated EEPROM -+void eeprom_write(uint16_t addr, uint8_t val); -+ -+// Read loaded debug key mask -+uint16_t debug_loaded_keys(void); -+ -+// The following location (via either EC0 or EC1) can be used to interact with the debug interface -+#define EC_DEBUG_CMD 0x3d -+ -+void debug_read_key(uint8_t i, uint8_t *key); -+ -+void debug_write_key(uint8_t i, const uint8_t *key); -+ -+uint32_t debug_read_dword(uint32_t addr); -+ -+void debug_write_dword(uint32_t addr, uint32_t val); -+ -+// RW unlock key index -+#define DEBUG_RW_KEY_IDX 1 -+ -+// RW unlock key for EC version N24HT37W -+extern const uint8_t debug_rw_key[8]; -+ -+#endif diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h new file mode 100644 index 0000000000..d89ed712d4 @@ -859,18 +524,19 @@ index 0000000000..d89ed712d4 +#endif diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c new file mode 100644 -index 0000000000..44c8578852 +index 0000000000..eb582a7948 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c -@@ -0,0 +1,105 @@ +@@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + -+#include <arch/io.h> ++#include <acpi/acpigen.h> ++#include <console/console.h> +#include <device/device.h> -+#include <drivers/intel/gma/int15.h> ++#include <device/pci_rom.h> +#include <option.h> +#include <soc/ramstage.h> -+#include "ec.h" ++#include <static.h> +#include "gpio.h" + +#define GPIO_GPU_RST GPP_E22 // active low @@ -884,13 +550,38 @@ index 0000000000..44c8578852 + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ ++ // Setup GPIOs ++ variant_config_gpios(); ++} ++ ++static void mainboard_fill_ssdt(const struct device *dev) ++{ ++ struct rom_header *rom; ++ struct device *dgpu = DEV_PTR(dgpu); ++ ++ /* Add entry for dGPU if present/enabled */ ++ if (!dgpu || !dgpu->enabled) ++ return; ++ ++ /* ROM should be already loaded? */ ++ rom = dgpu->pci_vga_option_rom; ++ if (!rom) { ++ rom = pci_rom_probe(dgpu); ++ if (!pci_rom_load(dgpu, rom)) ++ return; ++ } ++ ++ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP"); ++ acpigen_write_rom((void *)rom, rom->size * 512); ++ acpigen_pop_len(); ++} ++ ++static void dgpu_detect(void) ++{ + static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" }; + + int dgfx_vram_id; + -+ // Setup GPIOs -+ variant_config_gpios(); -+ + // Detect and enable dGPU + if (gpio_get(GPIO_DISCRETE_PRESENCE) == 0) { // active low + dgfx_vram_id = gpio_get(GPIO_DGFX_VRAM_ID0) | gpio_get(GPIO_DGFX_VRAM_ID1) << 1; @@ -914,59 +605,15 @@ index 0000000000..44c8578852 + } +} + -+static void dump_ec_cfg(uint16_t port) -+{ -+ microchip_pnp_enter_conf_state(port); -+ -+ // Device info -+ printk(BIOS_DEBUG, "Device id %02x\n", pnp_read(port, EC_DEVICE_ID)); -+ printk(BIOS_DEBUG, "Device rev %02x\n", pnp_read(port, EC_DEVICE_REV)); -+ -+ // Switch to LPCIF LDN -+ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF); -+ -+ // Dump SIRQs -+ for (int i = 0; i <= 15; i += 1) -+ printk(BIOS_DEBUG, "SIRQ%d = %02x\n", i, pnp_read(port, LPCIF_SIRQ(i))); -+ -+ // Dump BARs -+ printk(BIOS_DEBUG, "BAR CFG = %08x\n", pnp_read_le32(port, LPCIF_BAR_CFG)); -+ printk(BIOS_DEBUG, "BAR MAILBOX = %08x\n", pnp_read_le32(port, LPCIF_BAR_MAILBOX)); -+ printk(BIOS_DEBUG, "BAR 8042 = %08x\n", pnp_read_le32(port, LPCIF_BAR_8042)); -+ printk(BIOS_DEBUG, "BAR ACPI_EC0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC0)); -+ printk(BIOS_DEBUG, "BAR ACPI_EC1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC1)); -+ printk(BIOS_DEBUG, "BAR ACPI_EC2 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC2)); -+ printk(BIOS_DEBUG, "BAR ACPI_EC3 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC3)); -+ printk(BIOS_DEBUG, "BAR ACPI_PM0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_PM0)); -+ printk(BIOS_DEBUG, "BAR UART = %08x\n", pnp_read_le32(port, LPCIF_BAR_UART)); -+ printk(BIOS_DEBUG, "BAR FAST_KYBD = %08x\n", pnp_read_le32(port, LPCIF_BAR_FAST_KYBD)); -+ printk(BIOS_DEBUG, "BAR EMBED_FLASH = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMBED_FLASH)); -+ printk(BIOS_DEBUG, "BAR GP_SPI = %08x\n", pnp_read_le32(port, LPCIF_BAR_GP_SPI)); -+ printk(BIOS_DEBUG, "BAR EMI = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMI)); -+ printk(BIOS_DEBUG, "BAR PMH7 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PMH7)); -+ printk(BIOS_DEBUG, "BAR PORT80_DBG0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG0)); -+ printk(BIOS_DEBUG, "BAR PORT80_DBG1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG1)); -+ printk(BIOS_DEBUG, "BAR RTC = %08x\n", pnp_read_le32(port, LPCIF_BAR_RTC)); -+ -+ microchip_pnp_exit_conf_state(port); -+} -+ +static void mainboard_enable(struct device *dev) +{ -+ if (CONFIG(VGA_ROM_RUN)) -+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, -+ GMA_INT15_PANEL_FIT_DEFAULT, -+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -+} ++ dgpu_detect(); + -+static void mainboard_init(void *chip_info) -+{ -+ dump_ec_cfg(EC_CFG_PORT); ++ dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, -+ .init = mainboard_init, +}; diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt new file mode 100644 @@ -1361,10 +1008,10 @@ index 0000000000..5252a402f9 +} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb new file mode 100644 -index 0000000000..bf66bd3a69 +index 0000000000..9acb823c10 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb -@@ -0,0 +1,103 @@ +@@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake @@ -1390,12 +1037,6 @@ index 0000000000..bf66bd3a69 + }" + end + -+ device ref sata on -+ # SATA_2 - JHDD1 SATA SSD -+ register "SataPortsEnable[2]" = "1" -+ register "SataPortsDevSlp[2]" = "1" -+ end -+ + # PCIe controller 1 - 1x4 + # PCIE 1-4 - RP1 - dGPU - CLKOUT0 - CLKREQ0 + # @@ -1410,12 +1051,12 @@ index 0000000000..bf66bd3a69 + + # dGPU - x4 + device ref pcie_rp1 on -+ register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" ++ device generic 0 alias dgpu on end + end + + # Ethernet (clobbers RP8) @@ -1428,7 +1069,6 @@ index 0000000000..bf66bd3a69 + + # M.2 WLAN - x1 + device ref pcie_rp7 on -+ register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "2" + register "PcieRpClkSrcNumber[6]" = "2" @@ -1438,7 +1078,6 @@ index 0000000000..bf66bd3a69 + + # M.2 WWAN - x2 + device ref pcie_rp5 on -+ register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" @@ -1448,7 +1087,6 @@ index 0000000000..bf66bd3a69 + + # TB3 (Alpine Ridge LP) - x2 + device ref pcie_rp9 on -+ register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + register "PcieRpClkSrcNumber[8]" = "4" @@ -1459,7 +1097,6 @@ index 0000000000..bf66bd3a69 + + # M.2 2280 caddy - x2 + device ref pcie_rp11 on -+ register "PcieRpEnable[10]" = "1" + register "PcieRpClkReqSupport[10]" = "1" + register "PcieRpClkReqNumber[10]" = "5" + register "PcieRpClkSrcNumber[10]" = "5" @@ -1881,10 +1518,10 @@ index 0000000000..001e934b3a +} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb new file mode 100644 -index 0000000000..d4afca20c4 +index 0000000000..14fcf371c7 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -@@ -0,0 +1,103 @@ +@@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake @@ -1910,12 +1547,6 @@ index 0000000000..d4afca20c4 + }" + end + -+ device ref sata on -+ # SATA_2 - Main M.2 SATA SSD -+ register "SataPortsEnable[2]" = "1" -+ register "SataPortsDevSlp[2]" = "1" -+ end -+ + # PCIe controller 1 - 1x2+2x1 + # PCIE 1-2 - RP1 - dGPU - CLKOUT0 - CLKREQ0 + # PCIE 4 - RP4 - WWAN - CLKOUT1 - CLKREQ1 @@ -1930,17 +1561,16 @@ index 0000000000..d4afca20c4 + + # dGPU - x2 + device ref pcie_rp1 on -+ register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" ++ device generic 0 alias dgpu on end + end + + # M.2 WWAN - x1 + device ref pcie_rp4 on -+ register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" @@ -1958,7 +1588,6 @@ index 0000000000..d4afca20c4 + + # M.2 WLAN - x1 + device ref pcie_rp7 on -+ register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "3" + register "PcieRpClkSrcNumber[6]" = "3" @@ -1968,7 +1597,6 @@ index 0000000000..d4afca20c4 + + # TB3 (Alpine Ridge LP) - x2 + device ref pcie_rp5 on -+ register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "4" + register "PcieRpClkSrcNumber[4]" = "4" @@ -1979,7 +1607,6 @@ index 0000000000..d4afca20c4 + + # M.2 2280 SSD - x2 + device ref pcie_rp9 on -+ register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" diff --git a/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0042-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch index dd566a37..2d6c13b0 100644 --- a/config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch +++ b/config/coreboot/default/patches/0042-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -1,7 +1,7 @@ -From 17791a403c7887c9b48eab578e3bf977d9ba84a3 Mon Sep 17 00:00:00 2001 +From 8109392f8998878939c942f2608cf8c7ece5847a Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 18 Dec 2024 02:06:18 +0000 -Subject: [PATCH 32/41] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN +Subject: [PATCH 42/43] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN This is used by lbmk to know where a tb.bin file goes, when extracting and padding TBT.bin from Lenovo ThunderBolt diff --git a/config/coreboot/default/patches/0037-Conditional-TBFW-setting-for-T480-T480S.patch b/config/coreboot/default/patches/0043-Conditional-TBFW-setting-for-T480-T480S.patch index fbe70b0d..bf2d7637 100644 --- a/config/coreboot/default/patches/0037-Conditional-TBFW-setting-for-T480-T480S.patch +++ b/config/coreboot/default/patches/0043-Conditional-TBFW-setting-for-T480-T480S.patch @@ -1,7 +1,7 @@ -From 3b6c8e02eba287727b3abc96ffe5612f28c27df3 Mon Sep 17 00:00:00 2001 +From 951040d7f9193c90e707988a2e7a043a2ba942e7 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 05:14:45 +0100 -Subject: [PATCH 37/41] Conditional TBFW setting for T480/T480S +Subject: [PATCH 43/43] Conditional TBFW setting for T480/T480S Otherwise, other boards will define it, which might trigger the vendor download script, and diff --git a/config/coreboot/default/target.cfg b/config/coreboot/default/target.cfg index c84cd896..7c6bf44e 100644 --- a/config/coreboot/default/target.cfg +++ b/config/coreboot/default/target.cfg @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-3.0-or-later tree="default" -rev="812d0e2f626dfea7e7deb960a8dc08ff0e026bc1" +rev="8b52167a9f7d31a009b123e152c5c62dcf0a5202" diff --git a/config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb index fcd29012..e734dadb 100644 --- a/config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb @@ -173,6 +173,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode b/config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode index 009b7345..517ad32d 100644 --- a/config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode @@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb b/config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb index 8f767a60..7b953cff 100644 --- a/config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb @@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode b/config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode index d2d0e504..d9be7fdf 100644 --- a/config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode @@ -169,6 +169,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb index fe8f0fa2..ef2bd843 100644 --- a/config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb @@ -170,6 +170,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode b/config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode index 92515c07..0df99d3c 100644 --- a/config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode @@ -168,6 +168,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8200sff_4mb/config/libgfxinit_corebootfb b/config/coreboot/hp8200sff_4mb/config/libgfxinit_corebootfb index 90d25c44..ef110ae5 100644 --- a/config/coreboot/hp8200sff_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8200sff_4mb/config/libgfxinit_corebootfb @@ -173,6 +173,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8200sff_4mb/config/libgfxinit_txtmode b/config/coreboot/hp8200sff_4mb/config/libgfxinit_txtmode index 88435fa2..0df68553 100644 --- a/config/coreboot/hp8200sff_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8200sff_4mb/config/libgfxinit_txtmode @@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8200sff_8mb/config/libgfxinit_corebootfb b/config/coreboot/hp8200sff_8mb/config/libgfxinit_corebootfb index e1ef6986..4a46ba5b 100644 --- a/config/coreboot/hp8200sff_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8200sff_8mb/config/libgfxinit_corebootfb @@ -173,6 +173,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8200sff_8mb/config/libgfxinit_txtmode b/config/coreboot/hp8200sff_8mb/config/libgfxinit_txtmode index 0c9caa1c..6295a22b 100644 --- a/config/coreboot/hp8200sff_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8200sff_8mb/config/libgfxinit_txtmode @@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp820g2_12mb/config/libgfxinit_corebootfb b/config/coreboot/hp820g2_12mb/config/libgfxinit_corebootfb index 15569ec1..bef0f52e 100644 --- a/config/coreboot/hp820g2_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp820g2_12mb/config/libgfxinit_corebootfb @@ -169,6 +169,7 @@ CONFIG_PCIEXP_AER=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set CONFIG_BOARD_HP_ELITEBOOK_820_G2=y diff --git a/config/coreboot/hp820g2_12mb/config/libgfxinit_txtmode b/config/coreboot/hp820g2_12mb/config/libgfxinit_txtmode index 69692fcd..9ddee822 100644 --- a/config/coreboot/hp820g2_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp820g2_12mb/config/libgfxinit_txtmode @@ -167,6 +167,7 @@ CONFIG_PCIEXP_AER=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set CONFIG_BOARD_HP_ELITEBOOK_820_G2=y diff --git a/config/coreboot/hp8300cmt_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp8300cmt_16mb/config/libgfxinit_corebootfb index d7a98a79..3f83d6ab 100644 --- a/config/coreboot/hp8300cmt_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8300cmt_16mb/config/libgfxinit_corebootfb @@ -172,6 +172,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT=y # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8300cmt_16mb/config/libgfxinit_txtmode b/config/coreboot/hp8300cmt_16mb/config/libgfxinit_txtmode index 931f9848..814275e7 100644 --- a/config/coreboot/hp8300cmt_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8300cmt_16mb/config/libgfxinit_txtmode @@ -170,6 +170,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT=y # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8300usdt_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp8300usdt_16mb/config/libgfxinit_corebootfb index 970c7ab7..64dc2901 100644 --- a/config/coreboot/hp8300usdt_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8300usdt_16mb/config/libgfxinit_corebootfb @@ -172,6 +172,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8300usdt_16mb/config/libgfxinit_txtmode b/config/coreboot/hp8300usdt_16mb/config/libgfxinit_txtmode index 17bccd0e..9330e338 100644 --- a/config/coreboot/hp8300usdt_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8300usdt_16mb/config/libgfxinit_txtmode @@ -170,6 +170,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8460pintel_8mb/config/libgfxinit_corebootfb b/config/coreboot/hp8460pintel_8mb/config/libgfxinit_corebootfb index 6760785c..31b9d737 100644 --- a/config/coreboot/hp8460pintel_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8460pintel_8mb/config/libgfxinit_corebootfb @@ -173,6 +173,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8460pintel_8mb/config/libgfxinit_txtmode b/config/coreboot/hp8460pintel_8mb/config/libgfxinit_txtmode index 0104743b..e24295f3 100644 --- a/config/coreboot/hp8460pintel_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8460pintel_8mb/config/libgfxinit_txtmode @@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8470pintel_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp8470pintel_16mb/config/libgfxinit_corebootfb index a380ee28..5a472c2a 100644 --- a/config/coreboot/hp8470pintel_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp8470pintel_16mb/config/libgfxinit_corebootfb @@ -172,6 +172,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8470pintel_16mb/config/libgfxinit_txtmode b/config/coreboot/hp8470pintel_16mb/config/libgfxinit_txtmode index 257a7e7e..19127844 100644 --- a/config/coreboot/hp8470pintel_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp8470pintel_16mb/config/libgfxinit_txtmode @@ -170,6 +170,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp8560w_8mb/config/normal b/config/coreboot/hp8560w_8mb/config/normal index 7652a564..4c1cc1b9 100644 --- a/config/coreboot/hp8560w_8mb/config/normal +++ b/config/coreboot/hp8560w_8mb/config/normal @@ -169,6 +169,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp9470m_16mb/config/libgfxinit_corebootfb b/config/coreboot/hp9470m_16mb/config/libgfxinit_corebootfb index 789633f0..e931b384 100644 --- a/config/coreboot/hp9470m_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hp9470m_16mb/config/libgfxinit_corebootfb @@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hp9470m_16mb/config/libgfxinit_txtmode b/config/coreboot/hp9470m_16mb/config/libgfxinit_txtmode index 90c7d32d..5b5acc17 100644 --- a/config/coreboot/hp9470m_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/hp9470m_16mb/config/libgfxinit_txtmode @@ -169,6 +169,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb b/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb index e01a0f5d..c6c8596c 100644 --- a/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/hppro3500series_8mb/config/libgfxinit_corebootfb @@ -168,6 +168,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode b/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode index a9358a5e..6aaf9cfe 100644 --- a/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/hppro3500series_8mb/config/libgfxinit_txtmode @@ -166,6 +166,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_HP_260_G1_DM is not set # CONFIG_BOARD_HP_280_G2 is not set # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set diff --git a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb index e4de2ae7..f4dd091b 100644 --- a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r400_16mb/config/libgfxinit_txtmode b/config/coreboot/r400_16mb/config/libgfxinit_txtmode index 76f734e9..cefb2e7f 100644 --- a/config/coreboot/r400_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_16mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb index 77201d6f..3406c4f8 100644 --- a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r400_4mb/config/libgfxinit_txtmode b/config/coreboot/r400_4mb/config/libgfxinit_txtmode index bfe81488..b0aecef9 100644 --- a/config/coreboot/r400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_4mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb index 07f12819..73ea948f 100644 --- a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r400_8mb/config/libgfxinit_txtmode b/config/coreboot/r400_8mb/config/libgfxinit_txtmode index ca9843c4..856780d3 100644 --- a/config/coreboot/r400_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_8mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb index ccb870a7..5969b55b 100644 --- a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb @@ -378,6 +378,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/r500_4mb/config/libgfxinit_txtmode b/config/coreboot/r500_4mb/config/libgfxinit_txtmode index 41cf6001..5bae0f85 100644 --- a/config/coreboot/r500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/r500_4mb/config/libgfxinit_txtmode @@ -376,6 +376,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb index 5ea07cc3..b04c8531 100644 --- a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_16mb/config/libgfxinit_txtmode b/config/coreboot/t400_16mb/config/libgfxinit_txtmode index f37428d4..61d4040b 100644 --- a/config/coreboot/t400_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_16mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb index 1f8c824f..d6f80065 100644 --- a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_4mb/config/libgfxinit_txtmode b/config/coreboot/t400_4mb/config/libgfxinit_txtmode index 53641b72..2e878426 100644 --- a/config/coreboot/t400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_4mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb index d62c8a54..b3c9a4fc 100644 --- a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t400_8mb/config/libgfxinit_txtmode b/config/coreboot/t400_8mb/config/libgfxinit_txtmode index c9cd21d1..d47db263 100644 --- a/config/coreboot/t400_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_8mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t420_8mb/config/libgfxinit_corebootfb b/config/coreboot/t420_8mb/config/libgfxinit_corebootfb index a780deb7..eeed98c6 100644 --- a/config/coreboot/t420_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t420_8mb/config/libgfxinit_corebootfb @@ -395,6 +395,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t420_8mb/config/libgfxinit_txtmode b/config/coreboot/t420_8mb/config/libgfxinit_txtmode index 44c4a8a4..46d361f3 100644 --- a/config/coreboot/t420_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t420_8mb/config/libgfxinit_txtmode @@ -393,6 +393,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb b/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb index 589c472f..ba181603 100644 --- a/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb @@ -395,6 +395,7 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t420s_8mb/config/libgfxinit_txtmode b/config/coreboot/t420s_8mb/config/libgfxinit_txtmode index ead84d30..b3286dfb 100644 --- a/config/coreboot/t420s_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t420s_8mb/config/libgfxinit_txtmode @@ -393,6 +393,7 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t430_12mb/config/libgfxinit_corebootfb b/config/coreboot/t430_12mb/config/libgfxinit_corebootfb index ca288aa5..18be2432 100644 --- a/config/coreboot/t430_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t430_12mb/config/libgfxinit_corebootfb @@ -395,6 +395,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t430_12mb/config/libgfxinit_txtmode b/config/coreboot/t430_12mb/config/libgfxinit_txtmode index f180cd85..e5753d98 100644 --- a/config/coreboot/t430_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t430_12mb/config/libgfxinit_txtmode @@ -393,6 +393,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t480_vfsp_16mb/config/libgfxinit_corebootfb b/config/coreboot/t480_vfsp_16mb/config/libgfxinit_corebootfb index 84d1ff80..af19a3c5 100644 --- a/config/coreboot/t480_vfsp_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t480_vfsp_16mb/config/libgfxinit_corebootfb @@ -216,11 +216,13 @@ CONFIG_BOARD_LENOVO_T480=y # CONFIG_BOARD_LENOVO_X230S is not set # CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN0094" +CONFIG_THINKPADEC_HKEY_EISAID="LEN0268" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y +CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480/tb.bin" CONFIG_TTYS0_BAUD=115200 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set @@ -497,11 +499,13 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y -# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +CONFIG_H8_SUPPORT_BT_ON_WIFI=y # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y CONFIG_H8_HAS_LEDLOGO=y +CONFIG_EC_LENOVO_MEC1653=y +CONFIG_MEC1653_SEND_DEBUG_UNLOCK=y CONFIG_EC_LENOVO_PMH7=y # @@ -645,7 +649,6 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set # CONFIG_BUILDING_WITH_DEBUG_FSP is not set -CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_VBT_CBFS_COMPRESSION_LZMA=y # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set diff --git a/config/coreboot/t480_vfsp_16mb/config/libgfxinit_txtmode b/config/coreboot/t480_vfsp_16mb/config/libgfxinit_txtmode index 123091c8..25bc9357 100644 --- a/config/coreboot/t480_vfsp_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t480_vfsp_16mb/config/libgfxinit_txtmode @@ -214,11 +214,13 @@ CONFIG_BOARD_LENOVO_T480=y # CONFIG_BOARD_LENOVO_X230S is not set # CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN0094" +CONFIG_THINKPADEC_HKEY_EISAID="LEN0268" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y +CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480/tb.bin" CONFIG_TTYS0_BAUD=115200 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set @@ -495,11 +497,13 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y -# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +CONFIG_H8_SUPPORT_BT_ON_WIFI=y # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y CONFIG_H8_HAS_LEDLOGO=y +CONFIG_EC_LENOVO_MEC1653=y +CONFIG_MEC1653_SEND_DEBUG_UNLOCK=y CONFIG_EC_LENOVO_PMH7=y # @@ -637,7 +641,6 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set # CONFIG_BUILDING_WITH_DEBUG_FSP is not set -CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_VBT_CBFS_COMPRESSION_LZMA=y # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set diff --git a/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_corebootfb b/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_corebootfb index 60043754..cf41cb6d 100644 --- a/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_corebootfb @@ -216,11 +216,13 @@ CONFIG_BOARD_LENOVO_T480S=y # CONFIG_BOARD_LENOVO_X230S is not set # CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN0094" +CONFIG_THINKPADEC_HKEY_EISAID="LEN0268" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y +CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480s/tb.bin" CONFIG_TTYS0_BAUD=115200 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set @@ -497,11 +499,12 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y -# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +CONFIG_H8_SUPPORT_BT_ON_WIFI=y # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y CONFIG_H8_HAS_LEDLOGO=y +CONFIG_EC_LENOVO_MEC1653=y CONFIG_EC_LENOVO_PMH7=y # @@ -645,7 +648,6 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set # CONFIG_BUILDING_WITH_DEBUG_FSP is not set -CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_VBT_CBFS_COMPRESSION_LZMA=y # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set diff --git a/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_txtmode b/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_txtmode index 76de6ae2..bba6087b 100644 --- a/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t480s_vfsp_16mb/config/libgfxinit_txtmode @@ -214,11 +214,13 @@ CONFIG_BOARD_LENOVO_T480S=y # CONFIG_BOARD_LENOVO_X230S is not set # CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN0094" +CONFIG_THINKPADEC_HKEY_EISAID="LEN0268" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y +CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480s/tb.bin" CONFIG_TTYS0_BAUD=115200 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set @@ -495,11 +497,12 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y -# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +CONFIG_H8_SUPPORT_BT_ON_WIFI=y # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y CONFIG_H8_HAS_LEDLOGO=y +CONFIG_EC_LENOVO_MEC1653=y CONFIG_EC_LENOVO_PMH7=y # @@ -637,7 +640,6 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set # CONFIG_BUILDING_WITH_DEBUG_FSP is not set -CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_VBT_CBFS_COMPRESSION_LZMA=y # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set diff --git a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb index f6c37a55..375b0b01 100644 --- a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t500_16mb/config/libgfxinit_txtmode b/config/coreboot/t500_16mb/config/libgfxinit_txtmode index ab08ab0e..3d797080 100644 --- a/config/coreboot/t500_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_16mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb index 2acd637d..5e5d3ade 100644 --- a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t500_4mb/config/libgfxinit_txtmode b/config/coreboot/t500_4mb/config/libgfxinit_txtmode index be8a63fc..9a7e5617 100644 --- a/config/coreboot/t500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_4mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb index a3f26365..c8732a48 100644 --- a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t500_8mb/config/libgfxinit_txtmode b/config/coreboot/t500_8mb/config/libgfxinit_txtmode index df65012c..c4b3c004 100644 --- a/config/coreboot/t500_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_8mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t520_8mb/config/libgfxinit_corebootfb b/config/coreboot/t520_8mb/config/libgfxinit_corebootfb index 5d8c9a7c..95e50779 100644 --- a/config/coreboot/t520_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t520_8mb/config/libgfxinit_corebootfb @@ -396,6 +396,8 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t520_8mb/config/libgfxinit_txtmode b/config/coreboot/t520_8mb/config/libgfxinit_txtmode index 897bf5f4..5dfa0496 100644 --- a/config/coreboot/t520_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t520_8mb/config/libgfxinit_txtmode @@ -394,6 +394,8 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t530_12mb/config/libgfxinit_corebootfb b/config/coreboot/t530_12mb/config/libgfxinit_corebootfb index eb09038d..46986899 100644 --- a/config/coreboot/t530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t530_12mb/config/libgfxinit_corebootfb @@ -396,6 +396,8 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t530_12mb/config/libgfxinit_txtmode b/config/coreboot/t530_12mb/config/libgfxinit_txtmode index 3c01cd8f..005437ca 100644 --- a/config/coreboot/t530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t530_12mb/config/libgfxinit_txtmode @@ -394,6 +394,8 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb index 4a943565..83e57e15 100644 --- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb +++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb @@ -375,6 +375,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode index 095dd8ef..0fecf0a1 100644 --- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode +++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode @@ -375,6 +375,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb index 3eb06179..635cc7d1 100644 --- a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb +++ b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb @@ -375,6 +375,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode index dbe9b6c5..b11e0db9 100644 --- a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode +++ b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode @@ -375,6 +375,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb index 11054290..91cea560 100644 --- a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w500_16mb/config/libgfxinit_txtmode b/config/coreboot/w500_16mb/config/libgfxinit_txtmode index 466a524b..59326aca 100644 --- a/config/coreboot/w500_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_16mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb index c687a752..be7c6931 100644 --- a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w500_4mb/config/libgfxinit_txtmode b/config/coreboot/w500_4mb/config/libgfxinit_txtmode index e02e254f..cc520d46 100644 --- a/config/coreboot/w500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_4mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb index 8dff38ca..8af6b5b5 100644 --- a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb @@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w500_8mb/config/libgfxinit_txtmode b/config/coreboot/w500_8mb/config/libgfxinit_txtmode index e0d68412..19d473b2 100644 --- a/config/coreboot/w500_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_8mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w530_12mb/config/libgfxinit_corebootfb b/config/coreboot/w530_12mb/config/libgfxinit_corebootfb index 69e8845c..50141db1 100644 --- a/config/coreboot/w530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w530_12mb/config/libgfxinit_corebootfb @@ -396,6 +396,8 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/w530_12mb/config/libgfxinit_txtmode b/config/coreboot/w530_12mb/config/libgfxinit_txtmode index 76de1779..35e909a6 100644 --- a/config/coreboot/w530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w530_12mb/config/libgfxinit_txtmode @@ -394,6 +394,8 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_16mb/config/libgfxinit_corebootfb b/config/coreboot/x200_16mb/config/libgfxinit_corebootfb index a6020ff5..20f5bbda 100644 --- a/config/coreboot/x200_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_16mb/config/libgfxinit_corebootfb @@ -374,6 +374,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_16mb/config/libgfxinit_txtmode b/config/coreboot/x200_16mb/config/libgfxinit_txtmode index aeac6173..d1635db3 100644 --- a/config/coreboot/x200_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_16mb/config/libgfxinit_txtmode @@ -372,6 +372,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_4mb/config/libgfxinit_corebootfb b/config/coreboot/x200_4mb/config/libgfxinit_corebootfb index 73f0def5..63166703 100644 --- a/config/coreboot/x200_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_4mb/config/libgfxinit_corebootfb @@ -374,6 +374,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_4mb/config/libgfxinit_txtmode b/config/coreboot/x200_4mb/config/libgfxinit_txtmode index e4d8caa8..197e4ea4 100644 --- a/config/coreboot/x200_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_4mb/config/libgfxinit_txtmode @@ -372,6 +372,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_8mb/config/libgfxinit_corebootfb b/config/coreboot/x200_8mb/config/libgfxinit_corebootfb index 8ecc6c43..ddaefa7a 100644 --- a/config/coreboot/x200_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_8mb/config/libgfxinit_corebootfb @@ -374,6 +374,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x200_8mb/config/libgfxinit_txtmode b/config/coreboot/x200_8mb/config/libgfxinit_txtmode index 357d6609..ccc5904d 100644 --- a/config/coreboot/x200_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_8mb/config/libgfxinit_txtmode @@ -372,6 +372,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x220_8mb/config/libgfxinit_corebootfb b/config/coreboot/x220_8mb/config/libgfxinit_corebootfb index 6945cfa1..e72892ff 100644 --- a/config/coreboot/x220_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x220_8mb/config/libgfxinit_corebootfb @@ -396,6 +396,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x220_8mb/config/libgfxinit_txtmode b/config/coreboot/x220_8mb/config/libgfxinit_txtmode index 316a4bd9..e0072f13 100644 --- a/config/coreboot/x220_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x220_8mb/config/libgfxinit_txtmode @@ -394,6 +394,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230_12mb/config/libgfxinit_corebootfb b/config/coreboot/x230_12mb/config/libgfxinit_corebootfb index 54f491f3..cba17129 100644 --- a/config/coreboot/x230_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230_12mb/config/libgfxinit_corebootfb @@ -396,6 +396,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230_12mb/config/libgfxinit_txtmode b/config/coreboot/x230_12mb/config/libgfxinit_txtmode index 42442f6d..73fe0a42 100644 --- a/config/coreboot/x230_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230_12mb/config/libgfxinit_txtmode @@ -394,6 +394,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230_16mb/config/libgfxinit_corebootfb b/config/coreboot/x230_16mb/config/libgfxinit_corebootfb index b4b8d280..f8348375 100644 --- a/config/coreboot/x230_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230_16mb/config/libgfxinit_corebootfb @@ -396,6 +396,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230_16mb/config/libgfxinit_txtmode b/config/coreboot/x230_16mb/config/libgfxinit_txtmode index 59b9f22c..c4dda6a9 100644 --- a/config/coreboot/x230_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230_16mb/config/libgfxinit_txtmode @@ -394,6 +394,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb b/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb index 7dffd236..c2ef35aa 100644 --- a/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb @@ -396,6 +396,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230t_12mb/config/libgfxinit_txtmode b/config/coreboot/x230t_12mb/config/libgfxinit_txtmode index e774d160..b161f781 100644 --- a/config/coreboot/x230t_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230t_12mb/config/libgfxinit_txtmode @@ -394,6 +394,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb b/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb index d38d447d..9a1dd06b 100644 --- a/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb @@ -396,6 +396,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x230t_16mb/config/libgfxinit_txtmode b/config/coreboot/x230t_16mb/config/libgfxinit_txtmode index 2f901f5d..5a213187 100644 --- a/config/coreboot/x230t_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230t_16mb/config/libgfxinit_txtmode @@ -394,6 +394,7 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y CONFIG_EC_LENOVO_PMH7=y # diff --git a/config/coreboot/x60/config/libgfxinit_corebootfb b/config/coreboot/x60/config/libgfxinit_corebootfb index 3bfe9434..e2c15f7e 100644 --- a/config/coreboot/x60/config/libgfxinit_corebootfb +++ b/config/coreboot/x60/config/libgfxinit_corebootfb @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/x60/config/libgfxinit_txtmode b/config/coreboot/x60/config/libgfxinit_txtmode index 48c20b09..3163fda6 100644 --- a/config/coreboot/x60/config/libgfxinit_txtmode +++ b/config/coreboot/x60/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/x60_16mb/config/libgfxinit_corebootfb b/config/coreboot/x60_16mb/config/libgfxinit_corebootfb index ada7ba5d..92a46efc 100644 --- a/config/coreboot/x60_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x60_16mb/config/libgfxinit_corebootfb @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/coreboot/x60_16mb/config/libgfxinit_txtmode b/config/coreboot/x60_16mb/config/libgfxinit_txtmode index d2132064..c21c7ba5 100644 --- a/config/coreboot/x60_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x60_16mb/config/libgfxinit_txtmode @@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y # CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BDC_GPIO_DETECTION=y +CONFIG_H8_HAS_2ND_THERMAL_ZONE=y CONFIG_EC_LENOVO_PMH7=y CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_ARCH_X86=y diff --git a/config/submodule/coreboot/default/libgfxinit/patches/0002-re-try-EDID-reading-when-it-fails.patch b/config/submodule/coreboot/default/libgfxinit/patches/0002-re-try-EDID-reading-when-it-fails.patch new file mode 100644 index 00000000..889218fe --- /dev/null +++ b/config/submodule/coreboot/default/libgfxinit/patches/0002-re-try-EDID-reading-when-it-fails.patch @@ -0,0 +1,38 @@ +From cbac507d93dc357a75ccc11fdda5c7ed60935538 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Sun, 13 Jul 2025 15:18:53 +0100 +Subject: [PATCH 1/1] re-try EDID reading when it fails + +some video converters are a bit buggy and have to be +probed twice; linux works fine, but in these cases, +coreboot won't set up the display. + +try it twice, to mitigate, when probing the EDID + +This entire function should probably be rewritten, since +it's buggy in general. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + common/hw-gfx-gma-display_probing.adb | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/common/hw-gfx-gma-display_probing.adb b/common/hw-gfx-gma-display_probing.adb +index 67f8ddf..0500217 100644 +--- a/common/hw-gfx-gma-display_probing.adb ++++ b/common/hw-gfx-gma-display_probing.adb +@@ -122,6 +122,11 @@ is + Read_EDID (Raw_EDID, Port, Success); + end if; + ++ if not Success then ++ Panel.Wait_On (Config_Helpers.To_Panel (Port)); ++ Read_EDID (Raw_EDID, Port, Success); ++ end if; ++ + if Success and then + ((not Is_DVI_I (Port) or EDID.Compatible_Display + (Raw_EDID, Config_Helpers.To_Display_Type (Port))) and +-- +2.39.5 + |