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authorLeah Rowe <leah@libreboot.org>2021-12-01 03:00:46 +0000
committerLeah Rowe <leah@libreboot.org>2021-12-01 04:32:02 +0000
commit9938fa14b1bf54db37c0c18bdfec051cae41448e (patch)
treec1ab96a280259001743d1f139b257e8e959c9a4b /resources/coreboot/d945gclf_16mb/config
parent4b64e34fc2d3ebfe22d350f0b04023fe60e0df3e (diff)
Fix broken SpeedStep on GM45 laptops such as ThinkPad X200, T400, T500, W500
Coreboot is enabling PECI on these CPUs which, according to Intel erratum, must only be done after loading microcode updates, otherwise the CPUID feature set becomes corrupted. That's my understanding, and I think this is why SpeedStep is broken. To be specific, it could but but operating systems no longer detect that the feature is supported. In any case, belgin on IRC found the commit in coreboot, after a bisect, enabling PECI. This commit in Libreboot adds a patch, reverting coreboot's PECI patch.
Diffstat (limited to 'resources/coreboot/d945gclf_16mb/config')
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