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authorLeah Rowe <leah@libreboot.org>2026-05-05 23:21:30 +0100
committerLeah Rowe <leah@libreboot.org>2026-05-05 23:21:30 +0100
commit0aa019d323d822f6a1e5c7a8f9a4e463e3d7105f (patch)
treea35059017a3441ceb7c683eaf95c0a745b9a1c87 /config
parentf60350344a56fa2b9db2b0653f69a7b036da8aab (diff)
coreboot/x2e_n150: fix mismatching fsp headerHEADmaster
thanks to sirlami on irc for pointing this out. due to lbmk blob policy, we must not distribute fsp except as the full, concatenated binary, thus complying with intel's license. it is removed from builds before release, re-inserted via vendor inject scripts in the usual way. a while ago, coreboot updated fsp but i had to keep it on the earlier version for this board, lest old releases no longer match vendor insertion; the new fsp version also wasnet well tested, and didn't seem to contain any changes reported that pertained to our use of it. the fsp headers do not match the fsp binary in use, causing boot issues for users on topton x2e n150. this patch should fix the issue, as reported by sirlami who is the one who found and first tested this fix; i'm simply changing the configuration, as per sirlami's guidance. Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config')
-rw-r--r--config/coreboot/x2e_n150/config/fspgop2
1 files changed, 1 insertions, 1 deletions
diff --git a/config/coreboot/x2e_n150/config/fspgop b/config/coreboot/x2e_n150/config/fspgop
index 2ce472f7..28eda68d 100644
--- a/config/coreboot/x2e_n150/config/fspgop
+++ b/config/coreboot/x2e_n150/config/fspgop
@@ -262,7 +262,7 @@ CONFIG_SOC_INTEL_UART_DEV_MAX=7
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x25a
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0x7fff
CONFIG_FSP_TYPE_IOT=y
-CONFIG_FSP_HEADER_PATH="3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Include/"
+CONFIG_FSP_HEADER_PATH="3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Include/"
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
CONFIG_DATA_BUS_WIDTH=128
CONFIG_DIMMS_PER_CHANNEL=2