u-boot: Update ARM64 boards to v2024.10

Set default U-Boot revision to v2024.10 and rebase patches on top of
that. The video subsystem now has switched to using the 'cyclic'
mechanism, so the code around one of the video patches changed a bit.

x86 boards were already switched to v2024.10. Update U-Boot for the
remaining ARM64 boards as usual:

- Turn old configs into defconfigs (./update trees -s u-boot)
- Save the diff from old upstream defconfig (diffconfig $theirs $ours)
- Update U-Boot revision, rebase patches, and clean old trees
- Prepare new U-Boot tree (./update trees -f u-boot)
- Review the diffconfigs to see if any options were renamed upstream
- Copy over the new upstream defconfigs and apply earlier diff
- Turn new defconfigs into configs (./update trees -l u-boot)

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>

1 files changed, 5 insertions, 5 deletions

diff --git a/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch b/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch
index 4ceeac59..32647ed0 100644
--- a/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch
+++ b/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch
@@ -1,4 +1,4 @@
-From f98475a64fcfe6ef710acb29391c33c17903e580 Mon Sep 17 00:00:00 2001
+From bc5204d0d28bb431186fd106f9a79f69bfad005d Mon Sep 17 00:00:00 2001
 From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
 Date: Fri, 8 Oct 2021 17:33:22 +0300
 Subject: [PATCH] clk: rockchip: rk3399: Set hardcoded clock rates same as
@@ -60,10 +60,10 @@ index d941a129f3e5..54035c0df1f3 100644
  #define PWM_CLOCK_HZ    PMU_PCLK_HZ
  
 diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
-index 67b2c05ec9ed..754b35c23197 100644
+index 24cefebd1b2a..6f874bd347e0 100644
 --- a/drivers/clk/rockchip/clk_rk3399.c
 +++ b/drivers/clk/rockchip/clk_rk3399.c
-@@ -54,10 +54,11 @@ struct pll_div {
+@@ -53,10 +53,11 @@ struct pll_div {
  	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  
@@ -78,7 +78,7 @@ index 67b2c05ec9ed..754b35c23197 100644
  #endif
  
  static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
-@@ -682,7 +683,7 @@ static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
+@@ -681,7 +682,7 @@ static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
  static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
  {
  	struct pll_div vpll_config = {0};
@@ -87,7 +87,7 @@ index 67b2c05ec9ed..754b35c23197 100644
  	void *aclkreg_addr, *dclkreg_addr;
  	u32 div;
  
-@@ -1395,6 +1396,7 @@ static void rkclk_init(struct rockchip_cru *cru)
+@@ -1394,6 +1395,7 @@ static void rkclk_init(struct rockchip_cru *cru)
  	/* configure gpll cpll */
  	rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
  	rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);