summaryrefslogtreecommitdiff
path: root/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch
diff options
context:
space:
mode:
authorLeah Rowe <vimuser@noreply.codeberg.org>2023-10-14 19:42:54 +0000
committerLeah Rowe <vimuser@noreply.codeberg.org>2023-10-14 19:42:54 +0000
commit8583a05dde772923125976a9ba7c85d249306126 (patch)
treee6cd786f0d4b55e0303da296d4bbea24ca6544cc /config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch
parent65af756fc33ce1a8960c690e681d12ebeef20750 (diff)
parent4d9567a7561df6eeb0dd81f2faf522c8526163b0 (diff)
Merge pull request 'Update U-Boot to v2023.10 and use default coreboot tree for gru chromebooks' (#136) from alpernebbi/lbmk:uboot-v2023.10 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/136
Diffstat (limited to 'config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch')
-rw-r--r--config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch10
1 files changed, 5 insertions, 5 deletions
diff --git a/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch b/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch
index 044ea768..4a3e8687 100644
--- a/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch
+++ b/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch
@@ -1,4 +1,4 @@
-From 7e73b7a7550cfdd22a1413c263026e41e56e7617 Mon Sep 17 00:00:00 2001
+From 27d49512277677afb7f71e093b007b3e2022b83e Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Fri, 8 Oct 2021 17:33:22 +0300
Subject: [PATCH] clk: rockchip: rk3399: Set hardcoded clock rates same as
@@ -13,8 +13,8 @@ Also update VOP ACLK to 400MHz as it divides from CPLL (now 800MHz).
All this stops the displayed vendor bitmap from getting disfigured
when chainloading U-Boot from coreboot+depthcharge (as RW_LEGACY).
-Link: https://github.com/alpernebbi/u-boot/commit/7e73b7a7550cfdd22a1413c263026e41e56e7617
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+Link: https://github.com/alpernebbi/u-boot/commit/7e73b7a7550cfdd22a1413c263026e41e56e7617
---
.../include/asm/arch-rockchip/cru_rk3399.h | 19 ++++++++++---------
drivers/clk/rockchip/clk_rk3399.c | 10 ++++++----
@@ -60,7 +60,7 @@ index d941a129f3e5..54035c0df1f3 100644
#define PWM_CLOCK_HZ PMU_PCLK_HZ
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
-index 7d31a9f22a85..7cb3b0c23b72 100644
+index f748fb5189e0..33f02c2d633c 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -54,10 +54,11 @@ struct pll_div {
@@ -87,7 +87,7 @@ index 7d31a9f22a85..7cb3b0c23b72 100644
void *aclkreg_addr, *dclkreg_addr;
u32 div;
-@@ -1316,6 +1317,7 @@ static void rkclk_init(struct rockchip_cru *cru)
+@@ -1336,6 +1337,7 @@ static void rkclk_init(struct rockchip_cru *cru)
/* configure gpll cpll */
rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
@@ -96,5 +96,5 @@ index 7d31a9f22a85..7cb3b0c23b72 100644
/* configure perihp aclk, hclk, pclk */
aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
--
-2.37.2
+2.42.0