diff options
| author | Ron Nazarov <ron@noisytoot.org> | 2026-02-14 20:17:41 +0000 |
|---|---|---|
| committer | Ron Nazarov <ron@noisytoot.org> | 2026-02-14 20:17:41 +0000 |
| commit | 1017f16c3e361eddc50916940da132c55e754d6a (patch) | |
| tree | 073449aef2d42401e0ae1e0cb98d35e49c489571 /config/coreboot | |
| parent | 80be5ce87e07a0bf48f3e2d681cc3dc76c203307 (diff) | |
supermicro x11ssh_f: Disable ME HECI in devicetree
Since we always use me_cleaner, this speeds up boot time by preventing
coreboot from wasting a few seconds waiting for HECI.
Diffstat (limited to 'config/coreboot')
| -rw-r--r-- | config/coreboot/default/patches/0049-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/config/coreboot/default/patches/0049-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch b/config/coreboot/default/patches/0049-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch new file mode 100644 index 00000000..cae84975 --- /dev/null +++ b/config/coreboot/default/patches/0049-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch @@ -0,0 +1,31 @@ +From 6c6b7a71bfb36f9639abe72066851de22aa4f1ca Mon Sep 17 00:00:00 2001 +From: Ron Nazarov <ron@noisytoot.org> +Date: Sat, 14 Feb 2026 20:13:01 +0000 +Subject: [PATCH] mb/supermicro/x11-lga1151-series: Disable ME HECI in + devicetree + +Since we always use me_cleaner, this speeds up boot time by preventing +coreboot from wasting a few seconds waiting for HECI. + +Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350 +Signed-off-by: Ron Nazarov <ron@noisytoot.org> +--- + src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +index fbf896c6ae..aa09a41f2f 100644 +--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb ++++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +@@ -15,7 +15,7 @@ chip soc/intel/skylake + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end +- device ref heci1 on end ++ device ref heci1 off end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ +-- +2.52.0 + |