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authorLeah Rowe <leah@libreboot.org>2023-10-31 19:02:04 +0000
committerLeah Rowe <leah@libreboot.org>2023-10-31 19:08:51 +0000
commitd218088d8b9164d5349ebcfcc744ea4c48399cc1 (patch)
tree47978b1800a61c74a4fdc63774318c076a0e381d /config/coreboot/t60_16mb_intelgpu
parent91faeb8d091070d2eee61934e9e77b03221ba2dc (diff)
coreboot/all: disable TSEG stage cache
this is to work around recent s3 suspend/resume issues Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/t60_16mb_intelgpu')
-rw-r--r--config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb4
-rw-r--r--config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode4
2 files changed, 4 insertions, 4 deletions
diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb
index 79f7c0d7..eb29a939 100644
--- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb
+++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
+CONFIG_NO_STAGE_CACHE=y
+# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode
index 8a99fe3d..83814bf0 100644
--- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode
+++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
+CONFIG_NO_STAGE_CACHE=y
+# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set