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authorLeah Rowe <leah@libreboot.org>2024-08-11 23:09:25 +0100
committerLeah Rowe <leah@libreboot.org>2024-08-11 23:09:25 +0100
commit8ca56f96c12241aa36add827c489aeeed5260e22 (patch)
tree8e438c67569929ed9266219b0f7c2270be3206de /config/coreboot/t520_8mb/target.cfg
parent3ee4cc9ddec62276c374f8c7f0c0b3322cfaa9f6 (diff)
coreboot/default: fix build issue with DDR2 fix
some of my DDR2 checks were unnecessary, as nicholas pointed out on irc, because they were in places that only ran if DDR2 memory was used anyway. in another, valid place, I was checking the wrong variable for knowing what memory type is used. this patch fixes build errors in lbmk: src/northbridge/intel/gm45/raminit.c: In function 'dram_program_timings': src/northbridge/intel/gm45/raminit.c:1120:29: error: 'sysinfo' undeclared (first use in this function); did you mean 'sysinfo_t'? 1120 | if (sysinfo->spd_type == DDR2) | ^~~~~~~ | sysinfo_t src/northbridge/intel/gm45/raminit.c:1120:29: note: each undeclared identifier is reported only once for each function it appears in src/northbridge/intel/gm45/raminit.c: In function 'ddr2_odt_setup': src/northbridge/intel/gm45/raminit.c:1291:21: error: 'sysinfo' undeclared (first use in this function); did you mean 'sysinfo_t'? 1291 | if (sysinfo->spd_type == DDR2) { | ^~~~~~~ | sysinfo_t make: *** [Makefile:423: build/romstage/northbridge/intel/gm45/raminit.o] Error 1 Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/t520_8mb/target.cfg')
0 files changed, 0 insertions, 0 deletions