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authorLeah Rowe <leah@libreboot.org>2023-10-31 08:11:53 +0000
committerLeah Rowe <leah@libreboot.org>2023-10-31 08:27:37 +0000
commit29e9c32e32f8e947f51a3efe375dab3ef8e1987e (patch)
tree65cbdeae7ed5639deaa5294bd40c01788be0cd1e /config/coreboot/r400_4mb
parent9606c68c5b5becfb09da45e027e2398e5ff33dfa (diff)
coreboot/default: use alternative heap size fix
My previous fix to revert didn't fix S3 on GM45, one of the platforms reported fixed by 78263; I'm merging that instead, at patch set 10. It is referenced by 78815/1 which was split from it, so merge that too (restores overrides of higher values, on certain platforms that we don't use yet). https://review.coreboot.org/c/coreboot/+/78623/10 https://review.coreboot.org/c/coreboot/+/78815/1 Accordingly, update configs to match the new default. Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/r400_4mb')
-rw-r--r--config/coreboot/r400_4mb/config/libgfxinit_corebootfb2
-rw-r--r--config/coreboot/r400_4mb/config/libgfxinit_txtmode2
2 files changed, 2 insertions, 2 deletions
diff --git a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb
index b7decbd2..84221206 100644
--- a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -249,6 +248,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_HEAP_SIZE=0x80000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
diff --git a/config/coreboot/r400_4mb/config/libgfxinit_txtmode b/config/coreboot/r400_4mb/config/libgfxinit_txtmode
index 656f107b..9c85e14c 100644
--- a/config/coreboot/r400_4mb/config/libgfxinit_txtmode
+++ b/config/coreboot/r400_4mb/config/libgfxinit_txtmode
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -247,6 +246,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_HEAP_SIZE=0x80000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000