coreboot/default: update coreboot to January 2024

Base revision changed to:

commit b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a
Author: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Date:   Fri Jan 5 16:48:17 2024 +0800

    mb/google/dedede/var/metaknight:Add fw_config probe for multi codec
    and amplifier

Of note:

Several out-of-tree ports have been adjusted to use the new SPD config
style, where it is defined in devicetree. I manually updated the E6530
patch myself, based on the update that Nicholas did on E6430 (Nicholas
will later update the E6530 patch himself, and I'll re-merge the patch).

Several upstream patches now exist in this revision, that we were able
to remove from lbmk.

The heap size patch was reverted upstream, as we did, but see:
https://review.coreboot.org/c/coreboot/+/80023
https://review.coreboot.org/c/coreboot/+/79525
Although we still disable the TSEG Stage Cache, ivy/sandy/haswell should
be reliable on S3 now (leaving TSEG Stage Cache disabled, for now, anyway).

Also included in upstream now:

commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94
Author: Bill Xie <persmule@hardenedlinux.org>
Date:   Sat Oct 7 01:32:51 2023 +0800

    drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume

Further patches from upstream:

commit 432e92688eca0e85cbaebca3232f65936b305a98
Author: Bill Xie <persmule@hardenedlinux.org>
Date:   Fri Nov 3 12:34:01 2023 +0800

    drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum

This should fix S3 on GM45 thinkpads.

Signed-off-by: Leah Rowe <leah@libreboot.org>

1 files changed, 13 insertions, 7 deletions

diff --git a/config/coreboot/qemu_arm64_12mb/config/libgfxinit_corebootfb b/config/coreboot/qemu_arm64_12mb/config/libgfxinit_corebootfb
index 45c86d25..8c435502 100644
--- a/config/coreboot/qemu_arm64_12mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/qemu_arm64_12mb/config/libgfxinit_corebootfb
@@ -20,6 +20,7 @@ CONFIG_OPTION_BACKEND_NONE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
 CONFIG_COMPRESS_PRERAM_STAGES=y
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 # CONFIG_COLLECT_TIMESTAMPS is not set
 CONFIG_USE_BLOBS=y
@@ -118,6 +119,8 @@ CONFIG_DEVICETREE="devicetree.cb"
 CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_DRAM_SIZE_MB=261120
 # CONFIG_CONSOLE_POST is not set
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_BOARD_EMULATION_QEMU_AARCH64=y
 # CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set
 # CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set
@@ -133,17 +136,13 @@ CONFIG_MEMLAYOUT_LD_FILE="src/mainboard/emulation/qemu-aarch64/memlayout.ld"
 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
 CONFIG_DRIVERS_INTEL_WIFI=y
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_TTYS0_BAUD=115200
 CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_16384=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -157,6 +156,7 @@ CONFIG_BOARD_ROMSIZE_KB_16384=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=12288
@@ -178,10 +178,11 @@ CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION=y
 CONFIG_GENERIC_UDELAY=y
 CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 
 #
 # CPU
@@ -245,8 +246,6 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
 # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -297,6 +296,7 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -313,6 +313,7 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y
 CONFIG_ACPI_HAVE_PCAT_8259=y
 CONFIG_ACPI_CUSTOM_MADT=y
 CONFIG_BOOT_DEVICE_NOT_SPI_FLASH=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -373,6 +374,10 @@ CONFIG_PAYLOAD_NONE=y
 #
 
 #
+# Vendorcode Debug Settings
+#
+
+#
 # BLOB Debug Settings
 #
 
@@ -390,6 +395,7 @@ CONFIG_PAYLOAD_NONE=y
 
 CONFIG_MISSING_BOARD_RESET=y
 CONFIG_DECOMPRESS_OFAST=y
+CONFIG_PROBE_RAM=y
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_NO_XIP_EARLY_STAGES=y