cb/kabylake: don't hardcode power_on_after_fail

I realised that the Dell OptiPlex 3050 Micro has NVRAM available.
Use that backend, and hardcode power_on_after_fail to Disable,
which is already done in cmos.default.

The Lenovo ThinkPad T480 currently has no option table in coreboot,
besides the CBFS one. For this, the CBFS option table has been
enabled, and the build system has been modified to insert
a relevant config for power_on_after_fail.

Nicholas Chin informs me that Kabylake generally has legacy NVRAM,
so enabling it for the T480/T480s should work, but we'll need
to use it in the future anyway; better to just use CBFS now.

I *could* use the CBFS backend on 3050micro as well.

Signed-off-by: Leah Rowe <leah@libreboot.org>

41 files changed, 148 insertions, 233 deletions

diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch
index 34d2d170..04e896d9 100644
--- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch
+++ b/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch
@@ -1,7 +1,7 @@
-From 26399f33428040acd69ebe02dd9f7f53d37e62a1 Mon Sep 17 00:00:00 2001
+From 7436b357fbe12233f3fbc5d360f296e6e15d3c2d Mon Sep 17 00:00:00 2001
 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
 Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 01/35] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 01/40] add c3 and clockgen to apple/macbook21
 
 ---
  src/mainboard/apple/macbook21/Kconfig       |  1 +
@@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644
  	end
  end
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
index 7b426dc3..2040cbc2 100644
--- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
+++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
@@ -1,7 +1,7 @@
-From 190bf09b5260bf94f9654294887cf916aa805fa8 Mon Sep 17 00:00:00 2001
+From 7d2e54028f5558f0ccea5ecd8f5f812e28597a47 Mon Sep 17 00:00:00 2001
 From: persmule <persmule@gmail.com>
 Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 02/35] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 02/40] lenovo/t400: Enable all SATA ports
 
 There are 2 SATA ports on the chassis of t400(s), but at least one dock for
 t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -30,5 +30,5 @@ index 9e056772e9..9361f330d2 100644
  			register "sata_traffic_monitor"		= "0"
  
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
index aea813b1..89294d6f 100644
--- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
+++ b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
@@ -1,7 +1,7 @@
-From c89826daea80f0e0e403808a8158c035a8c0423d Mon Sep 17 00:00:00 2001
+From 61051fbf9f1da48932930b512527626d1cf5bfbd Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 03/35] lenovo/x230: set me_state=Disabled in cmos.default
+Subject: [PATCH 03/40] lenovo/x230: set me_state=Disabled in cmos.default
 
 I only recently found out about this. It's possible to use me_cleaner to
 do the same thing, but some people might just flash coreboot and not do
@@ -33,5 +33,5 @@ index 732e214b32..8454f0eac0 100644
 -me_state=Normal
 +me_state=Disabled
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch
index 412ce1ee..7b2ceabd 100644
--- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch
+++ b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch
@@ -1,7 +1,7 @@
-From a418125357321304c76c023b243242debf675779 Mon Sep 17 00:00:00 2001
+From be0124d69fef77370eff57cfdfb2d6eae4b0cec3 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 04/35] set me_state=Disabled on all cmos.default files!
+Subject: [PATCH 04/40] set me_state=Disabled on all cmos.default files!
 
 yeah. why the hell isn't this the default
 
@@ -120,5 +120,5 @@ index d61046df6b..8c793fd1c3 100644
 -me_state=Enable
 +me_state=Disabled
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
index 893b6f32..314c6932 100644
--- a/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
+++ b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
@@ -1,7 +1,7 @@
-From 9e40defe4a539949a8b8dd2d295e49bb1d918d7c Mon Sep 17 00:00:00 2001
+From d97018fc490daf106582b0b7885a497cc2daba5a Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 05/35] util/ifdtool: add --nuke flag (all 0xFF on region)
+Subject: [PATCH 05/40] util/ifdtool: add --nuke flag (all 0xFF on region)
 
 When this option is used, the region's contents are overwritten
 with all ones (0xFF).
@@ -201,5 +201,5 @@ index b21a89c0e1..fc91d4c239 100644
  		struct fpsba *fpsba = find_fpsba(image, size);
  		struct fmsba *fmsba = find_fmsba(image, size);
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
index 552dfeb9..104df923 100644
--- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
+++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
@@ -1,7 +1,7 @@
-From 1515f7ea03cd021aba1fcb7aae46693064cda87e Mon Sep 17 00:00:00 2001
+From 1acdf1d0ff0c7a7ab5f2a0d7e5b57e21bdfaa1ae Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 06/35] mb/dell/e6400: Enable 01.0 device in devicetree for
+Subject: [PATCH 06/40] mb/dell/e6400: Enable 01.0 device in devicetree for
  dGPU models
 
 Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
@@ -24,5 +24,5 @@ index 5919803be2..76dae87153 100644
  		device pci 02.1 on end # Display
  		device pci 03.0 on end # ME
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch
index dd20ca9d..e8c0f449 100644
--- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch
+++ b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch
@@ -1,7 +1,7 @@
-From 0a16c780932a176bba062a82df47dfebfa963e39 Mon Sep 17 00:00:00 2001
+From aab9296997bd88a86bbb40079a9caf504db81cea Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 07/35] Remove warning for coreboot images built without a
+Subject: [PATCH 07/40] Remove warning for coreboot images built without a
  payload
 
 I added this in upstream to prevent people from accidentally flashing
@@ -35,5 +35,5 @@ index 5f988dac1b..516133880f 100644
 -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
 +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch
index 71085827..66043dc3 100644
--- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch
+++ b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch
@@ -1,7 +1,7 @@
-From 894aa0d70567962d2c05e7bbf20fab4093c3f3ef Mon Sep 17 00:00:00 2001
+From 319a77d9eeaaf1e344a380b1b449e6a56b3dc92c Mon Sep 17 00:00:00 2001
 From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
 Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH 08/35] HACK: Disable coreboot related BL31 features
+Subject: [PATCH 08/40] HACK: Disable coreboot related BL31 features
 
 I don't know why, but removing this BL31 make argument lets gru-kevin
 power off properly when shut down from Linux. Needs investigation.
@@ -24,5 +24,5 @@ index f54c6d22fc..b075abfd42 100644
  BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
  
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch
index 39acc45a..5ffd4431 100644
--- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch
+++ b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch
@@ -1,7 +1,7 @@
-From 7b13246f8838344f65cdfc1a5012af757fda45de Mon Sep 17 00:00:00 2001
+From d9066d7f51d5742ae8ed1c7ab096ee857358cc48 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 11:41:41 +0000
-Subject: [PATCH 09/35] dell/e6430: use ME Soft Temporary Disable
+Subject: [PATCH 09/40] dell/e6430: use ME Soft Temporary Disable
 
 i overlooked this. it's set on other boards.
 
@@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644
 -me_state=Normal
 +me_state=Disabled
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch
index 99a59b89..f093db5c 100644
--- a/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch
+++ b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch
@@ -1,7 +1,7 @@
-From c08a6748a8cecb5b6332d7d1ac4e17e6ba7f1095 Mon Sep 17 00:00:00 2001
+From 922357b7d5b0b5304b0d4296b2f03961a17288a6 Mon Sep 17 00:00:00 2001
 From: Riku Viitanen <riku.viitanen@protonmail.com>
 Date: Sat, 23 Dec 2023 19:02:10 +0200
-Subject: [PATCH 10/35] mb/hp: Add Compaq Elite 8300 CMT port
+Subject: [PATCH 10/40] mb/hp: Add Compaq Elite 8300 CMT port
 
 Based on autoport and Z220 SuperIO code.
 
@@ -868,5 +868,5 @@ index 0000000000..8dbd95ef96
 +	.enable_dev = mainboard_enable,
 +};
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch
index bf280b43..4c773248 100644
--- a/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch
+++ b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch
@@ -1,7 +1,7 @@
-From ce20b7a589ce16190ec161d7e4bd018922fd4362 Mon Sep 17 00:00:00 2001
+From 41256272a7637426c9e68fd633ceb1c108f183c9 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 2 Mar 2024 22:51:09 +0000
-Subject: [PATCH 11/35] nb/intel/haswell: make IOMMU a runtime option
+Subject: [PATCH 11/40] nb/intel/haswell: make IOMMU a runtime option
 
 When I tested graphics cards on a coreboot port for Dell
 OptiPlex 9020 SFF, I could not use a graphics card unless
@@ -288,5 +288,5 @@ index e47deb5da6..1a7e0b1076 100644
  	if (capid0_a & VTD_DISABLE)
  		return;
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch
index 1d8fc217..24b769cd 100644
--- a/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch
+++ b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch
@@ -1,7 +1,7 @@
-From 35ebb618aac374cf50b8bde59cc06c884ff05a98 Mon Sep 17 00:00:00 2001
+From b243452bf1ed7c9aee1e6685091e98f52d7229c7 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 2 Mar 2024 23:00:09 +0000
-Subject: [PATCH 12/35] dell/optiplex_9020: Disable IOMMU by default
+Subject: [PATCH 12/40] dell/optiplex_9020: Disable IOMMU by default
 
 Needed to make graphics cards work. Turning it on is
 recommended if only using iGPU, otherwise leave it off
@@ -25,5 +25,5 @@ index 8000eea8c0..0700f971ee 100644
 -iommu=Enable
 +iommu=Disable
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch
index f192bd94..447693aa 100644
--- a/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch
+++ b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch
@@ -1,7 +1,7 @@
-From 7e7d44da5e5ee31307e99632e7b4c49b931d2118 Mon Sep 17 00:00:00 2001
+From 215661dbe631c21a2533cc93bdd1e9f82aa9601e Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 6 Apr 2024 01:22:47 +0100
-Subject: [PATCH 13/35] nb/haswell: Fully disable iGPU when dGPU is used
+Subject: [PATCH 13/40] nb/haswell: Fully disable iGPU when dGPU is used
 
 My earlier patch disabled decode *and* disabled the iGPU itself, but
 a subsequent revision disabled only VGA decode. Upon revisiting, I
@@ -47,5 +47,5 @@ index f7fad3183d..1b188e92e1 100644
  
  static struct device_operations gma_func0_ops = {
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch
index a9e2cdbe..bfbddae1 100644
--- a/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch
+++ b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch
@@ -1,7 +1,7 @@
-From d4c7fec4db5d8844260fcd511c77c3c60bc1d881 Mon Sep 17 00:00:00 2001
+From aadef041f002b9f0504fcc67df39654680d67bdd Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 3 May 2024 11:03:32 -0600
-Subject: [PATCH 14/35] ec/dell/mec5035: Add S3 suspend SMI handler
+Subject: [PATCH 14/40] ec/dell/mec5035: Add S3 suspend SMI handler
 
 This is necessary for S3 resume to work on SNB and newer Dell Latitude
 laptops. If a command isn't sent, the EC cuts power to the DIMMs,
@@ -143,5 +143,5 @@ index 0000000000..958733bf97
 +	}
 +}
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
index f02e26b7..c1ae05be 100644
--- a/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
+++ b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
@@ -1,7 +1,7 @@
-From 426a557f5ed8de5a565564f9d345d449b3255293 Mon Sep 17 00:00:00 2001
+From 4a24221fc735117e521cbd7e08d71b6e6a061517 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 4 May 2024 02:00:53 +0100
-Subject: [PATCH 15/35] nb/haswell: lock policy regs when disabling IOMMU
+Subject: [PATCH 15/40] nb/haswell: lock policy regs when disabling IOMMU
 
 Angel Pons told me I should do it. See comments here:
 https://review.coreboot.org/c/coreboot/+/81016
@@ -51,5 +51,5 @@ index 1a7e0b1076..e9506ee830 100644
  	/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
  	u32 reg32;
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch
index 4ba32368..7537c1a6 100644
--- a/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch
+++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch
@@ -1,7 +1,7 @@
-From 403c10efc815b6b58ddf8025916a5840d4f39d16 Mon Sep 17 00:00:00 2001
+From 20921eb7165b23e7b78e4c4126ff5bab8725404b Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH 16/35] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH 16/40] nb/intel/gm45: Make DDR2 raminit work
 
 List of changes:
  - Update some timing and ODT values
@@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644
 +	mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
  }
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
index a685da59..808d90d6 100644
--- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
+++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
@@ -1,7 +1,7 @@
-From 814f2a4a1daf8bfd923cbfe3e618a153a7ade41e Mon Sep 17 00:00:00 2001
+From b5fe5366a03f934df87c5537b12f006ccee0d695 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Tue, 6 Aug 2024 00:50:24 +0100
-Subject: [PATCH 17/35] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
+Subject: [PATCH 17/40] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
 
 We add this patch:
 
@@ -236,5 +236,5 @@ index b74765fd9c..5d4505e063 100644
 +	}
  }
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
index 77401f78..b537346e 100644
--- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
+++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
@@ -1,7 +1,7 @@
-From bea563e3288d3cae4cab410cf818552abbd3bba4 Mon Sep 17 00:00:00 2001
+From c075c12d5549cc6cfaa4fbb6bb3abd5e17503b04 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Mon, 20 May 2024 10:24:16 -0600
-Subject: [PATCH 18/35] mb/dell/e6400: Use 100 MHz reference clock for display
+Subject: [PATCH 18/40] mb/dell/e6400: Use 100 MHz reference clock for display
 
 The E6400 uses a 100 MHz reference clock for spread spectrum support on
 LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
@@ -47,5 +47,5 @@ index fef0d735b3..fc5df8b11a 100644
  	select VBOOT_STARTS_IN_BOOTBLOCK
  
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
index 8f3caddb..cd1c919f 100644
--- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
+++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
@@ -1,7 +1,7 @@
-From 107e9bda542763b92f6e90031e0e3878d66e40fc Mon Sep 17 00:00:00 2001
+From 5833266cabd5dd38596b20d3353eb7b105ffd235 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Mon, 12 Aug 2024 02:15:24 +0100
-Subject: [PATCH 19/35] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
+Subject: [PATCH 19/40] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
 
 set it to 96MHz. fixes the following build error when
 building for x4x boards e.g. gigabyte ga-g41m-es2l:
@@ -48,5 +48,5 @@ index 097e11126c..6430319f6a 100644
  	default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
  
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch
index 61e4b308..3b2d59ce 100644
--- a/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch
+++ b/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch
@@ -1,7 +1,7 @@
-From aba3cfe3888960b342147f74a65cb436608ae632 Mon Sep 17 00:00:00 2001
+From 75620139fe2bd6898d51dd7bd02e1031369feeec Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Thu, 26 Sep 2024 19:51:25 -0600
-Subject: [PATCH 20/35] mb/dell/gm45_latitudes: Add E4300 variant
+Subject: [PATCH 20/40] mb/dell/gm45_latitudes: Add E4300 variant
 
 Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -328,5 +328,5 @@ index 0000000000..20dfa245fb
 +	end
 +end
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
index efd8b781..dcd75bb6 100644
--- a/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
+++ b/config/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
@@ -1,7 +1,7 @@
-From 9b43bbf06f7752045ec76ec5608d14f1d868e7f8 Mon Sep 17 00:00:00 2001
+From 26862554523e08ea1d1cd18cfd09e3434b12e2a3 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 3 May 2024 16:31:12 -0600
-Subject: [PATCH 21/35] mb/dell: Add S3 SMI handler for Dell Latitudes
+Subject: [PATCH 21/40] mb/dell: Add S3 SMI handler for Dell Latitudes
 
 Integrate the previously added mec5035_smi_sleep() function into
 mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
@@ -66,5 +66,5 @@ index 0000000000..00e55b51db
 +	mec5035_smi_sleep(slp_typ);
 +}
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch
index 36885752..ab85a389 100644
--- a/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch
+++ b/config/coreboot/default/patches/0022-ec-dell-mec5035-Route-power-button-event-to-host.patch
@@ -1,7 +1,7 @@
-From 31b7d8d2e853961ecce0ced86309e9e965a0d008 Mon Sep 17 00:00:00 2001
+From 849f0aba544d135e2028092862e5f030813c868e Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Tue, 18 Jun 2024 21:31:08 -0600
-Subject: [PATCH 22/35] ec/dell/mec5035: Route power button event to host
+Subject: [PATCH 22/40] ec/dell/mec5035: Route power button event to host
 
 If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
 power button results in the EC powering off the system without letting
@@ -88,5 +88,5 @@ index 8d4fded28b..51422598c4 100644
  void mec5035_sleep_enable(void);
  
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch
index 536f0429..17e630e3 100644
--- a/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch
+++ b/config/coreboot/default/patches/0023-Disable-compression-on-refcode-insertion.patch
@@ -1,7 +1,7 @@
-From 4dfcaaffc1fe01cd7676f804a7f1fd5f899beb36 Mon Sep 17 00:00:00 2001
+From 89ecd79ab46f56c65c0b5720d1c84b12698a02b4 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Tue, 31 Dec 2024 14:42:24 +0000
-Subject: [PATCH 23/35] Disable compression on refcode insertion
+Subject: [PATCH 23/40] Disable compression on refcode insertion
 
 Compression is not reliably reproducible. In an lbmk release
 context, this means we cannot rely on vendorfile insertion.
@@ -27,5 +27,5 @@ index 218e388bb5..a2163c4644 100644
  cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
  vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch
index db190832..cc9504e9 100644
--- a/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch
+++ b/config/coreboot/default/patches/0024-nb-intel-Disable-stack-overflow-debug-options.patch
@@ -1,7 +1,7 @@
-From c314d7a8a858c94d7a95b378951a5f22d62a51f9 Mon Sep 17 00:00:00 2001
+From df60dac9dbaf0c71008dbead7dc1a8c8881c5e33 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 21 Apr 2025 02:58:47 +0100
-Subject: [PATCH 24/35] nb/intel/*: Disable stack overflow debug options
+Subject: [PATCH 24/40] nb/intel/*: Disable stack overflow debug options
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -183,5 +183,5 @@ index 6430319f6a..1803ef5733 100644
 +
  endif
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch
index 17a5ee5c..70bb9ae9 100644
--- a/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch
+++ b/config/coreboot/default/patches/0025-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch
@@ -1,7 +1,7 @@
-From 1661af1ef80d7dce6aaba575bdcb52cc7c04e0da Mon Sep 17 00:00:00 2001
+From c3af549f5b6431475f3d180eb3b3041d9bfc5d81 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Mon, 30 Sep 2024 20:44:38 -0400
-Subject: [PATCH 25/35] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
+Subject: [PATCH 25/40] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
 
 Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -704,5 +704,5 @@ index 0000000000..555b1c1f5c
 +	end
 +end
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch
index 09929786..231e303e 100644
--- a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch
+++ b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch
@@ -1,7 +1,7 @@
-From ec5c7627e90eb136a41bbe179e744a9d300a79fc Mon Sep 17 00:00:00 2001
+From bb14741af8e4a16d3d098d79fb8df0c3a45e6ccb Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Wed, 30 Oct 2024 20:55:25 -0600
-Subject: [PATCH 26/35] mb/dell/optiplex_780: Add USFF variant
+Subject: [PATCH 26/40] mb/dell/optiplex_780: Add USFF variant
 
 Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -322,5 +322,5 @@ index 0000000000..555b1c1f5c
 +	end
 +end
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch
index 864ab7cb..94186a30 100644
--- a/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch
+++ b/config/coreboot/default/patches/0027-src-intel-x4x-Disable-stack-overflow-debug.patch
@@ -1,7 +1,7 @@
-From e1d09409f6062eb9798b2a63d555ef418a46f47b Mon Sep 17 00:00:00 2001
+From 1685de1beee49456e9f6f578ca6e37219fe7dfff Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 6 Jan 2025 01:53:53 +0000
-Subject: [PATCH 27/35] src/intel/x4x: Disable stack overflow debug
+Subject: [PATCH 27/40] src/intel/x4x: Disable stack overflow debug
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -29,5 +29,5 @@ index 1803ef5733..7129aabf72 100644
  config DOMAIN_RESOURCE_32BIT_LIMIT
  	default 0xfec00000
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch
index 77e43be6..c42b3cf0 100644
--- a/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch
+++ b/config/coreboot/default/patches/0028-hp-8300cmt-remove-xhci_overcurrent_mapping.patch
@@ -1,7 +1,7 @@
-From 1cb3f95c58d501fe33dc2a3d090a84cd7d5d42d3 Mon Sep 17 00:00:00 2001
+From 6f54ed4b0622c7772561760ea4b435bd236ac834 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Tue, 22 Apr 2025 10:21:59 +0100
-Subject: [PATCH 28/35] hp/8300cmt: remove xhci_overcurrent_mapping
+Subject: [PATCH 28/40] hp/8300cmt: remove xhci_overcurrent_mapping
 
 No longer needed, as per the following commit:
 
@@ -38,5 +38,5 @@ index 3d21739b72..3a0b6d5c59 100644
  			register "usb_port_config" = "{
  				{ 1, 0, 0 },
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch b/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch
index 4f1cb7d1..4b036e02 100644
--- a/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch
+++ b/config/coreboot/default/patches/0029-dell-3050micro-disable-nvme-hotplug.patch
@@ -1,7 +1,7 @@
-From 4ac77dd7d5c5759c546266003f7e705aae04860b Mon Sep 17 00:00:00 2001
+From 17c67799604e0e29192415e97293d71deb457cb2 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Wed, 11 Dec 2024 01:06:01 +0000
-Subject: [PATCH 29/35] dell/3050micro: disable nvme hotplug
+Subject: [PATCH 29/40] dell/3050micro: disable nvme hotplug
 
 in my testing, when running my 3050micro for a few days,
 the nvme would sometimes randomly rename.
@@ -45,5 +45,5 @@ index 0d2adff74a..829acacab3 100644
  
  		# Realtek LAN
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch
index a3638dd8..8a328251 100644
--- a/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch
+++ b/config/coreboot/default/patches/0030-soc-intel-skylake-configure-usb-acpi.patch
@@ -1,7 +1,7 @@
-From c58079787f45fd9d42bfaedfcb540634787c3010 Mon Sep 17 00:00:00 2001
+From 819fe0e89e426d3d875cf8ab4d2de439ba716848 Mon Sep 17 00:00:00 2001
 From: Felix Singer <felixsinger@posteo.net>
 Date: Wed, 26 Jun 2024 04:24:31 +0200
-Subject: [PATCH 30/35] soc/intel/skylake: configure usb acpi
+Subject: [PATCH 30/40] soc/intel/skylake: configure usb acpi
 
 Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
 Signed-off-by: Felix Singer <felixsinger@posteo.net>
@@ -90,5 +90,5 @@ index 6538a1475b..dfb81d496e 100644
  		device pci 14.2 alias thermal      off                     end
  		device pci 14.3 alias cio          off                     end
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch
index fab52017..916e54dc 100644
--- a/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch
+++ b/config/coreboot/default/patches/0031-src-intel-skylake-Disable-stack-overflow-debug-optio.patch
@@ -1,7 +1,7 @@
-From f449b429996bab8d6429c7bb83c84061b4b2284e Mon Sep 17 00:00:00 2001
+From 7194444fbddcf6567d0c82f0986e5deeacaea680 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 6 Jan 2025 01:36:23 +0000
-Subject: [PATCH 31/35] src/intel/skylake: Disable stack overflow debug options
+Subject: [PATCH 31/40] src/intel/skylake: Disable stack overflow debug options
 
 The option was appearing in T480/3050micro configs of lbmk,
 after updating on the coreboot/next uprev for 20241206 rev8:
@@ -57,5 +57,5 @@ index 9191ed0ff8..493a2d835a 100644
  	hex
  	default 0x20400 if FSP_USES_CB_STACK
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch
index 63e05d66..cd1ed452 100644
--- a/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch
+++ b/config/coreboot/default/patches/0032-soc-intel-skylake-Don-t-compress-FSP-S.patch
@@ -1,7 +1,7 @@
-From 26716653f9991ca8cce2766024522b8832607006 Mon Sep 17 00:00:00 2001
+From 81360b8c28293856e964934d1f356b1312b39ff2 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Thu, 26 Dec 2024 19:45:20 +0000
-Subject: [PATCH 32/35] soc/intel/skylake: Don't compress FSP-S
+Subject: [PATCH 32/40] soc/intel/skylake: Don't compress FSP-S
 
 Build systems like lbmk need to reproducibly insert
 certain vendor files on release images.
@@ -32,5 +32,5 @@ index 493a2d835a..42af82a5d8 100644
  	select GENERIC_GPIO_LIB
  	select HAVE_FSP_GOP
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0034-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch
index 985d4648..487b32a2 100644
--- a/config/coreboot/default/patches/0034-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch
+++ b/config/coreboot/default/patches/0033-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch
@@ -1,7 +1,7 @@
-From c0d4d83f662499d501fd0ca606bae9cf2d4de56d Mon Sep 17 00:00:00 2001
+From 25ff99ff021312387734a10836232a5f3a2d2a12 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Wed, 18 Dec 2024 02:06:18 +0000
-Subject: [PATCH 34/35] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
+Subject: [PATCH 33/40] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
 
 This is used by lbmk to know where a tb.bin file goes,
 when extracting and padding TBT.bin from Lenovo ThunderBolt
@@ -74,5 +74,5 @@ index 2ffbaab85f..512b326381 100644
 +
  endif # VENDOR_LENOVO
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0033-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch b/config/coreboot/default/patches/0033-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch
deleted file mode 100644
index bdc43616..00000000
--- a/config/coreboot/default/patches/0033-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From ee40e9eee976162a79943618e70714dd4ff1bfb7 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 31 Dec 2024 01:40:42 +0000
-Subject: [PATCH 33/35] soc/intel/pmc: Hardcoded poweroff after power fail
-
-Coreboot can set the power state for power on after previous
-power failure, based on the option table. On the ThinkPad T480,
-we have no nvram and, due to coreboot's design, we therefore
-have no option table, so the default setting is enabled.
-
-In my testing, this seems to be that the system will turn on
-after a power failure. If your ThinkPad was previously in a state
-where it wouldn't turn on when plugging in the power, it'd be fine.
-
-If your battery ran out later on, this would be triggered and
-your ThinkPad would permanently turn on, when plugging in a charger,
-and there is currently no way to configure this behaviour.
-
-We currently only use the common SoC PMC code on the ThinkPad
-T480, T480s and the Dell OptiPlex 3050 Micro, at the time of
-this patch, and it is desirable that the system be set to power
-off after power fail anyway.
-
-In some cases, you might want the opposite, for example if you're
-running a server. This will be documented on the website, for that
-reason.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/soc/intel/common/block/pmc/pmclib.c | 36 +++----------------------
- 1 file changed, 4 insertions(+), 32 deletions(-)
-
-diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
-index 64b9bb997c..7823775bcb 100644
---- a/src/soc/intel/common/block/pmc/pmclib.c
-+++ b/src/soc/intel/common/block/pmc/pmclib.c
-@@ -776,38 +776,10 @@ void pmc_clear_pmcon_sts(void)
- 
- void pmc_set_power_failure_state(const bool target_on)
- {
--	const unsigned int state = get_uint_option("power_on_after_fail",
--					 CONFIG_MAINBOARD_POWER_FAILURE_STATE);
--
--	/*
--	 * On the shutdown path (target_on == false), we only need to
--	 * update the register for MAINBOARD_POWER_STATE_PREVIOUS. For
--	 * all other cases, we don't write the register to avoid clob-
--	 * bering the value set on the boot path. This is necessary,
--	 * for instance, when we can't access the option backend in SMM.
--	 */
--
--	switch (state) {
--	case MAINBOARD_POWER_STATE_OFF:
--		if (!target_on)
--			break;
--		printk(BIOS_INFO, "Set power off after power failure.\n");
--		pmc_soc_set_afterg3_en(false);
--		break;
--	case MAINBOARD_POWER_STATE_ON:
--		if (!target_on)
--			break;
--		printk(BIOS_INFO, "Set power on after power failure.\n");
--		pmc_soc_set_afterg3_en(true);
--		break;
--	case MAINBOARD_POWER_STATE_PREVIOUS:
--		printk(BIOS_INFO, "Keep power state after power failure.\n");
--		pmc_soc_set_afterg3_en(target_on);
--		break;
--	default:
--		printk(BIOS_WARNING, "Unknown power-failure state: %d\n", state);
--		break;
--	}
-+	if (!target_on)
-+		return;
-+	printk(BIOS_INFO, "Set power off after power failure.\n");
-+	pmc_soc_set_afterg3_en(false);
- }
- 
- /* This function returns the highest assertion duration of the SLP_Sx assertion widths */
--- 
-2.39.5
-
diff --git a/config/coreboot/default/patches/0035-Conditional-TBFW-setting-for-T480-T480S.patch b/config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch
index 85174c56..1aeae433 100644
--- a/config/coreboot/default/patches/0035-Conditional-TBFW-setting-for-T480-T480S.patch
+++ b/config/coreboot/default/patches/0034-Conditional-TBFW-setting-for-T480-T480S.patch
@@ -1,7 +1,7 @@
-From 2dcd66e38b38b01d765dd8a84d1a866af61306e8 Mon Sep 17 00:00:00 2001
+From 57630265c7ba2429a8215757330348733c087db3 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 21 Apr 2025 05:14:45 +0100
-Subject: [PATCH 35/35] Conditional TBFW setting for T480/T480S
+Subject: [PATCH 34/40] Conditional TBFW setting for T480/T480S
 
 Otherwise, other boards will define it, which
 might trigger the vendor download script, and
@@ -33,5 +33,5 @@ index 512b326381..3d3490b35d 100644
 +
  endif # VENDOR_LENOVO
 -- 
-2.39.5
+2.47.3
 
diff --git a/config/coreboot/default/patches/0036-mb-topton-adl-Add-TWL-variant-X2E_N150.patch b/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch
index ae35c1cf..1edd0d27 100644
--- a/config/coreboot/default/patches/0036-mb-topton-adl-Add-TWL-variant-X2E_N150.patch
+++ b/config/coreboot/default/patches/0035-mb-topton-adl-Add-TWL-variant-X2E_N150.patch
@@ -1,7 +1,7 @@
-From 96a6735e7b59f1e538ed8c87993ed2d217c27891 Mon Sep 17 00:00:00 2001
+From 0a98ff0cbd20484ced53b15f16f8b77d881ffb9e Mon Sep 17 00:00:00 2001
 From: Riku Viitanen <riku.viitanen@protonmail.com>
 Date: Thu, 25 Sep 2025 22:45:37 +0300
-Subject: [PATCH] mb/topton/adl: Add TWL variant (X2E_N150)
+Subject: [PATCH 35/40] mb/topton/adl: Add TWL variant (X2E_N150)
 
 Seems to be the same board but with a Twin Lake processor.
 VBT extracted from vendor firmware. This makes HDMI and
@@ -67,44 +67,40 @@ new file mode 100644
 index 0000000000000000000000000000000000000000..05fbd5807365b3343e55ecedbd12fabb8a3199e9
 GIT binary patch
 literal 9216
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 literal 0
 HcmV?d00001
 
 -- 
-2.51.0
+2.47.3
 
diff --git a/config/coreboot/default/patches/0037-alderlake-Kconfig-disable-MRC_CACHE_USING_MRC_VERSIO.patch b/config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch
index e1dd16a5..565be85a 100644
--- a/config/coreboot/default/patches/0037-alderlake-Kconfig-disable-MRC_CACHE_USING_MRC_VERSIO.patch
+++ b/config/coreboot/default/patches/0036-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch
@@ -1,7 +1,8 @@
-From 31aae60ea0de0903759082cf90f78b8012850c5f Mon Sep 17 00:00:00 2001
+From 8e191c71f11de4cb3d08fe585537f15043cacb1b Mon Sep 17 00:00:00 2001
 From: Riku Viitanen <riku.viitanen@protonmail.com>
 Date: Sat, 27 Sep 2025 23:30:46 +0300
-Subject: [PATCH] soc/intel/alderlake: Disable MRC_CACHE_USING_MRC_VERSION
+Subject: [PATCH 36/40] soc/intel/alderlake: Disable
+ MRC_CACHE_USING_MRC_VERSION
 
 There's some issue with building against the FSP headers in src/vendorcode.
 Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing
@@ -25,5 +26,5 @@ index 51bdf98b9d..739faa3808 100644
  	select PARALLEL_MP_AP_WORK
  	select PLATFORM_USES_FSP2_2
 -- 
-2.51.0
+2.47.3
 
diff --git a/config/coreboot/default/patches/0038-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch
index abc232c5..8cff0c56 100644
--- a/config/coreboot/default/patches/0038-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch
+++ b/config/coreboot/default/patches/0037-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch
@@ -1,7 +1,7 @@
-From 273fec95778f53a622ff1e2a64c15b74813f48d2 Mon Sep 17 00:00:00 2001
+From 8ab86ffd25fc013790c260e564c8b770c13a5342 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 28 Sep 2025 03:17:50 +0100
-Subject: [PATCH 1/1] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks)
+Subject: [PATCH 37/40] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks)
 
 if you pass -k (keep fptr modules), don't use -r, don't
 use -t, you can essentially just use me_cleaner to
diff --git a/config/coreboot/default/patches/0039-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch
index b9c0e89c..545f2076 100644
--- a/config/coreboot/default/patches/0039-soc-intel-alderlake-Don-t-compress-FSP-S.patch
+++ b/config/coreboot/default/patches/0038-soc-intel-alderlake-Don-t-compress-FSP-S.patch
@@ -1,7 +1,7 @@
-From b5898dacf4306ff8a436cc02e664144bfb2cf52b Mon Sep 17 00:00:00 2001
+From c36ed52f7573563a9eaeeedd6e6c0ee75973a39d Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sat, 4 Oct 2025 21:57:43 +0100
-Subject: [PATCH 1/1] soc/intel/alderlake: Don't compress FSP-S
+Subject: [PATCH 38/40] soc/intel/alderlake: Don't compress FSP-S
 
 Build systems like lbmk need to reproducibly insert
 certain vendor files on release images.
diff --git a/config/coreboot/default/patches/0040-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch
index ebfdd640..ed7d98e0 100644
--- a/config/coreboot/default/patches/0040-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch
+++ b/config/coreboot/default/patches/0039-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch
@@ -1,7 +1,7 @@
-From 71687d1f0d938b22612ace6e0481ad3eb394c9ad Mon Sep 17 00:00:00 2001
+From e564490781b0b829da43534c6c2a1b26aeb3282f Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sat, 4 Oct 2025 22:20:11 +0100
-Subject: [PATCH 1/1] alderlake: don't require full fsp repo for fd path
+Subject: [PATCH 39/40] alderlake: don't require full fsp repo for fd path
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
diff --git a/config/coreboot/default/patches/0041-Haswell-NRI-Implement-SMBIOS-type-16-17.patch b/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch
index aeaf2fa2..4fdf2476 100644
--- a/config/coreboot/default/patches/0041-Haswell-NRI-Implement-SMBIOS-type-16-17.patch
+++ b/config/coreboot/default/patches/0040-Haswell-NRI-Implement-SMBIOS-type-16-17.patch
@@ -1,7 +1,7 @@
-From b00d35efc78b13d53c8f0b35b869811c5a2c56cf Mon Sep 17 00:00:00 2001
+From 0fdb23e899e31b17a774ae9151410b11ccf13022 Mon Sep 17 00:00:00 2001
 From: Ron Nazarov <ron@noisytoot.org>
 Date: Tue, 30 Sep 2025 22:36:53 +0100
-Subject: [PATCH] Haswell NRI: Implement SMBIOS type 16/17
+Subject: [PATCH 40/40] Haswell NRI: Implement SMBIOS type 16/17
 
 Based on the implementation from Ivy/Sandy Bridge NRI.
 
@@ -180,5 +180,5 @@ index b9e84a11df..1401feedc5 100644
  enum raminit_status collect_spd_info(struct sysinfo *ctrl);
  enum raminit_status initialise_mpll(struct sysinfo *ctrl);
 -- 
-2.50.1
+2.47.3