diff options
| author | Leah Rowe <leah@libreboot.org> | 2024-01-25 15:24:02 +0000 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2024-01-25 15:41:15 +0000 |
| commit | 4a6dc5553f2a15542f730ca735fb8bf95fb8f49b (patch) | |
| tree | 2cd281908a37816a526a0b6deab51376fec9cf69 /config/coreboot/default/patches | |
| parent | ece5463109721347c2008b7791907ac4d6825588 (diff) | |
coreboot/default: update coreboot to January 2024
Base revision changed to:
commit b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a
Author: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Date: Fri Jan 5 16:48:17 2024 +0800
mb/google/dedede/var/metaknight:Add fw_config probe for multi codec
and amplifier
Of note:
Several out-of-tree ports have been adjusted to use the new SPD config
style, where it is defined in devicetree. I manually updated the E6530
patch myself, based on the update that Nicholas did on E6430 (Nicholas
will later update the E6530 patch himself, and I'll re-merge the patch).
Several upstream patches now exist in this revision, that we were able
to remove from lbmk.
The heap size patch was reverted upstream, as we did, but see:
https://review.coreboot.org/c/coreboot/+/80023
https://review.coreboot.org/c/coreboot/+/79525
Although we still disable the TSEG Stage Cache, ivy/sandy/haswell should
be reliable on S3 now (leaving TSEG Stage Cache disabled, for now, anyway).
Also included in upstream now:
commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94
Author: Bill Xie <persmule@hardenedlinux.org>
Date: Sat Oct 7 01:32:51 2023 +0800
drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
Further patches from upstream:
commit 432e92688eca0e85cbaebca3232f65936b305a98
Author: Bill Xie <persmule@hardenedlinux.org>
Date: Fri Nov 3 12:34:01 2023 +0800
drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum
This should fix S3 on GM45 thinkpads.
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/default/patches')
36 files changed, 491 insertions, 853 deletions
diff --git a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch index c494390e..d2bae2e4 100644 --- a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch +++ b/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch @@ -1,7 +1,7 @@ -From e8f5f6c372152c7deddd3080954d0f4fdd39ae2b Mon Sep 17 00:00:00 2001 +From 1195c954a3b6822e5e843067251c0c80c9520eab Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@retroboot.org> Date: Fri, 19 Mar 2021 05:54:58 +0000 -Subject: [PATCH 01/22] apple/macbook21: Set default VRAM to 64MiB instead of +Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of 8MiB --- diff --git a/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch index bf36faea..8cd272ec 100644 --- a/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From fdd756a8217548981a1eb62e504cc37371c9fd51 Mon Sep 17 00:00:00 2001 +From 50a52cea2b43e6e407b456c082e908c7d29e090b Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 02/22] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/macbook21/Kconfig | 1 + diff --git a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch index 98943d72..34e12a6b 100644 --- a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch +++ b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch @@ -1,7 +1,7 @@ -From c8332a8bac4986afec6c639f55c5876f83e50b76 Mon Sep 17 00:00:00 2001 +From ca4cd66f411247395a323e5ea1abf09e83057827 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@osboot.org> Date: Sun, 3 Jan 2021 03:34:01 +0000 -Subject: [PATCH 03/22] lenovo/x60: 64MiB Video RAM changed to default +Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default (previously it was 8MiB) --- diff --git a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch index 0f1f7b1b..ee90dd63 100644 --- a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch +++ b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch @@ -1,7 +1,7 @@ -From 2e3ad35c24a86cb3109f4e5139b9ffba931eb80b Mon Sep 17 00:00:00 2001 +From eca0f4a3a4d6907e92b948547a362ca0ac3fc382 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@osboot.org> Date: Mon, 22 Feb 2021 22:16:59 +0000 -Subject: [PATCH 04/22] lenovo/t60: make 64MiB VRAM the default in cmos.default +Subject: [PATCH 04/30] lenovo/t60: make 64MiB VRAM the default in cmos.default --- src/mainboard/lenovo/t60/cmos.default | 2 +- diff --git a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch index 0818f1f8..35d74c75 100644 --- a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch +++ b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch @@ -1,7 +1,7 @@ -From 5fc03fbf8c7fa30588dab93c76b5532ce03b1610 Mon Sep 17 00:00:00 2001 +From 2eae87815675aebd472b6042777fe51279be4550 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:10:33 +0100 -Subject: [PATCH 05/22] lenovo/t400: set VRAM to 256MiB VRAM by default +Subject: [PATCH 05/30] lenovo/t400: set VRAM to 256MiB VRAM by default Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch index cbb00058..cc6abb00 100644 --- a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch +++ b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch @@ -1,7 +1,7 @@ -From 93f607fed477b3e63b7929808937436ac2898b34 Mon Sep 17 00:00:00 2001 +From f6b4913a5eca619b745d5ccea9af022a54fb185b Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:11:59 +0100 -Subject: [PATCH 06/22] lenovo/x200: set VRAM to 256MiB by default +Subject: [PATCH 06/30] lenovo/x200: set VRAM to 256MiB by default Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch index bea37df8..c4840ecc 100644 --- a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch +++ b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch @@ -1,7 +1,7 @@ -From 9faa780b2ac45bc1bf61aa252364ee3158c4cb10 Mon Sep 17 00:00:00 2001 +From a3a0969075163be413f968b03671aa5d8662672a Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:18:26 +0100 -Subject: [PATCH 07/22] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default +Subject: [PATCH 07/30] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch index 949ea696..19977870 100644 --- a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch +++ b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch @@ -1,7 +1,7 @@ -From f1c59cd67446303a5cdf9107461247a63f894de3 Mon Sep 17 00:00:00 2001 +From 223ac17617b3a0c08925abbbe42d0d003e144a28 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 14 May 2021 13:21:39 +0100 -Subject: [PATCH 08/22] acer/g43t-am3: set VRAM to 256MiB by default +Subject: [PATCH 08/30] acer/g43t-am3: set VRAM to 256MiB by default Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch index 9d901c45..332b870e 100644 --- a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 75858ba200a2a5835bca0af9b5f508a52ed978de Mon Sep 17 00:00:00 2001 +From 80ebbfef42454ea0911e5fc3858103d905987ed8 Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 09/22] lenovo/t400: Enable all SATA ports +Subject: [PATCH 09/30] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its diff --git a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch index 297dd223..12917ed8 100644 --- a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch +++ b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch @@ -1,7 +1,7 @@ -From 2c103a71a37eb4db9d33928b2371a682ca04e65f Mon Sep 17 00:00:00 2001 +From 318a97c284f8d5030100476a32516ddc9e51603d Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 20 Dec 2021 01:29:31 +0000 -Subject: [PATCH 10/22] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by +Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by default --- diff --git a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index 2fe4460d..dc3a33ca 100644 --- a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From 040f15039fa59d70cd54b8fff5d947e155666aa1 Mon Sep 17 00:00:00 2001 +From 47afbe8b94edd1ff58c1daf0bda020e6afac35f4 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 11/22] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 11/30] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do diff --git a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch index b0dba3ba..49f4db9b 100644 --- a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From 81febff42c66bd53e44176f14b651339b503a9f3 Mon Sep 17 00:00:00 2001 +From 531ef34ece796f38cb8a13a54856e46e79842e29 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 12/22] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 12/30] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default diff --git a/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch b/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch index c940c9e1..a3810417 100644 --- a/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch +++ b/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch @@ -1,7 +1,7 @@ -From c73269315626678c191ea494338581abdc417f21 Mon Sep 17 00:00:00 2001 +From 7b9003f98c7c685b2fe56781f3b0916018037b72 Mon Sep 17 00:00:00 2001 From: Alexander Couzens <lynxis@fe80.eu> Date: Sat, 19 Mar 2022 13:42:33 +0000 -Subject: [PATCH 13/22] lenovo/x230: introduce FHD variant +Subject: [PATCH 13/30] lenovo/x230: introduce FHD variant There is a modification for the x230 which uses the 2nd DP from the dock as the integrated panel's connection, which allows using a custom eDP @@ -36,7 +36,7 @@ Signed-off-by: Felix Singer <felixsinger@posteo.net> --- src/mainboard/lenovo/x230/Kconfig | 15 ++++++++----- src/mainboard/lenovo/x230/Kconfig.name | 3 +++ - src/mainboard/lenovo/x230/Makefile.inc | 5 +++++ + src/mainboard/lenovo/x230/Makefile.mk | 5 +++++ .../lenovo/x230/variants/x230_edp/data.vbt | Bin 0 -> 4281 bytes .../x230/variants/x230_edp/gma-mainboard.ads | 21 ++++++++++++++++++ 5 files changed, 38 insertions(+), 6 deletions(-) @@ -111,10 +111,10 @@ index 1a01436879..e7290a12dd 100644 + +config BOARD_LENOVO_X230_EDP + bool "ThinkPad X230 eDP Mod (2K/FHD)" -diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc +diff --git a/src/mainboard/lenovo/x230/Makefile.mk b/src/mainboard/lenovo/x230/Makefile.mk index 8e801f145d..6e6f9f90b9 100644 ---- a/src/mainboard/lenovo/x230/Makefile.inc -+++ b/src/mainboard/lenovo/x230/Makefile.inc +--- a/src/mainboard/lenovo/x230/Makefile.mk ++++ b/src/mainboard/lenovo/x230/Makefile.mk @@ -5,4 +5,9 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/early_init.c romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch b/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch index 83f99148..f439f2e7 100644 --- a/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch +++ b/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch @@ -1,7 +1,7 @@ -From c32229e3f82c00abb2bee4d0f7ddf33d4c7a04dc Mon Sep 17 00:00:00 2001 +From 9959fe252cceca7005b63e3313f7f95114f1f93c Mon Sep 17 00:00:00 2001 From: Alexei Sorokin <sor.alexei@meowr.ru> Date: Sun, 27 Nov 2022 18:36:26 +0300 -Subject: [PATCH 14/22] lenovo/x230: fix the data.vbt path for the EDP variant +Subject: [PATCH 14/30] lenovo/x230: fix the data.vbt path for the EDP variant --- src/mainboard/lenovo/x230/Kconfig | 2 +- diff --git a/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index 6a293287..a71324db 100644 --- a/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From 38c76afbea4abfed2976bfbe10977e41f21665b0 Mon Sep 17 00:00:00 2001 +From 158b79e6057e071d039619f617c112d31fb13f64 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 15/22] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 15/30] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). @@ -16,91 +16,91 @@ Rebased since the last revision update in lbmk. Signed-off-by: Leah Rowe <leah@libreboot.org> --- - util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++----------- - 1 file changed, 83 insertions(+), 31 deletions(-) + util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------ + 1 file changed, 81 insertions(+), 31 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index ddbc0fb91b..7af9235ae3 100644 +index 191b3216de..38132b4a28 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c -@@ -1847,6 +1847,7 @@ static void print_usage(const char *name) +@@ -1942,6 +1942,7 @@ static void print_usage(const char *name) + " tgl - Tiger Lake\n" " wbg - Wellsburg\n" " -S | --setpchstrap Write a PCH strap\n" - " -V | --newvalue The new value to write into PCH strap specified by -S\n" + " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n" + " -V | --newvalue The new value to write into PCH strap specified by -S\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" - "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, " -@@ -1854,6 +1855,60 @@ static void print_usage(const char *name) +@@ -1950,6 +1951,60 @@ static void print_usage(const char *name) "\n"); } +static int +get_region_type_string(const char *region_type_string) +{ -+ if (!strcasecmp("Descriptor", region_type_string)) -+ return 0; -+ else if (!strcasecmp("BIOS", region_type_string)) -+ return 1; -+ else if (!strcasecmp("ME", region_type_string)) -+ return 2; -+ else if (!strcasecmp("GbE", region_type_string)) -+ return 3; -+ else if (!strcasecmp("Platform Data", region_type_string)) -+ return 4; -+ else if (!strcasecmp("Device Exp1", region_type_string)) -+ return 5; -+ else if (!strcasecmp("Secondary BIOS", region_type_string)) -+ return 6; -+ else if (!strcasecmp("Reserved", region_type_string)) -+ return 7; -+ else if (!strcasecmp("EC", region_type_string)) -+ return 8; -+ else if (!strcasecmp("Device Exp2", region_type_string)) -+ return 9; -+ else if (!strcasecmp("IE", region_type_string)) -+ return 10; -+ else if (!strcasecmp("10GbE_0", region_type_string)) -+ return 11; -+ else if (!strcasecmp("10GbE_1", region_type_string)) -+ return 12; -+ else if (!strcasecmp("PTT", region_type_string)) -+ return 15; -+ return -1; ++ if (!strcasecmp("Descriptor", region_type_string)) ++ return 0; ++ else if (!strcasecmp("BIOS", region_type_string)) ++ return 1; ++ else if (!strcasecmp("ME", region_type_string)) ++ return 2; ++ else if (!strcasecmp("GbE", region_type_string)) ++ return 3; ++ else if (!strcasecmp("Platform Data", region_type_string)) ++ return 4; ++ else if (!strcasecmp("Device Exp1", region_type_string)) ++ return 5; ++ else if (!strcasecmp("Secondary BIOS", region_type_string)) ++ return 6; ++ else if (!strcasecmp("Reserved", region_type_string)) ++ return 7; ++ else if (!strcasecmp("EC", region_type_string)) ++ return 8; ++ else if (!strcasecmp("Device Exp2", region_type_string)) ++ return 9; ++ else if (!strcasecmp("IE", region_type_string)) ++ return 10; ++ else if (!strcasecmp("10GbE_0", region_type_string)) ++ return 11; ++ else if (!strcasecmp("10GbE_1", region_type_string)) ++ return 12; ++ else if (!strcasecmp("PTT", region_type_string)) ++ return 15; ++ return -1; +} + +static void +nuke(const char *filename, char *image, int size, int region_type) +{ -+ int i; -+ struct region region; -+ const struct frba *frba = find_frba(image, size); -+ if (!frba) -+ exit(EXIT_FAILURE); ++ int i; ++ struct region region; ++ const struct frba *frba = find_frba(image, size); ++ if (!frba) ++ exit(EXIT_FAILURE); + -+ region = get_region(frba, region_type); -+ if (region.size > 0) { -+ for (i = region.base; i <= region.limit; i++) { -+ if ((i + 1) > (size)) -+ break; -+ image[i] = 0xFF; -+ } -+ write_image(filename, image, size); -+ } ++ region = get_region(frba, region_type); ++ if (region.size > 0) { ++ for (i = region.base; i <= region.limit; i++) { ++ if ((i + 1) > (size)) ++ break; ++ image[i] = 0xFF; ++ } ++ write_image(filename, image, size); ++ } +} + int main(int argc, char *argv[]) { int opt, option_index = 0; -@@ -1861,6 +1916,7 @@ int main(int argc, char *argv[]) +@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[]) int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; + int mode_nuke = 0; + int mode_gpr0_disable = 0; char *region_type_string = NULL, *region_fname = NULL; const char *layout_fname = NULL; - char *new_filename = NULL; -@@ -1892,6 +1948,7 @@ int main(int argc, char *argv[]) +@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[]) {"validate", 0, NULL, 't'}, {"setpchstrap", 1, NULL, 'S'}, {"newvalue", 1, NULL, 'V'}, @@ -108,7 +108,7 @@ index ddbc0fb91b..7af9235ae3 100644 {0, 0, 0, 0} }; -@@ -1941,35 +1998,8 @@ int main(int argc, char *argv[]) +@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[]) region_fname++; // Descriptor, BIOS, ME, GbE, Platform // valid type? @@ -141,12 +141,12 @@ index ddbc0fb91b..7af9235ae3 100644 - else if (!strcasecmp("PTT", region_type_string)) - region_type = 15; - if (region_type == -1) { -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { ++ if ((region_type = ++ get_region_type_string(region_type_string)) == -1) { fprintf(stderr, "No such region type: '%s'\n\n", region_type_string); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); -@@ -2135,6 +2165,22 @@ int main(int argc, char *argv[]) +@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[]) case 't': mode_validate = 1; break; @@ -169,31 +169,29 @@ index ddbc0fb91b..7af9235ae3 100644 case 'v': print_version(); exit(EXIT_SUCCESS); -@@ -2150,7 +2196,8 @@ int main(int argc, char *argv[]) - +@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | -- mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) { -+ mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + -+ mode_nuke) > 1) { + mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + +- mode_gpr0_disable) > 1) { ++ mode_gpr0_disable + mode_nuke) > 1) { fprintf(stderr, "You may not specify more than one mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); -@@ -2158,7 +2205,8 @@ int main(int argc, char *argv[]) - +@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + -- mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) { -+ mode_locked + mode_unlocked + mode_density + mode_altmedisable + -+ mode_validate + mode_nuke) == 0) { + mode_locked + mode_unlocked + mode_density + mode_altmedisable + +- mode_validate + mode_gpr0_disable) == 0) { ++ mode_validate + mode_gpr0_disable + mode_nuke) == 0) { fprintf(stderr, "You need to specify a mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); -@@ -2262,6 +2310,10 @@ int main(int argc, char *argv[]) +@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[]) write_image(new_filename, image, size); } -+ if (mode_nuke) { ++ if (mode_nuke) { + nuke(new_filename, image, size, region_type); + } + diff --git a/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch index 0f9b192d..279fdad1 100644 --- a/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch +++ b/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch @@ -1,7 +1,7 @@ -From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001 +From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 1 Dec 2021 02:53:00 +0000 -Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert +Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert "cpu/intel/model_1067x: enable PECI" This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f. diff --git a/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch index 4d7b3421..4e5f5089 100644 --- a/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch +++ b/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch @@ -1,7 +1,7 @@ -From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001 +From 8a94f38398b8fa554fa4ae53ecb88a372df634fd Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 17 Apr 2023 15:49:57 +0100 -Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR +Subject: [PATCH 17/30] GM45-type CPUs: don't enable alternative SMRR This reverts the changes in coreboot revision: df7aecd92643d207feaf7fd840f8835097346644 diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index 04f3bd63..bfc9231a 100644 --- a/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001 +From 2b899f40ce5d728faa7c1da23c3348435b7ac9cb Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 18/30] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed diff --git a/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch index 3f21ad02..090f2629 100644 --- a/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001 +From 2ccd3e71730004c3ffbed178087cb778c170079e Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 19/22] Remove warning for coreboot images built without a +Subject: [PATCH 19/30] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing @@ -9,19 +9,19 @@ roms without a payload resulting in a no boot situation, but in libreboot lbmk handles the payload and thus this warning always comes up. This has caused confusion and concern so just patch it out. --- - payloads/Makefile.inc | 13 +------------ + payloads/Makefile.mk | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) -diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc -index e735443a76..4f1692a873 100644 ---- a/payloads/Makefile.inc -+++ b/payloads/Makefile.inc +diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk +index a2336aa876..4f1692a873 100644 +--- a/payloads/Makefile.mk ++++ b/payloads/Makefile.mk @@ -49,16 +49,5 @@ distclean-payloads: print-repo-info-payloads: -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) -ifeq ($(CONFIG_PAYLOAD_NONE),y) --files_added:: warn_no_payload +-show_notices:: warn_no_payload -endif - -warn_no_payload: diff --git a/config/coreboot/default/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch b/config/coreboot/default/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch deleted file mode 100644 index 2f2cddfe..00000000 --- a/config/coreboot/default/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch +++ /dev/null @@ -1,61 +0,0 @@ -From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Sun, 27 Aug 2023 17:36:36 -0600 -Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios - -These were determined by sniffing the LPC bus while toggling the -hardware wireless switch on the Latitude E6400. To differentiate devices -options in the vendor BIOS to change which radios the switch controlled -were used. - -Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/ec/dell/mec5035/mec5035.c | 9 +++++++++ - src/ec/dell/mec5035/mec5035.h | 8 ++++++++ - 2 files changed, 17 insertions(+) - -diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index 8da11e5b1c..e0335a4635 100644 ---- a/src/ec/dell/mec5035/mec5035.c -+++ b/src/ec/dell/mec5035/mec5035.c -@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting) - return buf[0]; - } - -+void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on) -+{ -+ /* From LPC traces and userspace testing with other values, -+ the second byte has to be 2 for an unknown reason. */ -+ u8 buf[3] = {dev, 2, on}; -+ write_mailbox_regs(buf, 2, 3); -+ ec_command(CMD_RADIO_EN); -+} -+ - void mec5035_early_init(void) - { - /* If this isn't sent the EC shuts down the system after about 15 -diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index e7a05b64d4..16512e2cc2 100644 ---- a/src/ec/dell/mec5035/mec5035.h -+++ b/src/ec/dell/mec5035/mec5035.h -@@ -16,8 +16,16 @@ - - #define CMD_CPU_OK 0xc2 - -+#define CMD_RADIO_EN 0x2b -+enum mec5035_radio_dev { -+ RADIO_WLAN = 0, -+ RADIO_WWAN = 1, -+ RADIO_WPAN = 2, -+}; -+ - u8 mec5035_mouse_touchpad(u8 setting); - void mec5035_cpu_ok(void); - void mec5035_early_init(void); -+void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on); - - #endif /* _EC_DELL_MEC5035_H_ */ --- -2.39.2 - diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch b/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch index 586992c9..c182ce8c 100644 --- a/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch +++ b/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch @@ -1,14 +1,14 @@ -From b37175381a32d9d308b5c1d67e11cdc57a24c820 Mon Sep 17 00:00:00 2001 +From a49df0307455d6d8b7a9efb9f4639b72be1b64d4 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 19 Aug 2023 16:19:10 -0600 -Subject: [PATCH] mb/dell: Add Latitude E6430 (Ivy Bridge) +Subject: [PATCH 20/30] mb/dell: Add Latitude E6430 (Ivy Bridge) -Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. -This is based on the autoport output with some manual tweaks. The flash -is 8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. -It can also be internally flashed by sending a command to the EC, which +Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. This +is based on the autoport output with some manual tweaks. The flash is +8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. It +can also be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting -up any chipset based write protections. [1] The EC is the SMSC MEC5055, +up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Working: @@ -24,27 +24,29 @@ Working: - mPCIe WiFi - SeaBIOS 1.16.2 - edk2 (MrChromebox' fork, uefipayload_202306) -- Internal flashing +- Internal flashing using dell-flash-unlock Not working: -- S3 suspend: It seems like the EC also controls the DRAM reset gate so - there may be a command that needs to be implemented for this -- Physical Wireless switch -- Battery reporting -- Brightness hotkeys +- S3 suspend: Possibly EC related +- Physical wireless switch - this triggers an SMI handler in the vendor + firmware which sends commands to the EC to enable/disable wireless + devices +- Battery reporting - needs ACPI code for the EC +- Brightness hotkeys - probably EC related Unknown/untested: - Dock - eSATA - TPM - dGPU on non-UMA model +- Bluetooth module (not included on my system) -[1] https://github.com/nic3-14159/e6400-flash-unlock +[1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> --- - src/mainboard/dell/e6430/Kconfig | 37 ++++ + src/mainboard/dell/e6430/Kconfig | 44 +++++ src/mainboard/dell/e6430/Kconfig.name | 2 + src/mainboard/dell/e6430/Makefile.inc | 6 + src/mainboard/dell/e6430/acpi/ec.asl | 9 + @@ -55,14 +57,14 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> src/mainboard/dell/e6430/cmos.default | 9 + src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++ src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes - src/mainboard/dell/e6430/devicetree.cb | 68 ++++++++ + src/mainboard/dell/e6430/devicetree.cb | 70 ++++++++ src/mainboard/dell/e6430/dsdt.asl | 30 ++++ - src/mainboard/dell/e6430/early_init.c | 38 ++++ + src/mainboard/dell/e6430/early_init.c | 32 ++++ src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++ src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++ src/mainboard/dell/e6430/hda_verb.c | 33 ++++ src/mainboard/dell/e6430/mainboard.c | 21 +++ - 18 files changed, 590 insertions(+) + 18 files changed, 593 insertions(+) create mode 100644 src/mainboard/dell/e6430/Kconfig create mode 100644 src/mainboard/dell/e6430/Kconfig.name create mode 100644 src/mainboard/dell/e6430/Makefile.inc @@ -84,10 +86,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig new file mode 100644 -index 0000000000..ea691aeb4e +index 0000000000..e4c799803e --- /dev/null +++ b/src/mainboard/dell/e6430/Kconfig -@@ -0,0 +1,37 @@ +@@ -0,0 +1,44 @@ +if BOARD_DELL_LATITUDE_E6430 + +config BOARD_SPECIFIC_OPTIONS @@ -110,20 +112,27 @@ index 0000000000..ea691aeb4e + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + ++config DRAM_RESET_GATE_GPIO ++ default 60 ++ +config MAINBOARD_DIR + default "dell/e6430" + +config MAINBOARD_PART_NUMBER + default "Latitude E6430" + -+config VGA_BIOS_ID -+ default "8086,0166" ++config PS2K_EISAID ++ default "DLLK0534" + -+config DRAM_RESET_GATE_GPIO -+ default 60 ++config PS2M_EISAID ++ default "DLL0534" + +config USBDEBUG_HCD_INDEX + default 2 ++ ++config VGA_BIOS_ID ++ default "8086,0166" ++ +endif diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name new file mode 100644 @@ -238,7 +247,7 @@ index 0000000000..2a5b30f2b7 +me_state=Normal diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout new file mode 100644 -index 0000000000..e85ea4c661 +index 0000000000..1aa7e77bce --- /dev/null +++ b/src/mainboard/dell/e6430/cmos.layout @@ -0,0 +1,88 @@ @@ -269,7 +278,7 @@ index 0000000000..e85ea4c661 +# coreboot config options: EC +412 1 e 1 bluetooth +413 1 e 1 wwan -+415 1 e 1 wlan ++414 1 e 1 wlan + +# coreboot config options: ME +424 1 e 14 me_state @@ -374,10 +383,10 @@ HcmV?d00001 diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb new file mode 100644 -index 0000000000..56dd9e5fe2 +index 0000000000..054b01c5ac --- /dev/null +++ b/src/mainboard/dell/e6430/devicetree.cb -@@ -0,0 +1,68 @@ +@@ -0,0 +1,70 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + register "gpu_cpu_backlight" = "0x00001312" @@ -392,19 +401,21 @@ index 0000000000..56dd9e5fe2 + register "gpu_panel_power_up_delay" = "400" + register "gpu_pch_backlight" = "0x13121312" + ++ register "spd_addresses" = "{0x50, 0, 0x52, 0}" ++ + device domain 0x0 on + subsystemid 0x1028 0x0534 inherit + -+ device ref host_bridge on end # Host bridge -+ device ref peg10 off end # PEG -+ device ref igd on end # iGPU ++ device ref host_bridge on end ++ device ref peg10 off end ++ device ref igd on end + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "1" + register "gen1_dec" = "0x007c0681" + register "gen2_dec" = "0x005c0921" + register "gen3_dec" = "0x003c07e1" -+ register "gen4_dec" = "0x007c0901" ++ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC + register "gpi0_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" @@ -416,33 +427,33 @@ index 0000000000..56dd9e5fe2 + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + -+ device ref xhci on end # USB 3.0 Controller -+ device ref mei1 on end # Management Engine Interface 1 -+ device ref mei2 off end # Management Engine Interface 2 -+ device ref me_ide_r off end # Management Engine IDE-R -+ device ref me_kt on end # Management Engine KT -+ device ref gbe on end # Intel Gigabit Ethernet -+ device ref ehci2 on end # USB2 EHCI #2 -+ device ref hda on end # High Definition Audio -+ device ref pcie_rp1 on end # PCIe Port #1 -+ device ref pcie_rp2 on end # PCIe Port #2 -+ device ref pcie_rp3 on end # PCIe Port #3 -+ device ref pcie_rp4 on end # PCIe Port #4 -+ device ref pcie_rp5 off end # PCIe Port #5 -+ device ref pcie_rp6 on end # PCIe Port #6 -+ device ref pcie_rp7 off end # PCIe Port #7 -+ device ref pcie_rp8 off end # PCIe Port #8 -+ device ref ehci1 on end # USB2 EHCI #1 -+ device ref pci_bridge off end # PCI bridge -+ device ref lpc on # LPC bridge ++ device ref xhci on end ++ device ref mei1 on end ++ device ref mei2 off end ++ device ref me_ide_r off end ++ device ref me_kt on end ++ device ref gbe on end ++ device ref ehci2 on end ++ device ref hda on end ++ device ref pcie_rp1 on end # WWAN Slot ++ device ref pcie_rp2 on end # SLAN Slot ++ device ref pcie_rp3 on end # ExpressCard ++ device ref pcie_rp4 on end # E-Module (optical bay) ++ device ref pcie_rp5 on end # Extra Half Mini PCIe slot ++ device ref pcie_rp6 on end # SD/MMC Card Reader ++ device ref pcie_rp7 off end ++ device ref pcie_rp8 off end ++ device ref ehci1 on end ++ device ref pci_bridge off end ++ device ref lpc on + chip ec/dell/mec5035 + device pnp ff.0 on end + end + end -+ device ref sata1 on end # SATA Controller 1 -+ device ref smbus on end # SMBus -+ device ref sata2 off end # SATA Controller 2 -+ device ref thermal off end # Thermal ++ device ref sata1 on end ++ device ref smbus on end ++ device ref sata2 off end ++ device ref thermal off end + end + end +end @@ -484,17 +495,16 @@ index 0000000000..7d13c55b08 +} diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c new file mode 100644 -index 0000000000..7944157f59 +index 0000000000..d882c3d78b --- /dev/null +++ b/src/mainboard/dell/e6430/early_init.c -@@ -0,0 +1,38 @@ +@@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> -+#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -516,16 +526,11 @@ index 0000000000..7944157f59 + +void bootblock_mainboard_early_init(void) +{ -+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f); -+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} -+ -+void mainboard_get_spd(spd_raw_data *spd, bool id_only) -+{ -+ read_spd(&spd[0], 0x50, id_only); -+ read_spd(&spd[2], 0x52, id_only); -+} diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads new file mode 100644 index 0000000000..1310830c8e @@ -817,5 +822,5 @@ index 0000000000..31e49802fc + .enable_dev = mainboard_enable, +}; -- -2.42.0 +2.39.2 diff --git a/config/coreboot/default/patches/0023-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch index d179a05a..40e1ccee 100644 --- a/config/coreboot/default/patches/0023-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,19 +1,19 @@ -From 9f52555eac217623ad2edc72492f9ded6a5b538d Mon Sep 17 00:00:00 2001 +From 70262a5f4bf801814d68f8778ea89b5cd8ef8f9a Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH] HACK: Disable coreboot related BL31 features +Subject: [PATCH 21/30] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. --- - src/arch/arm64/Makefile.inc | 3 --- + src/arch/arm64/Makefile.mk | 3 --- 1 file changed, 3 deletions(-) -diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc -index 6b49743633c3..e1982d92cc5c 100644 ---- a/src/arch/arm64/Makefile.inc -+++ b/src/arch/arm64/Makefile.inc -@@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 +diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk +index 538d254ace..18e451d63c 100644 +--- a/src/arch/arm64/Makefile.mk ++++ b/src/arch/arm64/Makefile.mk +@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 # Always enable crash reporting, even on a release build BL31_MAKEARGS += CRASH_REPORTING=1 @@ -24,5 +24,5 @@ index 6b49743633c3..e1982d92cc5c 100644 BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)" -- -2.40.1 +2.39.2 diff --git a/config/coreboot/default/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch b/config/coreboot/default/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch deleted file mode 100644 index d02ad724..00000000 --- a/config/coreboot/default/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Sun, 27 Aug 2023 19:15:37 -0600 -Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API - -Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db -Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> ---- - src/ec/dell/mec5035/mec5035.c | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index e0335a4635..20a33cc0ad 100644 ---- a/src/ec/dell/mec5035/mec5035.c -+++ b/src/ec/dell/mec5035/mec5035.c -@@ -4,6 +4,7 @@ - #include <console/console.h> - #include <device/device.h> - #include <device/pnp.h> -+#include <option.h> - #include <pc80/keyboard.h> - #include <stdint.h> - #include "mec5035.h" -@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev) - mec5035_mouse_touchpad(TP_PS2_MOUSE); - - pc_keyboard_init(NO_AUX_DEVICE); -+ -+ mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1)); -+ mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1)); -+ mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1)); - } - - static struct device_operations ops = { --- -2.39.2 - diff --git a/config/coreboot/default/patches/0024-don-t-use-github-for-the-acpica-download.patch b/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch index 2c4c9e5f..f66909c6 100644 --- a/config/coreboot/default/patches/0024-don-t-use-github-for-the-acpica-download.patch +++ b/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch @@ -1,7 +1,7 @@ -From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001 +From 536a1dd349f590cbefccac7e7364cafcdaec9600 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 22 Oct 2023 15:02:25 +0100 -Subject: [PATCH 1/1] don't use github for the acpica download +Subject: [PATCH 22/30] don't use github for the acpica download i have the tarball from a previous download, and i placed it on libreboot rsync, which then got mirrored to princeton. @@ -22,7 +22,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index ebc9fcb49a..a857110b4b 100755 +index 23a5caf2bb..36565a906c 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" diff --git a/config/coreboot/default/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch b/config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch index afce453d..7701babf 100644 --- a/config/coreboot/default/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch +++ b/config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch @@ -1,7 +1,7 @@ -From 0721e7e984bc83861bce3d47632b717848673749 Mon Sep 17 00:00:00 2001 +From ad812d008d570c1655bff13a9026f39a9efdcbc9 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 31 Oct 2023 18:24:39 +0000 -Subject: [PATCH 1/1] crank up vram allocation on more intel boards +Subject: [PATCH 23/30] crank up vram allocation on more intel boards these were added to libreboot, and it's a policy of libreboot to max out the vram settings. this was diff --git a/config/coreboot/default/patches/0031-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch index a2f98404..79ee4b6c 100644 --- a/config/coreboot/default/patches/0031-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From e712efdaf46a09a107c88a273d9b00effb4d977e Mon Sep 17 00:00:00 2001 +From a9ab864aee1be7a03926443ddc94e4c5012719ba Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 1/1] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 24/30] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. diff --git a/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch b/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch deleted file mode 100644 index cca8901f..00000000 --- a/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch +++ /dev/null @@ -1,341 +0,0 @@ -From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 29 Oct 2023 01:18:50 +0000 -Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large - value" - -This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6. - -NOTE: - -this is done instead of merging: -https://review.coreboot.org/c/coreboot/+/78623 - -which is still under review for now - -the patch i'm reverting is this one: -https://review.coreboot.org/c/coreboot/+/78270 - -this was actually only merged the day before i -updated coreboot revs in lbmk to the 12 october rev, -so there's no harm in quickly reverting this for now - -however, later on, we will rely on the other patch ---- - src/Kconfig | 3 ++- - src/cpu/qemu-x86/Kconfig | 3 +++ - src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++ - src/northbridge/amd/pi/Kconfig | 4 ++++ - src/soc/amd/picasso/Kconfig | 4 ++++ - src/soc/amd/stoneyridge/Kconfig | 4 ++++ - src/soc/cavium/cn81xx/Kconfig | 3 +++ - src/soc/intel/alderlake/Kconfig | 5 +++++ - src/soc/intel/apollolake/Kconfig | 4 ++++ - src/soc/intel/cannonlake/Kconfig | 4 ++++ - src/soc/intel/elkhartlake/Kconfig | 4 ++++ - src/soc/intel/jasperlake/Kconfig | 4 ++++ - src/soc/intel/meteorlake/Kconfig | 5 +++++ - src/soc/intel/skylake/Kconfig | 4 ++++ - src/soc/intel/tigerlake/Kconfig | 4 ++++ - src/soc/intel/xeon_sp/Kconfig | 4 ++++ - src/soc/intel/xeon_sp/cpx/Kconfig | 4 ++++ - src/soc/intel/xeon_sp/skx/Kconfig | 4 ++++ - src/soc/intel/xeon_sp/spr/Kconfig | 4 ++++ - src/soc/qualcomm/ipq40xx/Kconfig | 4 ++++ - 20 files changed, 77 insertions(+), 1 deletion(-) - -diff --git a/src/Kconfig b/src/Kconfig -index ae8024089e..1549719dd0 100644 ---- a/src/Kconfig -+++ b/src/Kconfig -@@ -751,7 +751,8 @@ config RTC - - config HEAP_SIZE - hex -- default 0x100000 -+ default 0x100000 if FLATTENED_DEVICE_TREE -+ default 0x4000 - - config STACK_SIZE - hex -diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig -index 0fa999e1ac..f3e2c4cea9 100644 ---- a/src/cpu/qemu-x86/Kconfig -+++ b/src/cpu/qemu-x86/Kconfig -@@ -35,4 +35,7 @@ config MAX_CPUS - default 32 if SMM_TSEG - default 4 - -+config HEAP_SIZE -+ default 0x8000 -+ - endif -diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig -index 7bc3b0bcbb..7f9300f2a7 100644 ---- a/src/mainboard/sifive/hifive-unleashed/Kconfig -+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig -@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS - select FLATTENED_DEVICE_TREE - select SPI_SDCARD - -+config HEAP_SIZE -+ default 0x10000 -+ - config MAINBOARD_DIR - default "sifive/hifive-unleashed" - -diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig -index 4ffe82a15f..4518db149b 100644 ---- a/src/northbridge/amd/pi/Kconfig -+++ b/src/northbridge/amd/pi/Kconfig -@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -+config HEAP_SIZE -+ hex -+ default 0xc0000 -+ - endif # NORTHBRIDGE_AMD_PI -diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig -index c33f287067..796fe4eb13 100644 ---- a/src/soc/amd/picasso/Kconfig -+++ b/src/soc/amd/picasso/Kconfig -@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN - bool - default n - -+config HEAP_SIZE -+ hex -+ default 0xc0000 -+ - config SERIRQ_CONTINUOUS_MODE - bool - default n -diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig -index 6ff135e6a8..9af7455bae 100644 ---- a/src/soc/amd/stoneyridge/Kconfig -+++ b/src/soc/amd/stoneyridge/Kconfig -@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN - bool - default n - -+config HEAP_SIZE -+ hex -+ default 0xc0000 -+ - config EHCI_BAR - hex - default 0xfef00000 -diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig -index 77ca97202b..368581f8f1 100644 ---- a/src/soc/cavium/cn81xx/Kconfig -+++ b/src/soc/cavium/cn81xx/Kconfig -@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION - int - default 1 - -+config HEAP_SIZE -+ default 0x10000 -+ - config STACK_SIZE - default 0x2000 - -diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 4b960c1d22..82ec8f263e 100644 ---- a/src/soc/intel/alderlake/Kconfig -+++ b/src/soc/intel/alderlake/Kconfig -@@ -215,6 +215,11 @@ config IED_REGION_SIZE - hex - default 0x400000 - -+config HEAP_SIZE -+ hex -+ default 0x80000 if BMP_LOGO -+ default 0x10000 -+ - config GFX_GMA_DEFAULT_MMIO - default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT - -diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig -index 78ec2987ce..bce935d800 100644 ---- a/src/soc/intel/apollolake/Kconfig -+++ b/src/soc/intel/apollolake/Kconfig -@@ -252,6 +252,10 @@ config IFWI_FILE_NAME - help - Name of file to store in the IFWI region. - -+config HEAP_SIZE -+ hex -+ default 0x8000 -+ - config MAX_ROOT_PORTS - int - default 6 -diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig -index a42a3c365b..80237f9810 100644 ---- a/src/soc/intel/cannonlake/Kconfig -+++ b/src/soc/intel/cannonlake/Kconfig -@@ -160,6 +160,10 @@ config IED_REGION_SIZE - hex - default 0x400000 - -+config HEAP_SIZE -+ hex -+ default 0x8000 -+ - config NHLT_DMIC_1CH_16B - bool - depends on ACPI_NHLT -diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig -index 3361c0ddb9..7f1c767379 100644 ---- a/src/soc/intel/elkhartlake/Kconfig -+++ b/src/soc/intel/elkhartlake/Kconfig -@@ -104,6 +104,10 @@ config IED_REGION_SIZE - hex - default 0x0 - -+config HEAP_SIZE -+ hex -+ default 0x8000 -+ - config MAX_ROOT_PORTS - int - default 7 -diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig -index 3d84991e09..ff5def3263 100644 ---- a/src/soc/intel/jasperlake/Kconfig -+++ b/src/soc/intel/jasperlake/Kconfig -@@ -106,6 +106,10 @@ config IED_REGION_SIZE - hex - default 0x400000 - -+config HEAP_SIZE -+ hex -+ default 0x8000 -+ - config MAX_ROOT_PORTS - int - default 8 -diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig -index 590e8b80e1..48030a1911 100644 ---- a/src/soc/intel/meteorlake/Kconfig -+++ b/src/soc/intel/meteorlake/Kconfig -@@ -197,6 +197,11 @@ config IED_REGION_SIZE - hex - default 0x400000 - -+config HEAP_SIZE -+ hex -+ default 0x80000 if BMP_LOGO -+ default 0x10000 -+ - # Intel recommends reserving the PCIe TBT root port resources as below: - # - 42 buses - # - 194 MiB Non-prefetchable memory -diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index e0df501460..d6a11363ee 100644 ---- a/src/soc/intel/skylake/Kconfig -+++ b/src/soc/intel/skylake/Kconfig -@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE - help - If you set this option to n, will not use native SD controller. - -+config HEAP_SIZE -+ hex -+ default 0x80000 -+ - config IED_REGION_SIZE - hex - default 0x400000 -diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig -index c07a0d8365..0a4b7bfdb8 100644 ---- a/src/soc/intel/tigerlake/Kconfig -+++ b/src/soc/intel/tigerlake/Kconfig -@@ -152,6 +152,10 @@ config IED_REGION_SIZE - config INTEL_TME - default n - -+config HEAP_SIZE -+ hex -+ default 0x10000 -+ - config MAX_ROOT_PORTS - int - default 24 if SOC_INTEL_TIGERLAKE_PCH_H -diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig -index e63bee5451..63ced01067 100644 ---- a/src/soc/intel/xeon_sp/Kconfig -+++ b/src/soc/intel/xeon_sp/Kconfig -@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS - config ECAM_MMCONF_BUS_NUMBER - default 256 - -+config HEAP_SIZE -+ hex -+ default 0x80000 -+ - config HPET_MIN_TICKS - hex - default 0x80 -diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig -index ac166c3038..f54f7716b6 100644 ---- a/src/soc/intel/xeon_sp/cpx/Kconfig -+++ b/src/soc/intel/xeon_sp/cpx/Kconfig -@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN - hex - default 0x7C00 - -+config HEAP_SIZE -+ hex -+ default 0x80000 -+ - config STACK_SIZE - hex - default 0x4000 -diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig -index 5d843878e1..c2c3d4e2e8 100644 ---- a/src/soc/intel/xeon_sp/skx/Kconfig -+++ b/src/soc/intel/xeon_sp/skx/Kconfig -@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN - hex - default 0x7C00 - -+config HEAP_SIZE -+ hex -+ default 0x80000 -+ - config IED_REGION_SIZE - hex - default 0x400000 -diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig -index 43b87ade14..b1c4c783b7 100644 ---- a/src/soc/intel/xeon_sp/spr/Kconfig -+++ b/src/soc/intel/xeon_sp/spr/Kconfig -@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN - hex - default 0x8c00 - -+config HEAP_SIZE -+ hex -+ default 0x80000 -+ - config STACK_SIZE - hex - default 0x4000 -diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig -index 0ce92731c0..0eabb00752 100644 ---- a/src/soc/qualcomm/ipq40xx/Kconfig -+++ b/src/soc/qualcomm/ipq40xx/Kconfig -@@ -57,4 +57,8 @@ config SBL_UTIL_PATH - help - Path for utils to combine SBL_ELF and bootblock - -+config HEAP_SIZE -+ hex -+ default 0x8000 -+ - endif --- -2.39.2 - diff --git a/config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch index 2e653f83..8275d6c5 100644 --- a/config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch +++ b/config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch @@ -1,7 +1,7 @@ -From 89c47fad6e97fc6a7113ebbdedfcc42ae2b6fc7f Mon Sep 17 00:00:00 2001 +From 936a8f113772c93d7501e7133159ab4e23436222 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 22:57:08 +0000 -Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads +Subject: [PATCH 25/30] use mirrorservice.org for gcc downloads the gnu.org 302 redirect often fails @@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 87f80ba7f6..b3aad5df7d 100755 +index 36565a906c..4d4ca06113 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" diff --git a/config/coreboot/default/patches/0033-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch b/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch index babaf559..33d743f1 100644 --- a/config/coreboot/default/patches/0033-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch +++ b/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch @@ -1,7 +1,7 @@ -From 823da59b0bdaeb20d5f22da65e736acaa70b301e Mon Sep 17 00:00:00 2001 +From 973783a989cdcb7b77029e369156c81eefe8cc67 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 19 Aug 2023 16:19:10 -0600 -Subject: [PATCH] mb/dell: Add Latitude E6530 (Ivy Bridge) +Subject: [PATCH 26/30] mb/dell: Add Latitude E6530 (Ivy Bridge) Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested. This is based on the autoport output with some manual tweaks. The flash is @@ -788,5 +788,5 @@ index 0000000000..31e49802fc + .enable_dev = mainboard_enable, +}; -- -2.42.1 +2.39.2 diff --git a/config/coreboot/default/patches/0026-sb-intel-ibexpeak-setup_heci_uma.c-Add-timeouts-when.patch b/config/coreboot/default/patches/0026-sb-intel-ibexpeak-setup_heci_uma.c-Add-timeouts-when.patch deleted file mode 100644 index 8bca1b0a..00000000 --- a/config/coreboot/default/patches/0026-sb-intel-ibexpeak-setup_heci_uma.c-Add-timeouts-when.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 27bf50138af0c5267581f8cc1f80676fb1836572 Mon Sep 17 00:00:00 2001 -From: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> -Date: Mon, 27 Mar 2017 22:05:16 +0200 -Subject: [PATCH 1/1] sb/intel/ibexpeak/setup_heci_uma.c: Add timeouts when - waiting for heci - -Since until now, the code running on the management engine is: -- Signed by its manufacturer -- Proprietary software, without corresponding source code -It can desirable to run the least ammount possible of such -code, which is what me_cleaner[1] enables. - -It does it by removing partitions of the management engine -firmwares, however when doing so, the HECI interface might -not be present anymore. - -So it is desirable not to have the RAM initialisation code -wait forever for the HECI interface to appear. - -[1] https://github.com/corna/me_cleaner/ - -MERGENOTE: Adapted from this patch: -https://mail.coreboot.org/pipermail/coreboot/2017-March/083798.html -Author on this version of the patch set to same author as in the -linked one, with same date set, but the commit message is modified -to match the new code path. Patch author Denis Carikli, but this -versions of the patch was rebased from it by Leah Rowe on 29 Oct 2023. - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - src/southbridge/intel/ibexpeak/setup_heci_uma.c | 14 ++++++++------ - 1 file changed, 8 insertions(+), 6 deletions(-) - -diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c -index 572e5e7a76..3a68344d97 100644 ---- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c -+++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c -@@ -8,28 +8,30 @@ - #include <southbridge/intel/ibexpeak/me.h> - #include <southbridge/intel/ibexpeak/pch.h> - #include <types.h> -+#include <delay.h> - - #define HECIDEV PCI_DEV(0, 0x16, 0) - --/* FIXME: add timeout. */ - static void wait_heci_ready(void) - { -- while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c -- ; -+ int i = 1000*1000; - -+ while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8)) /* = 0x8000000c */ -+ udelay(1); - write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); - } - --/* FIXME: add timeout. */ - static void wait_heci_cb_avail(int len) - { -+ int i = 1000*1000; -+ - union { - struct mei_csr csr; - u32 raw; - } csr; - -- while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) -- ; -+ while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8)) -+ udelay(1); - - do { - csr.raw = read32(DEFAULT_HECIBAR + 0x4); --- -2.39.2 - diff --git a/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch b/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch new file mode 100644 index 00000000..c5d67ae8 --- /dev/null +++ b/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch @@ -0,0 +1,145 @@ +From 88652afd52b0a8e0fc8bb1656e59d8ae4796d847 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Thu, 25 Jan 2024 14:30:03 +0000 +Subject: [PATCH 27/30] rebase dell/e6530 to newer coreboot code + +i diffed nicholas's current e6430 patch, versus the old one, +prior to this revision update in lbmk, also cross referencing +the original e6430 and e6530 patches, diffing them, and the +result in this patch. most notably, spd data is now defined in +the devicetree, instead of early_init.c as per: + +commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da +Author: Keith Hui <buurin@gmail.com> +Date: Sat Jul 22 12:49:05 2023 -0400 + mb/*: Update SPD mapping for sandybridge boards + +This should work fine. Will test after this builds. + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/mainboard/dell/e6530/Kconfig | 15 +++++++++++---- + src/mainboard/dell/e6530/cmos.layout | 2 +- + src/mainboard/dell/e6530/devicetree.cb | 8 +++++--- + src/mainboard/dell/e6530/early_init.c | 12 +++--------- + 4 files changed, 20 insertions(+), 17 deletions(-) + +diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig +index 582adddbd4..a104566890 100644 +--- a/src/mainboard/dell/e6530/Kconfig ++++ b/src/mainboard/dell/e6530/Kconfig +@@ -20,18 +20,25 @@ config BOARD_SPECIFIC_OPTIONS + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + ++config DRAM_RESET_GATE_GPIO ++ default 60 ++ + config MAINBOARD_DIR + default "dell/e6530" + + config MAINBOARD_PART_NUMBER + default "Latitude E6530" + +-config VGA_BIOS_ID +- default "8086,0166" ++config PS2K_EISAID ++ default "DLLK0534" + +-config DRAM_RESET_GATE_GPIO +- default 60 ++config PS2M_EISAID ++ default "DLL0534" + + config USBDEBUG_HCD_INDEX + default 2 ++ ++config VGA_BIOS_ID ++ default "8086,0166" ++ + endif +diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout +index e85ea4c661..1aa7e77bce 100644 +--- a/src/mainboard/dell/e6530/cmos.layout ++++ b/src/mainboard/dell/e6530/cmos.layout +@@ -25,7 +25,7 @@ entries + # coreboot config options: EC + 412 1 e 1 bluetooth + 413 1 e 1 wwan +-415 1 e 1 wlan ++414 1 e 1 wlan + + # coreboot config options: ME + 424 1 e 14 me_state +diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb +index 96eed178c5..37135bcf0f 100644 +--- a/src/mainboard/dell/e6530/devicetree.cb ++++ b/src/mainboard/dell/e6530/devicetree.cb +@@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gpu_panel_power_up_delay" = "400" + register "gpu_pch_backlight" = "0x13121312" + ++ register "spd_addresses" = "{0x50, 0, 0x52, 0}" ++ + device domain 0x0 on + subsystemid 0x1028 0x0535 inherit + +@@ -24,7 +26,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gen1_dec" = "0x007c0681" + register "gen2_dec" = "0x005c0921" + register "gen3_dec" = "0x003c07e1" +- register "gen4_dec" = "0x007c0901" ++ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC + register "gpi0_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" +@@ -37,7 +39,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "xhci_switchable_ports" = "0x0000000f" + + device ref xhci on end # USB 3.0 Controller +- device ref mei1 off end # Management Engine Interface 1 ++ device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt on end # Management Engine KT +@@ -48,7 +50,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 on end # PCIe Port #3 + device ref pcie_rp4 on end # PCIe Port #4 +- device ref pcie_rp5 off end # PCIe Port #5 ++ device ref pcie_rp5 on end # PCIe Port #5 + device ref pcie_rp6 on end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 +diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c +index d57f48e7f1..2b40f6963f 100644 +--- a/src/mainboard/dell/e6530/early_init.c ++++ b/src/mainboard/dell/e6530/early_init.c +@@ -4,7 +4,6 @@ + #include <bootblock_common.h> + #include <device/pci_ops.h> + #include <ec/dell/mec5035/mec5035.h> +-#include <northbridge/intel/sandybridge/raminit_native.h> + #include <southbridge/intel/bd82x6x/pch.h> + + const struct southbridge_usb_port mainboard_usb_ports[] = { +@@ -26,13 +25,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { + + void bootblock_mainboard_early_init(void) + { +- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f); +- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); + } +- +-void mainboard_get_spd(spd_raw_data *spd, bool id_only) +-{ +- read_spd(&spd[0], 0x50, id_only); +- read_spd(&spd[2], 0x52, id_only); +-} +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch b/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch new file mode 100644 index 00000000..fa7ab40d --- /dev/null +++ b/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch @@ -0,0 +1,54 @@ +From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Thu, 25 Jan 2024 14:37:30 +0000 +Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree + +we neuter anyway. disabling it in devicetree will prevent linux +from ever trying to use it or load a driver for it, and thus +might prevent benign error messages from appearing in dmesg. + +this change was suggested by nicholas when asked on irc. + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/mainboard/dell/e6430/devicetree.cb | 4 ++-- + src/mainboard/dell/e6530/devicetree.cb | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb +index 054b01c5ac..2b8574c984 100644 +--- a/src/mainboard/dell/e6430/devicetree.cb ++++ b/src/mainboard/dell/e6430/devicetree.cb +@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "xhci_switchable_ports" = "0x0000000f" + + device ref xhci on end +- device ref mei1 on end ++ device ref mei1 off end + device ref mei2 off end + device ref me_ide_r off end +- device ref me_kt on end ++ device ref me_kt off end + device ref gbe on end + device ref ehci2 on end + device ref hda on end +diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb +index 37135bcf0f..010200bb6d 100644 +--- a/src/mainboard/dell/e6530/devicetree.cb ++++ b/src/mainboard/dell/e6530/devicetree.cb +@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "xhci_switchable_ports" = "0x0000000f" + + device ref xhci on end # USB 3.0 Controller +- device ref mei1 on end # Management Engine Interface 1 ++ device ref mei1 off end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R +- device ref me_kt on end # Management Engine KT ++ device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0034-x220_edp-modification-introduced-similar-to-x230_edp.patch b/config/coreboot/default/patches/0029-x220_edp-modification-introduced-similar-to-x230_edp.patch index 63e5232e..e0d39892 100644 --- a/config/coreboot/default/patches/0034-x220_edp-modification-introduced-similar-to-x230_edp.patch +++ b/config/coreboot/default/patches/0029-x220_edp-modification-introduced-similar-to-x230_edp.patch @@ -1,12 +1,12 @@ -From 38b9e571e5b2a7116b06fb9d99bccd8b03450f9a Mon Sep 17 00:00:00 2001 +From f07ed32c36978327709a113967ec40e5ba8d828e Mon Sep 17 00:00:00 2001 From: risapav <risapav@gmail.com> Date: Sun, 17 Dec 2023 16:54:07 +0100 -Subject: [PATCH] x220_edp modification introduced, similar to x230_edp +Subject: [PATCH 29/30] x220_edp modification introduced, similar to x230_edp --- src/mainboard/lenovo/x220/Kconfig | 13 ++++++----- src/mainboard/lenovo/x220/Kconfig.name | 3 +++ - src/mainboard/lenovo/x220/Makefile.inc | 6 +++++ + src/mainboard/lenovo/x220/Makefile.mk | 6 +++++ .../lenovo/x220/variants/x220_edp/data.vbt | Bin 0 -> 4281 bytes .../x220/variants/x220_edp/gma-mainboard.ads | 21 ++++++++++++++++++ 5 files changed, 38 insertions(+), 5 deletions(-) @@ -74,10 +74,10 @@ index 988ac4fb55..cd501954e0 100644 + +config BOARD_LENOVO_X220_EDP + bool "ThinkPad X220 eDP Mod (2K/FHD)" -diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc +diff --git a/src/mainboard/lenovo/x220/Makefile.mk b/src/mainboard/lenovo/x220/Makefile.mk index b104bb52a9..052bf17a22 100644 ---- a/src/mainboard/lenovo/x220/Makefile.inc -+++ b/src/mainboard/lenovo/x220/Makefile.inc +--- a/src/mainboard/lenovo/x220/Makefile.mk ++++ b/src/mainboard/lenovo/x220/Makefile.mk @@ -4,6 +4,12 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c @@ -160,5 +160,5 @@ index 0000000000..f7cf0bc264 + +end GMA.Mainboard; -- -2.40.1 +2.39.2 diff --git a/config/coreboot/default/patches/0036-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0030-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index 6ce09e6f..e0af8372 100644 --- a/config/coreboot/default/patches/0036-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/coreboot/default/patches/0030-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,11 +1,36 @@ -From 757b8965ccdd8ecd0eeec33aee3685dd9a33d34e Mon Sep 17 00:00:00 2001 +From 4e0b62e6f0977cf922b1947955538ddca63bb954 Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> -Date: Sat, 23 Dec 2023 23:09:46 +0200 -Subject: [PATCH] mb/hp: Add Compaq Elite 8300 CMT port +Date: Sat, 23 Dec 2023 19:02:10 +0200 +Subject: [PATCH 30/30] mb/hp: Add Compaq Elite 8300 CMT port +Based on autoport and Z220 SuperIO code. + +With SeaBIOS and Nouveau on Debian, only nomodeset works with GTX 780 +(must use proprietary driver instead). + +Tested by xilynx / spot_ on #libreboot: +- i3-3220, native raminit 2x2GB, M378B5773DH0-CH9 + MT8JTF25664AZ-1G6M1 +- Celeron G1620, native raminit 1x4GB, MT8JTF51264AZ-1G6E1 +- Booting Debian with Linux 6.1.0-16-amd64 via SeaBIOS +- All SATA ports +- Audio: internal speaker, headphone and microphone plugs +- Rebooting +- S3 suspend and wake +- libgfxinit: VGA, DisplayPort +- Ethernet +- Super I/O: fan speeds stay in control +- GPU in PEG slot + +Untested: +- EHCI debugging +- Other PCI/PCIe slots +- PS/2 +- Serial, parallel ports + +Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> --- - .../hp/compaq_elite_8300_cmt/Kconfig | 38 ++++ + .../hp/compaq_elite_8300_cmt/Kconfig | 39 ++++ .../hp/compaq_elite_8300_cmt/Kconfig.name | 2 + .../hp/compaq_elite_8300_cmt/Makefile.inc | 7 + .../hp/compaq_elite_8300_cmt/acpi/ec.asl | 1 + @@ -15,14 +40,15 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> .../hp/compaq_elite_8300_cmt/board_info.txt | 5 + .../hp/compaq_elite_8300_cmt/cmos.default | 7 + .../hp/compaq_elite_8300_cmt/cmos.layout | 74 +++++++ + .../hp/compaq_elite_8300_cmt/data.vbt | Bin 0 -> 3902 bytes .../hp/compaq_elite_8300_cmt/devicetree.cb | 161 +++++++++++++++ .../hp/compaq_elite_8300_cmt/dsdt.asl | 26 +++ - .../hp/compaq_elite_8300_cmt/early_init.c | 41 ++++ + .../hp/compaq_elite_8300_cmt/early_init.c | 31 +++ .../compaq_elite_8300_cmt/gma-mainboard.ads | 17 ++ src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++ .../hp/compaq_elite_8300_cmt/hda_verb.c | 33 +++ .../hp/compaq_elite_8300_cmt/mainboard.c | 16 ++ - 17 files changed, 670 insertions(+) + 18 files changed, 661 insertions(+) create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc @@ -33,6 +59,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.default create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout + create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/data.vbt create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/early_init.c @@ -43,10 +70,10 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig new file mode 100644 -index 0000000000..d3a5c3b389 +index 0000000000..d2bfd35dc4 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig -@@ -0,0 +1,38 @@ +@@ -0,0 +1,39 @@ +if BOARD_HP_COMPAQ_ELITE_8300_CMT + +config BOARD_SPECIFIC_OPTIONS @@ -56,6 +83,7 @@ index 0000000000..d3a5c3b389 + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_TPM1 + select MAINBOARD_HAS_LIBGFXINIT @@ -286,6 +314,43 @@ index 0000000000..1fc83b1a55 +checksums + +checksum 392 415 984 +diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt b/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..ba627e152b65d779a80529d3811ec4d21c1b1e54 +GIT binary patch +literal 3902 +zcmdT{U2GIp6h5;vvp;uc+U>N$b}h{<64)*MnJ%?9P1V_-)?HZIZFkwM#K;zQp(Lf0 +z<tLDc9kdaQ30aLnL^K;s2=dhMWTFo|nZ_7XjUmSPK!^{95W@p8ks#}tpO&8zIx!OQ +zPQE$ko;~;Lz2}~D=XOmtlA-CLNM|A&X^#!0H)V!X1yJCH+Hrg@ZIQ%qdRr`<32%!e +zhohV5IamQTwRf%o6o9FhLR}l4OH3XpP6S4SG(9$1II_L8yRfU+nK)!=G!;$I@QxkD +ziDGH&K(Rp6*_Xmpr<F+L;O>b69XhyYd$H6<buRR#UELiUx+zsQbar)jhLo-lr6HwH +z>Fo<WE0Nehba-<rkql=N!$Wj<l*SV2a5_D(Ig)&trbdV3iAW+d5R-_pl<3~6Bc<KD +z#t+ayG>9yU(vE~()R;1j?k!Dq(D1|r9o2pI)6wGoV(Cz^&><0>;1cWR7zP*~YL5XE +z{3`?=k6Yy2an&85Zl2-7jM~D`7^g}MH^6WOPE9askfBLVUBl5fj(Wi%F%Ax(<(|k= +zUH4c9hXO|5?0UW22lb}G1;Fb@mzSZ8u5fTU59si@;V}EXTQ}(rl%Wn?F&a92X)&+> +zPTj@>Ls7r4(ffK2={zn6t_hS-cTaC$zZ!`R#y2KYqnT`O>nqx^H{P7_!|gKQVi}A& +z)G!L9*Z>@59dMlOh4owoes{Vd<dPwV$RfrOM_mMtBi==PggB45i1-TeHR314Rm63~ +z9|&+0AczJ;Ga`TpA^H)6h!kQgqJWr0I1j?@szU?Z5NsM_$vRVlmxGf*(9T-+vzFa+ +z!`K`kmJ}>$kl1)tt1cJZseb2!YSsO`J_8jQ^hAhROmRyl4au@8tDixs`{k^Dwd%=Z +zH-yjQdy~%q^YKY<!Z~QsaFSLvP<_4(KebAii%moAUIzzXdbGph$OYv=h6VegT-HIX +zhmBa>th;}v$r!Z-pnAN<1I)+#R``=|huU|*W1ew~tpBFsG0q;_jCFT6Ulxt*TNv8# +z2{`>`$JM`Jd{F+EzpU7VIlvml?AFW1Xv$0tKyom(Ej2b-oERG0Q?%Jx8HYk6s9{*E +z_)hegWIm-8PLF`1DpU2QrTKj4;VUElwQBD4f+hZ<s%)PPsp_Q#i!T5@)2taxv1ghG +z<B&&<DI4jDn$!FOh>Zbggj@JDLYbjpK69X2PaAVr^Xn{6e+%<?63)ABGAHVvOwA0G +zop-g`)B~42TA5y1<#p#*n`4^oSOPu_>i&oRk>LBlzUQG|c;s(9<VO#^<&i}~RuI}x +z<RL<GguYJXG9hOOy+q_62>FFjhafiyq*<UbLCy*!FVMFH`LsYj73iEG|16MS1xiG@ +zNhE7UniS<%MKUhZlcHP^$pw+li}F>GTo<V<$!jFiA<>K^@07@tL{CZbd5K(<q}Cgp +z=D5OWb(o)+1@4lFyO?u`hP=smQS!Cx@SCx8`ItCXGEp|?Se~I$OQ9>*L<3rb71Ew* +zhn0l-*|a>v(n`=1+Du-&m2f&k|07qiv~u)9FuttfVcu_x;V>QXdsXjZ?db(%oNhK5 +zme#7yVBD-k)j4Zp4ohoWFJ0rv5wpCVNbYROUKoL9Ww31Rg%2ZHHV$2!ik&#T)={qH +z{mrUEty8JFXPPS;w@^`Y*;z%PU#m>bK7$Oci}}Epjc<@x;b&~*!<k@Zeq?5~lKODv +zA_EJ8u45$aFet6+Tz;mY_(sgz72qmZ5DkWZn3D#BWHRv7#wxD)p^~C26;X-mqrjL$ +z8S4>Op}BgEe0X$iI{Gx<zTS2<*M4^|Sg17^@EYY@zAl0)<Ta?zd%bn~D02?r)iu%P +wm+F7xwtgQt<KA_UyAYqlTkT_cS089?Pr=)R7|a9^*a9j1U$>1p1;4R>1E3jwQUCw| + +literal 0 +HcmV?d00001 + diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb new file mode 100644 index 0000000000..f4efabd792 @@ -487,16 +552,15 @@ index 0000000000..e8e2b3a3e5 +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c new file mode 100644 -index 0000000000..f6b9c0a106 +index 0000000000..99b7891c70 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c -@@ -0,0 +1,41 @@ +@@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/nuvoton/npcd378/npcd378.h> +#include <superio/nuvoton/common/nuvoton.h> -+#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) @@ -523,15 +587,6 @@ index 0000000000..f6b9c0a106 + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} -+ -+void mainboard_get_spd(spd_raw_data *spd, bool id_only) -+{ -+ /* BTX mainboard: Reversed mapping */ -+ read_spd(&spd[3], 0x50, id_only); -+ read_spd(&spd[2], 0x51, id_only); -+ read_spd(&spd[1], 0x52, id_only); -+ read_spd(&spd[0], 0x53, id_only); -+} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads new file mode 100644 index 0000000000..686f7d44db @@ -814,5 +869,5 @@ index 0000000000..8dbd95ef96 + .enable_dev = mainboard_enable, +}; -- -2.43.0 +2.39.2 diff --git a/config/coreboot/default/patches/0035-Add-VBT-for-EliteBook-8460p.patch b/config/coreboot/default/patches/0035-Add-VBT-for-EliteBook-8460p.patch deleted file mode 100644 index be01bb76..00000000 --- a/config/coreboot/default/patches/0035-Add-VBT-for-EliteBook-8460p.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 1811aef1046298c490125e1bfc2be4b9cfb69aca Mon Sep 17 00:00:00 2001 -From: Riku Viitanen <riku.viitanen@protonmail.com> -Date: Tue, 19 Dec 2023 20:15:44 +0200 -Subject: [PATCH] Add VBT for EliteBook 8460p - -Extracted from a running system myself. Also sent upstream, of course: -https://review.coreboot.org/c/coreboot/+/79625 - -Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> ---- - src/mainboard/hp/snb_ivb_laptops/Kconfig | 1 + - .../hp/snb_ivb_laptops/variants/8460p/data.vbt | Bin 0 -> 3985 bytes - 2 files changed, 1 insertion(+) - create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8460p/data.vbt - -diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig -index 2ef8956caf..f0bd55f64f 100644 ---- a/src/mainboard/hp/snb_ivb_laptops/Kconfig -+++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig -@@ -54,6 +54,7 @@ config BOARD_HP_8460P - select BOARD_HP_SNB_IVB_LAPTOPS_COMMON - select BOARD_ROMSIZE_KB_8192 - select GFX_GMA_PANEL_1_ON_LVDS -+ select INTEL_GMA_HAVE_VBT - select INTEL_INT15 - select MAINBOARD_HAS_LIBGFXINIT - select SOUTHBRIDGE_INTEL_BD82X6X -diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/data.vbt b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..61d69494c61c08d93e3404c6f096b098a03d0b3a -GIT binary patch -literal 3985 -zcmdT`Z)_A*5TCuhKihY^?R8t=dO$NR1g@o}+XG6eCG7P|X`!^&KQy(0^bfZ{lcTNI -zR!U;RfsJ5LazsPW5Urmyd_YW0j4?5&iPn%9f{CB_fQdonix^QO0_VKFe}sniA|cA# -z{NB7bJ3Bk`-pstWvZtXNyZmj9&o*?nG;Z5kxf3x28l2ASqke8{Xld{2Z}fNj`x{!@ -z13T~?SPX-C_iqA(1VL4NTJ5HmkqIO0?JVmW90?sBiVTPL8@O|HXgF+OFwlbjy?c$Y -z5gD8?LfF-_&5vBA!Wt%r!y#;&JUC=T>M#%<96!+CYz#&wu!jpE*IZfctEygK<<qJ) -zg|&Bg;l@qtwOU^t;=0x@Y~tVGkTG${Fh<ZHsA>%0Sa@>(15N}+#|}q^_aB%*Z=j4+ -zYFZ_A>(DeA1EZ0#wdfCrv6IV;W2Z50M4mT7YZaz2fJ>re6#xVq<cYc<-19+>1hNFp -z5_l!BS;4PE2|}X|iUeDA2<gxwL74=t60EdBg#<3JD1yZbP$EI8D`^-41TPa$%*<(I -zg)a|)E68~WFmp}fEc&?v1tcQ?bW^}of?Oa6z|Q#&O+X7D;6oZ505)O^4wrzbe{nh9 -z(Cp{wo|J${zF3!m=38G=TUW0)G&VJFZw+>K_w@GdjvhVs;<N|uUdY&Gdd{c0f(D=4 -zi=j{S!g0|8r^Q;hD$YWwU4vbAH;fTZ5>7cJxav^h2f`l&Nm60C#9%d{n(z#vnb1kt -zP1r}6A{-;ULO4U1A)F_CNcfa6OSnq7Mz}$^MYuz-<}k=5*!RHQxFrg-;MAf*lIABU -zxU6uh45H_f{BtS3DZOwPk2@T2KmLsy;&Ev+|C4^p3bZgnBT?R(leE>Oq8LohyNU7z -z>`l(&adsIft`jXDf7(aRub?DKP9%dHxj%w!Y&oat7NyaH0v20jeu4Ctslme<Qv5W1 -zd;z%t+9};dtba){)$RiL@u(ugpQ0}}2ZYybeejE|67o(0#oH5WIlNwE-(1sF;CMm{ -zRIDVRA|zOO(X!I?(M@{vC;#qMe&%<oYzBPl=LHCPW@$_@=F-Bq!0t(~9rbfx|Mzbe -z?;smQvy@2bYN$=;0<<;-`-6icM!0S8ppoTdNi&3sK=;Ec&3&RK;hkG6hqE1^>DpL9 -zf>Zon)ztM4&nmt5Y>LyoMc0Nd`gHwLisSY|%@HxN-g3<m8{dBb8VNBo-)Lkvk1&vn -zyif#p=qZAjfRK1*K~FvvLT2RQT9(ej6$c~S7EToWKS$ixY?{|i>oRUiCW<wX`;;uy -z%3cTY_Z(cx)Jn!SGTg(|QN|84e4D8sF!l+<@0t1=WA_-YaH<=eY>N{Or+UcAjymyO -zr~0vzec{BPo$B9CW|MJ^tZtUsHW?4f>Jgc}EaUsK`kBlw%lNCTigcw>aGj!VrJIz3 -zlZtv=VW$=RNKwC5*tZJ)rKrwawkTIAzh#YDt_#t83NhM9DI(KG^jc(--WFU$ZF#Hd -zF#0Yh8pG?$UD80Q=^qr+-Y4S$#a_$88fNkks(Y8AH(Hq1U`fVNj}63x229#eAtY?L -z0T~<Ar9Gh_6lxk4!iEbj01uDJMEue1$I3O-&+En9;ODVy?v*@c^JJxA3OhV5-IY!s -zo&#nn%~HeMbmJP#+nuc2FJ@uG-1OwxXI2e4vy$`e=Dw1i^BqvEHN}#9;ii?0nSn~C -zWU~%0tc}eKc#3rmlZA!i!5X7$DpiH3BO5Qg_0gHJiz`S&c{(0!G4sHaXKd5Sc$m+N -zH_K+ObWE3O!8ewqHHhFeZP4x6Xwb^_*@5Yh=I%)5D|sP;Y-->~^ukd+r@)#T%yXSm -z2eZ&{(*rX>T%yTZAmc@h^3hz$S~DKz&rM5R)css-rQTba*$WZ!5?)APUpOzybQp+2 -z!GOz^pRs|?du~IPhs{$Xwq_9QZL@SyKA-5fU$aT6@q_%w8CNWVSDR?@TIdG83xW`W -K3gHa=B>n?bM39pJ - -literal 0 -HcmV?d00001 - --- -2.43.0 - diff --git a/config/coreboot/default/patches/0037-mb-hp-elitebook_820_g2-do-not-set-EC-SLPT-on-S5.patch b/config/coreboot/default/patches/0037-mb-hp-elitebook_820_g2-do-not-set-EC-SLPT-on-S5.patch deleted file mode 100644 index bc584ffe..00000000 --- a/config/coreboot/default/patches/0037-mb-hp-elitebook_820_g2-do-not-set-EC-SLPT-on-S5.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 6202669b8e8f50837448e2d4c482671abf72f648 Mon Sep 17 00:00:00 2001 -From: Iru Cai <mytbk920423@gmail.com> -Date: Sun, 5 Nov 2023 17:12:43 +0800 -Subject: [PATCH 1/1] mb/hp/elitebook_820_g2: do not set EC SLPT on S5 - -Setting EC SLPT bit in S5 will make HP EliteBook 820 G2 -fail to reboot under Linux 6.1 and later kernel versions. - -Change-Id: I48f5a35cd78db3b32d9f76cb8e266c738da34e7c -Signed-off-by: Iru Cai <mytbk920423@gmail.com> -Reviewed-on: https://review.coreboot.org/c/coreboot/+/78907 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> ---- - src/mainboard/hp/elitebook_820_g2/acpi/platform.asl | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl b/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl -index 8023ae826c..d17f575c40 100644 ---- a/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl -+++ b/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl -@@ -10,5 +10,8 @@ Method(_WAK,1) - - Method(_PTS,1) - { -- \_SB.PCI0.LPCB.EC0.SLPT = Arg0 -+ If (Arg0 != 5) -+ { -+ \_SB.PCI0.LPCB.EC0.SLPT = Arg0 -+ } - } --- -2.39.2 - |