diff options
| author | Leah Rowe <leah@libreboot.org> | 2024-10-26 05:41:46 +0100 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2024-10-26 06:26:25 +0100 |
| commit | 99a88ebfa20421909675e9de6ed9376049f433d4 (patch) | |
| tree | f106402f6bc17d10bd888cf10866ff71121ef417 /config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch | |
| parent | 3f63c6d12f6b9ad8e0d7846c313f5adfb46a942e (diff) | |
Update dell 3050 patch to patch 15 (pwm fix)
Use patchset 15 instead of 14:
config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch
Rebase the verb patch; patchset 15 modified the Makefile:
config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch
We were using patchset 14 for the 3050 micro:
https://review.coreboot.org/c/coreboot/+/82053/14
Now we use patchset 15:
https://review.coreboot.org/c/coreboot/+/82053/15
Without this patch, the fans are always on a low setting, on
the Dell OptiPlex 3050 Micro, even under stress conditions. With
this patch, the fans change speed according to CPU temperature.
I had to rebase my verb patch, because Mate modified the Makefile
to add his sch5555 handler, on the same line where I add hda_verb.
Mate tells me he will merge my verb and vbt patches into a further
patchset later on. For now, I've simply rebased these patches on
top of Mate's newer work; I've told him he can use them in his port.
I'm probably going to now issue a new revision ROM image for
Libreboot 20241008, so that users can get this fix sooner.
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch')
| -rw-r--r-- | config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch b/config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch index 9f074e17..b4108c7b 100644 --- a/config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch +++ b/config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch @@ -1,7 +1,7 @@ -From eb8150a07c472078ad37887de13a166e6cf8bdad Mon Sep 17 00:00:00 2001 +From cc302630662eee011a903df4fd7a36d82bd22203 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 21:49:40 +0200 -Subject: [PATCH 06/17] haswell NRI: Add DDR3 JEDEC reset and init +Subject: [PATCH 48/65] haswell NRI: Add DDR3 JEDEC reset and init Implement JEDEC reset and init sequence for DDR3. The MRS commands are issued through the REUT (Robust Electrical Unified Testing) hardware. @@ -1032,5 +1032,5 @@ index 07f4b9dc16..5b3696347c 100644 #define PMSYNC_CONFIG2 0x33cc /* 32bit */ #define SOFT_RESET_CTRL 0x38f4 -- -2.39.2 +2.39.5 |