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| author | Leah Rowe <leah@libreboot.org> | 2024-10-26 05:41:46 +0100 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2024-10-26 06:26:25 +0100 |
| commit | 99a88ebfa20421909675e9de6ed9376049f433d4 (patch) | |
| tree | f106402f6bc17d10bd888cf10866ff71121ef417 /config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch | |
| parent | 3f63c6d12f6b9ad8e0d7846c313f5adfb46a942e (diff) | |
Update dell 3050 patch to patch 15 (pwm fix)
Use patchset 15 instead of 14:
config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch
Rebase the verb patch; patchset 15 modified the Makefile:
config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch
We were using patchset 14 for the 3050 micro:
https://review.coreboot.org/c/coreboot/+/82053/14
Now we use patchset 15:
https://review.coreboot.org/c/coreboot/+/82053/15
Without this patch, the fans are always on a low setting, on
the Dell OptiPlex 3050 Micro, even under stress conditions. With
this patch, the fans change speed according to CPU temperature.
I had to rebase my verb patch, because Mate modified the Makefile
to add his sch5555 handler, on the same line where I add hda_verb.
Mate tells me he will merge my verb and vbt patches into a further
patchset later on. For now, I've simply rebased these patches on
top of Mate's newer work; I've told him he can use them in his port.
I'm probably going to now issue a new revision ROM image for
Libreboot 20241008, so that users can get this fix sooner.
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch')
| -rw-r--r-- | config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch b/config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch index 924385ed..69e32d2f 100644 --- a/config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch +++ b/config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch @@ -1,7 +1,7 @@ -From adde2e8d038b2d07ab7287eedab5888d92a56a60 Mon Sep 17 00:00:00 2001 +From 876011559681881d950ad3b6742b40322f1f5a6d Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 16:29:55 +0200 -Subject: [PATCH 02/17] haswell NRI: Post-process selected timings +Subject: [PATCH 44/65] haswell NRI: Post-process selected timings Once the MPLL has been initialised, convert the timings from the SPD to be in DCLKs, which is what the hardware expects. In addition, calculate @@ -245,5 +245,5 @@ index eff993800b..4f7fe46494 100644 + return RAMINIT_STATUS_SUCCESS; +} -- -2.39.2 +2.39.5 |