diff options
| author | Leah Rowe <leah@libreboot.org> | 2025-07-14 11:18:42 +0100 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2025-07-14 11:26:58 +0100 |
| commit | cc2f08e7bbf9fc32bdd37079ee93b477ef4e8d09 (patch) | |
| tree | 3283ed01c1d2cdedf255257cbcf0849e24f54566 /config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch | |
| parent | 32dfdfbb01b84bb9c058e9b84305f15a14d4e231 (diff) | |
This reverts commit 32dfdfbb01b84bb9c058e9b84305f15a14d4e231.
The update caused an issue on T480:
Backlight comes on, then off, then on, then off, repeatedly, and
never gets to the payload. Will have to investigate further.
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch')
| -rw-r--r-- | config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch | 1859 |
1 files changed, 0 insertions, 1859 deletions
diff --git a/config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch b/config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch deleted file mode 100644 index 8f9d1d97..00000000 --- a/config/coreboot/default/patches/0041-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch +++ /dev/null @@ -1,1859 +0,0 @@ -From 05d402ba24e80a164fc3f7332ef9086a4750d266 Mon Sep 17 00:00:00 2001 -From: Matt DeVillier <matt.devillier@gmail.com> -Date: Wed, 9 Jul 2025 12:28:48 -0500 -Subject: [PATCH 41/43] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s - -These machine have BootGuard fused and requires deguard to -boot coreboot. - -Known issues: -- Alpine Ridge Thunderbolt 3 controller does not work -- Some Fn+F{1-12} keys aren't handled correctly -- Nvidia dGPU is finicky - - Needs option ROM - - Power enable code is buggy - - Nouveau only works on linux 6.8-6.9 -- Headphone jack isn't detected as plugged in despite correct verbs - -Thanks to Leah Rowe for helping with the T480s. - -Change-Id: I19d421412c771c1f242f6ff39453f824fa866163 -Signed-off-by: Mate Kukri <km@mkukri.xyz> -Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> ---- - src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 84 ++++++++ - .../lenovo/sklkbl_thinkpad/Kconfig.name | 7 + - .../lenovo/sklkbl_thinkpad/Makefile.mk | 21 ++ - .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 12 ++ - .../lenovo/sklkbl_thinkpad/acpi/superio.asl | 3 + - .../lenovo/sklkbl_thinkpad/board_info.txt | 6 + - .../lenovo/sklkbl_thinkpad/bootblock.c | 9 + - src/mainboard/lenovo/sklkbl_thinkpad/cfr.c | 82 +++++++ - .../lenovo/sklkbl_thinkpad/devicetree.cb | 78 +++++++ - src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 33 +++ - src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 + - .../lenovo/sklkbl_thinkpad/ramstage.c | 87 ++++++++ - .../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes - .../variants/t480/gma-mainboard.ads | 19 ++ - .../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++ - .../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++ - .../variants/t480/memory_init_params.c | 20 ++ - .../variants/t480/overridetree.cb | 93 ++++++++ - .../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes - .../variants/t480s/gma-mainboard.ads | 19 ++ - .../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++ - .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++ - .../variants/t480s/memory_init_params.c | 44 ++++ - .../variants/t480s/overridetree.cb | 93 ++++++++ - .../variants/t480s/spd/spd_0.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_1.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_10.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_11.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_12.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_13.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_14.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_15.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_16.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_17.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_18.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_19.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_2.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_20.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_3.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_4.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_5.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_6.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_7.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_8.bin | Bin 0 -> 512 bytes - .../variants/t480s/spd/spd_9.bin | Bin 0 -> 512 bytes - 45 files changed, 1300 insertions(+) - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/cfr.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_20.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin - create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -new file mode 100644 -index 0000000000..ccf43ea5c0 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -@@ -0,0 +1,84 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ bool -+ select BOARD_ROMSIZE_KB_16384 -+ select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE -+ select EC_LENOVO_H8 -+ select EC_LENOVO_MEC1653 -+ select EC_LENOVO_PMH7 -+ select H8_HAS_BAT_THRESHOLDS_IMPL -+ select H8_HAS_LEDLOGO -+ select H8_HAS_PRIMARY_FN_KEYS -+ select H8_SUPPORT_BT_ON_WIFI -+ select HAVE_ACPI_RESUME -+ select HAVE_ACPI_TABLES -+ select INTEL_GMA_HAVE_VBT -+ select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_HAS_TPM2 -+ select MAINBOARD_USES_IFD_GBE_REGION -+ select MEMORY_MAPPED_TPM -+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB -+ select SOC_INTEL_KABYLAKE -+ select SPD_READ_BY_WORD -+ select SYSTEM_TYPE_LAPTOP -+ -+config BOARD_LENOVO_T480 -+ bool -+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ select MEC1653_SEND_DEBUG_UNLOCK -+ -+config BOARD_LENOVO_T480S -+ bool -+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ -+if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON -+ -+config MAINBOARD_DIR -+ default "lenovo/sklkbl_thinkpad" -+ -+config VARIANT_DIR -+ default "t480" if BOARD_LENOVO_T480 -+ default "t480s" if BOARD_LENOVO_T480S -+ -+config OVERRIDE_DEVICETREE -+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -+ -+config MAINBOARD_PART_NUMBER -+ default "T480" if BOARD_LENOVO_T480 -+ default "T480s" if BOARD_LENOVO_T480S -+ -+config CBFS_SIZE -+ default 0x900000 -+ -+config DIMM_MAX -+ default 2 -+ -+config DIMM_SPD_SIZE -+ default 512 # DDR4 -+ -+config CONSOLE_SERIAL -+ default n -+ -+config NO_POST -+ default y -+ -+config EDK2_BOOT_MANAGER_ESCAPE -+ default y -+ -+config EDK2_FOLLOW_BGRT_SPEC -+ default y -+ -+config EDK2_FULL_SCREEN_SETUP -+ default n -+ -+config PS2K_EISAID -+ default "LEN0071" -+ -+config PS2M_EISAID -+ default "LEN0094" -+ -+config THINKPADEC_HKEY_EISAID -+ default "LEN0268" -+ -+endif -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -new file mode 100644 -index 0000000000..abc273f387 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -@@ -0,0 +1,7 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config BOARD_LENOVO_T480 -+ bool "ThinkPad T480" -+ -+config BOARD_LENOVO_T480S -+ bool "ThinkPad T480s" -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk -new file mode 100644 -index 0000000000..7122a232b4 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk -@@ -0,0 +1,21 @@ -+## SPDX-License-Identifier: GPL-2.0-only -+ -+bootblock-y += bootblock.c -+ -+romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c -+ -+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c -+ramstage-y += ramstage.c -+ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads -+ -+# Add files spd_0.bin to spd_20.bin to the cbfs image -+ifeq ($(CONFIG_BOARD_LENOVO_T480S),y) -+SPD_BINS := $(shell seq 0 20) -+define SPD_template -+cbfs-files-y += spd_$(1).bin -+spd_$(1).bin-file := variants/$(VARIANT_DIR)/spd/spd_$(1).bin -+spd_$(1).bin-type := raw -+endef -+$(foreach n,$(SPD_BINS),$(eval $(call SPD_template,$(n)))) -+endif -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl -new file mode 100644 -index 0000000000..3a949a2fca ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -+#define THINKPAD_EC_GPE 22 -+ -+Name(\TCRT, 100) -+Name(\TPSV, 90) -+Name(\FLVL, 0) -+ -+#include <ec/lenovo/h8/acpi/ec.asl> -+#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl> -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl -new file mode 100644 -index 0000000000..55b1db5b11 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl -@@ -0,0 +1,3 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <drivers/pc80/pc/ps2_controller.asl> -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt b/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt -new file mode 100644 -index 0000000000..07ab6a3cd0 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt -@@ -0,0 +1,6 @@ -+Category: laptop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: y -+Release year: 2016 -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c -new file mode 100644 -index 0000000000..e1fdf18add ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <bootblock_common.h> -+#include <ec/lenovo/mec1653/mec1653.h> -+ -+void bootblock_mainboard_early_init(void) -+{ -+ bootblock_ec_init(); -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c -new file mode 100644 -index 0000000000..45f344b939 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c -@@ -0,0 +1,82 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <boot/coreboot_tables.h> -+#include <drivers/option/cfr_frontend.h> -+#include <ec/lenovo/h8/cfr.h> -+#include <ec/lenovo/pmh7/cfr.h> -+#include <intelblocks/cfr.h> -+#include <soc/cfr.h> -+#include <static.h> -+ -+/* Hide the dGPU CFR entry if dGPU not present */ -+static void update_dgpu(const struct sm_object *obj, struct sm_object *new) -+{ -+ struct device *dgpu = DEV_PTR(dgpu); -+ if (!dgpu || !dgpu->enabled) { -+ new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS; -+ } -+} -+ -+/* dGPU */ -+static const struct sm_object dgpu = SM_DECLARE_ENUM({ -+ .opt_name = "dgpu_enable", -+ .ui_name = "dGPU", -+ .ui_helptext = "Enable or disable the dGPU", -+ .default_value = 0, -+ .values = (const struct sm_enum_value[]) { -+ { "Disabled", 0 }, -+ { "Enabled", 1 }, -+ SM_ENUM_VALUE_END }, -+}, WITH_CALLBACK(update_dgpu)); -+ -+static struct sm_obj_form system = { -+ .ui_name = "System", -+ .obj_list = (const struct sm_object *[]) { -+ &dgpu, -+ &hyper_threading, -+ &igd_dvmt, -+ &igd_aperture, -+ &legacy_8254_timer, -+ &me_state, -+ &me_state_counter, -+ &pciexp_aspm, -+ &pciexp_clk_pm, -+ &pciexp_l1ss, -+ &pciexp_speed, -+ &s0ix_enable, -+ &vtd, -+ NULL -+ }, -+}; -+ -+static struct sm_obj_form ec = { -+ .ui_name = "Embedded Controller", -+ .obj_list = (const struct sm_object *[]) { -+ &bluetooth, -+ &backlight, -+ &uwb, -+ &usb_always_on, -+ &volume, -+ &wlan, -+ &wwan, -+ &pm_beeps, -+ &battery_beep, -+ &fn_ctrl_swap, -+ &sticky_fn, -+ &f1_to_f12_as_primary, -+ &touchpad, -+ &trackpoint, -+ NULL -+ }, -+}; -+ -+static struct sm_obj_form *sm_root[] = { -+ &ec, -+ &system, -+ NULL -+}; -+ -+void mb_cfr_setup_menu(struct lb_cfr *cfr_root) -+{ -+ cfr_write_setup_menu(cfr_root, sm_root); -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb -new file mode 100644 -index 0000000000..5ec7750025 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb -@@ -0,0 +1,78 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ -+ # Power -+ register "PmConfigSlpS3MinAssert" = "2" # 50ms -+ register "PmConfigSlpS4MinAssert" = "1" # 1s -+ register "PmConfigSlpSusMinAssert" = "3" # 500ms -+ register "PmConfigSlpAMinAssert" = "3" # 2s -+ -+ device domain 0 on -+ subsystemid 0x17aa 0x225d inherit -+ device ref igpu on -+ register "gfx" = "GMA_STATIC_DISPLAYS(0)" -+ register "panel_cfg" = "{ -+ .up_delay_ms = 200, -+ .down_delay_ms = 50, -+ .cycle_delay_ms = 600, -+ .backlight_on_delay_ms = 1, -+ .backlight_off_delay_ms = 200, -+ .backlight_pwm_hz = 200, -+ }" -+ end -+ device ref sa_thermal on end -+ device ref thermal on end -+ device ref south_xhci on end -+ device ref sata on -+ register "SataPortsEnable[2]" = "1" -+ register "SataPortsDevSlp[2]" = "1" -+ end -+ device ref lpc_espi on -+ register "serirq_mode" = "SERIRQ_CONTINUOUS" -+ -+ register "gen1_dec" = "0x007c1601" -+ register "gen2_dec" = "0x000c15e1" -+ register "lpc_ioe" = "LPC_IOE_EC_4E_4F | -+ LPC_IOE_EC_62_66 | -+ LPC_IOE_KBC_60_64" -+ -+ chip ec/lenovo/pmh7 -+ register "backlight_enable" = "true" -+ register "dock_event_enable" = "true" -+ device pnp ff.1 on end # dummy -+ end -+ -+ chip ec/lenovo/h8 -+ register "beepmask0" = "0x00" -+ register "beepmask1" = "0x86" -+ register "config0" = "0xa6" -+ register "config1" = "0x0d" -+ register "config2" = "0xa8" -+ register "config3" = "0xc4" -+ register "has_keyboard_backlight" = "1" -+ register "event2_enable" = "0xff" -+ register "event3_enable" = "0xff" -+ register "event4_enable" = "0xd0" -+ register "event5_enable" = "0x3c" -+ register "event7_enable" = "0x01" -+ register "event8_enable" = "0x7b" -+ register "event9_enable" = "0xff" -+ register "eventc_enable" = "0xff" -+ register "eventd_enable" = "0xff" -+ register "evente_enable" = "0x9d" -+ device pnp ff.2 on # dummy -+ io 0x60 = 0x62 -+ io 0x62 = 0x66 -+ io 0x64 = 0x1600 -+ io 0x66 = 0x1604 -+ end -+ end -+ -+ chip drivers/pc80/tpm -+ device pnp 0c31.0 on end -+ end -+ end -+ device ref hda on end -+ end -+end -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl -new file mode 100644 -index 0000000000..aa4d4de2a6 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpi.h> -+DefinitionBlock( -+ "dsdt.aml", -+ "DSDT", -+ ACPI_DSDT_REV_2, -+ OEM_ID, -+ ACPI_TABLE_CREATOR, -+ 0x20110725 -+) -+{ -+ #include <acpi/dsdt_top.asl> -+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> -+ #include <cpu/intel/common/acpi/cpu.asl> -+ -+ Device (\_SB.PCI0) -+ { -+ #include <soc/intel/skylake/acpi/systemagent.asl> -+ #include <soc/intel/skylake/acpi/pch.asl> -+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> -+ } -+ -+ Scope (\_SB.PCI0.RP01) -+ { -+ Device (PEGP) -+ { -+ Name (_ADR, Zero) -+ } -+ } -+ -+ #include <southbridge/intel/common/acpi/sleepstates.asl> -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h -new file mode 100644 -index 0000000000..d89ed712d4 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef GPIO_H -+#define GPIO_H -+ -+void variant_config_gpios(void); -+ -+#endif -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c -new file mode 100644 -index 0000000000..eb582a7948 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c -@@ -0,0 +1,87 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <acpi/acpigen.h> -+#include <console/console.h> -+#include <device/device.h> -+#include <device/pci_rom.h> -+#include <option.h> -+#include <soc/ramstage.h> -+#include <static.h> -+#include "gpio.h" -+ -+#define GPIO_GPU_RST GPP_E22 // active low -+#define GPIO_1R8VIDEO_AON_ON GPP_E23 -+ -+#define GPIO_DGFX_PWRGD GPP_F3 -+ -+#define GPIO_DISCRETE_PRESENCE GPP_D9 // active low -+#define GPIO_DGFX_VRAM_ID0 GPP_D11 -+#define GPIO_DGFX_VRAM_ID1 GPP_D12 -+ -+void mainboard_silicon_init_params(FSP_SIL_UPD *params) -+{ -+ // Setup GPIOs -+ variant_config_gpios(); -+} -+ -+static void mainboard_fill_ssdt(const struct device *dev) -+{ -+ struct rom_header *rom; -+ struct device *dgpu = DEV_PTR(dgpu); -+ -+ /* Add entry for dGPU if present/enabled */ -+ if (!dgpu || !dgpu->enabled) -+ return; -+ -+ /* ROM should be already loaded? */ -+ rom = dgpu->pci_vga_option_rom; -+ if (!rom) { -+ rom = pci_rom_probe(dgpu); -+ if (!pci_rom_load(dgpu, rom)) -+ return; -+ } -+ -+ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP"); -+ acpigen_write_rom((void *)rom, rom->size * 512); -+ acpigen_pop_len(); -+} -+ -+static void dgpu_detect(void) -+{ -+ static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" }; -+ -+ int dgfx_vram_id; -+ -+ // Detect and enable dGPU -+ if (gpio_get(GPIO_DISCRETE_PRESENCE) == 0) { // active low -+ dgfx_vram_id = gpio_get(GPIO_DGFX_VRAM_ID0) | gpio_get(GPIO_DGFX_VRAM_ID1) << 1; -+ printk(BIOS_DEBUG, "Discrete GPU present with %s VRAM\n", dgfx_vram_id_str[dgfx_vram_id]); -+ -+ // NOTE: i pulled this GPU enable sequence from thin air -+ // it sometimes works but is buggy and the GPU disappears in some cases so disabling it by default. -+ // also unrelated to this enable sequence the nouveau driver only works on 6.8-6.9 kernels -+ if (get_uint_option("dgpu_enable", 0)) { -+ printk(BIOS_DEBUG, "Enabling discrete GPU\n"); -+ gpio_set(GPIO_1R8VIDEO_AON_ON, 1); // Enable GPU power rail -+ while (!gpio_get(GPIO_DGFX_PWRGD)) // Wait for power good signal from GPU -+ ; -+ gpio_set(GPIO_GPU_RST, 1); // Release GPU from reset -+ } else { -+ printk(BIOS_DEBUG, "Discrete GPU will remain disabled\n"); -+ } -+ -+ } else { -+ printk(BIOS_DEBUG, "Discrete GPU not present\n"); -+ } -+} -+ -+static void mainboard_enable(struct device *dev) -+{ -+ dgpu_detect(); -+ -+ dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; -+} -+ -+struct chip_operations mainboard_ops = { -+ .enable_dev = mainboard_enable, -+}; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3 -GIT binary patch -literal 4106 -zcmeHJU2GIp6h5=FKeKmc=rAo()>4l^U|XP_ZDGYy!|YE>mu}hZ4|PdQy1<TF-O}0? -zDF)LeX(GlTYoZ2xkUp4bc(Fbi;|s>bV0gipVB&+pHzmFpc`=IXxii}qiqH*)7}PU+ -z?woV)x!<09?wNbfhQa6n_IK}3M!Gw&OgS)sY2Q$LJ4F+z{-JneATkt9refXr6+8sr -zR{e1eASVcGl#mf_O&p%I^1;3af=xDeN0ZnydT=;zHOH-q=O;(UFda)^<j^52Z;c<A -zv~t)#xI2OzS7p&7!}%QUJu-688gD}mM%EbG*3`NU(Fiq%!p$v4=y8%;+qQ?>LXW8| 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constant Port_List := -+ (eDP, -+ DP1, -+ DP2, -+ HDMI1, -+ HDMI2, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -new file mode 100644 -index 0000000000..f7c29e1f39 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c -@@ -0,0 +1,203 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <soc/gpio.h> -+#include "../../gpio.h" -+ -+/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style -+ * attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */ -+ -+static const struct pad_config gpio_table[] = { -+ -+ /* ------- GPIO Community 0 ------- */ -+ -+ /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ -+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ -+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ -+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ -+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ -+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ -+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ -+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ -+ PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1), /* LPCCLK_EC_24M */ -+ PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1), /* LPCCLK_DEBUG_24M */ -+ PAD_NC(GPP_A11, NONE), -+ PAD_NC(GPP_A12, NONE), -+ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */ -+ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */ -+ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSWARN */ -+ PAD_NC(GPP_A16, NONE), -+ PAD_NC(GPP_A17, NONE), -+ PAD_NC(GPP_A18, NONE), -+ PAD_NC(GPP_A19, NONE), -+ PAD_NC(GPP_A20, NONE), -+ PAD_NC(GPP_A21, NONE), -+ PAD_NC(GPP_A22, NONE), -+ PAD_NC(GPP_A23, NONE), -+ -+ /* ------- GPIO Group GPP_B ------- */ -+ PAD_NC(GPP_B0, NONE), -+ PAD_NC(GPP_B1, NONE), -+ PAD_NC(GPP_B2, NONE), -+ PAD_NC(GPP_B3, NONE), -+ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */ -+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 */ -+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 */ -+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 */ -+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 */ -+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 */ -+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE10 */ -+ PAD_NC(GPP_B11, NONE), -+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ -+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ -+ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */ -+ PAD_CFG_GPO(GPP_B15, 1, DEEP), /* NFC_DLREQ */ -+ PAD_NC(GPP_B16, NONE), -+ PAD_NC(GPP_B17, NONE), -+ PAD_NC(GPP_B18, NONE), -+ PAD_NC(GPP_B19, NONE), -+ PAD_NC(GPP_B20, NONE), -+ PAD_NC(GPP_B21, NONE), -+ PAD_NC(GPP_B22, NONE), -+ PAD_NC(GPP_B23, NONE), -+ -+ /* ------- GPIO Community 1 ------- */ -+ -+ /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ -+ PAD_NC(GPP_C2, NONE), -+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ -+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ -+ PAD_NC(GPP_C5, NONE), -+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ -+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ -+ PAD_NC(GPP_C8, NONE), -+ PAD_NC(GPP_C9, NONE), -+ PAD_NC(GPP_C10, NONE), -+ PAD_NC(GPP_C11, NONE), -+ PAD_NC(GPP_C12, NONE), -+ PAD_NC(GPP_C13, NONE), -+ PAD_NC(GPP_C14, NONE), -+ PAD_NC(GPP_C15, NONE), -+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ -+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ -+ PAD_NC(GPP_C18, NONE), -+ PAD_NC(GPP_C19, NONE), -+ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -+ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ -+ -+ /* ------- GPIO Group GPP_D ------- */ -+ PAD_NC(GPP_D0, NONE), -+ PAD_NC(GPP_D1, NONE), -+ PAD_NC(GPP_D2, NONE), -+ PAD_NC(GPP_D3, NONE), -+ PAD_NC(GPP_D4, NONE), -+ PAD_NC(GPP_D5, NONE), -+ PAD_NC(GPP_D6, NONE), -+ PAD_NC(GPP_D7, NONE), -+ PAD_NC(GPP_D8, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */ -+ PAD_NC(GPP_D10, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */ -+ PAD_NC(GPP_D13, NONE), -+ PAD_NC(GPP_D14, NONE), -+ PAD_NC(GPP_D15, NONE), -+ PAD_NC(GPP_D16, NONE), -+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY1 */ -+ PAD_NC(GPP_D18, NONE), -+ PAD_NC(GPP_D19, NONE), -+ PAD_NC(GPP_D20, NONE), -+ PAD_NC(GPP_D21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ -+ PAD_NC(GPP_D23, NONE), -+ -+ /* ------- GPIO Group GPP_E ------- */ -+ PAD_NC(GPP_E0, NONE), -+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -WWAN_SATA_DTCT (always HIGH) */ -+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -PE_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */ -+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ -+ PAD_NC(GPP_E5, NONE), -+ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */ -+ PAD_NC(GPP_E7, NONE), -+ PAD_NC(GPP_E8, NONE), -+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 (AON port) */ -+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 (regular port) */ -+ PAD_NC(GPP_E11, NONE), -+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ -+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ -+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ -+ PAD_NC(GPP_E15, NONE), -+ PAD_NC(GPP_E16, NONE), -+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ -+ PAD_NC(GPP_E18, NONE), -+ PAD_NC(GPP_E19, NONE), -+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ -+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ -+ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */ -+ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */ -+ -+ /* ------- GPIO Community 2 ------- */ -+ -+ /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ -+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ -+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ -+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ -+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ -+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ -+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ -+ PAD_NC(GPD7, NONE), -+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ -+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ -+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ -+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ -+ -+ /* ------- GPIO Community 3 ------- */ -+ -+ /* ------- GPIO Group GPP_F ------- */ -+ PAD_NC(GPP_F0, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */ -+ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* DGFX_PWRGD */ -+ PAD_CFG_GPO(GPP_F4, 1, DEEP), /* -WWAN_RESET */ -+ PAD_NC(GPP_F5, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */ -+ PAD_NC(GPP_F16, NONE), -+ PAD_NC(GPP_F17, NONE), -+ PAD_NC(GPP_F18, NONE), -+ PAD_NC(GPP_F19, NONE), -+ PAD_NC(GPP_F20, NONE), -+ PAD_NC(GPP_F21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -INTRUDER_PCH */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */ -+ -+ /* ------- GPIO Group GPP_G ------- */ -+ PAD_NC(GPP_G0, NONE), -+ PAD_NC(GPP_G1, NONE), -+ PAD_NC(GPP_G2, NONE), -+ PAD_NC(GPP_G3, NONE), -+ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ -+}; -+ -+void variant_config_gpios(void) -+{ -+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -new file mode 100644 -index 0000000000..3a951ce0da ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c -@@ -0,0 +1,90 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 -+ 0x17aa225d, // Subsystem ID -+ 11, -+ AZALIA_SUBVENDOR(0, 0x17aa225d), -+ -+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_MIC_IN, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_SPEAKER, -+ AZALIA_OTHER_ANALOG, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_MIC_IN, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 3, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_HP_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 15 -+ )), -+ -+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI -+ 0x80860101, // Subsystem ID -+ 4, -+ AZALIA_SUBVENDOR(2, 0x80860101), -+ -+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 3, 0 -+ )), -+}; -+ -+const u32 pc_beep_verbs[] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c -new file mode 100644 -index 0000000000..5252a402f9 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c -@@ -0,0 +1,20 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <soc/romstage.h> -+#include <spd_bin.h> -+ -+void mainboard_memory_init_params(FSPM_UPD *mupd) -+{ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */ -+ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ -+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; -+ -+ /* Get SPD for memory slots */ -+ struct spd_block blk = { .addr_map = { 0x50, 0x51, } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; -+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb -new file mode 100644 -index 0000000000..9acb823c10 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb -@@ -0,0 +1,93 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ device domain 0 on -+ device ref south_xhci on -+ register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC1), // USB-A -+ [1] = USB2_PORT_MID(OC0), // USB-A (always on) -+ [2] = USB2_PORT_MID(OC_SKIP), // JSC-1 (smartcard slot) -+ [3] = USB2_PORT_MID(OC_SKIP), // USB-C (charging port) -+ [4] = USB2_PORT_MID(OC_SKIP), // JCAM1 (IR camera) -+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN1 (M.2 WWAN USB) -+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN1 (M.2 WLAN USB) -+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM1 (webcam) -+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR1 (fingerprint reader) -+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD1 (touch panel) -+ }" -+ register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC1), // USB-A -+ [1] = USB3_PORT_DEFAULT(OC0), // USB-A (always on) -+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // RTS5344S (SD card reader) -+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C (charging port) -+ }" -+ end -+ -+ # PCIe controller 1 - 1x4 -+ # PCIE 1-4 - RP1 - dGPU - CLKOUT0 - CLKREQ0 -+ # -+ # PCIe controller 2 - 2x1+1x2 (lane reversal) -+ # PCIE 5 - GBE - GBE - CLKOUT1 - CLKREQ1 (clobbers RP8) -+ # PCIE 6 - RP7 - WLAN - CLKOUT2 - CLKREQ2 -+ # PCIE 7-8 - RP5 - WWAN - CLKOUT3 - CLKREQ3 -+ # -+ # PCIe controller 3 - 2x2 -+ # PCIE 9-10 - RP9 - TB3 - CLKOUT4 - CLKREQ4 -+ # PCIE 11-12 - RP11 - SSD - CLKOUT5 - CLKREQ5 -+ -+ # dGPU - x4 -+ device ref pcie_rp1 on -+ register "PcieRpClkReqSupport[0]" = "1" -+ register "PcieRpClkReqNumber[0]" = "0" -+ register "PcieRpClkSrcNumber[0]" = "0" -+ register "PcieRpAdvancedErrorReporting[0]" = "1" -+ register "PcieRpLtrEnable[0]" = "1" -+ device generic 0 alias dgpu on end -+ end -+ -+ # Ethernet (clobbers RP8) -+ device ref gbe on -+ register "LanClkReqSupported" = "1" -+ register "LanClkReqNumber" = "1" -+ register "EnableLanLtr" = "1" -+ register "EnableLanK1Off" = "1" -+ end -+ -+ # M.2 WLAN - x1 -+ device ref pcie_rp7 on -+ register "PcieRpClkReqSupport[6]" = "1" -+ register "PcieRpClkReqNumber[6]" = "2" -+ register "PcieRpClkSrcNumber[6]" = "2" -+ register "PcieRpAdvancedErrorReporting[6]" = "1" -+ register "PcieRpLtrEnable[6]" = "1" -+ end -+ -+ # M.2 WWAN - x2 -+ device ref pcie_rp5 on -+ register "PcieRpClkReqSupport[4]" = "1" -+ register "PcieRpClkReqNumber[4]" = "3" -+ register "PcieRpClkSrcNumber[4]" = "3" -+ register "PcieRpAdvancedErrorReporting[4]" = "1" -+ register "PcieRpLtrEnable[4]" = "1" -+ end -+ -+ # TB3 (Alpine Ridge LP) - x2 -+ device ref pcie_rp9 on -+ register "PcieRpClkReqSupport[8]" = "1" -+ register "PcieRpClkReqNumber[8]" = "4" -+ register "PcieRpClkSrcNumber[8]" = "4" -+ register "PcieRpAdvancedErrorReporting[8]" = "1" -+ register "PcieRpLtrEnable[8]" = "1" -+ register "PcieRpHotPlug[8]" = "1" -+ end -+ -+ # M.2 2280 caddy - x2 -+ device ref pcie_rp11 on -+ register "PcieRpClkReqSupport[10]" = "1" -+ register "PcieRpClkReqNumber[10]" = "5" -+ register "PcieRpClkSrcNumber[10]" = "5" -+ register "PcieRpAdvancedErrorReporting[10]" = "1" -+ register "PcieRpLtrEnable[10]" = "1" -+ end -+ end -+end -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840 -GIT binary patch -literal 4106 -zcmeHJUu+a*5TCu>yW9JAmoD2P<t%lC2CfC#y%tU^HSGOq>9tqx`iFWXCLD09R<E?S -zMT)`nNScT-%9*GEA8a2?G`v`!jPV6yVlcd5OnC6Y;F}U&jJz1db9VRID@E)DLk#NN -z&9^i2&Hiq_`R2ZF8ipf7IM{nI5$^585@kULrrx0OPKv~ngNI__q41$dA{p()ui+v1 -zw(9rm09lUPAP4nOTm0CRnF|aw5^SQSH<G}<u_Gfnvn6IuK0h@!j;UxI!$*&rIdkIh -zl$piB;eBDWa1|CgK9bAg{^O%Z%!ziiz{neeJDb~fBI?1GV5p^44?a$ETl=n1d+;%Z -z#X6(OzEnIB9*QUTV{!mv@xk!mU}s+>aS&4j$?kY0KGYdgn6;MZ*!anbk!PNr!a%eU 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-z`jLfJ!?;*R@Bp=Nw2EPOC7FEs(cugIP_K6tN_$~tvS8nx6iOv|IMrO3&-m*N9ZP#b -znG^~>I|l1cUVSeD9r^k3h0TP}WWD9=MZxY<<azgO1@-W5<NTHW*-d)t{Q4yX9_+?a -zHawLe=uO6@%xqS#?JxafX%#$`BhkIqq>Z3B2yU!k71#YRpThOJtVheMDA50rV#s@U -z+nKbA{O(olYR}icuzQD*-cjBQ9;%!eMDVP>7mWsF@=%>o)wSgq=n%DHNOYwRr4Ao6 -zbNdgEn*RdDS>Rud+fIY0N8JkP3q6;>8o%R(CE2n3?Xg%qP+U%~6|{XFyxv7Y#;J2Z -XK$lk*wsY^m4}9|iz?mg_AjCfat$CyH - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads -new file mode 100644 -index 0000000000..fcfbd75a92 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads -@@ -0,0 +1,19 @@ -+-- SPDX-License-Identifier: GPL-2.0-or-later -+ -+with HW.GFX.GMA; -+with HW.GFX.GMA.Display_Probing; -+ -+use HW.GFX.GMA; -+use HW.GFX.GMA.Display_Probing; -+ -+private package GMA.Mainboard is -+ -+ ports : constant Port_List := -+ (eDP, -+ DP1, -+ DP2, -+ HDMI1, -+ HDMI2, -+ others => Disabled); -+ -+end GMA.Mainboard; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -new file mode 100644 -index 0000000000..a98dd2bc4e ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c -@@ -0,0 +1,199 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <soc/gpio.h> -+#include "../../gpio.h" -+ -+static const struct pad_config gpio_table[] = { -+ /* ------- GPIO Community 0 ------- */ -+ -+ /* ------- GPIO Group GPP_A ------- */ -+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ -+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ -+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ -+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ -+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ -+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ -+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ -+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ -+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ -+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ -+ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ -+ PAD_NC(GPP_A11, NONE), -+ PAD_NC(GPP_A12, NONE), -+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* -SUSWARN */ -+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* -SUS_STAT */ -+ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* -SUSWARN */ -+ PAD_NC(GPP_A16, NONE), -+ PAD_NC(GPP_A17, NONE), -+ PAD_NC(GPP_A18, NONE), -+ PAD_NC(GPP_A19, NONE), -+ PAD_NC(GPP_A20, NONE), -+ PAD_NC(GPP_A21, NONE), -+ PAD_NC(GPP_A22, NONE), -+ PAD_NC(GPP_A23, NONE), -+ -+ /* ------- GPIO Group GPP_B ------- */ -+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), -+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), -+ PAD_NC(GPP_B2, NONE), -+ PAD_NC(GPP_B3, NONE), -+ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */ -+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (dGPU) */ -+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (WWAN) */ -+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 (GBE) */ -+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WLAN) */ -+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 (TB3) */ -+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 (SSD) */ -+ PAD_NC(GPP_B11, NONE), -+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ -+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ -+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* PCH_SPKR */ -+ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ -+ PAD_NC(GPP_B16, NONE), -+ PAD_NC(GPP_B17, NONE), -+ PAD_NC(GPP_B18, NONE), -+ PAD_NC(GPP_B19, NONE), -+ PAD_NC(GPP_B20, NONE), -+ PAD_NC(GPP_B21, NONE), -+ PAD_NC(GPP_B22, NONE), -+ PAD_NC(GPP_B23, NONE), -+ -+ /* ------- GPIO Community 1 ------- */ -+ -+ /* ------- GPIO Group GPP_C ------- */ -+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ -+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ -+ PAD_CFG_GPO(GPP_C2, 1, DEEP), -+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ -+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ -+ PAD_NC(GPP_C5, NONE), -+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ -+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ -+ PAD_NC(GPP_C8, NONE), -+ PAD_NC(GPP_C9, NONE), -+ PAD_NC(GPP_C10, NONE), -+ PAD_NC(GPP_C11, NONE), -+ PAD_NC(GPP_C12, NONE), -+ PAD_NC(GPP_C13, NONE), -+ PAD_NC(GPP_C14, NONE), -+ PAD_NC(GPP_C15, NONE), -+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ -+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ -+ PAD_NC(GPP_C18, NONE), -+ PAD_NC(GPP_C19, NONE), -+ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ -+ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ -+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ -+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ -+ -+ /* ------- GPIO Group GPP_D ------- */ -+ PAD_NC(GPP_D0, NONE), -+ PAD_NC(GPP_D1, NONE), -+ PAD_NC(GPP_D2, NONE), -+ PAD_NC(GPP_D3, NONE), -+ PAD_NC(GPP_D4, NONE), -+ PAD_NC(GPP_D5, NONE), -+ PAD_NC(GPP_D6, NONE), -+ PAD_NC(GPP_D7, NONE), -+ PAD_NC(GPP_D8, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */ -+ PAD_NC(GPP_D10, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */ -+ PAD_NC(GPP_D13, NONE), -+ PAD_NC(GPP_D14, NONE), -+ PAD_NC(GPP_D15, NONE), -+ PAD_NC(GPP_D16, NONE), -+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ -+ PAD_NC(GPP_D18, NONE), -+ PAD_NC(GPP_D19, NONE), -+ PAD_NC(GPP_D20, NONE), -+ PAD_NC(GPP_D21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ -+ PAD_NC(GPP_D23, NONE), -+ -+ /* ------- GPIO Group GPP_E ------- */ -+ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ -+ PAD_NC(GPP_E1, NONE), -+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -SATA2_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */ -+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ -+ PAD_NC(GPP_E5, NONE), -+ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */ -+ PAD_NC(GPP_E7, NONE), -+ PAD_NC(GPP_E8, NONE), -+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ -+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ -+ PAD_NC(GPP_E11, NONE), -+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ -+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ -+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ -+ PAD_NC(GPP_E15, NONE), -+ PAD_NC(GPP_E16, NONE), -+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ -+ PAD_NC(GPP_E18, NONE), -+ PAD_CFG_GPO(GPP_E19, 0, DEEP), -+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ -+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ -+ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */ -+ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */ -+ -+ /* ------- GPIO Community 2 ------- */ -+ -+ /* -------- GPIO Group GPD -------- */ -+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ -+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ -+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ -+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ -+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ -+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ -+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ -+ PAD_NC(GPD7, NONE), -+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ -+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ -+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ -+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ -+ -+ /* ------- GPIO Community 3 ------- */ -+ -+ /* ------- GPIO Group GPP_F ------- */ -+ PAD_CFG_GPO(GPP_F0, 0, DEEP), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */ -+ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* DGFX_PWRGD */ -+ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ -+ PAD_NC(GPP_F5, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R37 to GND) */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ -+ PAD_NC(GPP_F21, NONE), -+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -TAMPER_SW_DTCT */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */ -+ -+ /* ------- GPIO Group GPP_G ------- */ -+ PAD_NC(GPP_G0, NONE), -+ PAD_NC(GPP_G1, NONE), -+ PAD_NC(GPP_G2, NONE), -+ PAD_NC(GPP_G3, NONE), -+ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ -+ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ -+ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ -+ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ -+}; -+ -+void variant_config_gpios(void) -+{ -+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -new file mode 100644 -index 0000000000..b1d96c5a76 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c -@@ -0,0 +1,90 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <device/azalia_device.h> -+ -+const u32 cim_verb_data[] = { -+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 -+ 0x17aa2258, // Subsystem ID -+ 11, -+ AZALIA_SUBVENDOR(0, 0x17aa2258), -+ -+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_MIC_IN, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 2, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( -+ AZALIA_INTEGRATED, -+ AZALIA_INTERNAL, -+ AZALIA_SPEAKER, -+ AZALIA_OTHER_ANALOG, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_NO_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_MIC_IN, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 3, 0 -+ )), -+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device -+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), -+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, -+ AZALIA_HP_OUT, -+ AZALIA_STEREO_MONO_1_8, -+ AZALIA_BLACK, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 15 -+ )), -+ -+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI -+ 0x80860101, // Subsystem ID -+ 4, -+ AZALIA_SUBVENDOR(2, 0x80860101), -+ -+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( -+ AZALIA_JACK, -+ AZALIA_DIGITAL_DISPLAY, -+ AZALIA_DIGITAL_OTHER_OUT, -+ AZALIA_OTHER_DIGITAL, -+ AZALIA_COLOR_UNKNOWN, -+ AZALIA_JACK_PRESENCE_DETECT, -+ 1, 0 -+ )), -+}; -+ -+const u32 pc_beep_verbs[] = {}; -+ -+AZALIA_ARRAY_SIZES; -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c -new file mode 100644 -index 0000000000..001e934b3a ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c -@@ -0,0 +1,44 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <cbfs.h> -+#include <gpio.h> -+#include <soc/gpio.h> -+#include <soc/romstage.h> -+#include <spd_bin.h> -+#include <stdio.h> -+ -+static const struct pad_config memory_id_gpio_table[] = { -+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ -+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ -+}; -+ -+void mainboard_memory_init_params(FSPM_UPD *mupd) -+{ -+ int spd_idx; -+ char spd_name[20]; -+ size_t spd_size; -+ -+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; -+ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */ -+ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ -+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; -+ -+ /* Get SPD for soldered RAM SPD (CH A) */ -+ gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table)); -+ -+ spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 | -+ gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4; -+ printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx); -+ snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx); -+ mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map(spd_name, &spd_size); -+ -+ /* Get SPD for memory slot (CH B) */ -+ struct spd_block blk = { .addr_map = { [1] = 0x51, } }; -+ get_spd_smbus(&blk); -+ dump_spd_info(&blk); -+ -+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; -+} -diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -new file mode 100644 -index 0000000000..14fcf371c7 ---- /dev/null -+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb -@@ -0,0 +1,93 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+chip soc/intel/skylake -+ device domain 0 on -+ device ref south_xhci on -+ register "usb2_ports" = "{ -+ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) -+ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) -+ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) -+ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB-C) -+ [4] = USB2_PORT_MID(OC_SKIP), // JCAM (IR camera) -+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) -+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) -+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) -+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) -+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) -+ }" -+ register "usb3_ports" = "{ -+ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) -+ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) -+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) -+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSBC (USB-C) -+ }" -+ end -+ -+ # PCIe controller 1 - 1x2+2x1 -+ # PCIE 1-2 - RP1 - dGPU - CLKOUT0 - CLKREQ0 -+ # PCIE 4 - RP4 - WWAN - CLKOUT1 - CLKREQ1 -+ # -+ # PCIe controller 2 - 2x1+1x2 (lane reversal) -+ # PCIE 5 - GBE - GBE - CLKOUT2 - CLKREQ2 (clobbers RP8) -+ # PCIE 6 - RP7 - WLAN - CLKOUT3 - CLKREQ3 -+ # PCIE 7-8 - RP5 - TB3 - CLKOUT4 - CLKREQ4 -+ # -+ # PCIe controller 3 - 1x4 (lane reversal) -+ # PCIE 9-12 - RP9 - SSD - CLKOUT5 - CLKREQ5 -+ -+ # dGPU - x2 -+ device ref pcie_rp1 on -+ register "PcieRpClkReqSupport[0]" = "1" -+ register "PcieRpClkReqNumber[0]" = "0" -+ register "PcieRpClkSrcNumber[0]" = "0" -+ register "PcieRpAdvancedErrorReporting[0]" = "1" -+ register "PcieRpLtrEnable[0]" = "1" -+ device generic 0 alias dgpu on end -+ end -+ -+ # M.2 WWAN - x1 -+ device ref pcie_rp4 on -+ register "PcieRpClkReqSupport[3]" = "1" -+ register "PcieRpClkReqNumber[3]" = "1" -+ register "PcieRpClkSrcNumber[3]" = "1" -+ register "PcieRpAdvancedErrorReporting[3]" = "1" -+ register "PcieRpLtrEnable[3]" = "1" -+ end -+ -+ # Ethernet (clobbers RP8) -+ device ref gbe on -+ register "LanClkReqSupported" = "1" -+ register "LanClkReqNumber" = "2" -+ register "EnableLanLtr" = "1" -+ register "EnableLanK1Off" = "1" -+ end -+ -+ # M.2 WLAN - x1 -+ device ref pcie_rp7 on -+ register "PcieRpClkReqSupport[6]" = "1" -+ register "PcieRpClkReqNumber[6]" = "3" -+ register "PcieRpClkSrcNumber[6]" = "3" -+ register "PcieRpAdvancedErrorReporting[6]" = "1" -+ register "PcieRpLtrEnable[6]" = "1" -+ end -+ -+ # TB3 (Alpine Ridge LP) - x2 -+ device ref pcie_rp5 on -+ register "PcieRpClkReqSupport[4]" = "1" -+ register "PcieRpClkReqNumber[4]" = "4" -+ register "PcieRpClkSrcNumber[4]" = "4" -+ register "PcieRpAdvancedErrorReporting[4]" = "1" -+ register "PcieRpLtrEnable[4]" = "1" -+ register "PcieRpHotPlug[4]" = "1" -+ end -+ -+ # M.2 2280 SSD - x2 -+ device ref pcie_rp9 on -+ register "PcieRpClkReqSupport[8]" = "1" -+ register "PcieRpClkReqNumber[8]" = "5" -+ register "PcieRpClkSrcNumber[8]" = "5" -+ register "PcieRpAdvancedErrorReporting[8]" = "1" -+ register "PcieRpLtrEnable[8]" = "1" -+ end -+ end -+end -diff --git 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