coreboot: rev 8b52167a9f 13 July 2025, rebase t480

coreboot/default: update t480 patches to set 38

see: https://review.coreboot.org/c/coreboot/+/83274/38

I was previously using:
https://review.coreboot.org/c/coreboot/+/83274/25

Matt DeViller aka MrChromeBox, recently took over the
patch set, tidying up and re-factoring the code so that
it's more suitable for upstream. Several hacky behaviours
were removed, for example the MEC1663 code is now its own
code in coreboot, rather than being bolted onto the H8s code.

Certain T480-specific changes made to global parts of the
coreboot code are now done only on the tree itself.

Mate Kukri has also tested Matt's recent updates. More
testing still needed on Nvidia dGPU models, which never
worked before anyway; Intel GPU models should still work.

Thermas zone handling is also improved. See patch:
https://review.coreboot.org/c/coreboot/+/88415/1
https://review.coreboot.org/c/coreboot/+/88416/2

Functionally, this is mostly the same as before. As I said,
Matt has focused on code cleanup, so that the board can be
properly upstreamed. Hopefully this will be merged soon,
in coreboot-main.

Besides this, the following upstream changes were imported:

* 8b52167a9f arch/x86: Add support for cooperative multitasking on x86_64
* 569b7a8861 Docs/releases: Finalize 25.06 release notes
* 5db8bf0cfa mb/trulo/var/pujjolo: Enable USB3 WWAN device
* e013c9586c mb/trulo/var/pujjolo: Modify mipi camera parameters
* 7b8520ab69 mb/trulo/var/pujjolo: Update fingerprint enable pin status
* f74027d5ae mb/google/nissa/var/craask: Add elan touchscreen support
* 396a883a0c mb/hp/snb_ivb_desktops: Include PS/2 controller ASL code for MS Windows
* 18c067d392 mb/google/fatcat/var/kinmen: Add Synaptics touchpad
* 2f5b384ba5 soc/mediatek/mt8189: Enable EARLY_MMU_INIT to improve boot time
* d5bce8c420 mb/hp: Add HP 260 G1 DM Business PC (Haswell)
* 48c6f66fa4 mb/google/ocelot: Update TPM_TIS_ACPI_INTERRUPT value in Kconfig
* 0660fe50de mb/google/ocelot: Update GPE configuration
* 5b3063802e mb/google/fatcat/var/kinmen: Fix touchscreen IRQ setting
* 6c4e502fdd mb/google/nissa/var/pujjocento: Reduce PL4 to 38W with no battery
* 6e92554ab6 mb/trulo/var/pujjolo: Modify FW_CONFIG for mipi camera
* 4f5f75da34 mb/trulo/var/pujjolo: Correct USB3 Type-A OC pins
* a1dfd39e04 mb/google/fatcat/var/kinmen: Add AUDIO_UNKNOWN and probe for ALC721
* 306544b427 mb/google/fatcat/var/francka: Add AUDIO_UNKNOWN and audio probes
* edf47d44cd mb/google/fatcat/var/fatcat: Disable Audio for invalid Audio FW_CONFIG
* 454079c3bc lib/cbfs: Ensure cache buffer alignment in ramstage
* 0ef670a66a mb/google/ocelot/var/ocelot: Configure FPS related changes
* 6ab37f0e0e mb/google/ocelot/var/ocelot: Add FW_CONFIG for Finger Print
* 3f61df24d5 mb/google/ocelot/var/ocelot: Add FW_CONFIG for Storage
* bb95a26cda mb/google/ocelot/var/ocelot: Add FW_CONFIG for WiFi
* 410b3c697f mb/google/ocelot/var/ocelot: Add FW_CONIG for ISH
* afaf4c3d7b mb/google/brya/variants/pujjolo: Update ISH GPIOs and add ISH firmware name
* f6de6f8933 mb/google/fatcat: Drop redundant SNDW GPIO mapping
* 584fdd6572 soc/mediatek/mt8196: Remove redundant bootblock.c from Makefile.mk
* 24ea6937f2 soc/intel/apollolake: Add the Kconfig options for IFWI Boot Profile
* c68645cd88 util/supermicro: Fix mem leak in get_line_as_int error conditions
* 05396238da libpayload/drivers: Fix mem-leak in cbmem_console error condition
* 1219981177 drivers/emu/qemu: Add a comment about fw_cfg assumptions
* d866e72b3a mb/google/fatcat/var/kinmen: Set CRFP to use GPIO for status
* 4367daae20 drivers/spi: Add option to generate proper PowerResource _STA
* 03c331399c mb/google/nissa/var/craask: Add focaltech touchscreen support
* b3d7c40fb5 mb/siemens/mc_rpl: Remove code for board_id
* 5de16ed1b8 mb/siemens/mc_rpl: Remove unused embedded controller code
* a1067ec6de mb/siemens/mc_rpl: Remove unneeded code to select a VBT name in CBFS
* 463cda84d2 mb/siemens/mc_rpl: Remove unused Type-C data definition
* dcbe591201 mb/siemens/mc_rpl: Use SPD data from HWInfo instead of from CBFS
* 6c059f8af3 IVB mainboards: Drop 1024M option for gfx_uma_size
* 3b61dbaa06 mb/asus/p8z77-m_pro: Remove incorrect gfx_uma_size options
* 2b7115b139 mb/hp/snb_ivb_desktops: Add gfx_uma_size options up to 512MB
* d99769bbde mb/hp/snb_ivb_desktops/variants: enable 4th sata port on tested models
* 95784dbafb mb/google/ocelot/var/ocelot: Add FW_CONFIG for Audio
* f323adb19f soc/mediatek/mt8189: Increase SPI NOR clock rate from 26MHz to 52MHz
* 689af47b52 commonlib: Add pvmfw related timestamps
* f1d06a5ad4 soc/intel/common/block/memory: Provide a way to use SPD data from memory
* 11b1dc0a97 Reapply "util/cbmem: Consolidate CBMEM and coreboot table access"
* 13f1c6118e Documentation: Update cbmem.md with more information
* 07267d19ce arch/x86/postcar_loader: Add comment line for reloc_params assignment
* e94ac6e655 mb/google/nissa/var/pujjocento: Reduce PL4 to 38 W with no battery
* 2eaec1b53a sbom: Fix build with merged bootblock and romstage
* 267f08dafd MAINTAINERS: Add KunYi Chen as maintainer for LattePanda Mu

Signed-off-by: Leah Rowe <leah@libreboot.org>

1 files changed, 371 insertions, 0 deletions

diff --git a/config/coreboot/default/patches/0040-ec-lenovo-Add-support-for-MEC1653-EC.patch b/config/coreboot/default/patches/0040-ec-lenovo-Add-support-for-MEC1653-EC.patch
new file mode 100644
index 00000000..8972e90e
--- /dev/null
+++ b/config/coreboot/default/patches/0040-ec-lenovo-Add-support-for-MEC1653-EC.patch
@@ -0,0 +1,371 @@
+From c88b371cb56046f79710143866562e119a8318ca Mon Sep 17 00:00:00 2001
+From: Matt DeVillier <matt.devillier@gmail.com>
+Date: Fri, 11 Jul 2025 16:11:47 -0500
+Subject: [PATCH 40/43] ec/lenovo: Add support for MEC1653 EC
+
+Add support for the MEC1653 EC as used by the Thinkpad T480/480s.
+
+Change-Id: If82a7d27eb3163f51565c0c6e60cab60753611a7
+Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
+---
+ src/ec/lenovo/mec1653/Kconfig     |  11 ++
+ src/ec/lenovo/mec1653/Makefile.mk |   8 ++
+ src/ec/lenovo/mec1653/mec1653.c   | 207 ++++++++++++++++++++++++++++++
+ src/ec/lenovo/mec1653/mec1653.h   |  98 ++++++++++++++
+ 4 files changed, 324 insertions(+)
+ create mode 100644 src/ec/lenovo/mec1653/Kconfig
+ create mode 100644 src/ec/lenovo/mec1653/Makefile.mk
+ create mode 100644 src/ec/lenovo/mec1653/mec1653.c
+ create mode 100644 src/ec/lenovo/mec1653/mec1653.h
+
+diff --git a/src/ec/lenovo/mec1653/Kconfig b/src/ec/lenovo/mec1653/Kconfig
+new file mode 100644
+index 0000000000..858f13897b
+--- /dev/null
++++ b/src/ec/lenovo/mec1653/Kconfig
+@@ -0,0 +1,11 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++config EC_LENOVO_MEC1653
++	bool
++
++if EC_LENOVO_MEC1653
++
++config MEC1653_SEND_DEBUG_UNLOCK
++	bool
++
++endif
+diff --git a/src/ec/lenovo/mec1653/Makefile.mk b/src/ec/lenovo/mec1653/Makefile.mk
+new file mode 100644
+index 0000000000..4cb4b20cbb
+--- /dev/null
++++ b/src/ec/lenovo/mec1653/Makefile.mk
+@@ -0,0 +1,8 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++ifeq ($(CONFIG_EC_LENOVO_MEC1653),y)
++
++bootblock-y += mec1653.c
++ramstage-y += mec1653.c
++
++endif
+diff --git a/src/ec/lenovo/mec1653/mec1653.c b/src/ec/lenovo/mec1653/mec1653.c
+new file mode 100644
+index 0000000000..098ae47425
+--- /dev/null
++++ b/src/ec/lenovo/mec1653/mec1653.c
+@@ -0,0 +1,207 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <arch/io.h>
++#include "mec1653.h"
++
++#define MICROCHIP_CONFIGURATION_ENTRY_KEY	0x55
++#define MICROCHIP_CONFIGURATION_EXIT_KEY	0xaa
++
++#define UART_PORT				0x3f8
++#define UART_IRQ				4
++
++// RW unlock key for EC version N24HT37W
++const uint8_t debug_rw_key[8] = { 0x7a, 0x41, 0xb1, 0x49, 0xfe, 0x21, 0x01, 0xcf };
++
++void microchip_pnp_enter_conf_state(uint16_t port)
++{
++	outb(MICROCHIP_CONFIGURATION_ENTRY_KEY, port);
++}
++
++void microchip_pnp_exit_conf_state(uint16_t port)
++{
++	outb(MICROCHIP_CONFIGURATION_EXIT_KEY, port);
++}
++
++uint8_t pnp_read(uint16_t port, uint8_t index)
++{
++	outb(index, port);
++	return inb(port + 1);
++}
++
++uint32_t pnp_read_le32(uint16_t port, uint8_t index)
++{
++	return (uint32_t) pnp_read(port, index) |
++			(uint32_t) pnp_read(port, index + 1) << 8 |
++			(uint32_t) pnp_read(port, index + 2) << 16 |
++			(uint32_t) pnp_read(port, index + 3) << 24;
++}
++
++void pnp_write(uint16_t port, uint8_t index, uint8_t value)
++{
++	outb(index, port);
++	outb(value, port + 1);
++}
++
++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value)
++{
++	pnp_write(port, index, value & 0xff);
++	pnp_write(port, index + 1, value >> 8 & 0xff);
++	pnp_write(port, index + 2, value >> 16 & 0xff);
++	pnp_write(port, index + 3, value >> 24 & 0xff);
++}
++
++static void ecN_clear_out_queue(uint16_t cmd_port, uint16_t data_port)
++{
++	while (inb(cmd_port) & EC_OBF)
++		inb(data_port);
++}
++
++static void ecN_wait_to_send(uint16_t cmd_port, uint16_t data_port)
++{
++	while (inb(cmd_port) & EC_IBF)
++		;
++}
++
++static void ecN_wait_to_recv(uint16_t cmd_port, uint16_t data_port)
++{
++	while (!(inb(cmd_port) & EC_OBF))
++		;
++}
++
++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr)
++{
++	ecN_clear_out_queue(cmd_port, data_port);
++	ecN_wait_to_send(cmd_port, data_port);
++	outb(EC_READ, cmd_port);
++	ecN_wait_to_send(cmd_port, data_port);
++	outb(addr, data_port);
++	ecN_wait_to_recv(cmd_port, data_port);
++	return inb(data_port);
++}
++
++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val)
++{
++	ecN_clear_out_queue(cmd_port, data_port);
++	ecN_wait_to_send(cmd_port, data_port);
++	outb(EC_WRITE, cmd_port);
++	ecN_wait_to_send(cmd_port, data_port);
++	outb(addr, data_port);
++	ecN_wait_to_send(cmd_port, data_port);
++	outb(val, data_port);
++}
++
++uint8_t eeprom_read(uint16_t addr)
++{
++	ecN_clear_out_queue(EC2_CMD, EC2_DATA);
++	ecN_wait_to_send(EC2_CMD, EC2_DATA);
++	outl(1, EC2_CMD);
++	ecN_wait_to_send(EC2_CMD, EC2_DATA);
++	outl(addr, EC2_DATA);
++	ecN_wait_to_recv(EC2_CMD, EC2_DATA);
++	return inl(EC2_DATA);
++}
++
++void eeprom_write(uint16_t addr, uint8_t val)
++{
++	ecN_clear_out_queue(EC2_CMD, EC2_DATA);
++	ecN_wait_to_send(EC2_CMD, EC2_DATA);
++	outl(2, EC2_CMD);
++	ecN_wait_to_send(EC2_CMD, EC2_DATA);
++	outl((uint32_t) addr | (uint32_t) val << 16, EC2_DATA);
++	ecN_wait_to_recv(EC2_CMD, EC2_DATA);
++	inl(EC2_DATA);
++}
++
++uint16_t debug_loaded_keys(void)
++{
++	return (uint16_t) ec0_read(0x87) << 8 | (uint16_t) ec0_read(0x86);
++}
++
++static void debug_cmd(uint8_t cmd)
++{
++	ec0_write(EC_DEBUG_CMD, cmd);
++	while (ec0_read(EC_DEBUG_CMD) & 0x80)
++		;
++}
++
++void debug_read_key(uint8_t i, uint8_t *key)
++{
++	debug_cmd(0x80 | (i & 0xf));
++	for (int j = 0; j < 8; ++j)
++		key[j] = ec0_read(0x3e + j);
++}
++
++void debug_write_key(uint8_t i, const uint8_t *key)
++{
++	for (int j = 0; j < 8; ++j)
++		ec0_write(0x3e + j, key[j]);
++	debug_cmd(0xc0 |  (i & 0xf));
++}
++
++uint32_t debug_read_dword(uint32_t addr)
++{
++	ecN_clear_out_queue(EC3_CMD, EC3_DATA);
++	ecN_wait_to_send(EC3_CMD, EC3_DATA);
++	outl(addr << 8 | 0xE2, EC3_DATA);
++	ecN_wait_to_recv(EC3_CMD, EC3_DATA);
++	return inl(EC3_DATA);
++}
++
++void debug_write_dword(uint32_t addr, uint32_t val)
++{
++	ecN_clear_out_queue(EC3_CMD, EC3_DATA);
++	ecN_wait_to_send(EC3_CMD, EC3_DATA);
++	outl(addr << 8 | 0xEA, EC3_DATA);
++	ecN_wait_to_send(EC3_CMD, EC3_DATA);
++	outl(val, EC3_DATA);
++}
++
++static void configure_uart(uint16_t port, uint16_t iobase, uint8_t irqno)
++{
++	microchip_pnp_enter_conf_state(port);
++
++	// Select LPC I/F LDN
++	pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF);
++	// Write UART BAR
++	pnp_write_le32(port, LPCIF_BAR_UART, (uint32_t) iobase << 16 | 0x8707);
++	// Set SIRQ4 to UART
++	pnp_write(port, LPCIF_SIRQ(irqno), LDN_UART);
++
++	// Configure UART LDN
++	pnp_write(port, PNP_LDN_SELECT, LDN_UART);
++	pnp_write(port, UART_ACTIVATE, 0x01);
++	pnp_write(port, UART_CONFIG_SELECT, 0x00);
++
++	microchip_pnp_exit_conf_state(port);
++
++	if (CONFIG(MEC1653_SEND_DEBUG_UNLOCK)) {
++		// Supply debug unlock key
++		debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key);
++
++		// Use debug writes to set UART_TX and UART_RX GPIOs
++		debug_write_dword(0xf0c400 + 0x110, 0x00001000);
++		debug_write_dword(0xf0c400 + 0x114, 0x00001000);
++	}
++}
++
++void bootblock_ec_init(void)
++{
++	// Tell EC via BIOS Debug Port 1 that the world isn't on fire
++
++	// Let the EC know that BIOS code is running
++	outb(0x11, 0x86);
++	outb(0x6e, 0x86);
++
++	// Enable accesses to EC1 interface
++	ec0_write(0, ec0_read(0) | 0x20);
++
++	// Reset LEDs to power on state
++	// (Without this warm reboot leaves LEDs off)
++	ec0_write(0x0c, 0x80);
++	ec0_write(0x0c, 0x07);
++	ec0_write(0x0c, 0x8a);
++
++	// Setup debug UART
++	if (CONFIG(CONSOLE_SERIAL))
++		configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ);
++}
+diff --git a/src/ec/lenovo/mec1653/mec1653.h b/src/ec/lenovo/mec1653/mec1653.h
+new file mode 100644
+index 0000000000..7dc4c1f635
+--- /dev/null
++++ b/src/ec/lenovo/mec1653/mec1653.h
+@@ -0,0 +1,98 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef EC_LENOVO_MEC1653_H
++#define EC_LENOVO_MEC1653_H
++
++// EC configuration base address
++#define EC_CFG_PORT		0x4e
++
++// Chip global registers
++#define PNP_LDN_SELECT		0x07
++# define LDN_UART		0x07
++# define LDN_LPCIF		0x0c
++#define EC_DEVICE_ID		0x20
++#define EC_DEVICE_REV		0x21
++
++// LPC I/F registers
++#define LPCIF_SIRQ(i)		(0x40 + (i))
++
++#define LPCIF_BAR_CFG		0x60
++#define LPCIF_BAR_MAILBOX	0x64
++#define LPCIF_BAR_8042		0x68
++#define LPCIF_BAR_ACPI_EC0	0x6c
++#define LPCIF_BAR_ACPI_EC1	0x70
++#define LPCIF_BAR_ACPI_EC2	0x74
++#define LPCIF_BAR_ACPI_EC3	0x78
++#define LPCIF_BAR_ACPI_PM0	0x7c
++#define LPCIF_BAR_UART		0x80
++#define LPCIF_BAR_FAST_KYBD	0x84
++#define LPCIF_BAR_EMBED_FLASH	0x88
++#define LPCIF_BAR_GP_SPI	0x8c
++#define LPCIF_BAR_EMI		0x90
++#define LPCIF_BAR_PMH7		0x94
++#define LPCIF_BAR_PORT80_DBG0	0x98
++#define LPCIF_BAR_PORT80_DBG1	0x9c
++#define LPCIF_BAR_RTC		0xa0
++
++// UART registers
++#define UART_ACTIVATE		0x30
++#define UART_CONFIG_SELECT	0xf0
++
++void microchip_pnp_enter_conf_state(uint16_t port);
++void microchip_pnp_exit_conf_state(uint16_t port);
++uint8_t pnp_read(uint16_t port, uint8_t index);
++uint32_t pnp_read_le32(uint16_t port, uint8_t index);
++void pnp_write(uint16_t port, uint8_t index, uint8_t value);
++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value);
++
++#define EC0_CMD		0x0066
++#define EC0_DATA	0x0062
++#define EC1_CMD		0x1604
++#define EC1_DATA	0x1600
++#define EC2_CMD		0x1634
++#define EC2_DATA	0x1630
++#define EC3_CMD		0x161c
++#define EC3_DATA	0x1618
++
++#define EC_OBF		(1 << 0)
++#define EC_IBF		(1 << 1)
++
++#define EC_READ		0x80
++#define EC_WRITE	0x81
++
++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr);
++
++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val);
++
++// EC0 and EC1 mostly are useful with the READ/WRITE commands
++#define ec0_read(addr) ecN_read(EC0_CMD, EC0_DATA, addr)
++#define ec0_write(addr, val) ecN_write(EC0_CMD, EC0_DATA, addr, val)
++#define ec1_read(addr) ecN_read(EC1_CMD, EC1_DATA, addr)
++#define ec1_write(addr, val) ecN_write(EC1_CMD, EC1_DATA, addr, val)
++
++// Read from the emulated EEPROM
++uint8_t eeprom_read(uint16_t addr);
++
++// Write to the emulated EEPROM
++void eeprom_write(uint16_t addr, uint8_t val);
++
++// Read loaded debug key mask
++uint16_t debug_loaded_keys(void);
++
++// The following location (via either EC0 or EC1) can be used to interact with the debug interface
++#define EC_DEBUG_CMD 0x3d
++
++void debug_read_key(uint8_t i, uint8_t *key);
++
++void debug_write_key(uint8_t i, const uint8_t *key);
++
++uint32_t debug_read_dword(uint32_t addr);
++
++void debug_write_dword(uint32_t addr, uint32_t val);
++
++// RW unlock key index
++#define DEBUG_RW_KEY_IDX 1
++
++void bootblock_ec_init(void);
++
++#endif /* EC_LENOVO_MEC1653_H */
+-- 
+2.39.5
+