diff options
| author | Leah Rowe <leah@libreboot.org> | 2025-07-20 04:44:14 +0100 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2025-07-23 04:09:47 +0100 |
| commit | 84a1ff85b0706d7eb47118dd37f0f16443d48108 (patch) | |
| tree | afcd8209ec94e904875fc0062ab837068a7dd8a8 /config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch | |
| parent | cc2f08e7bbf9fc32bdd37079ee93b477ef4e8d09 (diff) | |
T480/T480s patches were dropped since they're included as
part of the upstream code now.
This update brings the following upstream changes:
* 9e41c7cec7 soc/intel/cmn/block/fast_spi: Lock DMA before exiting coreboot
* c1d45ef93b mb/google/trulo/var/kaladin: Update touchpad settings
* f13f980e03 mb/google/trulo/var/kaladin: Add fw_config probe for storage
* 50c39b3a22 mb/google/trulo/var/kaladin: Fix Type C function
* f0d50aa404 commonlib/include/commonlib: Add volatile qualifier
* 3828153ea5 soc/intel/xeon_sp/gnr: Use official microcodes
* a87cbcd3c9 soc/intel/xeon_sp/ibl: Config ACPI base using PMC device
* 480ac15044 util/cbfstool: Prevent overflow when sorting fit table entries
* bf4f08f3b6 mb/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff: early VGA output
* dd19f6bc5a util/cbmem: Extract devmem and common code to separate files
* def945f3ba soc/intel/apollolake: Measure the IBBL, IBB and OBB from the bootblock
* fbb0738272 mb/google/brox/var/lotso: Decrease cpu power limits
* ce88b12420 mb/google/ocelot: Set correct TPM I2C bus for all ocelot model variants
* e050e2fbfc mb/google/ocelot/var/ocelot: Remove irrelevant comment
* b66c8ea3d3 mb/google/ocelot/var/ocelot: Remove Bluetooth Audio offload
* d5d633f607 mb/google/ocelot/var/ocelot: Update variant.c
* 3b069d320c cbfs: Add a function to wait for all CBFS preload operations to complete
* a7710ed8fd Documentation: coding_style: Add *long* to long multi-line comment example
* 19d7104d85 drivers/intel/touch: Use recommended short multi-line comment style
* 451988d015 mb/google/trulo/var/pujjolo: Fix Goodix touchscreen function
* 542e52c126 soc/qualcomm/x1p42100: Optimize memory layout for X1P42100
* 2e47bd50f2 mb/google/trulo/var/pujjocento: Add 6W and 15W DPTF parameters
* 6e4f4538bb soc/intel/{tgl,adl,mtl,ptl}: Default to Software Connection Manager
* 1b8dd662a9 soc/qualcomm/x1p42100: Add PCIE Clock support for x1p42100
* 4d3def7514 soc/mediatek/mt8189: Fix timer reset in BL31 by using time_prepare_v2
* d898653b0e soc/meidatek/mt8196: Extract common timer code for reuse
* d1c096a5b9 src/soc/mt8196: Correct systimer register offset
* edaa67d0c9 mb/google/skywalker: Add thermal init flow in romstage
* 6aec09875b soc/mediatek/mt8189: Add thermal driver
* 5cc4b9e6ce soc/amd/common/cpu/noncar: Add bootblock overlap detection
* 67cd138df9 soc/intel/apollolake: Add missing header in measured_boot.h
* a428481574 mb/google/nissa/var/dirks: Update power limits
* 55ae0d8a37 mb/google/nissa/var/baseboard/nissa: Add power limits functions
* 82163aedc6 soc/amd/common/block/cpu/noncar: Move BSS and DATA out of PT_LOAD
* 6405641647 mb/google/fatcat: Use same mainboard part number for all fatcat variants
* c5613469ae device: Make a note that SeaBIOS doesn't support above 4G MMIO
* ced4c09359 soc/intel/xeon_sp/gnr: Implement get_mmio_high_base_size
* 7100f226ca vc/intel/fsp/fsp2_0/wcl: Add FSP headers for WCL FSP
* 5171098814 drivers/qemu/bochs: Allow building for non-x86 architectures
* d233b6c903 payloads/external/LinuxBoot/Makefile: Fix build prerequisite
* 502d19be89 payloads/external/LinuxBoot/targets/u-root.mk: Add missing prerequisite
* cba0f0b8b9 payloads/external/LinuxBoot: Rename build target
* 43a54e3b1b util/amdfwtool: Add binary parsing
* 85da3954d0 .gitmodules: Ignore changes make by what-jenkins-does
* 397c5fe420 Documentation: Add a mainboard entry for the Lenovo T480/T480s
* 6768586353 Documentation: Add information about the deguard utility
* ad8b738af0 mb/lenovo: Add ThinkPad T480 and ThinkPad T480s
* 96e381766e ec/lenovo: Add support for MEC1653 EC
* 2181b02765 util/smmstoretool: Properly initialise the authenticated variable header
* 3058464263 util/smmstoretool: Add support for creating variable from file contents
* b49f567e45 util/smmstoretool: Ensure that the FVB header isn't too large
* a6fbaa47ea util/smmstoretool: Clarify the `auth_vars` field
* 3698517d82 mb/amd: Use mec152x tool
* 5a0953614b util/amdtools: Add ec_usb_pd_fw
* e63620012c util: Add Microchip EC FW tool
* 0b5ce9d9f0 soc/intel/apollolake: Add support for IFWI Measured Boot
* 289cff3423 soc/intel/apollolake: Load the IBB into CAR
* 2408695dd3 soc/intel/apollolake: Add a loader for the IBB
* 61b66e9a81 soc/intel/apollolake: Add function to clear MCA in Bank 4
* 138402e7ff soc/intel/apollolake: Create IBB, IBBL and OBB
* 61b4e1983c mb/google/fatcat: Update PCH reset power cycle duration to 1 second
* e9af95d5ab soc/intel/pantherlake: Configure FSP UPDs for minimum assertion widths
* 79bd154b49 drivers/genesyslogic/gl9763e: Mask replay timer timeout of AER
* a775bfc2b2 soc/mediatek/mt8189: Specify MTKLIB_PATH for building BL31
* e583b2ffb7 soc/meidatek/mt8196: Extract common thermal code for reuse
* f62734976c mb/dell: Convert E6400 into a variant
* 8d60bf9975 mb/google/fatcat: select MIPI pre-prod if PTL pre-prod SoC is set
* 2f978ecab3 mb/google/fatcat: Choose platforms with pre-prod Panther Lake SoC
* eb1483ba17 soc/mediatek/mt8189: Increase SCP clock frequency from 26MHz to 416MHz
* 9c5557f982 util/abuild: Add --sequential-boards option
* 9e5234feee payloads/external/edk2: Drop our toolchain override
* 8d9e18a122 payloads/edk2: Indicate whether edk2-platforms is available
* 626fd50a94 mb/google/fatcat/var/kinmen: Enable ISH
* e7cefe4f41 soc/mediatek/mt8196: Move srclken_rc related code to common
* e9731f8925 soc/intel/pantherlake: Add configs for pre-production silicon
* 8687b3d108 mb/google/trulo/var/pujjolo: Add ISH firmware config
* 722c9314c7 mb/google/dedede/var/awasuki: Add 2 HYNIX modules to RAM id table
* 6082bd7711 ec/lenovo/h8: Rework invalid temperature reporting
* 621b1061d0 ec/lenovo/h8: Add Kconfig to select use of Thermal Zone 1
* bc116b8797 ec/lenovo/h8: Replace chip regs for BT/WWAN detect with Kconfig options
* d9169ef617 ec/lenovo/pmh7: Add CFR objects for existing options
* 45d9973a6d ec/lenovo/h8: Add CFR objects for existing options
* ce5a1e8a51 mb/google/brox: Create caboc variant
* d745d38393 soc/intel/cmn/block/fast_spi: Add DMA support
* 8e666c367d soc/qualcomm/x1p42100: Update boot critical firmware memory layout
* e35c784847 Doc/gfx/libgfxinit.md: Fix file names in source code references
* 0e682859e7 payloads/external/U-Boot: Upgrade from 2024.07 to v2025.07
* 8b52167a9f arch/x86: Add support for cooperative multitasking on x86_64
* 569b7a8861 Docs/releases: Finalize 25.06 release notes
* 5db8bf0cfa mb/trulo/var/pujjolo: Enable USB3 WWAN device
* e013c9586c mb/trulo/var/pujjolo: Modify mipi camera parameters
* 7b8520ab69 mb/trulo/var/pujjolo: Update fingerprint enable pin status
* f74027d5ae mb/google/nissa/var/craask: Add elan touchscreen support
* 396a883a0c mb/hp/snb_ivb_desktops: Include PS/2 controller ASL code for MS Windows
* 18c067d392 mb/google/fatcat/var/kinmen: Add Synaptics touchpad
* 2f5b384ba5 soc/mediatek/mt8189: Enable EARLY_MMU_INIT to improve boot time
* d5bce8c420 mb/hp: Add HP 260 G1 DM Business PC (Haswell)
* 48c6f66fa4 mb/google/ocelot: Update TPM_TIS_ACPI_INTERRUPT value in Kconfig
* 0660fe50de mb/google/ocelot: Update GPE configuration
* 5b3063802e mb/google/fatcat/var/kinmen: Fix touchscreen IRQ setting
* 6c4e502fdd mb/google/nissa/var/pujjocento: Reduce PL4 to 38W with no battery
* 6e92554ab6 mb/trulo/var/pujjolo: Modify FW_CONFIG for mipi camera
* 4f5f75da34 mb/trulo/var/pujjolo: Correct USB3 Type-A OC pins
* a1dfd39e04 mb/google/fatcat/var/kinmen: Add AUDIO_UNKNOWN and probe for ALC721
* 306544b427 mb/google/fatcat/var/francka: Add AUDIO_UNKNOWN and audio probes
* edf47d44cd mb/google/fatcat/var/fatcat: Disable Audio for invalid Audio FW_CONFIG
* 454079c3bc lib/cbfs: Ensure cache buffer alignment in ramstage
* 0ef670a66a mb/google/ocelot/var/ocelot: Configure FPS related changes
* 6ab37f0e0e mb/google/ocelot/var/ocelot: Add FW_CONFIG for Finger Print
* 3f61df24d5 mb/google/ocelot/var/ocelot: Add FW_CONFIG for Storage
* bb95a26cda mb/google/ocelot/var/ocelot: Add FW_CONFIG for WiFi
* 410b3c697f mb/google/ocelot/var/ocelot: Add FW_CONIG for ISH
* afaf4c3d7b mb/google/brya/variants/pujjolo: Update ISH GPIOs and add ISH firmware name
* f6de6f8933 mb/google/fatcat: Drop redundant SNDW GPIO mapping
* 584fdd6572 soc/mediatek/mt8196: Remove redundant bootblock.c from Makefile.mk
* 24ea6937f2 soc/intel/apollolake: Add the Kconfig options for IFWI Boot Profile
* c68645cd88 util/supermicro: Fix mem leak in get_line_as_int error conditions
* 05396238da libpayload/drivers: Fix mem-leak in cbmem_console error condition
* 1219981177 drivers/emu/qemu: Add a comment about fw_cfg assumptions
* d866e72b3a mb/google/fatcat/var/kinmen: Set CRFP to use GPIO for status
* 4367daae20 drivers/spi: Add option to generate proper PowerResource _STA
* 03c331399c mb/google/nissa/var/craask: Add focaltech touchscreen support
* b3d7c40fb5 mb/siemens/mc_rpl: Remove code for board_id
* 5de16ed1b8 mb/siemens/mc_rpl: Remove unused embedded controller code
* a1067ec6de mb/siemens/mc_rpl: Remove unneeded code to select a VBT name in CBFS
* 463cda84d2 mb/siemens/mc_rpl: Remove unused Type-C data definition
* dcbe591201 mb/siemens/mc_rpl: Use SPD data from HWInfo instead of from CBFS
* 6c059f8af3 IVB mainboards: Drop 1024M option for gfx_uma_size
* 3b61dbaa06 mb/asus/p8z77-m_pro: Remove incorrect gfx_uma_size options
* 2b7115b139 mb/hp/snb_ivb_desktops: Add gfx_uma_size options up to 512MB
* d99769bbde mb/hp/snb_ivb_desktops/variants: enable 4th sata port on tested models
* 95784dbafb mb/google/ocelot/var/ocelot: Add FW_CONFIG for Audio
* f323adb19f soc/mediatek/mt8189: Increase SPI NOR clock rate from 26MHz to 52MHz
* 689af47b52 commonlib: Add pvmfw related timestamps
* f1d06a5ad4 soc/intel/common/block/memory: Provide a way to use SPD data from memory
* 11b1dc0a97 Reapply "util/cbmem: Consolidate CBMEM and coreboot table access"
* 13f1c6118e Documentation: Update cbmem.md with more information
* 07267d19ce arch/x86/postcar_loader: Add comment line for reloc_params assignment
* e94ac6e655 mb/google/nissa/var/pujjocento: Reduce PL4 to 38 W with no battery
* 2eaec1b53a sbom: Fix build with merged bootblock and romstage
* 267f08dafd MAINTAINERS: Add KunYi Chen as maintainer for LattePanda Mu
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch')
| -rw-r--r-- | config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch | 326 |
1 files changed, 326 insertions, 0 deletions
diff --git a/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch new file mode 100644 index 00000000..09929786 --- /dev/null +++ b/config/coreboot/default/patches/0026-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -0,0 +1,326 @@ +From ec5c7627e90eb136a41bbe179e744a9d300a79fc Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Wed, 30 Oct 2024 20:55:25 -0600 +Subject: [PATCH 26/35] mb/dell/optiplex_780: Add USFF variant + +Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 +Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> +--- + src/mainboard/dell/optiplex_780/Kconfig | 5 + + src/mainboard/dell/optiplex_780/Kconfig.name | 3 + + .../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes + .../variants/780_usff/early_init.c | 9 + + .../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++ + .../optiplex_780/variants/780_usff/hda_verb.c | 26 +++ + .../variants/780_usff/overridetree.cb | 10 ++ + 7 files changed, 219 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb + +diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig +index 2d06c75c9a..fc649e35d5 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig ++++ b/src/mainboard/dell/optiplex_780/Kconfig +@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON + config BOARD_DELL_OPTIPLEX_780_MT + select BOARD_DELL_OPTIPLEX_780_COMMON + ++config BOARD_DELL_OPTIPLEX_780_USFF ++ select BOARD_DELL_OPTIPLEX_780_COMMON ++ + if BOARD_DELL_OPTIPLEX_780_COMMON + + config VGA_BIOS_ID +@@ -30,11 +33,13 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT ++ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + + config VARIANT_DIR + default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT ++ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF + + endif # BOARD_DELL_OPTIPLEX_780_COMMON +diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name +index db7f2e8fe3..bc84c82a79 100644 +--- a/src/mainboard/dell/optiplex_780/Kconfig.name ++++ b/src/mainboard/dell/optiplex_780/Kconfig.name +@@ -2,3 +2,6 @@ + + config BOARD_DELL_OPTIPLEX_780_MT + bool "OptiPlex 780 MT" ++ ++config BOARD_DELL_OPTIPLEX_780_USFF ++ bool "OptiPlex 780 USFF" +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7 +GIT binary patch +literal 1917 +zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@i<uQKf!)+gO;| +zveT#>P+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G +z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX +zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv +zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB +zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU<Iv53Rb6YTgMPOY8;~P1Yglh^6Fgt1^ +zCTz|SVPcSpZ44F@&oNPUMO@&BE3y(57YP_Y!4SZhE?GXYa7k+b0(X|s7u3GDRf^1# +zOd2ZCCPO|I&sHEt;p8UshhHtYQ>7!7x2m<d`Gu2<r+Qc4|6pwd8&zFboH_W7XE7uU +zWW-@Cim&mdY2!O{JANR)OTJG2z>LBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T +z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`<pE+J?KFZ=&_JVP1YL=#z<-Q*24K4 +zn+$YxrHNJJc`k?_8N=Kres26_#E8GLn2{jfW5P%ge`kL(Btkt=>xo)V)Ow=U6P12c +z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8 +zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE +zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb +zV99s{>`r76L#Hr6XW6r|<iq#4Jr?XsxKyeJKEj7;e4SZ^1B12u&iV_9M0*Kem@fmn +z1C>>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq<Gj{q2D( +z>&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a= +T#w3FFBiyj<XAh$hb(enud`r7S + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c +new file mode 100644 +index 0000000000..2a55fc3a6e +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include <northbridge/intel/x4x/x4x.h> ++ ++void mb_get_spd_map(u8 spd_map[4]) ++{ ++ spd_map[0] = 0x50; ++ spd_map[2] = 0x52; ++} +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +new file mode 100644 +index 0000000000..389f4077d7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c +@@ -0,0 +1,166 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_NATIVE, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_GPIO, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_NATIVE, ++ .gpio8 = GPIO_MODE_NATIVE, ++ .gpio9 = GPIO_MODE_GPIO, ++ .gpio10 = GPIO_MODE_GPIO, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_NATIVE, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_NATIVE, ++ .gpio16 = GPIO_MODE_GPIO, ++ .gpio17 = GPIO_MODE_NATIVE, ++ .gpio18 = GPIO_MODE_GPIO, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_GPIO, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio5 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio9 = GPIO_DIR_OUTPUT, ++ .gpio10 = GPIO_DIR_INPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio16 = GPIO_DIR_INPUT, ++ .gpio18 = GPIO_DIR_OUTPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio20 = GPIO_DIR_OUTPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_OUTPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_INPUT, ++ .gpio31 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio9 = GPIO_LEVEL_HIGH, ++ .gpio18 = GPIO_LEVEL_HIGH, ++ .gpio20 = GPIO_LEVEL_HIGH, ++ .gpio28 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio13 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_GPIO, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_NATIVE, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_GPIO, ++ .gpio50 = GPIO_MODE_NATIVE, ++ .gpio51 = GPIO_MODE_NATIVE, ++ .gpio52 = GPIO_MODE_NATIVE, ++ .gpio53 = GPIO_MODE_NATIVE, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_NATIVE, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio32 = GPIO_DIR_INPUT, ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_INPUT, ++ .gpio35 = GPIO_DIR_OUTPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_INPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio49 = GPIO_DIR_OUTPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio56 = GPIO_DIR_OUTPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio35 = GPIO_LEVEL_LOW, ++ .gpio49 = GPIO_LEVEL_HIGH, ++ .gpio56 = GPIO_LEVEL_HIGH, ++ .gpio60 = GPIO_LEVEL_LOW, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio72 = GPIO_MODE_GPIO, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio72 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ }, ++}; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +new file mode 100644 +index 0000000000..c94e06b156 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header */ ++ 0x11d4194a, /* Analog Devices AD1984A */ ++ 0x10280420, /* Subsystem ID */ ++ 10, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ AZALIA_PIN_CFG(0, 0x11, 0x02214040), ++ AZALIA_PIN_CFG(0, 0x12, 0x01014010), ++ AZALIA_PIN_CFG(0, 0x13, 0x991301f0), ++ AZALIA_PIN_CFG(0, 0x14, 0x02a19020), ++ AZALIA_PIN_CFG(0, 0x15, 0x01813030), ++ AZALIA_PIN_CFG(0, 0x16, 0x413301f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0), ++ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0), ++ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0), ++ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0), ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +new file mode 100644 +index 0000000000..555b1c1f5c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb +@@ -0,0 +1,10 @@ ++## SPDX-License-Identifier: GPL-2.0-or-later ++ ++chip northbridge/intel/x4x ++ device domain 0 on ++ chip southbridge/intel/i82801jx ++ device pci 1c.0 on end # PCIe 1 ++ device pci 1c.1 on end # PCIe 2 ++ end ++ end ++end +-- +2.39.5 + |