Revert "consolidate haswell iommu patches"

This reverts commit f60350344a56fa2b9db2b0653f69a7b036da8aab.

1 files changed, 54 insertions, 0 deletions

diff --git a/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
new file mode 100644
index 00000000..17cfdac2
--- /dev/null
+++ b/config/coreboot/default/patches/0016-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
@@ -0,0 +1,54 @@
+From 3c1416797f2deafbd6b56774d890706aaea3614f Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Sat, 4 May 2024 02:00:53 +0100
+Subject: [PATCH 16/51] nb/haswell: lock policy regs when disabling IOMMU
+
+Angel Pons told me I should do it. See comments here:
+https://review.coreboot.org/c/coreboot/+/81016
+
+I see no harm in complying with the request. I'll merge
+this into the main patch at a later date and try to
+get this upstreamed.
+
+Just a reminder: on Optiplex 9020 variants, Xorg locks up
+under Linux when tested with a graphics card; disabling
+IOMMU works around the issue. Intel graphics work just fine
+with IOMMU turned on. Libreboot disables IOMMU by default,
+on the 9020, so that users can install graphics cards easily.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/northbridge/intel/haswell/early_init.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
+index 5f07fa0b17..30660e3903 100644
+--- a/src/northbridge/intel/haswell/early_init.c
++++ b/src/northbridge/intel/haswell/early_init.c
+@@ -86,15 +86,17 @@ static void northbridge_setup_iommu(void)
+ 	if (!enable_iommu)
+ 		return;
+ 
++	if (enable_iommu) {
++		/* Setup BARs: zeroize top 32 bits; set enable bit */
++		mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
++		mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
++		mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
++		mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
++	}
++
+ 	if (capid0_a & VTD_DISABLE)
+ 		return;
+ 
+-	/* Setup BARs: zeroize top 32 bits; set enable bit */
+-	mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
+-	mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
+-	mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
+-	mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
+-
+ 	if (cpu_is_haswell()) {
+ 		/*
+ 		 * Intel Document 492662 (Haswell System Agent BIOS Spec), Rev 1.6.0
+-- 
+2.47.3
+