coreboot/default: Re-base all patchesHEADmaster

There were a lot of unnecessary patches, such as the VRAM
patches; as Nicholas Chin has explained to me, the drivers
for these machines will just allocate what RAM they want
anyway, so in a lot of cases the extra allocated Video RAM
simply reduces the total amount of memory for other uses.

In general, we have a lot of patches that have existed for
years. A much more aggressive sweep will be done in the next
major audit, especially when the revisions are updated again.

Signed-off-by: Leah Rowe <leah@libreboot.org>

1 files changed, 34 insertions, 0 deletions

diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
new file mode 100644
index 00000000..ee605e58
--- /dev/null
+++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
@@ -0,0 +1,34 @@
+From 8821f229d4fe48153ec7a45e0e04c3b2a3cd8c7c Mon Sep 17 00:00:00 2001
+From: persmule <persmule@gmail.com>
+Date: Sun, 31 Oct 2021 23:33:26 +0000
+Subject: [PATCH 02/51] lenovo/t400: Enable all SATA ports
+
+There are 2 SATA ports on the chassis of t400(s), but at least one dock for
+t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
+chassis, and another one on its dock.
+
+They have to be unmasked via device tree to use.
+
+This patch unmasked all SATA ports found within t400s with factory firmware.
+---
+ src/mainboard/lenovo/t400/devicetree.cb | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
+index 259c3e1b21..3d007533a4 100644
+--- a/src/mainboard/lenovo/t400/devicetree.cb
++++ b/src/mainboard/lenovo/t400/devicetree.cb
+@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
+ 			register "gpe0_en" = "0x01000000"
+ 			register "gpi1_routing"  = "2"
+ 
+-			# Set AHCI mode, enable ports 1 and 2.
+-			register "sata_port_map"		= "0x03"
++			# Set AHCI mode, enable ports 1, 2, 5 and 6.
++			register "sata_port_map"		= "0x33"
+ 			register "sata_clock_request"		= "0"
+ 			register "sata_traffic_monitor"		= "0"
+ 
+-- 
+2.39.5
+