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authorLeah Rowe <leah@libreboot.org>2023-11-01 08:44:03 +0000
committerLeah Rowe <leah@libreboot.org>2023-11-01 08:45:03 +0000
commit971f651775b761b131218dfc24618eb15bce0dc8 (patch)
tree0f3edde64755a9ff1d1c8ef9ae5a27481357ef4b /config/coreboot/d945gclf_8mb
parentdfc5423cad2fc2646d64d69f99a06fc2fd7723c7 (diff)
add 512kb d945gclf config
Signed-off-by: Leah Rowe <leah@libreboot.org>
Diffstat (limited to 'config/coreboot/d945gclf_8mb')
-rw-r--r--config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode7
1 files changed, 4 insertions, 3 deletions
diff --git a/config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode b/config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode
index 3bc5d2be..2c59d001 100644
--- a/config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode
@@ -208,6 +208,7 @@ CONFIG_D3COLD_SUPPORT=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -296,10 +297,11 @@ CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-# CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS is not set
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
@@ -492,7 +494,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000
#
# Console