diff options
| author | Todd Baker <todd_baker@student.uml.edu> | 2026-03-14 04:53:58 -0400 |
|---|---|---|
| committer | Todd Baker <todd_baker@student.uml.edu> | 2026-03-14 04:57:22 -0400 |
| commit | f0ff5fca6a9f55ec5a815daf6382a5e0fc0f201c (patch) | |
| tree | f49f6c16f761f171edf3a5d59212907f59552fed | |
| parent | bdd23b234b5c23495740e897035297314069d47e (diff) | |
Add Dell OptiPlex 3040 Micro support
Adds libreboot support for the Dell OptiPlex 3040 Micro based on the
OptiPlex 3050 Micro (same Skylake H110 PCH-H platform). Key differences:
DDR3L SODIMMs, Pentium G4400T-class CPUs (Skylake only), Realtek ALC3234
HDA, and Boot Guard neutralization via deguard.
Tested and booted on hardware.
Signed-off-by: Todd Baker <todd_baker@student.uml.edu>
| -rw-r--r-- | config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch | 1528 | ||||
| -rw-r--r-- | config/coreboot/dell3040micro_vfsp_16mb/config/libgfxinit_corebootfb | 822 | ||||
| -rw-r--r-- | config/coreboot/dell3040micro_vfsp_16mb/config/libgfxinit_txtmode | 815 | ||||
| -rw-r--r-- | config/coreboot/dell3040micro_vfsp_16mb/target.cfg | 13 | ||||
| -rw-r--r-- | config/deguard/patches/0006-data-delta-Add-Dell-OptiPlex-3040-Micro.patch | 219 | ||||
| -rw-r--r-- | config/ifd/3040micro/ifd | bin | 0 -> 4096 bytes | |||
| -rw-r--r-- | config/vendor/3040micro/pkg.cfg | 22 |
7 files changed, 3419 insertions, 0 deletions
diff --git a/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch b/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch new file mode 100644 index 00000000..a2e5d5a2 --- /dev/null +++ b/config/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port.patch @@ -0,0 +1,1528 @@ +From 24856e5e383b1b9aa078b879064b8c2b99f4494c Mon Sep 17 00:00:00 2001 +From: Todd Baker <todd_baker@student.uml.edu> +Date: Thu, 12 Mar 2026 13:12:04 -0400 +Subject: [PATCH] mb/dell: Add OptiPlex 3040 Micro port (upstream-compatible) + +Based on the OptiPlex 3050 Micro (same Skylake H110 PCH-H platform). +Key differences from 3050: +- DDR3L SODIMMs (256-byte SPD at 0x50/0x52) +- Intel Pentium G4400T-class CPUs (Skylake only, no Kabylake/Coffeelake) +- Realtek ALC3234 HDA (subsystem ID 0x102806bb) +- VBT: DDI E entry removed (phantom port, causes i915 WARN_ON) +- PCIe root ports rp5/rp8/rp21 enabled (PcieRpEnable removed; use device on/off) +- HECI1 set off to prevent stall when HAP bit is set (ME neutralized) + +Signed-off-by: Todd Baker <todd_baker@student.uml.edu> +--- + src/mainboard/dell/optiplex_3040/Kconfig | 37 ++ + src/mainboard/dell/optiplex_3040/Kconfig.name | 4 + + src/mainboard/dell/optiplex_3040/Makefile.mk | 12 + + src/mainboard/dell/optiplex_3040/acpi/ec.asl | 3 + + .../dell/optiplex_3040/acpi/superio.asl | 3 + + .../dell/optiplex_3040/board_info.txt | 7 + + src/mainboard/dell/optiplex_3040/bootblock.c | 107 ++++ + src/mainboard/dell/optiplex_3040/cmos.default | 5 + + src/mainboard/dell/optiplex_3040/cmos.layout | 54 ++ + src/mainboard/dell/optiplex_3040/data.vbt | Bin 0 -> 4300 bytes + .../dell/optiplex_3040/devicetree.cb | 100 ++++ + src/mainboard/dell/optiplex_3040/dsdt.asl | 27 + + .../dell/optiplex_3040/gma-mainboard.ads | 19 + + src/mainboard/dell/optiplex_3040/hda_verb.c | 90 +++ + .../dell/optiplex_3040/include/early_gpio.h | 11 + + .../dell/optiplex_3040/include/gpio.h | 241 +++++++++ + src/mainboard/dell/optiplex_3040/ramstage.c | 512 ++++++++++++++++++ + src/mainboard/dell/optiplex_3040/romstage.c | 22 + + src/mainboard/dell/optiplex_3040/sch5555_ec.c | 54 ++ + src/mainboard/dell/optiplex_3040/sch5555_ec.h | 10 + + 20 files changed, 1318 insertions(+) + create mode 100644 src/mainboard/dell/optiplex_3040/Kconfig + create mode 100644 src/mainboard/dell/optiplex_3040/Kconfig.name + create mode 100644 src/mainboard/dell/optiplex_3040/Makefile.mk + create mode 100644 src/mainboard/dell/optiplex_3040/acpi/ec.asl + create mode 100644 src/mainboard/dell/optiplex_3040/acpi/superio.asl + create mode 100644 src/mainboard/dell/optiplex_3040/board_info.txt + create mode 100644 src/mainboard/dell/optiplex_3040/bootblock.c + create mode 100644 src/mainboard/dell/optiplex_3040/cmos.default + create mode 100644 src/mainboard/dell/optiplex_3040/cmos.layout + create mode 100644 src/mainboard/dell/optiplex_3040/data.vbt + create mode 100644 src/mainboard/dell/optiplex_3040/devicetree.cb + create mode 100644 src/mainboard/dell/optiplex_3040/dsdt.asl + create mode 100644 src/mainboard/dell/optiplex_3040/gma-mainboard.ads + create mode 100644 src/mainboard/dell/optiplex_3040/hda_verb.c + create mode 100644 src/mainboard/dell/optiplex_3040/include/early_gpio.h + create mode 100644 src/mainboard/dell/optiplex_3040/include/gpio.h + create mode 100644 src/mainboard/dell/optiplex_3040/ramstage.c + create mode 100644 src/mainboard/dell/optiplex_3040/romstage.c + create mode 100644 src/mainboard/dell/optiplex_3040/sch5555_ec.c + create mode 100644 src/mainboard/dell/optiplex_3040/sch5555_ec.h + +diff --git a/src/mainboard/dell/optiplex_3040/Kconfig b/src/mainboard/dell/optiplex_3040/Kconfig +new file mode 100644 +index 0000000000..eab8e7d814 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/Kconfig +@@ -0,0 +1,37 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++if BOARD_DELL_OPTIPLEX_3040 ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select BOARD_ROMSIZE_KB_16384 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_ADD_VBT ++ select INTEL_GMA_HAVE_VBT ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_SUPPORTS_SKYLAKE_CPU ++ select SKYLAKE_SOC_PCH_H ++ select AZALIA_USE_LEGACY_VERB_TABLE ++ select SOC_INTEL_COMMON_BLOCK_HDA_VERB ++ select SOC_INTEL_KABYLAKE ++ select SUPERIO_SMSC_SCH555x ++ ++config CBFS_SIZE ++ default 0x900000 ++ ++config MAINBOARD_DIR ++ default "dell/optiplex_3040" ++ ++config MAINBOARD_PART_NUMBER ++ default "OptiPlex 3040 Micro" ++ ++config INTEL_GMA_VBT_FILE ++ default "src/mainboard/$(MAINBOARDDIR)/data.vbt" ++ ++config DIMM_SPD_SIZE ++ default 256 # DDR3L ++ ++endif +diff --git a/src/mainboard/dell/optiplex_3040/Kconfig.name b/src/mainboard/dell/optiplex_3040/Kconfig.name +new file mode 100644 +index 0000000000..e06da5010a +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/Kconfig.name +@@ -0,0 +1,4 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_DELL_OPTIPLEX_3040 ++ bool "Dell OptiPlex 3040 Micro" +diff --git a/src/mainboard/dell/optiplex_3040/Makefile.mk b/src/mainboard/dell/optiplex_3040/Makefile.mk +new file mode 100644 +index 0000000000..0bd72fe691 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/Makefile.mk +@@ -0,0 +1,12 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++bootblock-y += bootblock.c ++bootblock-y += sch5555_ec.c ++ ++romstage-y += romstage.c ++ ++ramstage-y += ramstage.c ++ramstage-y += sch5555_ec.c ++ramstage-y += hda_verb.c ++ ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/dell/optiplex_3040/acpi/ec.asl b/src/mainboard/dell/optiplex_3040/acpi/ec.asl +new file mode 100644 +index 0000000000..16990d45f4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/acpi/ec.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ +diff --git a/src/mainboard/dell/optiplex_3040/acpi/superio.asl b/src/mainboard/dell/optiplex_3040/acpi/superio.asl +new file mode 100644 +index 0000000000..16990d45f4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: CC-PDDC */ ++ ++/* Please update the license if adding licensable material. */ +diff --git a/src/mainboard/dell/optiplex_3040/board_info.txt b/src/mainboard/dell/optiplex_3040/board_info.txt +new file mode 100644 +index 0000000000..e43a925ec3 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/board_info.txt +@@ -0,0 +1,7 @@ ++Category: desktop ++Board URL: https://www.dell.com/support/home/en-us/product-support/product/optiplex-3040-micro/overview ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2016 +diff --git a/src/mainboard/dell/optiplex_3040/bootblock.c b/src/mainboard/dell/optiplex_3040/bootblock.c +new file mode 100644 +index 0000000000..10689c42a1 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/bootblock.c +@@ -0,0 +1,107 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootblock_common.h> ++#include <device/pnp_ops.h> ++#include <soc/gpio.h> ++#include <superio/smsc/sch555x/sch555x.h> ++#include "include/early_gpio.h" ++#include "sch5555_ec.h" ++ ++struct ec_init_entry { ++ uint16_t addr; ++ uint8_t val; ++}; ++ ++static void bootblock_ec_init(void) ++{ ++ /* ++ * Early EC init ++ */ ++ ++ static const struct ec_init_entry init_table1[] = { ++ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, ++ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, ++ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, ++ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, ++ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, ++ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) ++ sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val); ++ ++ static const struct ec_init_entry init_table2[] = { ++ {0x0040, 0x00}, {0x00f8, 0x10}, {0x00f9, 0x00}, {0x00f0, 0x30}, ++ {0x00fa, 0x00}, {0x00fb, 0x00}, {0x00ea, 0x00}, {0x00eb, 0x00}, ++ {0x00ef, 0x7c}, {0x0005, 0x0f}, {0x0014, 0x01}, {0x0018, 0x2f}, ++ {0x0019, 0x2f}, {0x001a, 0x2f}, {0x001b, 0x2f}, {0x01d8, 0x01}, ++ {0x0040, 0x11}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) ++ sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val); ++ ++ sch5555_mbox_write(1, 0x000b, 0x01); ++ sch5555_mbox_write(4, 0x001a, 0x04); ++ sch5555_mbox_write(4, 0x0028, 0x18); ++ sch5555_mbox_write(4, 0x001a, 0x00); ++ sch5555_mbox_write(1, 0x000b, 0x03); ++ ++ /* ++ * Early HWM init ++ */ ++ ++ sch5555_mbox_read(1, 0xcb); ++ sch5555_mbox_read(1, 0xb8); ++ ++ static const struct ec_init_entry hwm_init_table[] = { ++ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, ++ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, ++ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, ++ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, ++ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, ++ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, ++ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, ++ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, ++ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, ++ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, ++ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, ++ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, ++ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, ++ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, ++ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, ++ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, ++ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, ++ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, ++ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, {0x0015, 0x33}, ++ {0x018b, 0x00}, {0x018c, 0x00}, {0x02f8, 0x5e}, {0x02f9, 0x01}, ++ }; ++ ++ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) ++ sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); ++} ++ ++ ++#define SCH555x_IOBASE 0x2e ++#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) ++#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) ++ ++void bootblock_mainboard_early_init(void) ++{ ++ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); ++ ++ // Super I/O early init will map Runtime and EMI registers ++ sch555x_early_init(GLOBAL_DEV); ++ ++ // Changes LED color among a few other things ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); ++ outb(0xf, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); ++ outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); ++ ++ // Perform bootblock EC initialization ++ bootblock_ec_init(); ++ ++ // Bootblock EC initialization is required for UART1 to work ++ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ++} +diff --git a/src/mainboard/dell/optiplex_3040/cmos.default b/src/mainboard/dell/optiplex_3040/cmos.default +new file mode 100644 +index 0000000000..79961f43d8 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/cmos.default +@@ -0,0 +1,5 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable +diff --git a/src/mainboard/dell/optiplex_3040/cmos.layout b/src/mainboard/dell/optiplex_3040/cmos.layout +new file mode 100644 +index 0000000000..54a5147b7d +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/cmos.layout +@@ -0,0 +1,54 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++#start-bit length config config-ID name ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++# coreboot config options: southbridge ++409 2 e 7 power_on_after_fail ++ ++# coreboot config options: bootloader ++#Used by ChromeOS: ++416 128 r 0 vbnv ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 415 984 +diff --git a/src/mainboard/dell/optiplex_3040/data.vbt b/src/mainboard/dell/optiplex_3040/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..b503dfc20277775982256a4bdc9108c2ad96f856 +GIT binary patch +literal 4300 +zcmeHJU2GIp6#nLSXYbBzr$d#pV7($jx3pz;m0GlwX?H0tEiwzWuF-@o*+oezEo~tM +zf4YX6kSJy!)Szid6JN~w(!}_rMiOHr!Jldr9_@>X5=}_J_yVk%JJapDM0Z0%l!R}R +zIrp4<=DX+Id*|M>Zm4^Z?&*JOpsRly^^k^%uk_0>aU;6>cJ0|4?;7md+dZ%=)=$5~ +z-I&#{Uj)(|w@Qten<IS(Co?0ByTi1<dw>o(A5h19#EjB-JKfpSLz9t6Gqt-rd*eI% +zXydjXI}&cDcC0gQN0=IQ)OcsyjxzPZa5LT3V@D}H&^<ajF-bEAhxd(S(l<s|39-?! +zqvHpjeQuIA#=<menr2JXj6^64nZ`!P$69IE$Ozr-_)O5<nTgE!kxaT(BN_qDKoL1` +zoP?SzI9!V&Wx=)(w_sAN6HzB(%tG42poNDhCav;#bnu%wUIf;c_D}!>5CAB!m<l+8 +z6Y+ftx~?3nb9DO$4v;=M3`pQ8$0(d{Eu3dwuQRX33ko1QTt3QCe#y&i=(=*6c>#Vv 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+znyF$xyc?cdNX)D??RQod83eG>SheJ87|bT?Y-%QL)+gM0(8)r8%Cfl0J;@j}mqDUc +zWN|TsIh(FDRWr7nMJ~t~oa(0Xf5AVJtv}S>VkKLa*Fr#z8-oJ5@_!Mwkji33O4q%s +znq{FghJhY?uRVM)GxGTG^O@UI$;9oJ$<daf?OpB+SHQ+sAn(vOAerBB7PsO}lKDaz +g_%bx#h2uQ{`atjmY^2f5y^UXl)_LGW5w}J2FT+;79{>OV + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/optiplex_3040/devicetree.cb b/src/mainboard/dell/optiplex_3040/devicetree.cb +new file mode 100644 +index 0000000000..f1c919fbc7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/devicetree.cb +@@ -0,0 +1,100 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN" ++ ++ # Enable Enhanced Intel SpeedStep ++ register "eist_enable" = "1" ++ ++ device domain 0 on ++ device ref igpu on ++ register "PrimaryDisplay" = "Display_iGFX" ++ end ++ ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC0), // Front panel (blue) ++ [1] = USB2_PORT_MID(OC0), // Front panel (blue) ++ [2] = USB2_PORT_MID(OC3), // Back panel (black) ++ [3] = USB2_PORT_MID(OC2), // Back panel (blue) ++ [4] = USB2_PORT_MID(OC1), // Back panel (blue) ++ [6] = USB2_PORT_MID(OC1), // Back panel (black) ++ [8] = USB2_PORT_MID(OC_SKIP), // WiFi slot ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) ++ [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) ++ [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) ++ [3] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) ++ }" ++ end ++ ++ # ME interface is 'off' to avoid HECI reset delay due to HAP ++ device ref heci1 off end ++ ++ device ref sata on ++ register "SataSalpSupport" = "1" ++ register "SataPortsEnable[0]" = "1" ++ end ++ ++ # M.2 SSD ++ device ref pcie_rp21 on ++ register "PcieRpClkReqSupport[20]" = "1" ++ register "PcieRpClkReqNumber[20]" = "3" ++ register "PcieRpAdvancedErrorReporting[20]" = "1" ++ register "PcieRpLtrEnable[20]" = "true" ++ register "PcieRpClkSrcNumber[20]" = "3" ++ register "PcieRpHotPlug[20]" = "0" ++ end ++ ++ # Realtek LAN ++ device ref pcie_rp5 on ++ register "PcieRpClkReqSupport[4]" = "0" ++ register "PcieRpHotPlug[4]" = "0" ++ end ++ ++ # M.2 WiFi ++ device ref pcie_rp8 on ++ register "PcieRpClkReqSupport[7]" = "0" ++ register "PcieRpHotPlug[7]" = "1" ++ end ++ ++ # UART0 is exposed on test points on the bottom of the board ++ device ref uart0 on ++ register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci" ++ end ++ ++ device ref lpc_espi on ++ register "serirq_mode" = "SERIRQ_CONTINUOUS" ++ ++ # I/O decode for EMI/Runtime registers ++ register "gen1_dec" = "0x007c0a01" ++ ++ # SCH5553 ++ chip superio/smsc/sch555x ++ device pnp 2e.0 on # EMI ++ io 0x60 = 0xa00 ++ end ++ device pnp 2e.1 off end # 8042 ++ device pnp 2e.7 on # UART1 ++ io 0x60 = 0x3f8 ++ irq 0x0f = 2 ++ irq 0x70 = 4 ++ end ++ device pnp 2e.8 off end # UART2 ++ device pnp 2e.c on # LPC interface ++ io 0x60 = 0x2e ++ end ++ device pnp 2e.a on # Runtime registers ++ io 0x60 = 0xa40 ++ end ++ device pnp 2e.b off end # Floppy Controller ++ device pnp 2e.11 off end # Parallel Port ++ end ++ end ++ ++ device ref hda on end ++ ++ device ref smbus on end ++ end ++end +diff --git a/src/mainboard/dell/optiplex_3040/dsdt.asl b/src/mainboard/dell/optiplex_3040/dsdt.asl +new file mode 100644 +index 0000000000..9762f6ff74 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/dsdt.asl +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <acpi/acpi.h> ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20110725 ++) ++{ ++ #include <acpi/dsdt_top.asl> ++ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> ++ #include <cpu/intel/common/acpi/cpu.asl> ++ ++ Scope (\_SB) ++ { ++ Device (PCI0) ++ { ++ #include <soc/intel/skylake/acpi/systemagent.asl> ++ #include <soc/intel/skylake/acpi/pch.asl> ++ } ++ } ++ ++ #include <southbridge/intel/common/acpi/sleepstates.asl> ++} +diff --git a/src/mainboard/dell/optiplex_3040/gma-mainboard.ads b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads +new file mode 100644 +index 0000000000..cb4c22f285 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads +@@ -0,0 +1,19 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (HDMI1, -- External HDMI ++ DP2, -- External DP (native) ++ HDMI2, -- External DP (DP++) ++ DP3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) ++ HDMI3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/optiplex_3040/hda_verb.c b/src/mainboard/dell/optiplex_3040/hda_verb.c +new file mode 100644 +index 0000000000..5a1db019c7 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/hda_verb.c +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header, codec 0 */ ++ 0x10ec0255, /* Realtek ALC3234 */ ++ 0x102806bb, /* Subsystem ID */ ++ 11, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_SUBVENDOR(0, 0x102806bb), ++ ++ AZALIA_PIN_CFG(0, 0x12, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 5, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, ++ AZALIA_LINE_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1d, 0x4054c029), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 5, 15 ++ )), ++ ++ /* coreboot specific header, codec 2 */ ++ 0x80862809, /* Intel Skylake HDMI */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/optiplex_3040/include/early_gpio.h b/src/mainboard/dell/optiplex_3040/include/early_gpio.h +new file mode 100644 +index 0000000000..fdf1a64c7c +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/include/early_gpio.h +@@ -0,0 +1,11 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __OPTIPLEX_3040_EARLY_GPIO_H__ ++#define __OPTIPLEX_3040_EARLY_GPIO_H__ ++ ++static const struct pad_config early_gpio_table[] = { ++ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ ++ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ ++}; ++ ++#endif +diff --git a/src/mainboard/dell/optiplex_3040/include/gpio.h b/src/mainboard/dell/optiplex_3040/include/gpio.h +new file mode 100644 +index 0000000000..29da4b11d4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/include/gpio.h +@@ -0,0 +1,241 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __OPTIPLEX_3040_GPIO_H__ ++#define __OPTIPLEX_3040_GPIO_H__ ++ ++static const struct pad_config gpio_table[] = { ++ ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, UP_20K, PLTRST, NF1), /* RCIN# */ ++ PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* LAD0 */ ++ PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* LAD1 */ ++ PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* LAD2 */ ++ PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* LAD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ ++ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# */ ++ PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */ ++ PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */ ++ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* PME# */ ++ PAD_CFG_GPO(GPP_A12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), /* SUSWARN#/SUSPWRDNACK */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_A15, UP_20K, PLTRST, NF1), /* SUS_ACK# */ ++ PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_CFG_GPO(GPP_B0, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B1, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B2, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_B3, 1, RSMRST), /* GPIO (ME_CNTL, B3 -> LOW => HDA_SDO -> HIGH) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_B5, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B6, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_B9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ ++ PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), /* PLTRST# */ ++ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ ++ PAD_CFG_GPO(GPP_B15, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* GSPIO_MOSI */ ++ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* GPIO */ ++ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GSPI1_MOSI */ ++ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* PCHHOT# */ ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_C2, DN_20K, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_C3, NONE, PLTRST, NF1), /* SML0CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, PLTRST, NF1), /* SML0DATA */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ ++ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ ++ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ ++ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ ++ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ ++ PAD_CFG_GPO(GPP_C18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_CFG_GPO(GPP_D0, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D1, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D2, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D3, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_D7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ ++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ ++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 */ ++ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ ++ PAD_CFG_NF(GPP_E9, UP_20K, PLTRST, NF1), /* USB_OC0# */ ++ PAD_CFG_NF(GPP_E10, UP_20K, PLTRST, NF1), /* USB_OC1# */ ++ PAD_CFG_NF(GPP_E11, UP_20K, PLTRST, NF1), /* USB_OC2# */ ++ PAD_CFG_NF(GPP_E12, UP_20K, PLTRST, NF1), /* USB_OC3# */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ ++ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* SATAXPCIE4 */ ++ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ ++ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ ++ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), /* SATA_DEVSLP4 */ ++ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_F9, 0, RSMRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_F13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), /* USB_OC4# */ ++ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), /* USB_OC5# */ ++ PAD_CFG_NF(GPP_F17, UP_20K, PLTRST, NF1), /* USB_OC6# */ ++ PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_F21, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F22, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F23, 1, RSMRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G9, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G12, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G14, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G16, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G17, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_G19, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G20, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_G21, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G22, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_H ------- */ ++ PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H3, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H4, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H5, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H6, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H8, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ ++ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ ++ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */ ++ PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PWRBTN# */ ++ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ ++ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ ++ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ ++ PAD_CFG_GPO(GPD7, 1, RSMRST), /* GPIO */ ++ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ ++ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ ++ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ ++ PAD_CFG_GPO(GPD11, 1, RSMRST), /* GPIO */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_I ------- */ ++ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ ++ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ ++ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ ++ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ ++ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */ ++ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ ++ PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* DDPB_CTRLDATA */ ++ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ ++ PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* DDPC_CTRLDATA */ ++ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ ++ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */ ++}; ++ ++#endif +diff --git a/src/mainboard/dell/optiplex_3040/ramstage.c b/src/mainboard/dell/optiplex_3040/ramstage.c +new file mode 100644 +index 0000000000..c391e4ac6d +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/ramstage.c +@@ -0,0 +1,512 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <bootstate.h> ++#include <arch/cpuid.h> ++#include <cpu/x86/msr.h> ++#include <soc/gpio.h> ++#include <soc/ramstage.h> ++#include "include/gpio.h" ++#include "sch5555_ec.h" ++ ++void mainboard_silicon_init_params(FSP_SIL_UPD *params) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} ++ ++#define FORM_FACTOR_MICRO 0 ++#define FORM_FACTOR_SFF 1 ++// Probably DT and MT ++#define FORM_FACTOR_UNK2 2 ++#define FORM_FACTOR_UNK3 3 ++ ++#define HWM_TAB_ADD_TEMP_TARGET 1 ++#define HWM_TAB_PKG_POWER_ANY 0xffff ++ ++struct hwm_tab_entry { ++ uint16_t addr; ++ uint8_t val; ++ uint8_t flags; ++ uint16_t pkg_power; ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_BASE[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x00, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xf1, 0, 0xffff }, ++ { 0x086, 0x88, 0, 0xffff }, ++ { 0x087, 0x61, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x7e, 0, 0xffff }, ++ { 0x092, 0x66, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x7c, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x5c, 0, 0xffff }, ++ { 0x0eb, 0x5c, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_TEMP80[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x00, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xf6, 0, 0xffff }, ++ { 0x086, 0x88, 0, 0xffff }, ++ { 0x087, 0x61, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x86, 0, 0xffff }, ++ { 0x092, 0x66, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x7c, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x50, 0, 0xffff }, ++ { 0x0eb, 0x50, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MICRO_EARLY_STEPPING[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x01b, 0x0f, 0, 0xffff }, ++ { 0x057, 0xff, 0, 0xffff }, ++ { 0x059, 0xff, 0, 0xffff }, ++ { 0x05b, 0xff, 0, 0xffff }, ++ { 0x05d, 0xff, 0, 0xffff }, ++ { 0x05f, 0xff, 0, 0xffff }, ++ { 0x061, 0xff, 0, 0xffff }, ++ { 0x06e, 0x01, 0, 0xffff }, ++ { 0x06f, 0x03, 0, 0xffff }, ++ { 0x070, 0x03, 0, 0xffff }, ++ { 0x071, 0x02, 0, 0xffff }, ++ { 0x072, 0x02, 0, 0xffff }, ++ { 0x073, 0x01, 0, 0xffff }, ++ { 0x074, 0x06, 0, 0xffff }, ++ { 0x075, 0x07, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x80, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xfd, 0, 0xffff }, ++ { 0x086, 0x60, 0, 0xffff }, ++ { 0x087, 0x50, 0, 0xffff }, ++ { 0x088, 0x08, 0, 0xffff }, ++ { 0x089, 0x00, 0, 0xffff }, ++ { 0x08a, 0x73, 0, 0xffff }, ++ { 0x08b, 0x73, 0, 0xffff }, ++ { 0x08c, 0x73, 0, 0xffff }, ++ { 0x090, 0x6d, 0, 0xffff }, ++ { 0x091, 0x7a, 0, 0xffff }, ++ { 0x092, 0x6b, 0, 0xffff }, ++ { 0x093, 0xa4, 0, 0xffff }, ++ { 0x094, 0x78, 0, 0xffff }, ++ { 0x095, 0xa4, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x2e, 0, 0xffff }, ++ { 0x0a1, 0x00, 0, 0xffff }, ++ { 0x0a2, 0x00, 0, 0xffff }, ++ { 0x0ae, 0xa4, 0, 0xffff }, ++ { 0x0af, 0xa4, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0xa4, 0, 0xffff }, ++ { 0x0b3, 0xa4, 0, 0xffff }, ++ { 0x0b6, 0x00, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0d1, 0xff, 0, 0xffff }, ++ { 0x0d6, 0xff, 0, 0xffff }, ++ { 0x0db, 0xff, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0eb, 0x64, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x184, 0xff, 0, 0xffff }, ++ { 0x186, 0xff, 0, 0xffff }, ++ { 0x1a1, 0xce, 0, 0xffff }, ++ { 0x1a2, 0x0c, 0, 0xffff }, ++ { 0x1a3, 0x0c, 0, 0xffff }, ++ { 0x1a6, 0x00, 0, 0xffff }, ++ { 0x1a7, 0x00, 0, 0xffff }, ++ { 0x1a8, 0xa4, 0, 0xffff }, ++ { 0x1a9, 0xa4, 0, 0xffff }, ++ { 0x1ab, 0x2d, 0, 0xffff }, ++ { 0x1ac, 0x2d, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1bb, 0x00, 0, 0xffff }, ++ { 0x1bc, 0x00, 0, 0xffff }, ++ { 0x1bd, 0x00, 0, 0xffff }, ++ { 0x1be, 0x01, 0, 0xffff }, ++ { 0x1bf, 0x01, 0, 0xffff }, ++ { 0x1c0, 0x01, 0, 0xffff }, ++ { 0x1c1, 0x01, 0, 0xffff }, ++ { 0x1c2, 0x01, 0, 0xffff }, ++ { 0x280, 0x00, 0, 0xffff }, ++ { 0x281, 0x00, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_SFF[] = { ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x040, 0x01, 0, 0xffff }, ++ { 0x072, 0x03, 0, 0xffff }, ++ { 0x075, 0x06, 0, 0xffff }, ++ { 0x07c, 0x00, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x59, 0, 0xffff }, ++ { 0x086, 0x6a, 0, 0xffff }, ++ { 0x087, 0xc0, 0, 0xffff }, ++ { 0x08a, 0x33, 0, 0xffff }, ++ { 0x090, 0x77, 0, 0xffff }, ++ { 0x091, 0x66, 0, 0xffff }, ++ { 0x092, 0x94, 0, 0xffff }, ++ { 0x093, 0x90, 0, 0xffff }, ++ { 0x094, 0x68, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x099, 0xa4, 0, 0xffff }, ++ { 0x09a, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x3e, 0, 0xffff }, ++ { 0x0ae, 0x86, 0, 0xffff }, ++ { 0x0af, 0x86, 0, 0xffff }, ++ { 0x0b0, 0xa4, 0, 0xffff }, ++ { 0x0b1, 0xa4, 0, 0xffff }, ++ { 0x0b2, 0x90, 0, 0xffff }, ++ { 0x0b6, 0x48, 0, 0xffff }, ++ { 0x0b7, 0x48, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x1b1, 0x48, 0, 0xffff }, ++ { 0x1b8, 0x00, 0, 0xffff }, ++ { 0x1be, 0x95, 0, 0xffff }, ++ { 0x1c1, 0x90, 0, 0xffff }, ++ { 0x1c6, 0x00, 0, 0xffff }, ++ { 0x1c9, 0x00, 0, 0xffff }, ++ { 0x280, 0x68, 0, 0xffff }, ++ { 0x281, 0x10, 0, 0xffff }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff} ++}; ++ ++static const struct hwm_tab_entry HWM_TAB_MT[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x082, 0x80, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0xb9, 0, 0x0010 }, ++ { 0x086, 0xac, 0, 0x0010 }, ++ { 0x087, 0x87, 0, 0x0010 }, ++ { 0x08a, 0x51, 0, 0x0010 }, ++ { 0x08b, 0x39, 0, 0x0010 }, ++ { 0x090, 0x78, 0, 0xffff }, ++ { 0x091, 0x6a, 0, 0xffff }, ++ { 0x092, 0x8f, 0, 0xffff }, ++ { 0x094, 0x68, 0, 0xffff }, ++ { 0x095, 0x5b, 0, 0xffff }, ++ { 0x096, 0x92, 0, 0xffff }, ++ { 0x097, 0x86, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09a, 0x8b, 0, 0xffff }, ++ { 0x0a0, 0x0a, 0, 0xffff }, ++ { 0x0a1, 0x26, 0, 0xffff }, ++ { 0x0a2, 0xd1, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x00, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0xffff }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x99, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1a4, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x00, 0, 0xffff }, ++ { 0x1be, 0x90, 0, 0xffff }, ++ { 0x280, 0xc4, 0, 0xffff }, ++ { 0x281, 0x09, 0, 0xffff }, ++ { 0x282, 0x0a, 0, 0xffff }, ++ { 0x283, 0x14, 0, 0xffff }, ++ { 0x284, 0x01, 0, 0xffff }, ++ { 0x285, 0x01, 0, 0xffff }, ++ { 0x288, 0x94, 0, 0xffff }, ++ { 0x289, 0x11, 0, 0xffff }, ++ { 0x28a, 0x0a, 0, 0xffff }, ++ { 0x28b, 0x14, 0, 0xffff }, ++ { 0x28c, 0x01, 0, 0xffff }, ++ { 0x28d, 0x01, 0, 0xffff }, ++ { 0x294, 0x24, 0, 0xffff }, ++}; ++ ++static uint8_t get_temp_target(void) ++{ ++ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; ++ if (!val) ++ val = 20; ++ return 0x95 - val; ++} ++ ++static uint16_t get_pkg_power(void) ++{ ++ const unsigned int pkg_power = rdmsr(0x614).lo & 0x7fff; ++ const unsigned int power_unit = 1 << (rdmsr(0x606).lo & 0xf); ++ if (pkg_power / power_unit > 65) ++ return 32; ++ else ++ return 16; ++} ++ ++static uint8_t get_core_cnt(void) ++{ ++ // Intel describes this CPUID field as: ++ // > Maximum number of addressable IDs for processor cores in the physical package ++ if (cpuid(0).eax >= 4) ++ return cpuid_ext(4, 0).eax >> 26; ++ return 0; ++} ++ ++static void apply_hwm_tab(const struct hwm_tab_entry *arr, size_t size) ++{ ++ uint8_t temp_target = get_temp_target(); ++ uint16_t pkg_power = get_pkg_power(); ++ ++ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); ++ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); ++ ++ for (size_t i = 0; i < size; ++i) { ++ // Skip entry if it doesn't apply for this package power ++ if (arr[i].pkg_power != pkg_power && ++ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) ++ continue; ++ ++ uint8_t val = arr[i].val; ++ ++ // Add temp target to value if requested (current tables never do) ++ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) ++ val += temp_target; ++ ++ // Perform write ++ sch5555_mbox_write(1, arr[i].addr, val); ++ } ++} ++ ++static void sch5555_ec_hwm_init(void *arg) ++{ ++ uint8_t form_fac_id, saved_2fc, core_cnt; ++ ++ printk(BIOS_DEBUG, "OptiPlex 3040 late HWM init\n"); ++ ++ form_fac_id = gpio_get(GPP_G2) | gpio_get(GPP_G3) << 1; ++ printk(BIOS_DEBUG, "Form Factor ID = %#x\n", form_fac_id); ++ ++ saved_2fc = sch5555_mbox_read(1, 0x2fc); ++ sch5555_mbox_write(1, 0x2fc, 0xa0); ++ sch5555_mbox_write(1, 0x2fd, 0x32); ++ ++ switch (form_fac_id) { ++ case FORM_FACTOR_MICRO: ++ // CPU stepping <= 3 ++ if ((cpuid(1).eax & 0xf) <= 3) ++ apply_hwm_tab(HWM_TAB_MICRO_EARLY_STEPPING, ARRAY_SIZE(HWM_TAB_MICRO_EARLY_STEPPING)); ++ // Tjunction == 80 ++ else if ((rdmsr(0x1a2).lo >> 16 & 0xff) == 80) ++ apply_hwm_tab(HWM_TAB_MICRO_TEMP80, ARRAY_SIZE(HWM_TAB_MICRO_TEMP80)); ++ else ++ apply_hwm_tab(HWM_TAB_MICRO_BASE, ARRAY_SIZE(HWM_TAB_MICRO_BASE)); ++ break; ++ case FORM_FACTOR_SFF: ++ apply_hwm_tab(HWM_TAB_SFF, ARRAY_SIZE(HWM_TAB_SFF)); ++ break; ++ default: ++ apply_hwm_tab(HWM_TAB_MT, ARRAY_SIZE(HWM_TAB_MT)); ++ break; ++ } ++ ++ core_cnt = get_core_cnt(); ++ printk(BIOS_DEBUG, "CPU Core Count = %#x\n", core_cnt); ++ if (core_cnt > 2) { ++ sch5555_mbox_write(1, 0x9e, 0x30); ++ sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea)); ++ } ++ ++ sch5555_mbox_write(1, 0x2fc, saved_2fc); ++ sch5555_mbox_read(1, 0xb8); ++} ++ ++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); +diff --git a/src/mainboard/dell/optiplex_3040/romstage.c b/src/mainboard/dell/optiplex_3040/romstage.c +new file mode 100644 +index 0000000000..c2ce2369a4 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/romstage.c +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <soc/romstage.h> ++#include <spd_bin.h> ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ /* ++ * OptiPlex 3040 Micro uses DDR3L SO-DIMMs. ++ * SODIMM slots are at I2C addresses 0x50 (slot 0) and 0x52 (slot 1). ++ * SPD size for DDR3L is 256 bytes. ++ */ ++ struct spd_block blk = { .addr_map = { 0x50, 0x52, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; ++ mem_cfg->MemorySpdDataLen = blk.len; ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; ++} +diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.c b/src/mainboard/dell/optiplex_3040/sch5555_ec.c +new file mode 100644 +index 0000000000..1df5026531 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.c +@@ -0,0 +1,54 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <arch/io.h> ++#include <device/pnp_ops.h> ++#include <superio/smsc/sch555x/sch555x.h> ++#include "sch5555_ec.h" ++ ++uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++ ++ // read result ++ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); ++ return inb(SCH555x_EMI_IOBASE + 4); ++} ++ ++void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address and value ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++} +diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.h b/src/mainboard/dell/optiplex_3040/sch5555_ec.h +new file mode 100644 +index 0000000000..9d262d5787 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.h +@@ -0,0 +1,10 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __SCH5555_EC_H__ ++#define __SCH5555_EC_H__ ++ ++uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2); ++ ++void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val); ++ ++#endif +-- +2.53.0 + diff --git a/config/coreboot/dell3040micro_vfsp_16mb/config/libgfxinit_corebootfb b/config/coreboot/dell3040micro_vfsp_16mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..ba239cdd --- /dev/null +++ b/config/coreboot/dell3040micro_vfsp_16mb/config/libgfxinit_corebootfb @@ -0,0 +1,822 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_LTO is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set +# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_TSEG_STAGE_CACHE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARM is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ERYING is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HARDKERNEL is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LATTEPANDA is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MITAC_COMPUTING is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NOVACUSTOM is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TOPTON is not set +# CONFIG_VENDOR_UP is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3040 Micro" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_3040" +CONFIG_VGA_BIOS_ID="8086,0406" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0xEEE000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840 +CONFIG_MAX_CPUS=16 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +# CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=256 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +# CONFIG_FATAL_ASSERTS is not set +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3040 Micro" +# CONFIG_CONSOLE_POST is not set +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_MAX_SOCKET=1 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_USE_PM_ACPI_TIMER=y +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set +# CONFIG_BOARD_DELL_E4300 is not set +# CONFIG_BOARD_DELL_E6400 is not set +CONFIG_BOARD_DELL_OPTIPLEX_3040=y +# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/3040micro/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/3040micro/me.bin" +CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y +CONFIG_USE_LEGACY_8254_TIMER=y +# CONFIG_DEBUG_SMI is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +CONFIG_D3COLD_SUPPORT=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x01000000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb" +CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd" +CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x800 +CONFIG_ACPI_BERT_SIZE=0x0 +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_MAX_ROOT_PORTS=24 +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_CPU_XTAL_HZ=24000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_ENABLE_SATA_TEST_MODE is not set +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0 +CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_FSP_PUBLISH_MBP_HOB=y +CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003 +CONFIG_MAX_HECI_DEVICES=5 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_HAVE_PAM0_REGISTER=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000 +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0 +CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003 +CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_SKYLAKE_SOC_PCH_H=y +# CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU is not set +# CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU is not set +# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set +CONFIG_FSP_T_LOCATION=0xfffe0000 +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_FIXED_SMBUS_IO_BASE=0xefa0 +CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code for IP blocks +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y +# CONFIG_USE_COREBOOT_MP_INIT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +CONFIG_INTEL_CAR_NEM_ENHANCED=y +# CONFIG_USE_INTEL_FSP_MP_INIT is not set +CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y +CONFIG_HAVE_HYPERTHREADING=y +# CONFIG_FSP_HYPERTHREADING is not set +# CONFIG_INTEL_KEYLOCKER is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y +CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME" +CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw" +CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version" +CONFIG_SOC_INTEL_CSE_RW_FILE="" +CONFIG_SOC_INTEL_CSE_RW_VERSION="" +CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom" +CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE="" +CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy" +CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE="" +CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y +# CONFIG_SOC_INTEL_DISABLE_IGD is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_ENABLE_DPR=y +CONFIG_HAVE_CAPID_A_REGISTER=y +CONFIG_HAVE_BDSM_BGSM_REGISTER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y +CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y +CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y + +# +# Intel SoC Common coreboot stages and non-IP blocks +# +CONFIG_SOC_INTEL_COMMON_BASECODE=y +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +CONFIG_PAVP=y +# CONFIG_MMA is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set + +# +# CPU +# +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_CPU_PT_ROM_MAP_GB=512 +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 +CONFIG_UDK_BASE=y +CONFIG_UDK_2017_BINDING=y +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_202005_VERSION=202005 +CONFIG_UDK_202111_VERSION=202111 +CONFIG_UDK_202302_VERSION=202302 +CONFIG_UDK_202305_VERSION=202305 +CONFIG_UDK_VERSION=2017 +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 +CONFIG_DEFAULT_EBDA_LOWMEM=0x100000 +CONFIG_DEFAULT_EBDA_SEGMENT=0xF600 +CONFIG_DEFAULT_EBDA_SIZE=0x400 +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_RUN_FSP_GOP is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y +# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set +# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set +# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set +CONFIG_DEFAULT_SCREEN_ROTATION_INT=0 +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x10000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set +# CONFIG_DRIVERS_EFI_FW_INFO is not set +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_DRIVERS_OPTION_CFR is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_MAX98396 is not set +# CONFIG_FSP_USE_REPO is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +CONFIG_PLATFORM_USES_FSP2_X86_32=y +CONFIG_HAVE_INTEL_FSP_REPO=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +# CONFIG_FSP_FULL_FD is not set +CONFIG_FSP_T_RESERVED_SIZE=0x0 +CONFIG_FSP_M_XIP=y +CONFIG_SOC_INTEL_COMMON_FSP_RESET=y +CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y +CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y +CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y +# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set +# CONFIG_BUILDING_WITH_DEBUG_FSP is not set +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Skylake" +CONFIG_GFX_GMA_PCH="Sunrise_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_USB_ACPI=y +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_CUSTOM_MADT=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_ACPI_LPIT=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_ACPI_S1_NOT_SUPPORTED=y +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y +# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y + +# +# Boot Logo Configuration +# +# CONFIG_BMP_LOGO is not set +# end of Boot Logo Configuration + +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell3040micro_vfsp_16mb/config/libgfxinit_txtmode b/config/coreboot/dell3040micro_vfsp_16mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..55a54af5 --- /dev/null +++ b/config/coreboot/dell3040micro_vfsp_16mb/config/libgfxinit_txtmode @@ -0,0 +1,815 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_LTO is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set +# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_TSEG_STAGE_CACHE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARM is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ERYING is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HARDKERNEL is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LATTEPANDA is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MITAC_COMPUTING is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NOVACUSTOM is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TOPTON is not set +# CONFIG_VENDOR_UP is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3040 Micro" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_3040" +CONFIG_VGA_BIOS_ID="8086,0406" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0xEEE000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=16 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +# CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=256 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +# CONFIG_FATAL_ASSERTS is not set +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3040 Micro" +# CONFIG_CONSOLE_POST is not set +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_MAX_SOCKET=1 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_USE_PM_ACPI_TIMER=y +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set +# CONFIG_BOARD_DELL_E4300 is not set +# CONFIG_BOARD_DELL_E6400 is not set +CONFIG_BOARD_DELL_OPTIPLEX_3040=y +# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/3040micro/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/3040micro/me.bin" +CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y +CONFIG_USE_LEGACY_8254_TIMER=y +# CONFIG_DEBUG_SMI is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +CONFIG_D3COLD_SUPPORT=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x01000000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb" +CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd" +CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x800 +CONFIG_ACPI_BERT_SIZE=0x0 +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_MAX_ROOT_PORTS=24 +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_CPU_XTAL_HZ=24000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_ENABLE_SATA_TEST_MODE is not set +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0 +CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_FSP_PUBLISH_MBP_HOB=y +CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003 +CONFIG_MAX_HECI_DEVICES=5 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_HAVE_PAM0_REGISTER=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000 +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0 +CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003 +CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_SKYLAKE_SOC_PCH_H=y +# CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU is not set +# CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU is not set +# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set +CONFIG_FSP_T_LOCATION=0xfffe0000 +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_FIXED_SMBUS_IO_BASE=0xefa0 +CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code for IP blocks +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y +# CONFIG_USE_COREBOOT_MP_INIT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +CONFIG_INTEL_CAR_NEM_ENHANCED=y +# CONFIG_USE_INTEL_FSP_MP_INIT is not set +CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y +CONFIG_HAVE_HYPERTHREADING=y +# CONFIG_FSP_HYPERTHREADING is not set +# CONFIG_INTEL_KEYLOCKER is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y +CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME" +CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw" +CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version" +CONFIG_SOC_INTEL_CSE_RW_FILE="" +CONFIG_SOC_INTEL_CSE_RW_VERSION="" +CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom" +CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE="" +CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy" +CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE="" +CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y +# CONFIG_SOC_INTEL_DISABLE_IGD is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_ENABLE_DPR=y +CONFIG_HAVE_CAPID_A_REGISTER=y +CONFIG_HAVE_BDSM_BGSM_REGISTER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y +CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y +CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y + +# +# Intel SoC Common coreboot stages and non-IP blocks +# +CONFIG_SOC_INTEL_COMMON_BASECODE=y +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +CONFIG_PAVP=y +# CONFIG_MMA is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set + +# +# CPU +# +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_CPU_PT_ROM_MAP_GB=512 +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 +CONFIG_UDK_BASE=y +CONFIG_UDK_2017_BINDING=y +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_202005_VERSION=202005 +CONFIG_UDK_202111_VERSION=202111 +CONFIG_UDK_202302_VERSION=202302 +CONFIG_UDK_202305_VERSION=202305 +CONFIG_UDK_VERSION=2017 +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 +CONFIG_DEFAULT_EBDA_LOWMEM=0x100000 +CONFIG_DEFAULT_EBDA_SEGMENT=0xF600 +CONFIG_DEFAULT_EBDA_SIZE=0x400 +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_RUN_FSP_GOP is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +CONFIG_DEFAULT_SCREEN_ROTATION_INT=0 +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x10000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set +# CONFIG_DRIVERS_EFI_FW_INFO is not set +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_DRIVERS_OPTION_CFR is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_MAX98396 is not set +# CONFIG_FSP_USE_REPO is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +CONFIG_PLATFORM_USES_FSP2_X86_32=y +CONFIG_HAVE_INTEL_FSP_REPO=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +# CONFIG_FSP_FULL_FD is not set +CONFIG_FSP_T_RESERVED_SIZE=0x0 +CONFIG_FSP_M_XIP=y +CONFIG_SOC_INTEL_COMMON_FSP_RESET=y +CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y +CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y +CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y +# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set +# CONFIG_BUILDING_WITH_DEBUG_FSP is not set +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Skylake" +CONFIG_GFX_GMA_PCH="Sunrise_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_USB_ACPI=y +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_CUSTOM_MADT=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_ACPI_LPIT=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_ACPI_S1_NOT_SUPPORTED=y +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y +# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y + +# +# Boot Logo Configuration +# +# CONFIG_BMP_LOGO is not set +# end of Boot Logo Configuration + +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell3040micro_vfsp_16mb/target.cfg b/config/coreboot/dell3040micro_vfsp_16mb/target.cfg new file mode 100644 index 00000000..1a3d751e --- /dev/null +++ b/config/coreboot/dell3040micro_vfsp_16mb/target.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-3.0-or-later + +tree="default" +xarch="i386-elf" +payload_seabios="y" +payload_grub="y" +payload_memtest="y" +grub_scan_disk="nvme ahci" +grubtree="xhci_nvme" +vcfg="3040micro" +build_depend="seabios/default grub/xhci_nvme memtest86plus u-boot/amd64coreboot" +IFD_platform="sklkbl" +payload_uboot="amd64" diff --git a/config/deguard/patches/0006-data-delta-Add-Dell-OptiPlex-3040-Micro.patch b/config/deguard/patches/0006-data-delta-Add-Dell-OptiPlex-3040-Micro.patch new file mode 100644 index 00000000..ba1bb4b1 --- /dev/null +++ b/config/deguard/patches/0006-data-delta-Add-Dell-OptiPlex-3040-Micro.patch @@ -0,0 +1,219 @@ +From 1b6633229a67d934adef8c775333ccfe81450efb Mon Sep 17 00:00:00 2001 +From: Todd Baker <todd_baker@student.uml.edu> +Date: Thu, 12 Mar 2026 11:45:48 -0400 +Subject: [PATCH] data/delta: Add Dell OptiPlex 3040 Micro + +Generated from stock flash dump of Dell OptiPlex 3040 Micro with ME version 11.0.0.1197, SKU 2M, PCH-H. + +Signed-off-by: Todd Baker <todd_baker@student.uml.edu> +--- + .../optiplex_3040/home/bup/bup_sku/emu_fuse_map | Bin 0 -> 7 bytes + .../optiplex_3040/home/bup/bup_sku/fuse_ip_base | Bin 0 -> 18 bytes + .../optiplex_3040/home/bup/bup_sku/plat_n_sku | Bin 0 -> 4 bytes + data/delta/optiplex_3040/home/fwupdate/fwuoemid | 1 + + data/delta/optiplex_3040/home/gpio/csme_pins | 0 + data/delta/optiplex_3040/home/icc/header | Bin 0 -> 4 bytes + data/delta/optiplex_3040/home/icc/namestr | Bin 0 -> 48 bytes + data/delta/optiplex_3040/home/icc/prof0 | Bin 0 -> 56 bytes + data/delta/optiplex_3040/home/icc/prof1 | 0 + data/delta/optiplex_3040/home/icc/prof2 | 0 + data/delta/optiplex_3040/home/icc/prof3 | 0 + data/delta/optiplex_3040/home/icc/prof4 | 0 + data/delta/optiplex_3040/home/icc/prof5 | 0 + data/delta/optiplex_3040/home/icc/prof6 | 0 + data/delta/optiplex_3040/home/mca/ish_policy | Bin 0 -> 1 bytes + data/delta/optiplex_3040/home/mctp/device_ports | Bin 0 -> 4 bytes + data/delta/optiplex_3040/home/pavp/hdcp_ports | Bin 0 -> 1 bytes + .../optiplex_3040/home/policy/cfgmgr/cfg_rules | Bin 0 -> 660 bytes + .../delta/optiplex_3040/home/policy/hci/sysintid1 | Bin 0 -> 4 bytes + .../delta/optiplex_3040/home/policy/hci/sysintid2 | Bin 0 -> 4 bytes + .../delta/optiplex_3040/home/policy/hci/sysintid3 | Bin 0 -> 4 bytes + 21 files changed, 1 insertion(+) + create mode 100644 data/delta/optiplex_3040/home/bup/bup_sku/emu_fuse_map + create mode 100644 data/delta/optiplex_3040/home/bup/bup_sku/fuse_ip_base + create mode 100644 data/delta/optiplex_3040/home/bup/bup_sku/plat_n_sku + create mode 100644 data/delta/optiplex_3040/home/fwupdate/fwuoemid + create mode 100644 data/delta/optiplex_3040/home/gpio/csme_pins + create mode 100644 data/delta/optiplex_3040/home/icc/header + create mode 100644 data/delta/optiplex_3040/home/icc/namestr + create mode 100644 data/delta/optiplex_3040/home/icc/prof0 + create mode 100644 data/delta/optiplex_3040/home/icc/prof1 + create mode 100644 data/delta/optiplex_3040/home/icc/prof2 + create mode 100644 data/delta/optiplex_3040/home/icc/prof3 + create mode 100644 data/delta/optiplex_3040/home/icc/prof4 + create mode 100644 data/delta/optiplex_3040/home/icc/prof5 + create mode 100644 data/delta/optiplex_3040/home/icc/prof6 + create mode 100644 data/delta/optiplex_3040/home/mca/ish_policy + create mode 100644 data/delta/optiplex_3040/home/mctp/device_ports + create mode 100644 data/delta/optiplex_3040/home/pavp/hdcp_ports + create mode 100644 data/delta/optiplex_3040/home/policy/cfgmgr/cfg_rules + create mode 100644 data/delta/optiplex_3040/home/policy/hci/sysintid1 + create mode 100644 data/delta/optiplex_3040/home/policy/hci/sysintid2 + create mode 100644 data/delta/optiplex_3040/home/policy/hci/sysintid3 + +diff --git a/data/delta/optiplex_3040/home/bup/bup_sku/emu_fuse_map b/data/delta/optiplex_3040/home/bup/bup_sku/emu_fuse_map +new file mode 100644 +index 0000000000000000000000000000000000000000..19d86a9897dad64f168d75bb0a4706e2d88a461c +GIT binary patch +literal 7 +OcmZ>3uVmn1U<LpOp8-|? + +literal 0 +HcmV?d00001 + +diff --git a/data/delta/optiplex_3040/home/bup/bup_sku/fuse_ip_base b/data/delta/optiplex_3040/home/bup/bup_sku/fuse_ip_base +new file mode 100644 +index 0000000000000000000000000000000000000000..658a9660e31c0501f3e9fba168279fecec236f8b +GIT binary patch +literal 18 +ZcmWe&P-3uPSje!M;Q^BeQzX+xCIBG91Q`GT + +literal 0 +HcmV?d00001 + +diff --git a/data/delta/optiplex_3040/home/bup/bup_sku/plat_n_sku b/data/delta/optiplex_3040/home/bup/bup_sku/plat_n_sku +new file mode 100644 +index 0000000000000000000000000000000000000000..f9ed9bc11e92f2c2ad9096ebe689993fdeff0d26 +GIT binary patch +literal 4 +Lcmc~~U~B*Y0xAIO + +literal 0 +HcmV?d00001 + +diff --git a/data/delta/optiplex_3040/home/fwupdate/fwuoemid b/data/delta/optiplex_3040/home/fwupdate/fwuoemid +new file mode 100644 +index 0000000..a174ee2 +--- /dev/null ++++ b/data/delta/optiplex_3040/home/fwupdate/fwuoemid +@@ -0,0 +1 @@ ++"6�h��N��l�1_kx +\ No newline at end of file +diff --git a/data/delta/optiplex_3040/home/gpio/csme_pins b/data/delta/optiplex_3040/home/gpio/csme_pins +new file mode 100644 +index 0000000..e69de29 +diff --git a/data/delta/optiplex_3040/home/icc/header b/data/delta/optiplex_3040/home/icc/header +new file mode 100644 +index 0000000000000000000000000000000000000000..4b75556082e2c00ea8a888450d05627b20f0ec61 +GIT binary patch +literal 4 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+literal 0 +HcmV?d00001 + +diff --git a/data/delta/optiplex_3040/home/policy/hci/sysintid1 b/data/delta/optiplex_3040/home/policy/hci/sysintid1 +new file mode 100644 +index 0000000000000000000000000000000000000000..6ffc797e4d9b08ba4549064dbb10b39ccb2ad38b +GIT binary patch +literal 4 +LcmdN8U|;|M0Mr0E + +literal 0 +HcmV?d00001 + +diff --git a/data/delta/optiplex_3040/home/policy/hci/sysintid2 b/data/delta/optiplex_3040/home/policy/hci/sysintid2 +new file mode 100644 +index 0000000000000000000000000000000000000000..593f4708db84ac8fd0f5cc47c634f38c013fe9e4 +GIT binary patch +literal 4 +LcmZQzU|;|M00aO5 + +literal 0 +HcmV?d00001 + +diff --git a/data/delta/optiplex_3040/home/policy/hci/sysintid3 b/data/delta/optiplex_3040/home/policy/hci/sysintid3 +new file mode 100644 +index 0000000000000000000000000000000000000000..593f4708db84ac8fd0f5cc47c634f38c013fe9e4 +GIT binary patch +literal 4 +LcmZQzU|;|M00aO5 + +literal 0 +HcmV?d00001 + +-- +2.53.0 + diff --git a/config/ifd/3040micro/ifd b/config/ifd/3040micro/ifd Binary files differnew file mode 100644 index 00000000..782c5697 --- /dev/null +++ b/config/ifd/3040micro/ifd diff --git a/config/vendor/3040micro/pkg.cfg b/config/vendor/3040micro/pkg.cfg new file mode 100644 index 00000000..88536e76 --- /dev/null +++ b/config/vendor/3040micro/pkg.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-3.0-or-later + +DL_hash="976bbb1e625f64df276d8343757d910c88b8a781f953bc2c41a7dd15184ec70d55f8081de2a0aaa83cddb8e73bdc2df6288fde6e0897e4928c48ca4bb30bea2d" +DL_url="https://download.asrock.com/BIOS/1151/H110M-DGS(7.30)ROM.zip" +DL_url_bkup="https://web.archive.org/web/20230822134231/https://download.asrock.com/BIOS/1151/H110M-DGS(7.30)ROM.zip" +ME_bin_hash="3231ddb79be81f0a631926fc0e533ee7bce2d10032d7d45e56ae8a9894bcf9b4ca0b4f6fd3bc4daa185a464e771e0bf3d1b771a3180739b6896cec911758145b" + +# for Fsp.fd, we don't rely on a download. Instead, +# we copy from coreboot.git. The file is defined +# by CONFIG_FSP_FD_PATH, split to CONFIG_FSP_M_FILE and CONFIG_FSP_S_FILE +# and inserted to CBFS with names CONFIG_FSP_S_CBFS and CONFIG_FSP_M_CBFS +# +FSPFD_hash="c500166a8553a80ba8db8b8185a896e0ae1562ea3c139e07acd9e7937baf8110ba743cc79b69db09a5f39c076d1d22bc45045223975f46aea2034ba82a6b0360" +FSPM_bin_hash="b15712a53f4d16f36b384beb6dbb716c0b0924751d6ca1e229cd4b8c03aef9eda025c235af247e53dac94d94b79559623974d0d21c7f97e125d8ecc2c86bf03f" +FSPS_bin_hash="64ac9f93e43efddc35931e168d6594c2b39fb5a0da863d22f2d000d7eacc0692b07ce89389cbb1c5b95ff9b2bba508c538e37d0e644fcab7b2cada773da65ce6" + +# We will use deguard to disable the Intel Boot Guard: +ME11bootguard="y" +ME11delta="optiplex_3040" # subdirectory under deguard's data/delta/ +ME11version="11.6.0.1126" +ME11sku="2M" +ME11pch="H" |