diff options
| author | Leah Rowe <leah@libreboot.org> | 2026-09-21 19:14:51 +0100 |
|---|---|---|
| committer | Leah Rowe <leah@libreboot.org> | 2026-09-21 20:22:37 +0100 |
| commit | 365d8b2d6facaec049c0b809dab1f1dcf0e07204 (patch) | |
| tree | 78b43a889a1f4df69d385a7cd994f363581aadd0 | |
| parent | 5fcf132432a13900094659c05b4fac7fd860dbb8 (diff) | |
coreboot: add dell optiplex 5050 sff mainboard
thank you Ron Nazarov for adding this board to coreboot.
thank you Nicholas Chin for assisting Ron with this port.
NOTE:
pcie hotplug disabled on pcie x4 and m2 slot. i added this
patch myself because ron neglected to. it's necessary for
stability in linux when using nvme ssds, otherwise devices
will rename. i don't need to actually confirm whether it
also happens on this board, because turn off hotplug doesn't
really affect the user anyway, so there's no harm turning
this off.
Signed-off-by: Leah Rowe <leah@libreboot.org>
65 files changed, 2826 insertions, 262 deletions
diff --git a/config/ifd/5050sff/gbe b/config/ifd/5050sff/gbe Binary files differnew file mode 100644 index 00000000..86f19e13 --- /dev/null +++ b/config/ifd/5050sff/gbe diff --git a/config/ifd/5050sff/ifd b/config/ifd/5050sff/ifd Binary files differnew file mode 100644 index 00000000..fb996c73 --- /dev/null +++ b/config/ifd/5050sff/ifd diff --git a/config/module/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/module/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch index d2b317d2..6e0d0d74 100644 --- a/config/module/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch +++ b/config/module/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch @@ -1,7 +1,7 @@ -From 73475b7a114430b1e35191113f7116a9d78247c7 Mon Sep 17 00:00:00 2001 +From a4f3d7b48e2f0ca3635fbfe8fc791e763e0f29de Mon Sep 17 00:00:00 2001 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> Date: Wed, 27 Oct 2021 13:36:01 +0200 -Subject: [PATCH 01/50] add c3 and clockgen to apple/macbook21 +Subject: [PATCH 01/56] add c3 and clockgen to apple/macbook21 --- src/mainboard/apple/i945_macs/cstates.c | 13 +++++++++++++ @@ -9,7 +9,7 @@ Subject: [PATCH 01/50] add c3 and clockgen to apple/macbook21 2 files changed, 19 insertions(+) diff --git a/src/mainboard/apple/i945_macs/cstates.c b/src/mainboard/apple/i945_macs/cstates.c -index 13d06f0839b1..88b8669c6181 100644 +index 13d06f0839..88b8669c61 100644 --- a/src/mainboard/apple/i945_macs/cstates.c +++ b/src/mainboard/apple/i945_macs/cstates.c @@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = { @@ -33,7 +33,7 @@ index 13d06f0839b1..88b8669c6181 100644 int get_cst_entries(const acpi_cstate_t **entries) diff --git a/src/mainboard/apple/i945_macs/devicetree.cb b/src/mainboard/apple/i945_macs/devicetree.cb -index e479c63db142..f7b97c516c58 100644 +index e479c63db1..f7b97c516c 100644 --- a/src/mainboard/apple/i945_macs/devicetree.cb +++ b/src/mainboard/apple/i945_macs/devicetree.cb @@ -89,7 +89,13 @@ chip northbridge/intel/i945 diff --git a/config/module/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/module/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch index c008b223..64750430 100644 --- a/config/module/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch +++ b/config/module/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch @@ -1,7 +1,7 @@ -From 0918026cbb81ba75f3ef9c23b1192380f8fe174a Mon Sep 17 00:00:00 2001 +From 1fa144817f28f667290747680f463f7d6d58f961 Mon Sep 17 00:00:00 2001 From: persmule <persmule@gmail.com> Date: Sun, 31 Oct 2021 23:33:26 +0000 -Subject: [PATCH 02/50] lenovo/t400: Enable all SATA ports +Subject: [PATCH 02/56] lenovo/t400: Enable all SATA ports There are 2 SATA ports on the chassis of t400(s), but at least one dock for t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its @@ -15,7 +15,7 @@ This patch unmasked all SATA ports found within t400s with factory firmware. 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb -index 467c09fb9410..7100eee639f3 100644 +index 467c09fb94..7100eee639 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -46,8 +46,8 @@ chip northbridge/intel/gm45 diff --git a/config/module/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/module/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch index 4a14f870..fc6a39aa 100644 --- a/config/module/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch +++ b/config/module/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch @@ -1,7 +1,7 @@ -From 20191528381c1c859471e0f8ad6a2ef72db3427d Mon Sep 17 00:00:00 2001 +From d88b7b987c792ba0c63eae4700ebf022dd12f58c Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 3 Jan 2022 19:06:22 +0000 -Subject: [PATCH 03/50] lenovo/x230: set me_state=Disabled in cmos.default +Subject: [PATCH 03/56] lenovo/x230: set me_state=Disabled in cmos.default I only recently found out about this. It's possible to use me_cleaner to do the same thing, but some people might just flash coreboot and not do @@ -23,7 +23,7 @@ Date: Thu Nov 21 21:47:31 2019 +0300 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default -index 089039caf60f..a7acdebdb014 100644 +index 089039caf6..a7acdebdb0 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -17,5 +17,5 @@ trackpoint=Enable diff --git a/config/module/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/module/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch index 7d022d48..cc1a1d58 100644 --- a/config/module/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch +++ b/config/module/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch @@ -1,7 +1,7 @@ -From fba0dac431484e16f3975844d8266eb6cccc98c3 Mon Sep 17 00:00:00 2001 +From 14e6d93a31b2e95d867ef0e4be0313fd0e55b56b Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Wed, 2 Mar 2022 21:50:01 +0000 -Subject: [PATCH 04/50] set me_state=Disabled on all cmos.default files! +Subject: [PATCH 04/56] set me_state=Disabled on all cmos.default files! yeah. why the hell isn't this the default @@ -19,7 +19,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default -index 0b8ffb94315d..b60703107152 100644 +index 0b8ffb9431..b607031071 100644 --- a/src/mainboard/lenovo/l520/cmos.default +++ b/src/mainboard/lenovo/l520/cmos.default @@ -16,5 +16,5 @@ sticky_fn=Disable @@ -30,7 +30,7 @@ index 0b8ffb94315d..b60703107152 100644 +me_state=Disabled hyper_threading=Enable diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default -index c52ea5e021c6..161a94b17622 100644 +index c52ea5e021..161a94b176 100644 --- a/src/mainboard/lenovo/t420/cmos.default +++ b/src/mainboard/lenovo/t420/cmos.default @@ -16,5 +16,5 @@ sticky_fn=Disable @@ -41,7 +41,7 @@ index c52ea5e021c6..161a94b17622 100644 +me_state=Disabled hyper_threading=Enable diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default -index c52ea5e021c6..161a94b17622 100644 +index c52ea5e021..161a94b176 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -16,5 +16,5 @@ sticky_fn=Disable @@ -52,7 +52,7 @@ index c52ea5e021c6..161a94b17622 100644 +me_state=Disabled hyper_threading=Enable diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default -index c5ee1836b12a..3015f4d4fa11 100644 +index c5ee1836b1..3015f4d4fa 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -18,5 +18,5 @@ backlight=Both @@ -63,7 +63,7 @@ index c5ee1836b12a..3015f4d4fa11 100644 +me_state=Disabled hyper_threading=Enable diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default -index 5891af92877c..d705f3e9e0e9 100644 +index 5891af9287..d705f3e9e0 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -17,5 +17,5 @@ trackpoint=Enable @@ -74,7 +74,7 @@ index 5891af92877c..d705f3e9e0e9 100644 +me_state=Disabled hyper_threading=Enable diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default -index 5891af92877c..d705f3e9e0e9 100644 +index 5891af9287..d705f3e9e0 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -17,5 +17,5 @@ trackpoint=Enable @@ -85,7 +85,7 @@ index 5891af92877c..d705f3e9e0e9 100644 +me_state=Disabled hyper_threading=Enable diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default -index 7b717ace03a9..4d941f0c7efa 100644 +index 7b717ace03..4d941f0c7e 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default @@ -15,5 +15,5 @@ usb_always_on=Disable @@ -96,7 +96,7 @@ index 7b717ace03a9..4d941f0c7efa 100644 +me_state=Disabled hyper_threading=Enable diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default -index d61046df6b0f..8c793fd1c31d 100644 +index d61046df6b..8c793fd1c3 100644 --- a/src/mainboard/protectli/vault_cml/cmos.default +++ b/src/mainboard/protectli/vault_cml/cmos.default @@ -2,4 +2,4 @@ @@ -106,7 +106,7 @@ index d61046df6b0f..8c793fd1c31d 100644 -me_state=Enable +me_state=Disabled diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default -index d61046df6b0f..8c793fd1c31d 100644 +index d61046df6b..8c793fd1c3 100644 --- a/src/mainboard/system76/tgl-u/cmos.default +++ b/src/mainboard/system76/tgl-u/cmos.default @@ -2,4 +2,4 @@ diff --git a/config/module/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/module/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch index f27a4105..e100be7b 100644 --- a/config/module/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ b/config/module/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -1,7 +1,7 @@ -From 276c395993d6c96e78620f1219e644885b8eda8d Mon Sep 17 00:00:00 2001 +From 990701ec0bbce4a5c01a1057b69378b47429567b Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 05/50] util/ifdtool: add --nuke flag (all 0xFF on region) +Subject: [PATCH 05/56] util/ifdtool: add --nuke flag (all 0xFF on region) When this option is used, the region's contents are overwritten with all ones (0xFF). @@ -20,7 +20,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 84 insertions(+), 32 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index a3b66fd4650d..ddc7c1943090 100644 +index a3b66fd465..ddc7c19430 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -2263,6 +2263,7 @@ static void print_usage(const char *name) diff --git a/config/module/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/module/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch index 198ce4e3..445d33bf 100644 --- a/config/module/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch +++ b/config/module/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch @@ -1,7 +1,7 @@ -From a5aa12209c05b8a471189d04d203dd8326eb594b Mon Sep 17 00:00:00 2001 +From fc07dc0a94ff7453508568b0f14c5b9e9edefb7e Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sat, 6 May 2023 15:53:41 -0600 -Subject: [PATCH 06/50] mb/dell/e6400: Enable 01.0 device in devicetree for +Subject: [PATCH 06/56] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU models Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed @@ -11,7 +11,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/dell/gm45_latitude/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb -index dcd208e80d2f..4dd5f3625b1f 100644 +index dcd208e80d..4dd5f3625b 100644 --- a/src/mainboard/dell/gm45_latitude/devicetree.cb +++ b/src/mainboard/dell/gm45_latitude/devicetree.cb @@ -18,7 +18,7 @@ chip northbridge/intel/gm45 diff --git a/config/module/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/module/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch index 636638f3..60865641 100644 --- a/config/module/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/module/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From 9431db28b0631106b8ea1de6fcfe915938ca1724 Mon Sep 17 00:00:00 2001 +From 5407081d9b539aa356ed6730ca5cfe5684af69ee Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 07/50] Remove warning for coreboot images built without a +Subject: [PATCH 07/56] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing @@ -13,7 +13,7 @@ up. This has caused confusion and concern so just patch it out. 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk -index 5f988dac1bbb..516133880f9b 100644 +index 5f988dac1b..516133880f 100644 --- a/payloads/Makefile.mk +++ b/payloads/Makefile.mk @@ -50,16 +50,5 @@ distclean-payloads: diff --git a/config/module/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/module/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch index ece1a524..0d0b3ada 100644 --- a/config/module/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch +++ b/config/module/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch @@ -1,7 +1,7 @@ -From e614d182df3131b72ddf03d0657fff0559fbc2a0 Mon Sep 17 00:00:00 2001 +From d287eb6df021afc78476a9ccbdfcc020cc6ee115 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak <alpernebiyasak@gmail.com> Date: Thu, 22 Jun 2023 16:44:27 +0300 -Subject: [PATCH 08/50] HACK: Disable coreboot related BL31 features +Subject: [PATCH 08/56] HACK: Disable coreboot related BL31 features I don't know why, but removing this BL31 make argument lets gru-kevin power off properly when shut down from Linux. Needs investigation. @@ -10,7 +10,7 @@ power off properly when shut down from Linux. Needs investigation. 1 file changed, 3 deletions(-) diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk -index 7310ce1c1f19..b0a6ed1f847e 100644 +index 7310ce1c1f..b0a6ed1f84 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk @@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40 diff --git a/config/module/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/module/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch index 89795b57..ce0d1a0d 100644 --- a/config/module/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch +++ b/config/module/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch @@ -1,7 +1,7 @@ -From d9b40319d0acfc1b925b3c7116301073c857bdb9 Mon Sep 17 00:00:00 2001 +From 6e81af254fa70cd11c6bffd0343da5eb855954f3 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 5 Nov 2023 11:41:41 +0000 -Subject: [PATCH 09/50] dell/e6430: use ME Soft Temporary Disable +Subject: [PATCH 09/56] dell/e6430: use ME Soft Temporary Disable i overlooked this. it's set on other boards. @@ -16,7 +16,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default -index c883ec40dee8..088da5d84401 100644 +index c883ec40de..088da5d844 100644 --- a/src/mainboard/dell/snb_ivb_latitude/cmos.default +++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default @@ -6,5 +6,5 @@ bluetooth=Enable diff --git a/config/module/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/module/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch index d9c3c473..2e40c41b 100644 --- a/config/module/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch +++ b/config/module/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch @@ -1,7 +1,7 @@ -From 682c2cb444b0d12cf15b5a82fa733be1b4aa9db0 Mon Sep 17 00:00:00 2001 +From 3fd2da0978e53ce6801cc3520788d5dcd52b6b0a Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 23 Dec 2023 19:02:10 +0200 -Subject: [PATCH 10/50] mb/hp: Add Compaq Elite 8300 CMT port +Subject: [PATCH 10/56] mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. @@ -70,7 +70,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig new file mode 100644 -index 000000000000..d2bfd35dc48e +index 0000000000..d2bfd35dc4 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig @@ -0,0 +1,39 @@ @@ -115,7 +115,7 @@ index 000000000000..d2bfd35dc48e +endif diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name new file mode 100644 -index 000000000000..bd399b1e7695 +index 0000000000..bd399b1e76 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name @@ -0,0 +1,2 @@ @@ -123,7 +123,7 @@ index 000000000000..bd399b1e7695 + bool "Compaq Elite 8300 CMT" diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk new file mode 100644 -index 000000000000..fb492d358372 +index 0000000000..fb492d3583 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk @@ -0,0 +1,7 @@ @@ -136,14 +136,14 @@ index 000000000000..fb492d358372 +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl new file mode 100644 -index 000000000000..73fa78ef14ea +index 0000000000..73fa78ef14 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl new file mode 100644 -index 000000000000..aff432b6f47a +index 0000000000..aff432b6f4 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl @@ -0,0 +1,10 @@ @@ -159,7 +159,7 @@ index 000000000000..aff432b6f47a +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl new file mode 100644 -index 000000000000..54f8e3fe9585 +index 0000000000..54f8e3fe95 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl @@ -0,0 +1,29 @@ @@ -194,7 +194,7 @@ index 000000000000..54f8e3fe9585 +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c new file mode 100644 -index 000000000000..8f4f83b826ee +index 0000000000..8f4f83b826 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c @@ -0,0 +1,12 @@ @@ -212,7 +212,7 @@ index 000000000000..8f4f83b826ee +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt new file mode 100644 -index 000000000000..16c29e82d837 +index 0000000000..16c29e82d8 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt @@ -0,0 +1,5 @@ @@ -223,7 +223,7 @@ index 000000000000..16c29e82d837 +Release year: 2012 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default new file mode 100644 -index 000000000000..6d27a79c66b4 +index 0000000000..6d27a79c66 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default @@ -0,0 +1,7 @@ @@ -236,7 +236,7 @@ index 000000000000..6d27a79c66b4 +psu_fan_lvl=3 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout new file mode 100644 -index 000000000000..1fc83b1a55e3 +index 0000000000..1fc83b1a55 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout @@ -0,0 +1,74 @@ @@ -353,7 +353,7 @@ HcmV?d00001 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb new file mode 100644 -index 000000000000..3d21739b7275 +index 0000000000..3d21739b72 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb @@ -0,0 +1,177 @@ @@ -536,7 +536,7 @@ index 000000000000..3d21739b7275 +end diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl new file mode 100644 -index 000000000000..e8e2b3a3e560 +index 0000000000..e8e2b3a3e5 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl @@ -0,0 +1,26 @@ @@ -568,7 +568,7 @@ index 000000000000..e8e2b3a3e560 +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c new file mode 100644 -index 000000000000..8d10c6317ca0 +index 0000000000..8d10c6317c --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c @@ -0,0 +1,14 @@ @@ -588,7 +588,7 @@ index 000000000000..8d10c6317ca0 +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads new file mode 100644 -index 000000000000..686f7d44db26 +index 0000000000..686f7d44db --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads @@ -0,0 +1,17 @@ @@ -611,7 +611,7 @@ index 000000000000..686f7d44db26 +end GMA.Mainboard; diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c new file mode 100644 -index 000000000000..2ae852ae5126 +index 0000000000..2ae852ae51 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c @@ -0,0 +1,191 @@ @@ -808,7 +808,7 @@ index 000000000000..2ae852ae5126 +}; diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c new file mode 100644 -index 000000000000..a1eafcda68ae +index 0000000000..a1eafcda68 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c @@ -0,0 +1,33 @@ @@ -847,7 +847,7 @@ index 000000000000..a1eafcda68ae +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c new file mode 100644 -index 000000000000..8dbd95ef961d +index 0000000000..8dbd95ef96 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c @@ -0,0 +1,16 @@ diff --git a/config/module/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/module/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch index c91adfc8..9df1f29e 100644 --- a/config/module/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ b/config/module/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -1,7 +1,7 @@ -From 60bc2adc88482d3e76cd7642e81653e4e61e12e8 Mon Sep 17 00:00:00 2001 +From 9fb0290711e7ece4a1d12b4297c8886980c8ccdf Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 11/50] nb/intel/haswell: make IOMMU a runtime option +Subject: [PATCH 11/56] nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless @@ -38,7 +38,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 14 files changed, 49 insertions(+) diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default -index 01bf20ad169c..dfc8b80fb0d1 100644 +index 01bf20ad16..dfc8b80fb0 100644 --- a/src/mainboard/asrock/b85m_pro4/cmos.default +++ b/src/mainboard/asrock/b85m_pro4/cmos.default @@ -4,3 +4,4 @@ boot_option=Fallback @@ -47,7 +47,7 @@ index 01bf20ad169c..dfc8b80fb0d1 100644 power_on_after_fail=Disable +iommu=Enable diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout -index efdc333fc26b..c9883ea71def 100644 +index efdc333fc2..c9883ea71d 100644 --- a/src/mainboard/asrock/b85m_pro4/cmos.layout +++ b/src/mainboard/asrock/b85m_pro4/cmos.layout @@ -11,6 +11,7 @@ @@ -68,7 +68,7 @@ index efdc333fc26b..c9883ea71def 100644 # ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default -index 01bf20ad169c..dfc8b80fb0d1 100644 +index 01bf20ad16..dfc8b80fb0 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.default +++ b/src/mainboard/asrock/h81m-hds/cmos.default @@ -4,3 +4,4 @@ boot_option=Fallback @@ -77,7 +77,7 @@ index 01bf20ad169c..dfc8b80fb0d1 100644 power_on_after_fail=Disable +iommu=Enable diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout -index c9ba76c78fe8..95ee3d36fb61 100644 +index c9ba76c78f..95ee3d36fb 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.layout +++ b/src/mainboard/asrock/h81m-hds/cmos.layout @@ -21,6 +21,9 @@ entries @@ -101,7 +101,7 @@ index c9ba76c78fe8..95ee3d36fb61 100644 checksums diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -index 6c4a2a1be762..8000eea8c01d 100644 +index 6c4a2a1be7..8000eea8c0 100644 --- a/src/mainboard/dell/optiplex_9020/cmos.default +++ b/src/mainboard/dell/optiplex_9020/cmos.default @@ -4,3 +4,4 @@ debug_level=Debug @@ -110,7 +110,7 @@ index 6c4a2a1be762..8000eea8c01d 100644 fan_full_speed=Disable +iommu=Enable diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout -index d10ad95b23ae..4a1496a8781b 100644 +index d10ad95b23..4a1496a878 100644 --- a/src/mainboard/dell/optiplex_9020/cmos.layout +++ b/src/mainboard/dell/optiplex_9020/cmos.layout @@ -21,6 +21,9 @@ entries @@ -134,7 +134,7 @@ index d10ad95b23ae..4a1496a8781b 100644 checksums diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout -index 78d44c14154f..c143979ae1ab 100644 +index 78d44c1415..c143979ae1 100644 --- a/src/mainboard/google/beltino/cmos.layout +++ b/src/mainboard/google/beltino/cmos.layout @@ -19,6 +19,9 @@ entries @@ -157,7 +157,7 @@ index 78d44c14154f..c143979ae1ab 100644 checksums diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout -index 78d44c14154f..c143979ae1ab 100644 +index 78d44c1415..c143979ae1 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -19,6 +19,9 @@ entries @@ -180,7 +180,7 @@ index 78d44c14154f..c143979ae1ab 100644 checksums diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout -index 78d44c14154f..f2c602f541c1 100644 +index 78d44c1415..f2c602f541 100644 --- a/src/mainboard/intel/baskingridge/cmos.layout +++ b/src/mainboard/intel/baskingridge/cmos.layout @@ -19,6 +19,8 @@ entries @@ -202,7 +202,7 @@ index 78d44c14154f..f2c602f541c1 100644 checksums diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default -index e1044343a9ef..13ee202983f5 100644 +index e1044343a9..13ee202983 100644 --- a/src/mainboard/lenovo/haswell/cmos.default +++ b/src/mainboard/lenovo/haswell/cmos.default @@ -13,3 +13,4 @@ trackpoint=Enable @@ -211,7 +211,7 @@ index e1044343a9ef..13ee202983f5 100644 usb_always_on=Disable +iommu=Enable diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout -index 5fb6972a92fc..a866b47f084f 100644 +index 5fb6972a92..a866b47f08 100644 --- a/src/mainboard/lenovo/haswell/cmos.layout +++ b/src/mainboard/lenovo/haswell/cmos.layout @@ -22,6 +22,7 @@ entries @@ -232,7 +232,7 @@ index 5fb6972a92fc..a866b47f084f 100644 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default -index 7ce38fb5d768..6049e7938aca 100644 +index 7ce38fb5d7..6049e7938a 100644 --- a/src/mainboard/supermicro/x10slm-f/cmos.default +++ b/src/mainboard/supermicro/x10slm-f/cmos.default @@ -5,3 +5,4 @@ debug_level=Debug @@ -241,7 +241,7 @@ index 7ce38fb5d768..6049e7938aca 100644 hide_ast2400=Disable +iommu=Enable diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout -index 38ba87aa452f..24d39e97ee87 100644 +index 38ba87aa45..24d39e97ee 100644 --- a/src/mainboard/supermicro/x10slm-f/cmos.layout +++ b/src/mainboard/supermicro/x10slm-f/cmos.layout @@ -21,6 +21,9 @@ entries @@ -265,7 +265,7 @@ index 38ba87aa452f..24d39e97ee87 100644 checksums diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c -index 6a5ce53a407d..5f07fa0b1731 100644 +index 6a5ce53a40..5f07fa0b17 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -6,6 +6,7 @@ diff --git a/config/module/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/module/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch index 47a5ece6..bae908c6 100644 --- a/config/module/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ b/config/module/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -1,7 +1,7 @@ -From 0d367d806a0acdcfa7a08e5b52e081adba33b2da Mon Sep 17 00:00:00 2001 +From 65517ed6a68335f0a4cd20cca52f4c190c0f8d83 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 12/50] dell/optiplex_9020: Disable IOMMU by default +Subject: [PATCH 12/56] dell/optiplex_9020: Disable IOMMU by default Needed to make graphics cards work. Turning it on is recommended if only using iGPU, otherwise leave it off @@ -15,7 +15,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -index 8000eea8c01d..0700f971ee47 100644 +index 8000eea8c0..0700f971ee 100644 --- a/src/mainboard/dell/optiplex_9020/cmos.default +++ b/src/mainboard/dell/optiplex_9020/cmos.default @@ -4,4 +4,4 @@ debug_level=Debug diff --git a/config/module/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/module/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch index 3a1da3f3..d99763d0 100644 --- a/config/module/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ b/config/module/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -1,7 +1,7 @@ -From 2da18395d54bb22452078c0a808e73cba4bef48e Mon Sep 17 00:00:00 2001 +From 688dcbc22e89ab83c7d1ea55273728e837964642 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 13/50] nb/haswell: Fully disable iGPU when dGPU is used +Subject: [PATCH 13/56] nb/haswell: Fully disable iGPU when dGPU is used My earlier patch disabled decode *and* disabled the iGPU itself, but a subsequent revision disabled only VGA decode. Upon revisiting, I @@ -33,7 +33,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 3 insertions(+) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c -index fc44a98a57e9..451147d08256 100644 +index fc44a98a57..451147d082 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -655,6 +655,9 @@ static void gma_func0_disable(struct device *dev) diff --git a/config/module/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/module/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch index f06695b5..cc527b9b 100644 --- a/config/module/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch +++ b/config/module/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -1,7 +1,7 @@ -From 9147383e561bfa65dbb5b0de31d00b4b4c68118d Mon Sep 17 00:00:00 2001 +From 8112eb9d74628c12daa136f1b7d91f51eacc08a5 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 11:03:32 -0600 -Subject: [PATCH 14/50] ec/dell/mec5035: Add S3 suspend SMI handler +Subject: [PATCH 14/56] ec/dell/mec5035: Add S3 suspend SMI handler This is necessary for S3 resume to work on SNB and newer Dell Latitude laptops. If a command isn't sent, the EC cuts power to the DIMMs, @@ -35,7 +35,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> create mode 100644 src/ec/dell/mec5035/smihandler.c diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk -index 4ebdd811f9a7..be557e4599ac 100644 +index 4ebdd811f9..be557e4599 100644 --- a/src/ec/dell/mec5035/Makefile.mk +++ b/src/ec/dell/mec5035/Makefile.mk @@ -5,5 +5,6 @@ ifeq ($(CONFIG_EC_DELL_MEC5035),y) @@ -46,7 +46,7 @@ index 4ebdd811f9a7..be557e4599ac 100644 endif diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index 17ac2c1dab1f..c5067c16f65d 100644 +index 17ac2c1dab..c5067c16f6 100644 --- a/src/ec/dell/mec5035/mec5035.c +++ b/src/ec/dell/mec5035/mec5035.c @@ -100,6 +100,19 @@ static void mec5035_power_button_route(enum ec_power_button_route target) @@ -70,7 +70,7 @@ index 17ac2c1dab1f..c5067c16f65d 100644 void mec5035_early_init(void) { diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 5fdf56631b14..5cd907bf71d5 100644 +index 5fdf56631b..5cd907bf71 100644 --- a/src/ec/dell/mec5035/mec5035.h +++ b/src/ec/dell/mec5035/mec5035.h @@ -4,6 +4,7 @@ @@ -121,7 +121,7 @@ index 5fdf56631b14..5cd907bf71d5 100644 #endif /* _EC_DELL_MEC5035_H_ */ diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c new file mode 100644 -index 000000000000..958733bf9758 +index 0000000000..958733bf97 --- /dev/null +++ b/src/ec/dell/mec5035/smihandler.c @@ -0,0 +1,17 @@ diff --git a/config/module/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/module/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch index b3d659b5..a8641cce 100644 --- a/config/module/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ b/config/module/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -1,7 +1,7 @@ -From ff87dbf28f565a6d227e98d2c71e99e47a34f261 Mon Sep 17 00:00:00 2001 +From 06a4925ea4ecb9015b1bd4007d305e26d0f61fbd Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 15/50] nb/haswell: lock policy regs when disabling IOMMU +Subject: [PATCH 15/56] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 @@ -22,7 +22,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c -index 5f07fa0b1731..e0007f72eea2 100644 +index 5f07fa0b17..e0007f72ee 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -83,17 +83,16 @@ static void northbridge_setup_iommu(void) diff --git a/config/module/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/module/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch index b5b534f5..f77d401b 100644 --- a/config/module/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch +++ b/config/module/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -1,7 +1,7 @@ -From ec6b4c8487026d393115e93a36939d14c0a9783b Mon Sep 17 00:00:00 2001 +From f9153059f6f23beaefa8af7eded6ad2614da01f6 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Mon, 10 May 2021 22:40:59 +0200 -Subject: [PATCH 16/50] nb/intel/gm45: Make DDR2 raminit work +Subject: [PATCH 16/56] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values @@ -20,7 +20,7 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> 3 files changed, 106 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h -index 90ab57052446..d537ef82afae 100644 +index 90ab570524..d537ef82af 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo); @@ -33,7 +33,7 @@ index 90ab57052446..d537ef82afae 100644 void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index def9e1e331e6..7b091cc5673f 100644 +index def9e1e331..7b091cc567 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping, @@ -156,7 +156,7 @@ index def9e1e331e6..7b091cc5673f 100644 /* Program final memory map (with real values). */ diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -index aef863f05a50..b74765fd9c33 100644 +index aef863f05a..b74765fd9c 100644 --- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c @@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step, diff --git a/config/module/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/module/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch index fdbb05d2..64be2c33 100644 --- a/config/module/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch +++ b/config/module/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch @@ -1,7 +1,7 @@ -From a9253c251232469644efe2794ec599de8bbbed9c Mon Sep 17 00:00:00 2001 +From 8206e34eb1e3f4270a81d642f317471c11c5886a Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 6 Aug 2024 00:50:24 +0100 -Subject: [PATCH 17/50] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards +Subject: [PATCH 17/56] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards We add this patch: @@ -32,7 +32,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 2 files changed, 88 insertions(+), 82 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c -index 7b091cc5673f..478898564a70 100644 +index 7b091cc567..478898564a 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi @@ -211,7 +211,7 @@ index 7b091cc5673f..478898564a70 100644 igd_compute_ggc(sysinfo); diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c -index b74765fd9c33..5d4505e0631f 100644 +index b74765fd9c..5d4505e063 100644 --- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c @@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { diff --git a/config/module/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/module/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch index dca26634..991fcc79 100644 --- a/config/module/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch +++ b/config/module/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch @@ -1,7 +1,7 @@ -From 0f98673d9063a74b7676fbe542cf777f274d32a0 Mon Sep 17 00:00:00 2001 +From 122c32bac999cb9f1d1902f8e8505de19b9c289b Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 20 May 2024 10:24:16 -0600 -Subject: [PATCH 18/50] mb/dell/e6400: Use 100 MHz reference clock for display +Subject: [PATCH 18/56] mb/dell/e6400: Use 100 MHz reference clock for display The E6400 uses a 100 MHz reference clock for spread spectrum support on LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For @@ -19,7 +19,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> 2 files changed, 6 insertions(+) diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index edc79b0d4322..502074499067 100644 +index edc79b0d43..5020744990 100644 --- a/src/mainboard/dell/gm45_latitude/Kconfig +++ b/src/mainboard/dell/gm45_latitude/Kconfig @@ -22,6 +22,8 @@ config BOARD_DELL_E6400 @@ -32,7 +32,7 @@ index edc79b0d4322..502074499067 100644 config MAINBOARD_DIR default "dell/gm45_latitude" diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index a776217475b9..35e89b0c889c 100644 +index a776217475..35e89b0c88 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45 diff --git a/config/module/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/module/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch index 457dcda5..a461d2a1 100644 --- a/config/module/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch +++ b/config/module/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch @@ -1,7 +1,7 @@ -From ba45e131dd80fd654dbce9784dcddfb7dde93f46 Mon Sep 17 00:00:00 2001 +From 527149c7ae247791e8e50c8e09d39f136a2510ec Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Mon, 12 Aug 2024 02:15:24 +0100 -Subject: [PATCH 19/50] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ +Subject: [PATCH 19/56] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ set it to 96MHz. fixes the following build error when building for x4x boards e.g. gigabyte ga-g41m-es2l: @@ -33,7 +33,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 4 insertions(+) diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 6fa455195753..646af3510b60 100644 +index 6fa4551957..646af3510b 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X diff --git a/config/module/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/module/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch index 485cc0f3..afb0d37c 100644 --- a/config/module/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch +++ b/config/module/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch @@ -1,7 +1,7 @@ -From 96ab76bbfff01f8140c2f4be223feb7b528a750e Mon Sep 17 00:00:00 2001 +From b6f82ec86cd3cc34264f999d6a9a5c30a72cea60 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Thu, 26 Sep 2024 19:51:25 -0600 -Subject: [PATCH 20/50] mb/dell/gm45_latitudes: Add E4300 variant +Subject: [PATCH 20/56] mb/dell/gm45_latitudes: Add E4300 variant Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> @@ -21,7 +21,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig -index 502074499067..d27d5728a82d 100644 +index 5020744990..d27d5728a8 100644 --- a/src/mainboard/dell/gm45_latitude/Kconfig +++ b/src/mainboard/dell/gm45_latitude/Kconfig @@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON @@ -50,7 +50,7 @@ index 502074499067..d27d5728a82d 100644 config USBDEBUG_HCD_INDEX default 1 diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name -index aefe777109b7..4dc95f46becc 100644 +index aefe777109..4dc95f46be 100644 --- a/src/mainboard/dell/gm45_latitude/Kconfig.name +++ b/src/mainboard/dell/gm45_latitude/Kconfig.name @@ -1,4 +1,7 @@ @@ -103,7 +103,7 @@ HcmV?d00001 diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads new file mode 100644 -index 000000000000..89b81b3d690e +index 0000000000..89b81b3d69 --- /dev/null +++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads @@ -0,0 +1,17 @@ @@ -126,7 +126,7 @@ index 000000000000..89b81b3d690e +end GMA.Mainboard; diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c new file mode 100644 -index 000000000000..b50f8da0b5b0 +index 0000000000..b50f8da0b5 --- /dev/null +++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c @@ -0,0 +1,138 @@ @@ -270,7 +270,7 @@ index 000000000000..b50f8da0b5b0 +}; diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c new file mode 100644 -index 000000000000..a9948a93dd81 +index 0000000000..a9948a93dd --- /dev/null +++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c @@ -0,0 +1,37 @@ @@ -313,7 +313,7 @@ index 000000000000..a9948a93dd81 +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb new file mode 100644 -index 000000000000..20dfa245fbdd +index 0000000000..20dfa245fb --- /dev/null +++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb @@ -0,0 +1,10 @@ diff --git a/config/module/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/module/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch index 358a7d65..ddcfc998 100644 --- a/config/module/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch +++ b/config/module/coreboot/default/patches/0021-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch @@ -1,7 +1,7 @@ -From 0d50772e7dc3423372300d337d9f7fa209ca2299 Mon Sep 17 00:00:00 2001 +From 95028f8238873d05e5e3feb35e4faf5873e15c84 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Fri, 3 May 2024 16:31:12 -0600 -Subject: [PATCH 21/50] mb/dell: Add S3 SMI handler for Dell Latitudes +Subject: [PATCH 21/56] mb/dell: Add S3 SMI handler for Dell Latitudes Integrate the previously added mec5035_smi_sleep() function into mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240. @@ -22,7 +22,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c new file mode 100644 -index 000000000000..00e55b51db04 +index 0000000000..00e55b51db --- /dev/null +++ b/src/mainboard/dell/gm45_latitude/smihandler.c @@ -0,0 +1,9 @@ @@ -37,7 +37,7 @@ index 000000000000..00e55b51db04 +} diff --git a/src/mainboard/dell/haswell_latitude/smihandler.c b/src/mainboard/dell/haswell_latitude/smihandler.c new file mode 100644 -index 000000000000..00e55b51db04 +index 0000000000..00e55b51db --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/smihandler.c @@ -0,0 +1,9 @@ @@ -52,7 +52,7 @@ index 000000000000..00e55b51db04 +} diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c new file mode 100644 -index 000000000000..00e55b51db04 +index 0000000000..00e55b51db --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c @@ -0,0 +1,9 @@ diff --git a/config/module/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch b/config/module/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch index 4b81cb57..4f823461 100644 --- a/config/module/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch +++ b/config/module/coreboot/default/patches/0022-Disable-compression-on-refcode-insertion.patch @@ -1,7 +1,7 @@ -From c54181a491e1f90649cfae2dff2adcc81e5c31ea Mon Sep 17 00:00:00 2001 +From f8473af3c923cd7cdc0f1d5d359dc0d52882e990 Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Tue, 31 Dec 2024 14:42:24 +0000 -Subject: [PATCH 22/50] Disable compression on refcode insertion +Subject: [PATCH 22/56] Disable compression on refcode insertion Compression is not reliably reproducible. In an lbmk release context, this means we cannot rely on vendorfile insertion. @@ -14,7 +14,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.mk b/Makefile.mk -index 7a208d041df4..688ba99c14ad 100644 +index 7a208d041d..688ba99c14 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -1457,7 +1457,7 @@ endif diff --git a/config/module/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch b/config/module/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch index 40704eeb..119a4d08 100644 --- a/config/module/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch +++ b/config/module/coreboot/default/patches/0023-nb-intel-Disable-stack-overflow-debug-options.patch @@ -1,7 +1,7 @@ -From 3d5ea8f81e3b65170a95dc5b8f0d1ad39d6b2ba2 Mon Sep 17 00:00:00 2001 +From 90eb04245922aaf89f2fb8ddf579124a7978282a Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 02:58:47 +0100 -Subject: [PATCH 23/50] nb/intel/*: Disable stack overflow debug options +Subject: [PATCH 23/56] nb/intel/*: Disable stack overflow debug options Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -17,7 +17,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 9 files changed, 85 insertions(+) diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig -index 039a7396f8cc..ddcb986f1007 100644 +index 039a7396f8..ddcb986f10 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505 @@ -34,7 +34,7 @@ index 039a7396f8cc..ddcb986f1007 100644 + bool + default n diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig -index 35e89b0c889c..c5456d0ddf02 100644 +index 35e89b0c88..c5456d0ddf 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE @@ -52,7 +52,7 @@ index 35e89b0c889c..c5456d0ddf02 100644 + endif diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig -index 6015c31702cb..d2ade2912f1c 100644 +index 6015c31702..d2ade2912f 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -9,6 +9,15 @@ config NORTHBRIDGE_INTEL_HASWELL @@ -72,7 +72,7 @@ index 6015c31702cb..d2ade2912f1c 100644 bool "[NOT COMPLETE] Use native raminit" default n diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig -index dbb2d7436b3e..5e9418b6a94a 100644 +index dbb2d7436b..5e9418b6a9 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM @@ -93,7 +93,7 @@ index dbb2d7436b3e..5e9418b6a94a 100644 + +endif diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig -index 5668fed4a8bc..a259d8e26b80 100644 +index 5668fed4a8..a259d8e26b 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -80,4 +80,13 @@ config FIXED_DMIBAR_MMIO_BASE @@ -111,7 +111,7 @@ index 5668fed4a8bc..a259d8e26b80 100644 + endif diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig -index 39566a6e5f13..f46acf693754 100644 +index 39566a6e5f..f46acf6937 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE @@ -129,7 +129,7 @@ index 39566a6e5f13..f46acf693754 100644 + endif diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig -index 341f29534da3..0f825781f990 100644 +index 341f29534d..0f825781f9 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE @@ -147,7 +147,7 @@ index 341f29534da3..0f825781f990 100644 + endif diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig -index 9972a43da0ba..fe4ac5106c6c 100644 +index 9972a43da0..fe4ac5106c 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX @@ -165,7 +165,7 @@ index 9972a43da0ba..fe4ac5106c6c 100644 + endif diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 646af3510b60..069fa0244df7 100644 +index 646af3510b..069fa0244d 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE diff --git a/config/module/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/module/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch index b42c5ecd..60309c79 100644 --- a/config/module/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ b/config/module/coreboot/default/patches/0024-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -1,7 +1,7 @@ -From 2ef5db0e6146613519ddd53fc326a2b73432a90c Mon Sep 17 00:00:00 2001 +From 07fd30a72490b28a591714ffa092ef763e813b7c Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 24/50] mb/dell: Add Optiplex 780 MT (x4x/ICH10) +Subject: [PATCH 24/56] mb/dell: Add Optiplex 780 MT (x4x/ICH10) Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> @@ -46,7 +46,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig new file mode 100644 -index 000000000000..2d06c75c9a52 +index 0000000000..2d06c75c9a --- /dev/null +++ b/src/mainboard/dell/optiplex_780/Kconfig @@ -0,0 +1,40 @@ @@ -92,7 +92,7 @@ index 000000000000..2d06c75c9a52 +endif # BOARD_DELL_OPTIPLEX_780_COMMON diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name new file mode 100644 -index 000000000000..db7f2e8fe3a0 +index 0000000000..db7f2e8fe3 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/Kconfig.name @@ -0,0 +1,4 @@ @@ -102,7 +102,7 @@ index 000000000000..db7f2e8fe3a0 + bool "OptiPlex 780 MT" diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk new file mode 100644 -index 000000000000..d462995d75f5 +index 0000000000..d462995d75 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/Makefile.mk @@ -0,0 +1,10 @@ @@ -118,7 +118,7 @@ index 000000000000..d462995d75f5 +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl new file mode 100644 -index 000000000000..479296cb76fc +index 0000000000..479296cb76 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl @@ -0,0 +1,5 @@ @@ -129,7 +129,7 @@ index 000000000000..479296cb76fc +/* dummy */ diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl new file mode 100644 -index 000000000000..b7588dcc41cb +index 0000000000..b7588dcc41 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl @@ -0,0 +1,32 @@ @@ -167,7 +167,7 @@ index 000000000000..b7588dcc41cb +} diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl new file mode 100644 -index 000000000000..9f3900b86cd8 +index 0000000000..9f3900b86c --- /dev/null +++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl @@ -0,0 +1,18 @@ @@ -191,7 +191,7 @@ index 000000000000..9f3900b86cd8 +#include <superio/ite/it8720f/acpi/superio.asl> diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt new file mode 100644 -index 000000000000..aaf657b583ae +index 0000000000..aaf657b583 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/board_info.txt @@ -0,0 +1,6 @@ @@ -203,7 +203,7 @@ index 000000000000..aaf657b583ae +Flashrom support: y diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default new file mode 100644 -index 000000000000..23f0e55f3e2c +index 0000000000..23f0e55f3e --- /dev/null +++ b/src/mainboard/dell/optiplex_780/cmos.default @@ -0,0 +1,8 @@ @@ -217,7 +217,7 @@ index 000000000000..23f0e55f3e2c +gfx_uma_size=64M diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout new file mode 100644 -index 000000000000..9f5012adb4fb +index 0000000000..9f5012adb4 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/cmos.layout @@ -0,0 +1,72 @@ @@ -295,7 +295,7 @@ index 000000000000..9f5012adb4fb +checksum 392 983 984 diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c new file mode 100644 -index 000000000000..4adf0edc6377 +index 0000000000..4adf0edc63 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/cstates.c @@ -0,0 +1,8 @@ @@ -309,7 +309,7 @@ index 000000000000..4adf0edc6377 +} diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb new file mode 100644 -index 000000000000..95e3bd517c68 +index 0000000000..95e3bd517c --- /dev/null +++ b/src/mainboard/dell/optiplex_780/devicetree.cb @@ -0,0 +1,63 @@ @@ -378,7 +378,7 @@ index 000000000000..95e3bd517c68 +end diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl new file mode 100644 -index 000000000000..9ad70469def3 +index 0000000000..9ad70469de --- /dev/null +++ b/src/mainboard/dell/optiplex_780/dsdt.asl @@ -0,0 +1,26 @@ @@ -410,7 +410,7 @@ index 000000000000..9ad70469def3 +} diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads new file mode 100644 -index 000000000000..bc81cf4a40df +index 0000000000..bc81cf4a40 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads @@ -0,0 +1,16 @@ @@ -459,7 +459,7 @@ HcmV?d00001 diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c new file mode 100644 -index 000000000000..e2fa05cd8f6a +index 0000000000..e2fa05cd8f --- /dev/null +++ b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c @@ -0,0 +1,12 @@ @@ -477,7 +477,7 @@ index 000000000000..e2fa05cd8f6a +} diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c new file mode 100644 -index 000000000000..9993f17c55d8 +index 0000000000..9993f17c55 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c @@ -0,0 +1,174 @@ @@ -657,7 +657,7 @@ index 000000000000..9993f17c55d8 +}; diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c new file mode 100644 -index 000000000000..4158bcf89950 +index 0000000000..4158bcf899 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c @@ -0,0 +1,26 @@ @@ -689,7 +689,7 @@ index 000000000000..4158bcf89950 +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb new file mode 100644 -index 000000000000..555b1c1f5c8a +index 0000000000..555b1c1f5c --- /dev/null +++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb @@ -0,0 +1,10 @@ diff --git a/config/module/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/module/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch index 41edac3f..68d01ee0 100644 --- a/config/module/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch +++ b/config/module/coreboot/default/patches/0025-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -1,7 +1,7 @@ -From 6df7d79ac7496d1074f0a953008ba2ca96bc59d5 Mon Sep 17 00:00:00 2001 +From bbab84fdcd02f2dac8b9c8a731f8ae9615074b0f Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 25/50] mb/dell/optiplex_780: Add USFF variant +Subject: [PATCH 25/56] mb/dell/optiplex_780: Add USFF variant Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> @@ -21,7 +21,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -index 2d06c75c9a52..fc649e35d5e7 100644 +index 2d06c75c9a..fc649e35d5 100644 --- a/src/mainboard/dell/optiplex_780/Kconfig +++ b/src/mainboard/dell/optiplex_780/Kconfig @@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON @@ -49,7 +49,7 @@ index 2d06c75c9a52..fc649e35d5e7 100644 endif # BOARD_DELL_OPTIPLEX_780_COMMON diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name -index db7f2e8fe3a0..bc84c82a7918 100644 +index db7f2e8fe3..bc84c82a79 100644 --- a/src/mainboard/dell/optiplex_780/Kconfig.name +++ b/src/mainboard/dell/optiplex_780/Kconfig.name @@ -2,3 +2,6 @@ @@ -88,7 +88,7 @@ HcmV?d00001 diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c new file mode 100644 -index 000000000000..2a55fc3a6e42 +index 0000000000..2a55fc3a6e --- /dev/null +++ b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c @@ -0,0 +1,9 @@ @@ -103,7 +103,7 @@ index 000000000000..2a55fc3a6e42 +} diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c new file mode 100644 -index 000000000000..389f4077d7b0 +index 0000000000..389f4077d7 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c @@ -0,0 +1,166 @@ @@ -275,7 +275,7 @@ index 000000000000..389f4077d7b0 +}; diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c new file mode 100644 -index 000000000000..c94e06b1569b +index 0000000000..c94e06b156 --- /dev/null +++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c @@ -0,0 +1,26 @@ @@ -307,7 +307,7 @@ index 000000000000..c94e06b1569b +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb new file mode 100644 -index 000000000000..555b1c1f5c8a +index 0000000000..555b1c1f5c --- /dev/null +++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb @@ -0,0 +1,10 @@ diff --git a/config/module/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch b/config/module/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch index 8032f157..bd4c0937 100644 --- a/config/module/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch +++ b/config/module/coreboot/default/patches/0026-src-intel-x4x-Disable-stack-overflow-debug.patch @@ -1,7 +1,7 @@ -From 064b3a3cd605ce33143967fca7f39a64eb0f3151 Mon Sep 17 00:00:00 2001 +From e539f904da3abb66255a112e9441c5f6611b26e8 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:53:53 +0000 -Subject: [PATCH 26/50] src/intel/x4x: Disable stack overflow debug +Subject: [PATCH 26/56] src/intel/x4x: Disable stack overflow debug Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,7 +9,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig -index 069fa0244df7..8c7034484644 100644 +index 069fa0244d..8c70344846 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER diff --git a/config/module/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch b/config/module/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch index 1cb5386c..bd6f3a64 100644 --- a/config/module/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch +++ b/config/module/coreboot/default/patches/0027-hp-8300cmt-remove-xhci_overcurrent_mapping.patch @@ -1,7 +1,7 @@ -From 652d51e6c125d6bc6d56f60da7ace1558be14493 Mon Sep 17 00:00:00 2001 +From 4007d60d44e646bd5081827b4679c0ddf4bb99ca Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 22 Apr 2025 10:21:59 +0100 -Subject: [PATCH 27/50] hp/8300cmt: remove xhci_overcurrent_mapping +Subject: [PATCH 27/56] hp/8300cmt: remove xhci_overcurrent_mapping No longer needed, as per the following commit: @@ -26,7 +26,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 deletion(-) diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb -index 3d21739b7275..3a0b6d5c59e2 100644 +index 3d21739b72..3a0b6d5c59 100644 --- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb +++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb @@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge diff --git a/config/module/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch b/config/module/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch index a5a62996..9b8b3822 100644 --- a/config/module/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch +++ b/config/module/coreboot/default/patches/0028-dell-3050micro-disable-nvme-hotplug.patch @@ -1,7 +1,7 @@ -From c6915f8753e297fc8cced223e128353796230627 Mon Sep 17 00:00:00 2001 +From 3ef3cc9f7089e85571480a6b7b171a7fa66cb33e Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 11 Dec 2024 01:06:01 +0000 -Subject: [PATCH 28/50] dell/3050micro: disable nvme hotplug +Subject: [PATCH 28/56] dell/3050micro: disable nvme hotplug in my testing, when running my 3050micro for a few days, the nvme would sometimes randomly rename. @@ -30,7 +30,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb -index c5f1749b2c61..ff48a8121ad5 100644 +index c5f1749b2c..ff48a8121a 100644 --- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb +++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb @@ -46,7 +46,7 @@ chip soc/intel/skylake diff --git a/config/module/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch b/config/module/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch index 50cdd870..15c866d1 100644 --- a/config/module/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch +++ b/config/module/coreboot/default/patches/0029-src-intel-skylake-Disable-stack-overflow-debug-optio.patch @@ -1,7 +1,7 @@ -From 2f493545f7e895b8eca3e8b9f7d83d354b0105bc Mon Sep 17 00:00:00 2001 +From 007a83486f5cd2528067f18059fcd81e5f5230fa Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Jan 2025 01:36:23 +0000 -Subject: [PATCH 29/50] src/intel/skylake: Disable stack overflow debug options +Subject: [PATCH 29/56] src/intel/skylake: Disable stack overflow debug options The option was appearing in T480/3050micro configs of lbmk, after updating on the coreboot/next uprev for 20241206 rev8: @@ -37,7 +37,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index beb6f13feea7..420dbf44f88c 100644 +index beb6f13fee..420dbf44f8 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -137,6 +137,15 @@ config DCACHE_RAM_SIZE diff --git a/config/module/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch b/config/module/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch index f5ae468d..8e44d8ba 100644 --- a/config/module/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch +++ b/config/module/coreboot/default/patches/0030-soc-intel-skylake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From 0b4725a1dd9939098d74ea6909a1abdb6c82e52b Mon Sep 17 00:00:00 2001 +From 0fb7c56281be432743531c033d1bae046f2004ef Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Thu, 26 Dec 2024 19:45:20 +0000 -Subject: [PATCH 30/50] soc/intel/skylake: Don't compress FSP-S +Subject: [PATCH 30/56] soc/intel/skylake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. @@ -19,7 +19,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig -index 420dbf44f88c..f0b8f92c0731 100644 +index 420dbf44f8..f0b8f92c07 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -15,7 +15,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE diff --git a/config/module/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch b/config/module/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch index 157f371d..50a8bbee 100644 --- a/config/module/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch +++ b/config/module/coreboot/default/patches/0031-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch @@ -1,7 +1,7 @@ -From e2f6685ed4d3f68e133e8449084c37fb67385b11 Mon Sep 17 00:00:00 2001 +From de812fb7f9d1a898c5a00ff61dcdf5fbbfee899d Mon Sep 17 00:00:00 2001 From: Leah Rowe <info@minifree.org> Date: Wed, 18 Dec 2024 02:06:18 +0000 -Subject: [PATCH 31/50] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN +Subject: [PATCH 31/56] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN This is used by lbmk to know where a tb.bin file goes, when extracting and padding TBT.bin from Lenovo ThunderBolt @@ -39,7 +39,7 @@ Signed-off-by: Leah Rowe <info@minifree.org> 1 file changed, 26 insertions(+) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 2ffbaab85f34..512b3263814b 100644 +index 2ffbaab85f..512b326381 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -18,4 +18,30 @@ config MAINBOARD_FAMILY diff --git a/config/module/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch b/config/module/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch index e30e6de5..1c5258e0 100644 --- a/config/module/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch +++ b/config/module/coreboot/default/patches/0032-Conditional-TBFW-setting-for-kabylake-thinkpads.patch @@ -1,7 +1,7 @@ -From 56d98be7f946866a46b8e9bca1e336cc8fff5fa7 Mon Sep 17 00:00:00 2001 +From c3d8d9b0433c6591b25d31e65e3b60f3d5645fc4 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Apr 2025 05:14:45 +0100 -Subject: [PATCH 32/50] Conditional TBFW setting for kabylake thinkpads +Subject: [PATCH 32/56] Conditional TBFW setting for kabylake thinkpads Otherwise, other boards will define it, which might trigger the vendor download script, and @@ -13,7 +13,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig -index 512b3263814b..b2c7763198a3 100644 +index 512b326381..b2c7763198 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -18,6 +18,8 @@ config MAINBOARD_FAMILY diff --git a/config/module/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch b/config/module/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch index a255851d..81e68d87 100644 --- a/config/module/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch +++ b/config/module/coreboot/default/patches/0033-soc-intel-alderlake-Disable-MRC_CACHE_USING_MRC_VERS.patch @@ -1,7 +1,7 @@ -From e2974b98b1892edfcfe2aff277b3111a5641f28d Mon Sep 17 00:00:00 2001 +From aa4d0e3c165d215788f576e99493b1cb5568be9d Mon Sep 17 00:00:00 2001 From: Riku Viitanen <riku.viitanen@protonmail.com> Date: Sat, 27 Sep 2025 23:30:46 +0300 -Subject: [PATCH 33/50] soc/intel/alderlake: Disable +Subject: [PATCH 33/56] soc/intel/alderlake: Disable MRC_CACHE_USING_MRC_VERSION There's some issue with building against the FSP headers in src/vendorcode. @@ -14,7 +14,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 57d3f34c04d1..f378b0d41048 100644 +index 57d3f34c04..f378b0d410 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE diff --git a/config/module/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch b/config/module/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch index 2e0bb9de..d446d839 100644 --- a/config/module/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch +++ b/config/module/coreboot/default/patches/0034-Subject-PATCH-1-1-Add-a-p-option-skip-FPTR-checks.patch @@ -1,7 +1,7 @@ -From 77d8ff6f0033c9fcb7994058cd30aab685335600 Mon Sep 17 00:00:00 2001 +From 7471f231a160ed66ed003ea5b79ffd7ae65c23a8 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sun, 28 Sep 2025 03:17:50 +0100 -Subject: [PATCH 34/50] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) +Subject: [PATCH 34/56] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks) if you pass -k (keep fptr modules), don't use -r, don't use -t, you can essentially just use me_cleaner to @@ -29,7 +29,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py -index fae5e567322f..228bac899f6d 100755 +index fae5e56732..228bac899f 100755 --- a/util/me_cleaner/me_cleaner.py +++ b/util/me_cleaner/me_cleaner.py @@ -246,8 +246,10 @@ def check_partition_signature(f, offset): diff --git a/config/module/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch b/config/module/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch index d973eab9..47be833a 100644 --- a/config/module/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch +++ b/config/module/coreboot/default/patches/0035-soc-intel-alderlake-Don-t-compress-FSP-S.patch @@ -1,7 +1,7 @@ -From f85b895d0e916fcd9cfd3372d3b616c74ffef593 Mon Sep 17 00:00:00 2001 +From 6f27a15dee6750784fce8b3a834ca4cf817c8b75 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 4 Oct 2025 21:57:43 +0100 -Subject: [PATCH 35/50] soc/intel/alderlake: Don't compress FSP-S +Subject: [PATCH 35/56] soc/intel/alderlake: Don't compress FSP-S Build systems like lbmk need to reproducibly insert certain vendor files on release images. @@ -18,7 +18,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index f378b0d41048..550da178d7b8 100644 +index f378b0d410..550da178d7 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE diff --git a/config/module/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch b/config/module/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch index f75843e6..83df3a7e 100644 --- a/config/module/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch +++ b/config/module/coreboot/default/patches/0036-alderlake-don-t-require-full-fsp-repo-for-fd-path.patch @@ -1,7 +1,7 @@ -From 04de5bd11352af80bae4d365d6fc476cd4e2a439 Mon Sep 17 00:00:00 2001 +From 10c8f14db5e2cdef10131cc4a73fdb9e2b02bc03 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 4 Oct 2025 22:20:11 +0100 -Subject: [PATCH 36/50] alderlake: don't require full fsp repo for fd path +Subject: [PATCH 36/56] alderlake: don't require full fsp repo for fd path Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,7 +9,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 550da178d7b8..2535454862ee 100644 +index 550da178d7..2535454862 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -435,7 +435,14 @@ config FSP_HEADER_PATH diff --git a/config/module/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch b/config/module/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch index 09d7652d..a9eb4153 100644 --- a/config/module/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch +++ b/config/module/coreboot/default/patches/0037-soc-alderlake-disable-stack-overflow-debug-option.patch @@ -1,7 +1,7 @@ -From f377d9ef7ae5118fdde83bafe327a876b728732e Mon Sep 17 00:00:00 2001 +From d595fa2a97396aee6ab2514db74027a597328639 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 6 Oct 2025 04:47:06 +0100 -Subject: [PATCH 37/50] soc/alderlake: disable stack overflow debug option +Subject: [PATCH 37/56] soc/alderlake: disable stack overflow debug option same as on other boards. based on this commit: @@ -22,7 +22,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 2535454862ee..6236def814fe 100644 +index 2535454862..6236def814 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -336,6 +336,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ diff --git a/config/module/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch b/config/module/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch index b4f0df39..c619424c 100644 --- a/config/module/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch +++ b/config/module/coreboot/default/patches/0038-ec-dell-mec5035-Add-command-to-disable-EC-initiated-.patch @@ -1,7 +1,7 @@ -From 5363b3620b56a7b61a8d679c80349c7ebd72dae3 Mon Sep 17 00:00:00 2001 +From 7c62f4dd41cf159c3021e93eb4b650c34083e06c Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 11 May 2025 15:41:22 -0600 -Subject: [PATCH 38/50] ec/dell/mec5035: Add command to disable EC-initiated +Subject: [PATCH 38/56] ec/dell/mec5035: Add command to disable EC-initiated thermal shutdown If command 0xBF isn't sent, the EC shuts down the system without warning @@ -39,7 +39,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> 2 files changed, 21 insertions(+) diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c -index c5067c16f65d..b316fa498906 100644 +index c5067c16f6..b316fa4989 100644 --- a/src/ec/dell/mec5035/mec5035.c +++ b/src/ec/dell/mec5035/mec5035.c @@ -114,6 +114,25 @@ void mec5035_sleep_enable(void) @@ -69,7 +69,7 @@ index c5067c16f65d..b316fa498906 100644 { /* If this isn't sent the EC shuts down the system after about 15 diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h -index 5cd907bf71d5..71d1a710753c 100644 +index 5cd907bf71..71d1a71075 100644 --- a/src/ec/dell/mec5035/mec5035.h +++ b/src/ec/dell/mec5035/mec5035.h @@ -14,6 +14,7 @@ enum mec5035_cmd { diff --git a/config/module/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch b/config/module/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch index 3b44bb1b..c4701463 100644 --- a/config/module/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch +++ b/config/module/coreboot/default/patches/0039-mb-dell-snb_ivb_latitude-Disable-EC-initiated-shutdo.patch @@ -1,7 +1,7 @@ -From 20316745dfe8855fd01514571da09a58171c76a7 Mon Sep 17 00:00:00 2001 +From df24178999fbc926bb6dfd98c5972a2cad620ab7 Mon Sep 17 00:00:00 2001 From: Nicholas Chin <nic.c3.14@gmail.com> Date: Sun, 11 May 2025 16:28:23 -0600 -Subject: [PATCH 39/50] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown +Subject: [PATCH 39/56] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown at 87 degrees If command 0xBF isn't sent, the EC will shut down the system without @@ -18,7 +18,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> 1 file changed, 5 insertions(+) diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c -index ff83db095b71..ef385a0a70d0 100644 +index ff83db095b..ef385a0a70 100644 --- a/src/mainboard/dell/snb_ivb_latitude/early_init.c +++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c @@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void) diff --git a/config/module/coreboot/default/patches/0040-fix-ifdtool-build.patch b/config/module/coreboot/default/patches/0040-fix-ifdtool-build.patch index bea56374..2312dadf 100644 --- a/config/module/coreboot/default/patches/0040-fix-ifdtool-build.patch +++ b/config/module/coreboot/default/patches/0040-fix-ifdtool-build.patch @@ -1,7 +1,7 @@ -From e28c3d2c580b1f046c1abf74ed150d7184a38ed3 Mon Sep 17 00:00:00 2001 +From 13a26f612918aa680ed4a397efc1467e837864b6 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 20 Dec 2025 20:12:48 +0100 -Subject: [PATCH 40/50] fix ifdtool build +Subject: [PATCH 40/56] fix ifdtool build not my mistake. someone messed up. @@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index ddc7c1943090..9aacccb54000 100644 +index ddc7c19430..9aacccb540 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -2623,7 +2623,7 @@ int main(int argc, char *argv[]) diff --git a/config/module/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch b/config/module/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch index e84414f2..9762deb7 100644 --- a/config/module/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch +++ b/config/module/coreboot/default/patches/0041-tests-Makefile.mk-use-3rdparty-cmocka-by-default.patch @@ -1,7 +1,7 @@ -From 5b01b298e9743a53617543ff5a32ed3b7f31db2e Mon Sep 17 00:00:00 2001 +From 7fea0ba7f8aa7b0de008ab3c6362c2ca46d4f9df Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Sat, 20 Dec 2025 22:36:18 +0100 -Subject: [PATCH 41/50] tests/Makefile.mk: use 3rdparty/cmocka by default +Subject: [PATCH 41/56] tests/Makefile.mk: use 3rdparty/cmocka by default (tests) @@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/Makefile.mk b/tests/Makefile.mk -index ab302634ecaa..7e6f260b27c5 100644 +index ab302634ec..7e6f260b27 100644 --- a/tests/Makefile.mk +++ b/tests/Makefile.mk @@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage diff --git a/config/module/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch b/config/module/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch index 8abc553c..b62ed52f 100644 --- a/config/module/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch +++ b/config/module/coreboot/default/patches/0042-mb-dell-optiplex_780-use-legacy-HDA-verb-table.patch @@ -1,7 +1,7 @@ -From 317b1b82965679561420ea2e367488f5943c2e63 Mon Sep 17 00:00:00 2001 +From 773efa2c4c42b949480f86db02ef2643ddece59d Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 23 Dec 2025 18:41:27 +0100 -Subject: [PATCH 42/50] mb/dell/optiplex_780: use legacy HDA verb table +Subject: [PATCH 42/56] mb/dell/optiplex_780: use legacy HDA verb table See: @@ -35,7 +35,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+) diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig -index fc649e35d5e7..172bb2fa87a7 100644 +index fc649e35d5..172bb2fa87 100644 --- a/src/mainboard/dell/optiplex_780/Kconfig +++ b/src/mainboard/dell/optiplex_780/Kconfig @@ -2,6 +2,7 @@ diff --git a/config/module/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch b/config/module/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch index 2029ad59..3dd15668 100644 --- a/config/module/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch +++ b/config/module/coreboot/default/patches/0043-hp8300cmt-use-legacy-verb-table.patch @@ -1,7 +1,7 @@ -From 7db4edf21c389134eeb1d573a50119468d585983 Mon Sep 17 00:00:00 2001 +From a0a8bd018b1b4e956597b7146324a47511d132ae Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 23 Dec 2025 18:46:45 +0100 -Subject: [PATCH 43/50] hp8300cmt: use legacy verb table +Subject: [PATCH 43/56] hp8300cmt: use legacy verb table same as for the 780 optiplex patch @@ -14,7 +14,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+) diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig -index d2bfd35dc48e..30be7fb3fea9 100644 +index d2bfd35dc4..30be7fb3fe 100644 --- a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig +++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig @@ -2,6 +2,7 @@ if BOARD_HP_COMPAQ_ELITE_8300_CMT diff --git a/config/module/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch b/config/module/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch index cdf74496..cedce086 100644 --- a/config/module/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch +++ b/config/module/coreboot/default/patches/0044-topton-x2e-n150-use-old-fsp.patch @@ -1,7 +1,7 @@ -From b46defe612d1ab51081863bc1c3bdfa7f9e0a0bc Mon Sep 17 00:00:00 2001 +From 0ba99e4d9c4bdc15063a314db9fc8e73e36637bc Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Tue, 6 Jan 2026 21:42:21 +0000 -Subject: [PATCH 44/50] topton x2e n150: use old fsp +Subject: [PATCH 44/56] topton x2e n150: use old fsp i added the old fsp back, so that we didn't have to mess around with vendor files in lbmk, because coreboot @@ -18,7 +18,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig -index 6236def814fe..919acd020e1e 100644 +index 6236def814..919acd020e 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -456,6 +456,7 @@ config FSP_FD_PATH diff --git a/config/module/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch b/config/module/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch index 4d8555bd..b830a30a 100644 --- a/config/module/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch +++ b/config/module/coreboot/default/patches/0045-mb-supermicro-x11-lga1151-series-Disable-ME-HECI-in-.patch @@ -1,7 +1,7 @@ -From 3dad4d4456a2f8ddf9161a24bf2724370c1b629e Mon Sep 17 00:00:00 2001 +From fe0e2fbff811e023d2cda01c8358c10bb1689a5e Mon Sep 17 00:00:00 2001 From: Ron Nazarov <ron@noisytoot.org> Date: Sat, 14 Feb 2026 20:13:01 +0000 -Subject: [PATCH 45/50] mb/supermicro/x11-lga1151-series: Disable ME HECI in +Subject: [PATCH 45/56] mb/supermicro/x11-lga1151-series: Disable ME HECI in devicetree Since we always use me_cleaner, this speeds up boot time by preventing @@ -14,7 +14,7 @@ Signed-off-by: Ron Nazarov <ron@noisytoot.org> 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb -index d25288420f48..edbb485969a3 100644 +index d25288420f..edbb485969 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/skylake diff --git a/config/module/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch b/config/module/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch index f6c1105b..95281619 100644 --- a/config/module/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch +++ b/config/module/coreboot/default/patches/0046-util-ifdtool-option-to-allow-region-override.patch @@ -1,7 +1,7 @@ -From c2e91bd82d65513e36c33556165bff58425737e7 Mon Sep 17 00:00:00 2001 +From 172dd89a05d02f074d9e17345c5a287d4f7ac27a Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 20 Feb 2026 01:23:32 +0000 -Subject: [PATCH 46/50] util/ifdtool: option to allow region override +Subject: [PATCH 46/56] util/ifdtool: option to allow region override Signed-off-by: Leah Rowe <leah@libreboot.org> --- @@ -9,7 +9,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 9aacccb54000..4ee1c413ae92 100644 +index 9aacccb540..4ee1c413ae 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -78,6 +78,8 @@ static unsigned int max_regions = 0; diff --git a/config/module/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch b/config/module/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch index 4153724d..5574206b 100644 --- a/config/module/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch +++ b/config/module/coreboot/default/patches/0047-me_cleaner-don-t-modify-if-k-is-used.patch @@ -1,7 +1,7 @@ -From 3a479ea3bfdf569eeafa10c94163fcf37b4376f2 Mon Sep 17 00:00:00 2001 +From 26a11c48236b9c0c871d7c9f9641b6e4283a6126 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Fri, 20 Feb 2026 19:31:19 +0000 -Subject: [PATCH 47/50] me_cleaner: don't modify if -k is used +Subject: [PATCH 47/56] me_cleaner: don't modify if -k is used don't remove *anything*. in libreboot, we only ever use -k when we werely want to extract the @@ -18,7 +18,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org> 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py -index 228bac899f6d..269aa4ad0432 100755 +index 228bac899f..269aa4ad04 100755 --- a/util/me_cleaner/me_cleaner.py +++ b/util/me_cleaner/me_cleaner.py @@ -677,7 +677,7 @@ if __name__ == "__main__": diff --git a/config/module/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch b/config/module/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch index b9a35c6a..83627f16 100644 --- a/config/module/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch +++ b/config/module/coreboot/default/patches/0048-mb-lenovo-sklkbl-Add-Lenovo-Thinkpad-X270-as-a-varia.patch @@ -1,7 +1,7 @@ -From abcbe7f3f81024721832bb54e08f56452cba59d4 Mon Sep 17 00:00:00 2001 +From 8b45c226090d4fef2303c3b3c16a3a167aa56fba Mon Sep 17 00:00:00 2001 From: Kat Inskip <kat@inskip.me> Date: Tue, 17 Feb 2026 16:18:15 -0800 -Subject: [PATCH 48/50] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant +Subject: [PATCH 48/56] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant This machine is somewhat dissimilar from the X280 in the PCIe allocations in the overridetree. It also lacks soldered RAM, having a single SODIMM slot. @@ -28,7 +28,7 @@ An untested variety allowing for a Skylake CPU (for 20K5 and 20K6) has been incl create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig -index 25c8ec6959c5..2a9cfba7f5d8 100644 +index 25c8ec6959..2a9cfba7f5 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig @@ -62,6 +62,16 @@ config BOARD_LENOVO_X380_YOGA @@ -67,7 +67,7 @@ index 25c8ec6959c5..2a9cfba7f5d8 100644 config CBFS_SIZE default 0x900000 diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name -index 96feb3169543..6fb68f44dd7d 100644 +index 96feb31695..6fb68f44dd 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name @@ -17,3 +17,6 @@ config BOARD_LENOVO_X280 @@ -116,7 +116,7 @@ HcmV?d00001 diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads new file mode 100644 -index 000000000000..fcfbd75a9261 +index 0000000000..fcfbd75a92 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads @@ -0,0 +1,19 @@ @@ -141,7 +141,7 @@ index 000000000000..fcfbd75a9261 +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c new file mode 100644 -index 000000000000..ec5db9c53c77 +index 0000000000..ec5db9c53c --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c @@ -0,0 +1,200 @@ @@ -347,7 +347,7 @@ index 000000000000..ec5db9c53c77 +} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c new file mode 100644 -index 000000000000..089e605eafe4 +index 0000000000..089e605eaf --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c @@ -0,0 +1,124 @@ @@ -477,7 +477,7 @@ index 000000000000..089e605eafe4 +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c new file mode 100644 -index 000000000000..a2317c026dd1 +index 0000000000..a2317c026d --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c @@ -0,0 +1,19 @@ @@ -502,7 +502,7 @@ index 000000000000..a2317c026dd1 +} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb new file mode 100644 -index 000000000000..3191cdfac59e +index 0000000000..3191cdfac5 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb @@ -0,0 +1,89 @@ diff --git a/config/module/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch b/config/module/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch index 72698a14..880775f3 100644 --- a/config/module/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch +++ b/config/module/coreboot/default/patches/0049-mb-lenovo-x270-Provide-correct-vbt-and-hda_verb.patch @@ -1,7 +1,7 @@ -From 44a66dba9b69cfff2f70477bd6078dca8859ba3e Mon Sep 17 00:00:00 2001 +From b06246d570246eb82d8019ac778106811ba3511a Mon Sep 17 00:00:00 2001 From: Kat Inskip <kat@inskip.me> Date: Sat, 21 Feb 2026 19:48:17 +0000 -Subject: [PATCH 49/50] mb/lenovo/x270: Provide correct vbt and hda_verb +Subject: [PATCH 49/56] mb/lenovo/x270: Provide correct vbt and hda_verb --- .../sklkbl_thinkpad/variants/x270/data.vbt | Bin 6144 -> 4449 bytes @@ -42,7 +42,7 @@ zOt#PQ3z%&Gr0KzQq%L?F$qyDI#p`ontd(z|4G<1OH}pZJatA(ZRZ|e`6IX&6k;fD! Re`fqpo`k>sC+JqU`~#!PkzxP< diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c -index 089e605eafe4..60289355f869 100644 +index 089e605eaf..60289355f8 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c @@ -3,10 +3,10 @@ diff --git a/config/module/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch b/config/module/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch index 18ea0974..7f2c3bb0 100644 --- a/config/module/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch +++ b/config/module/coreboot/default/patches/0050-mb-dell-Add-OptiPlex-3040-Micro-port-upstream-compat.patch @@ -1,7 +1,7 @@ -From 514f637be0f766d077a09a734832c0c9bfb376e1 Mon Sep 17 00:00:00 2001 +From 621fa31a5342d01c8d199d5f08e6862909e970b5 Mon Sep 17 00:00:00 2001 From: Todd Baker <todd_baker@student.uml.edu> Date: Thu, 12 Mar 2026 13:12:04 -0400 -Subject: [PATCH 50/50] mb/dell: Add OptiPlex 3040 Micro port +Subject: [PATCH 50/56] mb/dell: Add OptiPlex 3040 Micro port (upstream-compatible) Based on the OptiPlex 3050 Micro (same Skylake H110 PCH-H platform). @@ -59,7 +59,7 @@ Signed-off-by: Todd Baker <todd_baker@student.uml.edu> diff --git a/src/mainboard/dell/optiplex_3040/Kconfig b/src/mainboard/dell/optiplex_3040/Kconfig new file mode 100644 -index 000000000000..eab8e7d814de +index 0000000000..eab8e7d814 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/Kconfig @@ -0,0 +1,37 @@ @@ -102,7 +102,7 @@ index 000000000000..eab8e7d814de +endif diff --git a/src/mainboard/dell/optiplex_3040/Kconfig.name b/src/mainboard/dell/optiplex_3040/Kconfig.name new file mode 100644 -index 000000000000..e06da5010ad3 +index 0000000000..e06da5010a --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/Kconfig.name @@ -0,0 +1,4 @@ @@ -112,7 +112,7 @@ index 000000000000..e06da5010ad3 + bool "Dell OptiPlex 3040 Micro" diff --git a/src/mainboard/dell/optiplex_3040/Makefile.mk b/src/mainboard/dell/optiplex_3040/Makefile.mk new file mode 100644 -index 000000000000..0bd72fe691a4 +index 0000000000..0bd72fe691 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/Makefile.mk @@ -0,0 +1,12 @@ @@ -130,7 +130,7 @@ index 000000000000..0bd72fe691a4 +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/optiplex_3040/acpi/ec.asl b/src/mainboard/dell/optiplex_3040/acpi/ec.asl new file mode 100644 -index 000000000000..16990d45f428 +index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/acpi/ec.asl @@ -0,0 +1,3 @@ @@ -139,7 +139,7 @@ index 000000000000..16990d45f428 +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/dell/optiplex_3040/acpi/superio.asl b/src/mainboard/dell/optiplex_3040/acpi/superio.asl new file mode 100644 -index 000000000000..16990d45f428 +index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/acpi/superio.asl @@ -0,0 +1,3 @@ @@ -148,7 +148,7 @@ index 000000000000..16990d45f428 +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/dell/optiplex_3040/board_info.txt b/src/mainboard/dell/optiplex_3040/board_info.txt new file mode 100644 -index 000000000000..e43a925ec3c8 +index 0000000000..e43a925ec3 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/board_info.txt @@ -0,0 +1,7 @@ @@ -161,7 +161,7 @@ index 000000000000..e43a925ec3c8 +Release year: 2016 diff --git a/src/mainboard/dell/optiplex_3040/bootblock.c b/src/mainboard/dell/optiplex_3040/bootblock.c new file mode 100644 -index 000000000000..10689c42a1a9 +index 0000000000..10689c42a1 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/bootblock.c @@ -0,0 +1,107 @@ @@ -274,7 +274,7 @@ index 000000000000..10689c42a1a9 +} diff --git a/src/mainboard/dell/optiplex_3040/cmos.default b/src/mainboard/dell/optiplex_3040/cmos.default new file mode 100644 -index 000000000000..79961f43d82c +index 0000000000..79961f43d8 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/cmos.default @@ -0,0 +1,5 @@ @@ -285,7 +285,7 @@ index 000000000000..79961f43d82c +power_on_after_fail=Disable diff --git a/src/mainboard/dell/optiplex_3040/cmos.layout b/src/mainboard/dell/optiplex_3040/cmos.layout new file mode 100644 -index 000000000000..54a5147b7d50 +index 0000000000..54a5147b7d --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/cmos.layout @@ -0,0 +1,54 @@ @@ -381,7 +381,7 @@ HcmV?d00001 diff --git a/src/mainboard/dell/optiplex_3040/devicetree.cb b/src/mainboard/dell/optiplex_3040/devicetree.cb new file mode 100644 -index 000000000000..f1c919fbc799 +index 0000000000..f1c919fbc7 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/devicetree.cb @@ -0,0 +1,100 @@ @@ -487,7 +487,7 @@ index 000000000000..f1c919fbc799 +end diff --git a/src/mainboard/dell/optiplex_3040/dsdt.asl b/src/mainboard/dell/optiplex_3040/dsdt.asl new file mode 100644 -index 000000000000..9762f6ff74c6 +index 0000000000..9762f6ff74 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/dsdt.asl @@ -0,0 +1,27 @@ @@ -520,7 +520,7 @@ index 000000000000..9762f6ff74c6 +} diff --git a/src/mainboard/dell/optiplex_3040/gma-mainboard.ads b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads new file mode 100644 -index 000000000000..cb4c22f2859e +index 0000000000..cb4c22f285 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/gma-mainboard.ads @@ -0,0 +1,19 @@ @@ -545,7 +545,7 @@ index 000000000000..cb4c22f2859e +end GMA.Mainboard; diff --git a/src/mainboard/dell/optiplex_3040/hda_verb.c b/src/mainboard/dell/optiplex_3040/hda_verb.c new file mode 100644 -index 000000000000..5a1db019c7cc +index 0000000000..5a1db019c7 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/hda_verb.c @@ -0,0 +1,90 @@ @@ -641,7 +641,7 @@ index 000000000000..5a1db019c7cc +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/optiplex_3040/include/early_gpio.h b/src/mainboard/dell/optiplex_3040/include/early_gpio.h new file mode 100644 -index 000000000000..fdf1a64c7cf6 +index 0000000000..fdf1a64c7c --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/include/early_gpio.h @@ -0,0 +1,11 @@ @@ -658,7 +658,7 @@ index 000000000000..fdf1a64c7cf6 +#endif diff --git a/src/mainboard/dell/optiplex_3040/include/gpio.h b/src/mainboard/dell/optiplex_3040/include/gpio.h new file mode 100644 -index 000000000000..29da4b11d4b6 +index 0000000000..29da4b11d4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/include/gpio.h @@ -0,0 +1,241 @@ @@ -905,7 +905,7 @@ index 000000000000..29da4b11d4b6 +#endif diff --git a/src/mainboard/dell/optiplex_3040/ramstage.c b/src/mainboard/dell/optiplex_3040/ramstage.c new file mode 100644 -index 000000000000..c391e4ac6d45 +index 0000000000..c391e4ac6d --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/ramstage.c @@ -0,0 +1,512 @@ @@ -1423,7 +1423,7 @@ index 000000000000..c391e4ac6d45 +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); diff --git a/src/mainboard/dell/optiplex_3040/romstage.c b/src/mainboard/dell/optiplex_3040/romstage.c new file mode 100644 -index 000000000000..c2ce2369a4dc +index 0000000000..c2ce2369a4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/romstage.c @@ -0,0 +1,22 @@ @@ -1451,7 +1451,7 @@ index 000000000000..c2ce2369a4dc +} diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.c b/src/mainboard/dell/optiplex_3040/sch5555_ec.c new file mode 100644 -index 000000000000..1df5026531c6 +index 0000000000..1df5026531 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.c @@ -0,0 +1,54 @@ @@ -1511,7 +1511,7 @@ index 000000000000..1df5026531c6 +} diff --git a/src/mainboard/dell/optiplex_3040/sch5555_ec.h b/src/mainboard/dell/optiplex_3040/sch5555_ec.h new file mode 100644 -index 000000000000..9d262d578764 +index 0000000000..9d262d5787 --- /dev/null +++ b/src/mainboard/dell/optiplex_3040/sch5555_ec.h @@ -0,0 +1,10 @@ diff --git a/config/module/coreboot/default/patches/0051-remove-Werror-tree-wide.patch b/config/module/coreboot/default/patches/0051-remove-Werror-tree-wide.patch index 2b8a1237..bd3602df 100644 --- a/config/module/coreboot/default/patches/0051-remove-Werror-tree-wide.patch +++ b/config/module/coreboot/default/patches/0051-remove-Werror-tree-wide.patch @@ -1,7 +1,7 @@ -From 9e56e314f97f6e3d8f13d4a95284830dd5ae6612 Mon Sep 17 00:00:00 2001 +From c01e980e06601034fc911e3c5e1fdeebaf7eb3f8 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Sep 2026 10:46:07 +0100 -Subject: [PATCH 1/1] remove -Werror tree-wide +Subject: [PATCH 51/56] remove -Werror tree-wide Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/module/coreboot/default/patches/0052-Remove-KCONFIG_WERROR.patch b/config/module/coreboot/default/patches/0052-Remove-KCONFIG_WERROR.patch index 69d35d32..1ef4162b 100644 --- a/config/module/coreboot/default/patches/0052-Remove-KCONFIG_WERROR.patch +++ b/config/module/coreboot/default/patches/0052-Remove-KCONFIG_WERROR.patch @@ -1,7 +1,7 @@ -From 69aee4b8d9c61cc3eb832e8d7b8a2f8cd4be6e38 Mon Sep 17 00:00:00 2001 +From a0d7318453e1b4827175de4a848df85bff097f73 Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Sep 2026 11:20:54 +0100 -Subject: [PATCH 1/1] Remove KCONFIG_WERROR +Subject: [PATCH 52/56] Remove KCONFIG_WERROR Signed-off-by: Leah Rowe <leah@libreboot.org> --- diff --git a/config/module/coreboot/default/patches/0053-use-std-gnu2x.patch b/config/module/coreboot/default/patches/0053-use-std-gnu2x.patch index 46a42568..19bd5d59 100644 --- a/config/module/coreboot/default/patches/0053-use-std-gnu2x.patch +++ b/config/module/coreboot/default/patches/0053-use-std-gnu2x.patch @@ -1,7 +1,7 @@ -From d88dad002b5574fd49cf25211cd557cb938f80be Mon Sep 17 00:00:00 2001 +From 47a2305433ea6b123ef6baf65f496b4583e198da Mon Sep 17 00:00:00 2001 From: Leah Rowe <leah@libreboot.org> Date: Mon, 21 Sep 2026 13:00:09 +0100 -Subject: [PATCH 1/1] use -std=gnu2x +Subject: [PATCH 53/56] use -std=gnu2x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/config/module/coreboot/default/patches/0054-mb-dell-sklkbl_desktops-Enable-Coffee-Lake-CPU-suppo.patch b/config/module/coreboot/default/patches/0054-mb-dell-sklkbl_desktops-Enable-Coffee-Lake-CPU-suppo.patch new file mode 100644 index 00000000..50117c68 --- /dev/null +++ b/config/module/coreboot/default/patches/0054-mb-dell-sklkbl_desktops-Enable-Coffee-Lake-CPU-suppo.patch @@ -0,0 +1,29 @@ +From 33e43d984131b5573553af857beb0c5a1b3db763 Mon Sep 17 00:00:00 2001 +From: Ron Nazarov <ron@noisytoot.org> +Date: Sun, 21 Dec 2025 17:24:09 +0000 +Subject: [PATCH 54/56] mb/dell/sklkbl_desktops: Enable Coffee Lake CPU support + +Tested and working with i3-9100 on OptiPlex 5050 SFF, should work on +3050 Micro too. + +Change-Id: Ie2f8f5d6955b7fced12275f67d2f2c45669bc0ce +Signed-off-by: Ron Nazarov <ron@noisytoot.org> +--- + src/mainboard/dell/sklkbl_desktops/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/dell/sklkbl_desktops/Kconfig b/src/mainboard/dell/sklkbl_desktops/Kconfig +index 098d43dc22..0dce6a90bf 100644 +--- a/src/mainboard/dell/sklkbl_desktops/Kconfig ++++ b/src/mainboard/dell/sklkbl_desktops/Kconfig +@@ -13,6 +13,7 @@ config BOARD_DELL_SKLKBL_DESKTOPS_COMMON + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_SUPPORTS_KABYLAKE_CPU + select MAINBOARD_SUPPORTS_SKYLAKE_CPU ++ select MAINBOARD_SUPPORTS_COFFEELAKE_CPU + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE +-- +2.47.3 + diff --git a/config/module/coreboot/default/patches/0055-mb-dell-sklkbl_desktops-Enable-legacy-8254-timer.patch b/config/module/coreboot/default/patches/0055-mb-dell-sklkbl_desktops-Enable-legacy-8254-timer.patch new file mode 100644 index 00000000..dcae827f --- /dev/null +++ b/config/module/coreboot/default/patches/0055-mb-dell-sklkbl_desktops-Enable-legacy-8254-timer.patch @@ -0,0 +1,28 @@ +From bc353bd6ea7daf10f5b5883894bed1af1d056725 Mon Sep 17 00:00:00 2001 +From: Ron Nazarov <ron@noisytoot.org> +Date: Sun, 21 Dec 2025 17:29:16 +0000 +Subject: [PATCH 55/56] mb/dell/sklkbl_desktops: Enable legacy 8254 timer + +Without this, SeaBIOS hangs. + +Change-Id: I22a5fdc566e954ace00756beb7d2de3fd6621c7b +Signed-off-by: Ron Nazarov <ron@noisytoot.org> +--- + src/mainboard/dell/sklkbl_desktops/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/dell/sklkbl_desktops/Kconfig b/src/mainboard/dell/sklkbl_desktops/Kconfig +index 0dce6a90bf..1fab8b41d5 100644 +--- a/src/mainboard/dell/sklkbl_desktops/Kconfig ++++ b/src/mainboard/dell/sklkbl_desktops/Kconfig +@@ -18,6 +18,7 @@ config BOARD_DELL_SKLKBL_DESKTOPS_COMMON + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE + select SUPERIO_SMSC_SCH555x ++ select USE_LEGACY_8254_TIMER # SeaBIOS hangs without this + + config BOARD_DELL_OPTIPLEX_3050 + bool +-- +2.47.3 + diff --git a/config/module/coreboot/default/patches/0056-mb-dell-sklkbl_desktops-Add-OptiPlex-5050-SFF-varian.patch b/config/module/coreboot/default/patches/0056-mb-dell-sklkbl_desktops-Add-OptiPlex-5050-SFF-varian.patch new file mode 100644 index 00000000..41b2155d --- /dev/null +++ b/config/module/coreboot/default/patches/0056-mb-dell-sklkbl_desktops-Add-OptiPlex-5050-SFF-varian.patch @@ -0,0 +1,703 @@ +From 576d0d86086566b67b3b664024015fa6ad0162b9 Mon Sep 17 00:00:00 2001 +From: Ron Nazarov <ron@noisytoot.org> +Date: Mon, 22 Dec 2025 03:11:56 +0000 +Subject: [PATCH 56/56] mb/dell/sklkbl_desktops: Add OptiPlex 5050 SFF variant + +- Boots Linux 6.12.41-0-lts and 6.18.0-3-lts (Alpine, tested with SeaBIOS and EDK II) +- Tested with i5-6500 and i3-9100 +- All external USB ports work +- Serial port works +- PS/2 works in SeaBIOS and Linux +- Intel Gigabit Ethernet works +- All 3 SATA ports work, M.2 slot SATA untested (I don't have a + compatible SSD to test with) +- Sound works +- DisplayPort and HDMI works (however, I only tested DisplayPort with + a DP->DVI adapter as I don't have a native DisplayPort monitor, and + libgfxinit required a patch in order to correctly initialize it) +- M.2 slot (PCIe), PCIe x4 slot, and PCIe x16 slot mostly work +- VGA port and SD card reader untested, as mine does not have these +- me_cleaner works, provided you use --whitelist MFS (deguard relies + on the MFS partition, it won't boot otherwise) +- SeaBIOS hangs if compiled without USE_LEGACY_8254_TIMER + +PCIe hotplug is disabled since it apparently causes Linux to randomly +rename NVMe devices, potentially resulting in data loss. I haven't +actually tested this on a 5050 SFF myself, but this issue also affects the +OptiPlex 3050 Micro and ThinkPad T480/T480s. Libreboot disables PCIe +hotplug on those boards for this reason, but the fix doesn't seem to +have been submitted upstream. + +I say that PCIe mostly works because with one of the cards I was +testing with (Mellanox CX312C): +- With stock firmware it works in both x4 and x16 slots, but only at + 2.5GT/s for some reason. +- With coreboot it works in the x4 slot (again, at 2.5GT/s), but + doesn't even enumerate on the x16 slot. +- On another machine (OptiPlex 9020 SFF with coreboot) it works in the + x4 slot (at 5GT/s), but does not reliably work in the x16 slot (it + sometimes fails to enumerate, sometimes the driver fails to load with + different error messages). +I'm not quite sure what's going on there. There's probably a coreboot +bug involved, but it doesn't work quite right with the stock firmware +either. The other card I tested with (Intel X520-DA2) works at 5GT/s +in both slots. + +Thanks to Nicholas Chin for telling me where to find the USB +overcurrent pin mapping and helping with PS/2 and PCIe. + +Change-Id: I8dc6ed29abc6c14171ed060cea9b58a07f01bd7b +Signed-off-by: Ron Nazarov <ron@noisytoot.org> +--- + src/mainboard/dell/sklkbl_desktops/Kconfig | 8 + + .../dell/sklkbl_desktops/Kconfig.name | 3 + + .../variants/optiplex_5050sff/board_info.txt | 7 + + .../variants/optiplex_5050sff/data.vbt | Bin 0 -> 6144 bytes + .../variants/optiplex_5050sff/early_gpio.c | 15 ++ + .../optiplex_5050sff/gma-mainboard.ads | 19 ++ + .../variants/optiplex_5050sff/gpio.c | 245 ++++++++++++++++++ + .../variants/optiplex_5050sff/hda_verb.c | 90 +++++++ + .../optiplex_5050sff/include/acpi/superio.asl | 3 + + .../variants/optiplex_5050sff/overridetree.cb | 97 +++++++ + .../variants/optiplex_5050sff/romstage.c | 20 ++ + 11 files changed, 507 insertions(+) + create mode 100644 src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/board_info.txt + create mode 100644 src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/data.vbt + create mode 100644 src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/early_gpio.c + create mode 100644 src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/gma-mainboard.ads + create mode 100644 src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/gpio.c + create mode 100644 src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/hda_verb.c + create mode 100644 src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/include/acpi/superio.asl + create mode 100644 src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/overridetree.cb + create mode 100644 src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/romstage.c + +diff --git a/src/mainboard/dell/sklkbl_desktops/Kconfig b/src/mainboard/dell/sklkbl_desktops/Kconfig +index 1fab8b41d5..d6ac6551fb 100644 +--- a/src/mainboard/dell/sklkbl_desktops/Kconfig ++++ b/src/mainboard/dell/sklkbl_desktops/Kconfig +@@ -24,6 +24,11 @@ config BOARD_DELL_OPTIPLEX_3050 + bool + select BOARD_DELL_SKLKBL_DESKTOPS_COMMON + ++config BOARD_DELL_OPTIPLEX_5050_SFF ++ bool ++ select BOARD_DELL_SKLKBL_DESKTOPS_COMMON ++ select MAINBOARD_USES_IFD_GBE_REGION ++ + if BOARD_DELL_SKLKBL_DESKTOPS_COMMON + + config MAINBOARD_DIR +@@ -31,9 +36,11 @@ config MAINBOARD_DIR + + config MAINBOARD_PART_NUMBER + default "OptiPlex 3050 Micro" if BOARD_DELL_OPTIPLEX_3050 ++ default "OptiPlex 5050 SFF" if BOARD_DELL_OPTIPLEX_5050_SFF + + config VARIANT_DIR + default "optiplex_3050" if BOARD_DELL_OPTIPLEX_3050 ++ default "optiplex_5050sff" if BOARD_DELL_OPTIPLEX_5050_SFF + + config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" +@@ -46,6 +53,7 @@ config CBFS_SIZE + + config DIMM_SPD_SIZE + default 512 if BOARD_DELL_OPTIPLEX_3050 # DDR4 ++ default 512 if BOARD_DELL_OPTIPLEX_5050_SFF # DDR4 + + # Won't boot if MFS partition is missing, deguard requires it + config ME_CLEANER_ARGS +diff --git a/src/mainboard/dell/sklkbl_desktops/Kconfig.name b/src/mainboard/dell/sklkbl_desktops/Kconfig.name +index 14eab7f52c..e856f670ba 100644 +--- a/src/mainboard/dell/sklkbl_desktops/Kconfig.name ++++ b/src/mainboard/dell/sklkbl_desktops/Kconfig.name +@@ -2,3 +2,6 @@ + + config BOARD_DELL_OPTIPLEX_3050 + bool "OptiPlex 3050 Micro" ++ ++config BOARD_DELL_OPTIPLEX_5050_SFF ++ bool "OptiPlex 5050 SFF" +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/board_info.txt b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/board_info.txt +new file mode 100644 +index 0000000000..5554c934c0 +--- /dev/null ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/board_info.txt +@@ -0,0 +1,7 @@ ++Category: desktop ++Board URL: https://www.dell.com/support/product-details/en-uk/product/optiplex-5050-sff/overview ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2017 +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/data.vbt b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..a4e2ee4ade83e0d0e79ff8814fba96d130e2b7c6 +GIT binary patch +literal 6144 +zcmeHKU2GIp6h1SvzjtP~vs09^U_Bthw$OIAK!sXmw!4L0+S1)_txGgv3%f|;LQ7jr +z@sBmugv4m}K@A!-O?=SQmnOz1V<a&u2~p8R^i5t&lxSii#us2b^Fv!8(hc#CxM%jv +zx%b?&-@WJDzcZ@`I|ne+y{jkM-GvV2L4$9VCG@_YI+J~w-SOx^ba!V@U#uIygxldQ +z<??xeJjX4QBAOOS9-Jr?!~G2e+k?F$dxndJmUv<O(TR~!OvREI-MhC?EQ}3J6!MrE +z+#W>}Q)Zoqhl_dKdHBGd!dN>JkVe)R+1R{cBVwebm3~@e6BV`gNL%}+Ei#LD#rk?v +z$)4yyvTrB$^<zAliDoigy`4R~FxB6eNOmR%y5cgMb0an~dSq<)k^K`Gjx}H__0eR3 +zT0_Rz$k=EzMvF!4H*LnTzc5}Hd#sRemYE515_~QWfOA7l2{^da3ZMfZfD1sG>w^py +zl&>x-z;EJsGGF5ZPu;>cf)}XnBSf6jqYJ*ufui`%`)nN{yPXow_oBmD%j%+IMS{8@ +zLJoPWU{xHefZtY;@K_~{L$hm}6!>I6^$6%#iB}r*1y*=P`Ois#+`afX_2;<F0cR3G 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+zQ@N?UR+qN(K_D*#T1@78xXCqXA;>m@8!PbQd<dpfxKxw0*t{2I+K)5_GrL)QU-0dv +zx<i|r^la1oTnKa)nFw@<c^2On4LamXP@7Yfp!qMb<6wO}Nj=+AyHi643&ov72MV`l +zr4UawO^h_rN3HGMBJXw2fM<uY7P2!tPEn@**S}eI#<+&~YiRv#@a#4kXOc4a2OtG` +qSkJuzKM2jU0LSL&mMCs;zF8NEdbPP4focS*5vWF>8iD_P1pWYFD8nBB + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/early_gpio.c b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/early_gpio.c +new file mode 100644 +index 0000000000..1787d556ab +--- /dev/null ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/early_gpio.c +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <soc/gpe.h> ++#include <soc/gpio.h> ++#include "../../../include/variant/gpio.h" ++ ++static const struct pad_config early_gpio_table[] = { ++ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ ++ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ ++}; ++ ++void variant_configure_early_gpios(void) ++{ ++ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); ++} +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/gma-mainboard.ads b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/gma-mainboard.ads +new file mode 100644 +index 0000000000..f58e61cb8b +--- /dev/null ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/gma-mainboard.ads +@@ -0,0 +1,19 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (HDMI1, -- External HDMI ++ DP2, -- External DP (native) ++ DP3, -- External DP (native) ++ HDMI2, -- External DP (DP++) ++ HDMI3, -- External DP (DP++) ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/gpio.c b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/gpio.c +new file mode 100644 +index 0000000000..9a133a35de +--- /dev/null ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/gpio.c +@@ -0,0 +1,245 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <soc/gpe.h> ++#include <soc/gpio.h> ++#include "../../../include/variant/gpio.h" ++ ++static const struct pad_config gpio_table[] = { ++ ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, UP_20K, PLTRST, NF1), /* RCIN# */ ++ PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* LAD0 */ ++ PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* LAD1 */ ++ PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* LAD2 */ ++ PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* LAD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ ++ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# */ ++ PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */ ++ PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */ ++ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* PME# */ ++ PAD_CFG_GPO(GPP_A12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), /* SUSWARN#/SUSPWRDNACK */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_A15, UP_20K, PLTRST, NF1), /* SUS_ACK# */ ++ PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_CFG_GPO(GPP_B0, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B1, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B2, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_B3, 1, RSMRST), /* GPIO (ME_CNTL, B3 -> LOW => HDA_SDO -> HIGH) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_B5, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B6, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_B9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ ++ PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), /* PLTRST# */ ++ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ ++ PAD_CFG_GPO(GPP_B15, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* GSPIO_MOSI */ ++ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* GPIO */ ++ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GSPI1_MOSI */ ++ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* PCHHOT# */ ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_C2, DN_20K, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_C3, NONE, PLTRST, NF1), /* SML0CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, PLTRST, NF1), /* SML0DATA */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ ++ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ ++ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ ++ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ ++ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ ++ PAD_CFG_GPO(GPP_C18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_C22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_CFG_GPO(GPP_D0, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D1, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D2, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D3, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_D7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_D23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ ++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ ++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 */ ++ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ ++ PAD_CFG_NF(GPP_E9, UP_20K, PLTRST, NF1), /* USB_OC0# */ ++ PAD_CFG_NF(GPP_E10, UP_20K, PLTRST, NF1), /* USB_OC1# */ ++ PAD_CFG_NF(GPP_E11, UP_20K, PLTRST, NF1), /* USB_OC2# */ ++ PAD_CFG_NF(GPP_E12, UP_20K, PLTRST, NF1), /* USB_OC3# */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ ++ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* SATAXPCIE4 */ ++ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ ++ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ ++ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), /* SATA_DEVSLP4 */ ++ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_F9, 0, RSMRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_F13, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), /* USB_OC4# */ ++ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), /* USB_OC5# */ ++ PAD_CFG_NF(GPP_F17, UP_20K, PLTRST, NF1), /* USB_OC6# */ ++ PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_F21, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F22, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_F23, 1, RSMRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G9, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G12, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, ACPI), /* GPIO */ ++ PAD_CFG_GPO(GPP_G14, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G16, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G17, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_G19, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G20, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_G21, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G22, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_G23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Group GPP_H ------- */ ++ PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H3, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H4, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H5, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H6, 1, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H7, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H8, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H9, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H10, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H11, 0, PLTRST), /* GPIO */ ++ PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), /* GPIO */ ++ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H16, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H17, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H19, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H20, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H21, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H22, 0, PLTRST), /* GPIO */ ++ PAD_CFG_GPO(GPP_H23, 0, PLTRST), /* GPIO */ ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ ++ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ ++ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */ ++ PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PWRBTN# */ ++ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ ++ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ ++ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ ++ PAD_CFG_GPO(GPD7, 1, RSMRST), /* GPIO */ ++ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ ++ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ ++ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ ++ PAD_CFG_GPO(GPD11, 1, RSMRST), /* GPIO */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_I ------- */ ++ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ ++ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ ++ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ ++ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ ++ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */ ++ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ ++ PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* DDPB_CTRLDATA */ ++ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ ++ PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* DDPC_CTRLDATA */ ++ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ ++ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */ ++}; ++ ++void variant_configure_gpios(void) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/hda_verb.c b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/hda_verb.c +new file mode 100644 +index 0000000000..929bcee5ad +--- /dev/null ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/hda_verb.c +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ /* coreboot specific header, codec 0 */ ++ 0x10ec0255, /* Realtek ALC3234 */ ++ 0x102807a2, /* Subsystem ID */ ++ 11, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_SUBVENDOR(0, 0x102807a2), ++ ++ AZALIA_PIN_CFG(0, 0x12, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, ++ AZALIA_LINE_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1d, 0x4054c029), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 15 ++ )), ++ ++ /* coreboot specific header, codec 2 */ ++ 0x80862809, /* Intel Skylake HDMI */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of entries */ ++ ++ /* Pin Widget Verb Table */ ++ ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/include/acpi/superio.asl b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/include/acpi/superio.asl +new file mode 100644 +index 0000000000..55b1db5b11 +--- /dev/null ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/include/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <drivers/pc80/pc/ps2_controller.asl> +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/overridetree.cb +new file mode 100644 +index 0000000000..87c0e25b3e +--- /dev/null ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/overridetree.cb +@@ -0,0 +1,97 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ ++ device domain 0 on ++ ++ subsystemid 0x1028 0x07a2 inherit ++ ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC0), // Back panel (black) ++ [1] = USB2_PORT_MID(OC0), // Front panel (black) ++ [2] = USB2_PORT_MID(OC2), // Front panel (black) ++ [3] = USB2_PORT_MID(OC1), // Back panel (black) ++ [4] = USB2_PORT_MID(OC1), // Back panel (blue) ++ [5] = USB2_PORT_MID(OC3), // Back panel (blue) ++ [6] = USB2_PORT_MID(OC2), // Back panel (blue) ++ [7] = USB2_PORT_MID(OC3), // Back panel (blue) ++ [8] = USB2_PORT_MID(OC4), // Front panel (blue) ++ [9] = USB2_PORT_MID(OC6), // Front panel (blue) ++ [10] = USB2_PORT_MID(OC_SKIP), // Unknown ++ [11] = USB2_PORT_MID(OC5), // Unknown ++ [12] = USB2_PORT_MID(OC5), // Unknown ++ [13] = USB2_PORT_MID(OC_SKIP), // Unknown ++ [14] = USB2_PORT_MID(OC0), // Unknown ++ [15] = USB2_PORT_MID(OC0), // Unknown ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) ++ [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) ++ [2] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) ++ [3] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) ++ [4] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) ++ [5] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) ++ }" ++ end ++ ++ device ref sata on ++ register "SataSalpSupport" = "1" ++ register "SataPortsEnable[0]" = "1" ++ register "SataPortsEnable[1]" = "1" ++ register "SataPortsEnable[2]" = "1" ++ register "SataPortsEnable[3]" = "1" ++ end ++ ++ # Intel Gigabit Ethernet ++ device ref gbe on ++ register "PcieRpClkReqSupport[4]" = "0" ++ register "PcieRpHotPlug[4]" = "0" ++ end ++ ++ device ref lpc_espi on ++ # SCH5553 ++ chip superio/smsc/sch555x ++ device pnp 2e.0 on # EMI ++ io 0x60 = 0xa00 ++ end ++ device pnp 2e.1 on # 8042 ++ io 0x60 = 0x60 ++ irq 0x0f = 0 ++ irq 0x70 = 1 ++ irq 0x72 = 12 ++ end ++ device pnp 2e.7 on # UART1 ++ io 0x60 = 0x3f8 ++ irq 0x0f = 2 ++ irq 0x70 = 4 ++ end ++ device pnp 2e.8 off end # UART2 ++ device pnp 2e.c on # LPC interface ++ io 0x60 = 0x2e ++ end ++ device pnp 2e.a on # Runtime registers ++ io 0x60 = 0xa40 ++ end ++ device pnp 2e.b off end # Floppy Controller ++ device pnp 2e.11 off end # Parallel Port ++ end ++ end ++ ++ # PCIe x16 ++ device ref peg0 on ++ end ++ ++ # PCIe x4 ++ device ref pcie_rp9 on ++ register "PcieRpAdvancedErrorReporting[8]" = "1" ++ register "PcieRpLtrEnable[8]" = "true" ++ end ++ ++ # M.2 SSD ++ device ref pcie_rp17 on ++ register "PcieRpAdvancedErrorReporting[16]" = "1" ++ register "PcieRpLtrEnable[16]" = "true" ++ end ++ end ++end +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/romstage.c b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/romstage.c +new file mode 100644 +index 0000000000..1784eb9a11 +--- /dev/null ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/romstage.c +@@ -0,0 +1,20 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <soc/romstage.h> ++#include <spd_bin.h> ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ struct spd_block blk = { .addr_map = { 0x50, 0x51, 0x52, 0x53, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; ++ mem_cfg->CaVrefConfig = 2; ++ mem_cfg->MemorySpdDataLen = blk.len; ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; ++ mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; ++ mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; ++} +-- +2.47.3 + diff --git a/config/module/coreboot/default/patches/0057-5050sff-disable-hotplug-on-pcie-x4-and-m2-slot.patch b/config/module/coreboot/default/patches/0057-5050sff-disable-hotplug-on-pcie-x4-and-m2-slot.patch new file mode 100644 index 00000000..04919f58 --- /dev/null +++ b/config/module/coreboot/default/patches/0057-5050sff-disable-hotplug-on-pcie-x4-and-m2-slot.patch @@ -0,0 +1,42 @@ +From 76ee3bd2fc48cada3094798bc4f1c3f77f404a66 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Mon, 21 Sep 2026 19:49:34 +0100 +Subject: [PATCH 1/1] 5050sff: disable hotplug on pcie x4 and m2 slot + +hotplug is buggy with nvme ssds on these boards, when +using fsp. the device names get bumped in linux, which +can cause a crash (or if they're on a raid array, they +drop out of the array) + +ron forgot to add them here. i'm not even going to +entertain testing this board without this patch, as +turning off hotplug doesn't really affect anything +anyway, so there's no harm in doing it. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + .../sklkbl_desktops/variants/optiplex_5050sff/overridetree.cb | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/overridetree.cb +index 87c0e25b3e..a6d7e72fd1 100644 +--- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/overridetree.cb ++++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_5050sff/overridetree.cb +@@ -86,12 +86,14 @@ chip soc/intel/skylake + device ref pcie_rp9 on + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" ++ register "PcieRpHotPlug[8]" = "0" + end + + # M.2 SSD + device ref pcie_rp17 on + register "PcieRpAdvancedErrorReporting[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" ++ register "PcieRpHotPlug[16]" = "0" + end + end + end +-- +2.47.3 + diff --git a/config/module/coreboot/dell3050micro_vfsp_16mb/config/libgfxinit_corebootfb b/config/module/coreboot/dell3050micro_vfsp_16mb/config/libgfxinit_corebootfb index 9c6229d8..c4d12aa8 100644 --- a/config/module/coreboot/dell3050micro_vfsp_16mb/config/libgfxinit_corebootfb +++ b/config/module/coreboot/dell3050micro_vfsp_16mb/config/libgfxinit_corebootfb @@ -169,6 +169,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set CONFIG_BOARD_DELL_OPTIPLEX_3050=y +# CONFIG_BOARD_DELL_OPTIPLEX_5050_SFF is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E6220 is not set diff --git a/config/module/coreboot/dell3050micro_vfsp_16mb/config/libgfxinit_txtmode b/config/module/coreboot/dell3050micro_vfsp_16mb/config/libgfxinit_txtmode index f34aa5c1..dcff4726 100644 --- a/config/module/coreboot/dell3050micro_vfsp_16mb/config/libgfxinit_txtmode +++ b/config/module/coreboot/dell3050micro_vfsp_16mb/config/libgfxinit_txtmode @@ -167,6 +167,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set CONFIG_BOARD_DELL_OPTIPLEX_3050=y +# CONFIG_BOARD_DELL_OPTIPLEX_5050_SFF is not set # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E6220 is not set diff --git a/config/module/coreboot/dell5050sff_vfsp_16mb/config/libgfxinit_corebootfb b/config/module/coreboot/dell5050sff_vfsp_16mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..ff4b84ec --- /dev/null +++ b/config/module/coreboot/dell5050sff_vfsp_16mb/config/libgfxinit_corebootfb @@ -0,0 +1,866 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_LTO is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_TSEG_STAGE_CACHE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARM is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ERYING is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HARDKERNEL is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LATTEPANDA is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MITAC_COMPUTING is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NOVACUSTOM is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_QOTOM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TOPTON is not set +# CONFIG_VENDOR_UP is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 5050 SFF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/sklkbl_desktops" +CONFIG_VGA_BIOS_ID="8086,0406" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=512 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0xEEC000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840 +CONFIG_MAX_CPUS=16 +CONFIG_ME_CLEANER_ARGS="-S --whitelist MFS" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_VARIANT_DIR="optiplex_5050sff" +CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +# CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=256 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro" +# CONFIG_CONSOLE_POST is not set +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +CONFIG_MAX_SOCKET=1 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USE_PM_ACPI_TIMER=y +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_BOARD_DELL_E4300 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set +CONFIG_BOARD_DELL_OPTIPLEX_5050_SFF=y +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set +CONFIG_BOARD_DELL_SKLKBL_DESKTOPS_COMMON=y +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/5050sff/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/5050sff/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/5050sff/gbe" +CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y +CONFIG_D3COLD_SUPPORT=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_SYSTEM_SMBIOS_MANUFACTURER="Dell Inc." +# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set +CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y +CONFIG_USE_LEGACY_8254_TIMER=y +# CONFIG_DEBUG_SMI is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# CONFIG_BOOTMEDIA_SMM_BWP_RUNTIME_OPTION is not set +CONFIG_USE_PC_CMOS_ALTCENTURY=y +# CONFIG_DRIVERS_EFI_FW_INFO is not set +# CONFIG_TCG_OPAL_S3_UNLOCK is not set +CONFIG_BOARD_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x01000000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb" +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd" +CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x800 +CONFIG_ACPI_BERT_SIZE=0x0 +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +CONFIG_CPU_PT_ROM_MAP_GB=512 +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_MAX_ROOT_PORTS=24 +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_CPU_XTAL_HZ=24000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_ENABLE_SATA_TEST_MODE is not set +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0 +CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_FSP_PUBLISH_MBP_HOB=y +CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003 +CONFIG_SOC_HAS_MSR_VR_CURRENT_CONFIG=y +CONFIG_MAX_HECI_DEVICES=5 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_HAVE_PAM0_REGISTER=y +CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000 +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0 +CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003 +CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_SKYLAKE_SOC_PCH_H=y +CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y +CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y +# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set +CONFIG_FSP_T_LOCATION=0xfffe0000 +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_FIXED_SMBUS_IO_BASE=0xefa0 +CONFIG_UART_BITBANG_TX_DELAY_MS=5 +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code for IP blocks +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y +# CONFIG_USE_COREBOOT_MP_INIT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +CONFIG_INTEL_CAR_NEM_ENHANCED=y +# CONFIG_USE_INTEL_FSP_MP_INIT is not set +CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y +CONFIG_HAVE_HYPERTHREADING=y +# CONFIG_FSP_HYPERTHREADING is not set +# CONFIG_INTEL_KEYLOCKER is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y +CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME" +CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw" +CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version" +CONFIG_SOC_INTEL_CSE_RW_FILE="" +CONFIG_SOC_INTEL_CSE_RW_VERSION_FILE="" +CONFIG_SOC_INTEL_CSE_RW_VERSION="" +CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom" +CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE="" +CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy" +CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE="" +CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y +# CONFIG_SOC_INTEL_DISABLE_IGD is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_HAS_WADT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_ENABLE_DPR=y +CONFIG_HAVE_CAPID_A_REGISTER=y +CONFIG_HAVE_BDSM_BGSM_REGISTER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y + +# +# Intel SoC Common Code for features +# +CONFIG_SOC_INTEL_COMMON_FEATURE=y +CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y +CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y +CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y +CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y +CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y + +# +# Intel SoC Common coreboot stages and non-IP blocks +# +CONFIG_SOC_INTEL_COMMON_BASECODE=y +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +CONFIG_PAVP=y +# CONFIG_MMA is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set + +# +# CPU +# +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0 +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_HAVE_INSMM_STS=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 +CONFIG_UDK_BASE=y +CONFIG_UDK_2017_BINDING=y +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_202005_VERSION=202005 +CONFIG_UDK_202111_VERSION=202111 +CONFIG_UDK_202302_VERSION=202302 +CONFIG_UDK_202305_VERSION=202305 +CONFIG_UDK_VERSION=2017 +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_SMM_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 +CONFIG_DEFAULT_EBDA_LOWMEM=0x100000 +CONFIG_DEFAULT_EBDA_SEGMENT=0xF600 +CONFIG_DEFAULT_EBDA_SIZE=0x400 +CONFIG_IOAPIC=y +# CONFIG_ASYNC_FILE_LOADING_CACHE is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_RUN_FSP_GOP is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y +CONFIG_ON_DEVICE_ROM_LOAD=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y +# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set +# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set +# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set +CONFIG_DEFAULT_SCREEN_ROTATION_INT=0 +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x10000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_DRAM_SUPPORT_DDR4=y +CONFIG_DRAM_SUPPORT_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set +# CONFIG_ELOG is not set +# CONFIG_DRIVERS_HWID_DMI is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_DRIVERS_OPTION_CFR is not set +# CONFIG_SELF_TEST is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_MAX98396 is not set +# CONFIG_FSP_USE_REPO is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +CONFIG_PLATFORM_USES_FSP2_X86_32=y +CONFIG_HAVE_INTEL_FSP_REPO=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +# CONFIG_FSP_FULL_FD is not set +CONFIG_FSP_T_RESERVED_SIZE=0x0 +CONFIG_FSP_M_XIP=y +CONFIG_SOC_INTEL_COMMON_FSP_RESET=y +CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y +CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y +CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y +# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set +# CONFIG_BUILDING_WITH_DEBUG_FSP is not set +CONFIG_FSP_VGA_MODE12_BPP=0x0 +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Skylake" +CONFIG_GFX_GMA_PCH="Sunrise_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +CONFIG_DRIVERS_INTEL_OC_MAILBOX=y +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_USB_ACPI=y +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# TCG storage +# +# end of TCG storage + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_CUSTOM_MADT=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_ACPI_LPIT=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_ACPI_S1_NOT_SUPPORTED=y +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y +# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y + +# +# Boot Logo Configuration +# +# CONFIG_BMP_LOGO is not set +# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set +# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set +# end of Boot Logo Configuration + +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/module/coreboot/dell5050sff_vfsp_16mb/config/libgfxinit_txtmode b/config/module/coreboot/dell5050sff_vfsp_16mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..984db7cd --- /dev/null +++ b/config/module/coreboot/dell5050sff_vfsp_16mb/config/libgfxinit_txtmode @@ -0,0 +1,859 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_LTO is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_TSEG_STAGE_CACHE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARM is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ERYING is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HARDKERNEL is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LATTEPANDA is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MITAC_COMPUTING is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NOVACUSTOM is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_QOTOM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TOPTON is not set +# CONFIG_VENDOR_UP is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 5050 SFF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/sklkbl_desktops" +CONFIG_VGA_BIOS_ID="8086,0406" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=512 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0xEEC000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=16 +CONFIG_ME_CLEANER_ARGS="-S --whitelist MFS" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_VARIANT_DIR="optiplex_5050sff" +CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +# CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=256 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro" +# CONFIG_CONSOLE_POST is not set +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +CONFIG_MAX_SOCKET=1 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USE_PM_ACPI_TIMER=y +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_BOARD_DELL_E4300 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set +CONFIG_BOARD_DELL_OPTIPLEX_5050_SFF=y +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set +CONFIG_BOARD_DELL_SKLKBL_DESKTOPS_COMMON=y +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/5050sff/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/5050sff/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/5050sff/gbe" +CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y +CONFIG_D3COLD_SUPPORT=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_SYSTEM_SMBIOS_MANUFACTURER="Dell Inc." +# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set +CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y +CONFIG_USE_LEGACY_8254_TIMER=y +# CONFIG_DEBUG_SMI is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# CONFIG_BOOTMEDIA_SMM_BWP_RUNTIME_OPTION is not set +CONFIG_USE_PC_CMOS_ALTCENTURY=y +# CONFIG_DRIVERS_EFI_FW_INFO is not set +# CONFIG_TCG_OPAL_S3_UNLOCK is not set +CONFIG_BOARD_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x01000000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb" +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd" +CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x800 +CONFIG_ACPI_BERT_SIZE=0x0 +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +CONFIG_CPU_PT_ROM_MAP_GB=512 +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_MAX_ROOT_PORTS=24 +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_CPU_XTAL_HZ=24000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_ENABLE_SATA_TEST_MODE is not set +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0 +CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_FSP_PUBLISH_MBP_HOB=y +CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003 +CONFIG_SOC_HAS_MSR_VR_CURRENT_CONFIG=y +CONFIG_MAX_HECI_DEVICES=5 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_HAVE_PAM0_REGISTER=y +CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000 +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0 +CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003 +CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_SKYLAKE_SOC_PCH_H=y +CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y +CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y +# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set +CONFIG_FSP_T_LOCATION=0xfffe0000 +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_FIXED_SMBUS_IO_BASE=0xefa0 +CONFIG_UART_BITBANG_TX_DELAY_MS=5 +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code for IP blocks +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y +# CONFIG_USE_COREBOOT_MP_INIT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +CONFIG_INTEL_CAR_NEM_ENHANCED=y +# CONFIG_USE_INTEL_FSP_MP_INIT is not set +CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y +CONFIG_HAVE_HYPERTHREADING=y +# CONFIG_FSP_HYPERTHREADING is not set +# CONFIG_INTEL_KEYLOCKER is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y +CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME" +CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw" +CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version" +CONFIG_SOC_INTEL_CSE_RW_FILE="" +CONFIG_SOC_INTEL_CSE_RW_VERSION_FILE="" +CONFIG_SOC_INTEL_CSE_RW_VERSION="" +CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom" +CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE="" +CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy" +CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE="" +CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y +# CONFIG_SOC_INTEL_DISABLE_IGD is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_HAS_WADT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_ENABLE_DPR=y +CONFIG_HAVE_CAPID_A_REGISTER=y +CONFIG_HAVE_BDSM_BGSM_REGISTER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y + +# +# Intel SoC Common Code for features +# +CONFIG_SOC_INTEL_COMMON_FEATURE=y +CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y +CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y +CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y +CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y +CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y + +# +# Intel SoC Common coreboot stages and non-IP blocks +# +CONFIG_SOC_INTEL_COMMON_BASECODE=y +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +CONFIG_PAVP=y +# CONFIG_MMA is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set + +# +# CPU +# +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0 +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_HAVE_INSMM_STS=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 +CONFIG_UDK_BASE=y +CONFIG_UDK_2017_BINDING=y +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_202005_VERSION=202005 +CONFIG_UDK_202111_VERSION=202111 +CONFIG_UDK_202302_VERSION=202302 +CONFIG_UDK_202305_VERSION=202305 +CONFIG_UDK_VERSION=2017 +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_SMM_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 +CONFIG_DEFAULT_EBDA_LOWMEM=0x100000 +CONFIG_DEFAULT_EBDA_SEGMENT=0xF600 +CONFIG_DEFAULT_EBDA_SIZE=0x400 +CONFIG_IOAPIC=y +# CONFIG_ASYNC_FILE_LOADING_CACHE is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_RUN_FSP_GOP is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y +CONFIG_ON_DEVICE_ROM_LOAD=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +CONFIG_DEFAULT_SCREEN_ROTATION_INT=0 +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x10000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_DRAM_SUPPORT_DDR4=y +CONFIG_DRAM_SUPPORT_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set +# CONFIG_ELOG is not set +# CONFIG_DRIVERS_HWID_DMI is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_DRIVERS_OPTION_CFR is not set +# CONFIG_SELF_TEST is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_MAX98396 is not set +# CONFIG_FSP_USE_REPO is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +CONFIG_PLATFORM_USES_FSP2_X86_32=y +CONFIG_HAVE_INTEL_FSP_REPO=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +# CONFIG_FSP_FULL_FD is not set +CONFIG_FSP_T_RESERVED_SIZE=0x0 +CONFIG_FSP_M_XIP=y +CONFIG_SOC_INTEL_COMMON_FSP_RESET=y +CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y +CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y +CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y +# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set +# CONFIG_BUILDING_WITH_DEBUG_FSP is not set +CONFIG_FSP_VGA_MODE12_BPP=0x0 +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Skylake" +CONFIG_GFX_GMA_PCH="Sunrise_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +CONFIG_DRIVERS_INTEL_OC_MAILBOX=y +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_USB_ACPI=y +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# TCG storage +# +# end of TCG storage + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_CUSTOM_MADT=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_ACPI_LPIT=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_ACPI_S1_NOT_SUPPORTED=y +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y +# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y + +# +# Boot Logo Configuration +# +# CONFIG_BMP_LOGO is not set +# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set +# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set +# end of Boot Logo Configuration + +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/module/coreboot/dell5050sff_vfsp_16mb/target.cfg b/config/module/coreboot/dell5050sff_vfsp_16mb/target.cfg new file mode 100644 index 00000000..7d3b46e2 --- /dev/null +++ b/config/module/coreboot/dell5050sff_vfsp_16mb/target.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-3.0-or-later + +tree="default" +xarch="i386-elf" +payload_seabios="y" +payload_grub="y" +payload_memtest="y" +grub_scan_disk="nvme ahci" +grubtree="xhci_nvme" +vcfg="5050sff" +build_depend="seabios/build grub/xhci_nvme memtest86plus/default u-boot/amd64coreboot" +IFD_platform="sklkbl" +payload_uboot="amd64" diff --git a/config/vendor/5050sff/pkg.cfg b/config/vendor/5050sff/pkg.cfg new file mode 100644 index 00000000..8d8cb414 --- /dev/null +++ b/config/vendor/5050sff/pkg.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-3.0-or-later + +DL_hash="976bbb1e625f64df276d8343757d910c88b8a781f953bc2c41a7dd15184ec70d55f8081de2a0aaa83cddb8e73bdc2df6288fde6e0897e4928c48ca4bb30bea2d" +DL_url="https://download.asrock.com/BIOS/1151/H110M-DGS(7.30)ROM.zip" +DL_url_bkup="https://web.archive.org/web/20230822134231/https://download.asrock.com/BIOS/1151/H110M-DGS(7.30)ROM.zip" +ME_bin_hash="341ef8e1f2c276fc23368552c0bcbc9ce0ebca15f7281fd64783466dd199c9ffb618a72b2fd9a3b09fdb917516ede420c225c07cc68a761eeadbab3672bacf5b" + +# for Fsp.fd, we don't rely on a download. Instead, +# we copy from coreboot.git. The file is defined +# by CONFIG_FSP_FD_PATH, split to CONFIG_FSP_M_FILE and CONFIG_FSP_S_FILE +# and inserted to CBFS with names CONFIG_FSP_S_CBFS and CONFIG_FSP_M_CBFS +# +FSPFD_hash="c500166a8553a80ba8db8b8185a896e0ae1562ea3c139e07acd9e7937baf8110ba743cc79b69db09a5f39c076d1d22bc45045223975f46aea2034ba82a6b0360" +FSPM_bin_hash="b15712a53f4d16f36b384beb6dbb716c0b0924751d6ca1e229cd4b8c03aef9eda025c235af247e53dac94d94b79559623974d0d21c7f97e125d8ecc2c86bf03f" +FSPS_bin_hash="64ac9f93e43efddc35931e168d6594c2b39fb5a0da863d22f2d000d7eacc0692b07ce89389cbb1c5b95ff9b2bba508c538e37d0e644fcab7b2cada773da65ce6" + +# We will use deguard to disable the Intel Boot Guard: +ME11bootguard="y" +ME11delta="optiplex_5050sff" # subdirectory under deguard's data/delta/ +ME11version="11.6.0.1126" +ME11sku="2M" +ME11pch="H" |