blob: d67b38eb8fd20d10186dc4d614d183e64dd4fa55 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
|
From fb58f84592fbba25abafaccd9e868afa107c1051 Mon Sep 17 00:00:00 2001
From: Mate Kukri <km@mkukri.xyz>
Date: Thu, 5 Dec 2024 08:11:05 +0000
Subject: [PATCH] sata fix
Change-Id: I0eab7aaf9cf00085c97c637c9ffa14e38cf6d738
---
.../lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb | 9 +++------
.../sklkbl_thinkpad/variants/t480s/overridetree.cb | 9 +++------
2 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
index 4b68ec3f49..2f0b20d91a 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
@@ -42,12 +42,9 @@ chip soc/intel/skylake
end
device ref sata on
- # SATA_0 - NC
- # SATA_1A - NC
- # SATA_1B - NC
- # SATA_2 - SATA caddy
- register "SataPortsEnable[3]" = "1"
- register "SataPortsDevSlp[3]" = "1"
+ # SATA_2 - JHDD1 SATA SSD
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[2]" = "1"
end
# PCIe controller 1 - 1x4
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
index 5f1c38bc03..cea5e485d2 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
@@ -42,12 +42,9 @@ chip soc/intel/skylake
end
device ref sata on
- # SATA_0 - NC
- # SATA_1A - NC
- # SATA_1B - NC
- # SATA_2 - M.2 2280 SATA
- register "SataPortsEnable[3]" = "1"
- register "SataPortsDevSlp[3]" = "1"
+ # SATA_2 - Main M.2 SATA SSD
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[2]" = "1"
end
# PCIe controller 1 - 1x2+2x1
--
2.39.5
|
