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libreboot will still include microcode updates
by default, but mitigations against broken speedstep
and reboot (when microcode updates are excluded) were
removed following the merge with osboot
this patch restores those mitigations; the patch
reverts coreboot to older smrr code (which works fine, it
isn't critical to use the new behaviour) and disables peci
(pointless feature)
i'll probably re-tool this later to apply the changes
conditionally to whether ucode is present
this is not a change in policy. policy says:
include cpu microcode updates by default
policy also says:
libreboot must be configurable
microcode removal via cbfstool remove -n, counts as
configuration, and in practise is not possible on
gm45 patches in current libreboot; this patch corrects
that problem, allowing the machines to work somewhat
well (same stability issues as before, like MCE errors
resulting in kernel panic on high CPU/memory usage,
but i digress)
happy... hacking
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bl1 bootloader blobs needed, and lbmk doesn't currently
auto-download these for insertion, so their presence in
the build system is problematic because people might build
these and think they work - they don't, due to the lack of
those bl1 blobs
notes about this are included in lbwww, on the compatibility
list. these can be re-added and tested later, when lbmk handles
those bl1 bootloader blobs
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u-boot is known broken on these, last revision
known working is 2021.01
can bisect and find the fix. i'm putting this on
the issue tracker (new one on codeberg)
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i overlooked this one. the normal one was removed,
due to boot issues with the board. i need to look
at this board before re-adding it to libreboot
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these boards are almost impossible to find, and have always been
buggy, it doesn't look like there will be any viable testing or
development on it
it's currently broken in master, on coreboot. if someone wants to
fix and re-add to lbmk, they can do that
use older libreboot releases to flash this board, if you wish
(i *am* adding te the issue tracker, a note about this commit,
with a view to re-adding it one day)
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rename board configs, and add to sources file the
t530/w530 boards
in some situations, the files weren't being downloaded
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MRC caches in a certain way, that Heads was able to work
around in their build system, for this board.
I've adapted the relevant config differences, from their project
as of heads revision 96440b928acb06de5b925ea12014c9c280b23165
The downside is that CBFS now has to be 8MB in size. The upside
is that the machine also boots much faster
See:
https://github.com/osresearch/heads/pull/1282/commits/f0792117efa177ded19878f652c5a28e8cc62a71
https://github.com/osresearch/heads/pull/1282#issuecomment-1400634600
I have not adapted their IFD changes, versus Libreboot, because theirs
simply has a different version string, and uses different read/write
permission bits for regions as defined in the IFD.
This affects:
t440p_12mb_mrc
w541_12mb_mrc
S3 suspend/resume still broken on these targets which use the libre
MRC init (replacement code by Angel Pons, recently merged in lbmk):
t440p_12mb
w541_12mb
With clever use of FMAP, the rest of the BIOS region might still be
used. However, for our purposes, 8MB CBFS will do just fine.
Heads's changes configure MRC so that caching is handled properly,
for when the machine returns from sleep. Setting CBFS to be any
higher will result in slower boot times, and broken S3 resume, due
to MRC cache misalignment (this is based on my understanding, reading
through the Heads project looking at their research on this).
At some point in the future, Angel's libre MRC code will probably
be finished, and merged, with more fine tuning possible to allow
bigger CBFS sizes.
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libre mrc on haswell is quite buggy for now, but works in
a limited fashion
this patch re-adds the old configs, but as _mrc for example
t440p_12mb_mrc instead of t440p_12mb
and t440p_12mb (without _mrc) still uses the libre mrc code
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i found that with libre mrc, usb was broken in grub
however, it worked nicely in seabios
for our purposes, doing seabios-only roms in text mode
is best for now
i'm going to re-add mrc.bin, but for t440p_12mb_mrc
and w541_12mb_mrc, as new config names. the regular
t440p_12mb and w541_12mb will continue to use libre
mrc, but the _mrc ones will use mrc.bin and retain the
grub payload in board.cfg
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untested. removing.
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courtesy of Angel Pons from the coreboot project
this uses the following patch set from gerrit, as yet
unmerged (in coreboot master) on this date:
https://review.coreboot.org/c/coreboot/+/64198/5
logic for downloading mrc blobs has been deleted from
lbmk, as this is now completely obsolete (for haswell
boards)
if other platforms are added later that need mrc.bin,
then logic will be re-added again for that
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they don't even boot in pcbox properly, and the real
hardware is not much to talk about
useless port
delete
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using the same method as the previous patch for t440p
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352MB VRAM causes stability issues, according to some reports
users can still set it to the higher level when building, if
they wish to
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due to upstream bloat, these no longer fit. it will have to be
fixed in the next libreboot release
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memtest can't fit in such tiny space alongside SeaBIOS
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The configs were enabling SeaBIOS payload, but this is to be
handled by lbmk, not coreboot.
Further, they were enabling VGA ROM execution in coreboot, but
this should be handled by SeaBIOS.
This board should not have a GRUB payload enabled either; this
will be checked and fixed if necessary in the next commit.
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Add a build for QEMU AArch64 virtual machine using U-Boot as payload.
Coreboot config is based on the following defconfig:
CONFIG_CBFS_SIZE=0x00c00000
CONFIG_BOARD_EMULATION_QEMU_AARCH64=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
CONFIG_UART_PCI_ADDR=0x0
The resulting ROM can be booted with a command line like:
qemu-system-aarch64 \
-machine virt,secure=on,virtualization=on \
-cpu cortex-a53 -m 1G \
-vga none -display none -serial stdio \
-bios bin/qemu_arm64_12mb/uboot_*.rom
However, this is little more than a proof of concept because U-Boot
upstream is missing coreboot integration on non-x86 boards, which could
have been useful for e.g. a framebuffer.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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U-Boot doesn't run on this board when this SuperIO serial driver is
disabled. Enable it.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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Add a U-Boot build for the qemu_x86_12mb board. The config is a copy of
the upstream "coreboot" defconfig, but with OF_EMBED=y.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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e.g.
./ifdtool --nuke me coreboot.rom
this will be used by rom release build scripts, to scrub
stuff like intel me from the rom
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These boards are near-identical, this appears to suffice.
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New x230edp_12mb target uses the
https://review.coreboot.org/c/coreboot/+/28950 patchset to add an
X230_EDP target to the default coreboot branch.
Consequently the "fhd" coreboot branch is no longer needed and has
been safely removed.
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buggy, buggy, buggy, buggy, buggy, buggy, buggy
full of bugs, these boards never worked properly. i got ripped
off with these.
now i'm ripping off the band aid
use dasharo if you want d16 stuff. i'm done with it.
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backported from newer coreboot revisions, see patch
coreboot/default/patches/0014-coreboot-default-fix-crossgcc-build.patch
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osboot is now part of libreboot, and will soon shut down.
libreboot now conforms to osboot policy.
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This adds coreboot configuration for the Samsung Chromebook 2 11", which
is based on the "google/peach_pit" mainboard in upstream coreboot. Also
adds a shared "peach" board directory to share with others having the
same baseboard.
The config is based on the following defconfig:
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x00400000
CONFIG_UART_FOR_CONSOLE=3
CONFIG_BOARD_GOOGLE_PEACH_PIT=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the peach pit chromebook. This also fails
without a non-free 3rdparty/blobs/cpu/samsung/exynos5420/bl1.bin blob.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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This adds coreboot configuration for the HP Chromebook 11 G1, which is
part of the "google/daisy" mainboard in upstream coreboot. It uses the
shared tree for the "daisy" baseboard.
The config is based on the following defconfig:
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x00400000
CONFIG_UART_FOR_CONSOLE=3
CONFIG_BOARD_GOOGLE_DAISY=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS=0x4
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the spring chromebook. This also fails
without a non-free 3rdparty/blobs/cpu/samsung/exynos5250/bl1.bin blob.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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This adds coreboot configuration for the Samsung Chromebook - XE303,
which is based on the "google/daisy" mainboard in upstream coreboot.
Also adds a shared "daisy" board directory to share with others having
the same baseboard.
The config is based on the following defconfig:
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x00400000
CONFIG_UART_FOR_CONSOLE=3
CONFIG_BOARD_GOOGLE_DAISY=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS=0x4
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the snow chromebook. This also fails without
a non-free 3rdparty/blobs/cpu/samsung/exynos5250/bl1.bin blob.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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This adds coreboot configuration for the HP Chromebook 14 G3, which is
based on the "google/nyan_blaze" mainboard in upstream coreboot. It uses
the shared tree for the "nyan" baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=4
CONFIG_BOARD_GOOGLE_NYAN_BLAZE=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_DRIVERS_AS3722_RTC_BUS=4
CONFIG_DRIVERS_AS3722_RTC_ADDR=0x40
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the nyan blaze chromebook.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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This adds coreboot configuration for the Acer Chromebook 13 (CB5-311,
C810), which is based on the "google/nyan_big" mainboard in upstream
coreboot. Also adds a shared "nyan" board directory to share with
others having the same baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=4
CONFIG_BOARD_GOOGLE_NYAN_BIG=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_DRIVERS_AS3722_RTC_BUS=4
CONFIG_DRIVERS_AS3722_RTC_ADDR=0x40
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the nyan big chromebook.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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This adds coreboot configuration for the ASUS Chromebit CS10, which is
based on the "google/veyron_mickey" mainboard in upstream coreboot. It
uses the shared tree for the "veyron" baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_BOARD_GOOGLE_VEYRON_MICKEY=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the veyron mickey chromebit.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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