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2022-11-14pragmatic system distribution guideline compliancepsdgLeah Rowe
osboot is now part of libreboot, and will soon shut down. libreboot now conforms to osboot policy.
2022-08-29coreboot: Add peach pit chromebook configsAlper Nebi Yasak
This adds coreboot configuration for the Samsung Chromebook 2 11", which is based on the "google/peach_pit" mainboard in upstream coreboot. Also adds a shared "peach" board directory to share with others having the same baseboard. The config is based on the following defconfig: CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x00400000 CONFIG_UART_FOR_CONSOLE=3 CONFIG_BOARD_GOOGLE_PEACH_PIT=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 Untested since I don't have the peach pit chromebook. This also fails without a non-free 3rdparty/blobs/cpu/samsung/exynos5420/bl1.bin blob. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-08-29coreboot: Add spring chromebook configsAlper Nebi Yasak
This adds coreboot configuration for the HP Chromebook 11 G1, which is part of the "google/daisy" mainboard in upstream coreboot. It uses the shared tree for the "daisy" baseboard. The config is based on the following defconfig: CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x00400000 CONFIG_UART_FOR_CONSOLE=3 CONFIG_BOARD_GOOGLE_DAISY=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS=0x4 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 Untested since I don't have the spring chromebook. This also fails without a non-free 3rdparty/blobs/cpu/samsung/exynos5250/bl1.bin blob. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-08-29coreboot: Add snow chromebook configsAlper Nebi Yasak
This adds coreboot configuration for the Samsung Chromebook - XE303, which is based on the "google/daisy" mainboard in upstream coreboot. Also adds a shared "daisy" board directory to share with others having the same baseboard. The config is based on the following defconfig: CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x00400000 CONFIG_UART_FOR_CONSOLE=3 CONFIG_BOARD_GOOGLE_DAISY=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS=0x4 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 Untested since I don't have the snow chromebook. This also fails without a non-free 3rdparty/blobs/cpu/samsung/exynos5250/bl1.bin blob. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-08-29coreboot: Add nyan blaze chromebook configsAlper Nebi Yasak
This adds coreboot configuration for the HP Chromebook 14 G3, which is based on the "google/nyan_blaze" mainboard in upstream coreboot. It uses the shared tree for the "nyan" baseboard. The config is based on the following defconfig: # CONFIG_USE_BLOBS is not set CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x400000 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=4 CONFIG_BOARD_GOOGLE_NYAN_BLAZE=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_DRIVERS_AS3722_RTC_BUS=4 CONFIG_DRIVERS_AS3722_RTC_ADDR=0x40 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 Untested since I don't have the nyan blaze chromebook. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-08-29coreboot: Add nyan big chromebook configsAlper Nebi Yasak
This adds coreboot configuration for the Acer Chromebook 13 (CB5-311, C810), which is based on the "google/nyan_big" mainboard in upstream coreboot. Also adds a shared "nyan" board directory to share with others having the same baseboard. The config is based on the following defconfig: # CONFIG_USE_BLOBS is not set CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x400000 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=4 CONFIG_BOARD_GOOGLE_NYAN_BIG=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_DRIVERS_AS3722_RTC_BUS=4 CONFIG_DRIVERS_AS3722_RTC_ADDR=0x40 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 Untested since I don't have the nyan big chromebook. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-08-29coreboot: Add veyron mickey chromebit configsAlper Nebi Yasak
This adds coreboot configuration for the ASUS Chromebit CS10, which is based on the "google/veyron_mickey" mainboard in upstream coreboot. It uses the shared tree for the "veyron" baseboard. The config is based on the following defconfig: # CONFIG_USE_BLOBS is not set CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x400000 CONFIG_BOARD_GOOGLE_VEYRON_MICKEY=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 Untested since I don't have the veyron mickey chromebit. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-08-29coreboot: Add veyron jerry chromebook configsAlper Nebi Yasak
This adds coreboot configuration for a few white-label chromebooks which are based on the "google/veyron" mainboard in upstream coreboot. It uses the shared tree for the "veyron" baseboard. The config is based on the following defconfig: # CONFIG_USE_BLOBS is not set CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x400000 CONFIG_BOARD_GOOGLE_VEYRON_JERRY=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 Untested since I don't have any of the veyron jerry chromebooks. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-08-29coreboot: Add veyron minnie chromebook configsAlper Nebi Yasak
This adds coreboot configuration for the ASUS Chromebook Flip C100PA, which is based on the "google/veyron" mainboard in upstream coreboot. It uses the shared tree for the "veyron" baseboard. The config is based on the following defconfig: # CONFIG_USE_BLOBS is not set CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x400000 CONFIG_BOARD_GOOGLE_VEYRON_MINNIE=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 Untested since I don't have the veyron minnie chromebook. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-08-29coreboot: Add veyron speedy chromebook configsAlper Nebi Yasak
This adds coreboot configuration for the ASUS Chromebook C201PA, which is based on the "google/veyron" mainboard in upstream coreboot. Also adds a shared "veyron" board directory to share with others having the same baseboard. The config is based on the following defconfig: # CONFIG_USE_BLOBS is not set CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x400000 CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 Untested since I don't have the veyron speedy chromebook. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-08-29coreboot: Add bob chromebook configsAlper Nebi Yasak
This adds coreboot configuration for the ASUS Chromebook Flip C101, which is based on the "google/gru" mainboard in upstream coreboot. It uses the shared tree for the "gru" baseboard. The config is based on the following defconfig: # CONFIG_USE_BLOBS is not set CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x00800000 CONFIG_BOARD_GOOGLE_BOB=y CONFIG_DRIVER_TPM_SPI_BUS=0x0 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 CONFIG_PAYLOAD_FIT_SUPPORT=y Untested since I don't have the bob chromebook. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-08-29coreboot: Add kevin chromebook configsAlper Nebi Yasak
This adds coreboot configuration for the Samsung Chromebook Plus (v1), which is based on the "google/gru" mainboard in upstream coreboot. Also adds a shared "gru" board directory to share with others having the same baseboard. The config is based on the following defconfig: # CONFIG_USE_BLOBS is not set CONFIG_VENDOR_GOOGLE=y CONFIG_CBFS_SIZE=0x00800000 CONFIG_BOARD_GOOGLE_KEVIN=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_UART_PCI_ADDR=0x0 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 CONFIG_PAYLOAD_FIT_SUPPORT=y Most things work, but one significant problem is that the board can't power off properly. It also happens with my manual U-Boot-only builds, but not when I manually build coreboot with a U-Boot payload. Not sure why it is happening here as well. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-03-13specifically call python3, in scriptsLeah Rowe
with this change, it's unlikely we'll hit errors again. previously, some projects used were calling "python" which in context was python3, but on some setups, the user only has python2 and python3 but no symlink for "python" (which if exists, we assumed linked to python3) now it's unambiguous. docs/build/ can probably be updated now, as a result of this change, to remove the advice about that
2021-12-29coreboot/*: set grub_scan_disk to ahci on most boardsLeah Rowe
on ga-g41m-es2l, set it to ata
2021-12-29apple/macbook21: set grub_scan_disk to ahciLeah Rowe
2021-12-20lenovo/r400: disable death beepsLeah Rowe
2021-12-11coreboot configs: don't enable wifi during early initLeah Rowe
2021-12-11coreboot configs: disable serial output during coreboot initializationLeah Rowe
2021-12-07macbook21_16mb: always clear DRAM on regular bootLeah Rowe
2021-12-07Add macbook*1 16mb configsVitali64
2021-12-01Fix broken SpeedStep on GM45 laptops such as ThinkPad X200, T400, T500, W500Leah Rowe
Coreboot is enabling PECI on these CPUs which, according to Intel erratum, must only be done after loading microcode updates, otherwise the CPUID feature set becomes corrupted. That's my understanding, and I think this is why SpeedStep is broken. To be specific, it could but but operating systems no longer detect that the feature is supported. In any case, belgin on IRC found the commit in coreboot, after a bisect, enabling PECI. This commit in Libreboot adds a patch, reverting coreboot's PECI patch.
2021-11-22update coreboot and nuke tianocore20211122Leah Rowe
tianocore is a liability for the libreboot project. it's a bloated mess, and unreliable, broken on many boards, and basically impossible to audit. i don't trust tianocore, so i'm removing it.
2021-11-01build/roms: add g43t-am3_16mb configLeah Rowe
2021-11-01build/roms: add d945gclf_16mbLeah Rowe
2021-11-01build/roms: add 16mb d510mo configLeah Rowe
you must de-solder the default chip and install the new one. winbond w25q128fvsig is a nice choice of 16MB (128Mbit) IC
2021-11-01Include memtest86+ on setups where this is practicalLeah Rowe
2021-11-01nuke d8/d16 configs for 4mb/8mb setups. only have 2mb and 16mb configsLeah Rowe
4mb and 8mb users can just pad their roms to 16mb, using the instructions on <https://libreboot.org/faq.html#how-do-i-pad-a-rom-before-flashing> maintaining them in lbmk is a waste of time, and also a hazard because it's a lot of duplicated labour when making any changes, which could result in awful mistakes being made
2021-11-01build/boot/roms: add t60_16mb_intelgpu configsLeah Rowe
2021-11-01build/boot/roms: add x60_16mb configsLeah Rowe
2021-10-31lenovo/t400: Enable all SATA ports (add persmule's patch)Leah Rowe
See: <https://lists.nongnu.org/archive/html/libreboot/2016-08/msg00063.html> This enables all SATA ports, allowing full T400s compatibility. T400s already works just fine, when flashing a T400 ROM, but not all SATA ports were usable. The specific patch is here: <https://lists.nongnu.org/archive/html/libreboot/2016-08/txtgT_L8DC94R.txt> There was also this patch, which coreboot actually adapted upstream: <https://lists.nongnu.org/archive/html/libreboot/2016-08/txtMXyws85Q_P.txt> Yes, this patch was submitted in 2016. I overlooked it, during all this time.
2021-10-31re-add grub backgrounds and update grub. mitigate missing charactersLeah Rowe
mitigate missing characters in unifont for border/arrow characters. this saves space because now it is no longer necessary to add a custom font the background added has the libreboot logo on it, and it's 10kb in size unlike the old gnulove background that was hundreds of KB
2021-10-30Disable PIKE2008 option ROM loading on KGPE-D16/KCMA-D8Leah Rowe
These option ROMs are known to cause a system hang. If you insert an empty option ROM into CBFS, it disables any option ROM loading for those devices when using SeaBIOS.
2021-10-30update to coreboot master on macbook21, and add vitali64's cstate 3 patchLeah Rowe
improved battery life on macbook21
2021-08-23coreboot/default: Fix Werror when building ThinkPad T400 imagesLeah Rowe
2021-08-23coreboot: revert cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRRLeah Rowe
This fixes issue 3: https://notabug.org/libreboot/lbmk/issues/3 In this issue, GM45 laptops such as X200/T400 will hang on reboot (normal boot works, and shutting down works too).
2021-05-22board/x301: add new boardLeah Rowe
similar to x200
2021-05-22board/d945gclf/cfg: re-do configLeah Rowe
2021-05-22board/d510mo/cfg: re-do configLeah Rowe
2021-05-22board/d510mo/cfg: enable payload_grub_withseabiosLeah Rowe
2021-05-22board/kfsn4-dre/cfg: re-do config. 1mb and 2mb roms availableLeah Rowe
libgfxinit_txtmode with seabios only
2021-05-22board/g43t-am3/cfg: re-do configs. libgfxinit_txtmode onlyLeah Rowe
For add-on GPU, use one of the SeaBIOS images.
2021-05-22board/ga-g41m-es2l/cfg: re-do config. libgfxinit_txtmode onlyLeah Rowe
Use seabios ROM if you want to use an add-on GPU. seabios_withgrub and seabios_grubfirst are also available.
2021-05-22board/ga-g41m-es2l/cfg: enable payload_grub_withseabiosLeah Rowe
SeaBIOS should fit nicely, now that memtest is disabled
2021-05-22build/roms: re-do KCMA-D8 and KGPE-D16 configsLeah Rowe
2MiB and 16MiB were the only flash sizes supported. 4 and 8MiB have been added. Now there are only libgfxinit_txtmode configs. Use seabios_withgrub or seabios_grubfirst ROMs if you wish to use an add-on GPU.
2021-05-18libreboot!Leah Rowe
this is forked from the "libre" branch in osboot, which is itself a libre, deblobbed fork of osboot, a blobbed up fork of libreboot libreboot needed to be purged clean. this is the new libreboot development repository. the old one has been abandoned
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-26 18:18:46 +0000