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it's a bit buggy when building. disable for now.
will re-visit later.
Signed-off-by: Leah Rowe <leah@libreboot.org>
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the upstream link died. this patch makes it grab the
acpica tarball (for iasl) via libreboot rsync, where
i've added the corresponding tarball
Signed-off-by: Leah Rowe <leah@libreboot.org>
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Libreboot 20220710 was the last release to support these
boards. I plan to eventually port code differences between
D8/D16 to Dasharo, for KCMA-D8 support in Dasharo, to then
use in Libreboot for both KCMA-D8 and KGPE-D16, but I have
no plans to update the KFSN4-DRE code, at least for now.
Libreboot 20220710 used coreboot 4.11, whereas this patch
makes use of coreboot 4.11_branch; the crossgcc toolchains
no longer compile on modern distros, so I spent time patching
those (tested in Debian Sid, will also work on Arch Linux and
so on).
The acpica downloads now fail, in 4.11_branch, because Intel
made some changes upstream for these tarball downloads. Newer
coreboot works around this by grabbing tarballs from github,
itself a non-ideal solution, but I digress; this patch changes
coreboot crossgcc (in 4.11_branch) to download the acpica
tarball from libreboot rsync, where I've added it.
This patch also re-introduces the PIKE2008 fix, where empty
option ROMs for these are inserted into CBFS. This prevents
SeaBIOS from loading the real option ROMs, which would cause
SeaBIOS to hang. This means that SAS drives are not supported
in SeaBIOS, for these boards in Libreboot.
I previously said, in the Censored Libreboot c20230710
announcement, that I would *only* merge D8/D16 when I've
added Dasharo support to Libreboot, and use that, but the
work to make coreboot 4.11_branch compile is something I'm
quite proud of and I see no reason to exclude from lbmk
master branch.
Honestly, there's not much different than 4.11, code-wise.
I *probably* won't use 4.11_branch for the next Libreboot
release, on D8/D16. By then, I might have Dasharo integrated
in lbmk instead. We shall see.
Signed-off-by: Leah Rowe <leah@libreboot.org>
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upstream died. i put the corresponding tarball on
libreboot rsync. this is used by the coreboot build
system, specifically in crossgcc (cross compilers)
Signed-off-by: Leah Rowe <leah@libreboot.org>
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This reverts commit 2099545078d5a5586743d32b2470a296b66cb5c7.
Wasn't this config's fault, the problem happens elsewhere too.
I'm going to revert build/boot/roms to an older version and backport
a few recent changes, to see if that fixes the problem. If it does,
then I know that the recent linker issues happen due to recent changes
in build/boot/roms
The linker errors typically appear in util/kconfig/ but can happen
elsewhere, seemingly random, which means I'm not handling distclean
properly. Something isn't getting cleaned properly.
Signed-off-by: Leah Rowe <leah@libreboot.org>
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This reverts commit 0f7a5386b9219111418a8de8637039c8533d99ea.
Random linker errors, must investigate after release.
Signed-off-by: Leah Rowe <leah@libreboot.org>
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I don't know why, but removing this BL31 make argument lets gru-kevin
power off properly when shut down from Linux. Needs investigation.
Do it as a cros-only HACK patch so people don't have to hold the power
button after every shutdown.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
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turns out it's just picky ram.
errant reports of "no boot" (users did not have debug
dongles) were likely "bad" ram
notes will be written on libreboot.org about this
Signed-off-by: Leah Rowe <leah@libreboot.org>
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not well-tested, and existing testing has revealed video
issues on some of them (or just no boot)
for now, retain only qemu and gru-* on arm
Signed-off-by: Leah Rowe <leah@libreboot.org>
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t440pmrc_12mb is the blob one.
t440p_12mb is the libre one, but this isn't clear.
rename accordingly.
Signed-off-by: Leah Rowe <leah@libreboot.org>
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From now on, the following rules are available for all
mainboards, in resources/coreboot/boardname/board.cfg:
* blobs_required="n" or "y"
* microcode_required="n" or "y"
The blobs setting, if set to "n", simply renames filename.rom to
filename_noblobs.rom.
The microcode setting, if set to "n", copies the ROM (with or
without _noblobs) to filename_nomicrocode.rom (if blobs="n",
it would be filename_noblobs_nomicrocode.rom).
Where "nomicrocode" is set, ROMs with microcode will still be
provided by lbmk and in relesase, but ROMs will also be provided
alongside it that lacks any microcode updates.
If the *original* ROM already lacks microcode updates, then the
original ROM will be *renamed* to include "nomicrocode" in the name.
This is done on images for ARM platforms, for instance, where
microcode is never used whatsoever.
Example filenames now generated:
seabios_e6400_4mb_libgfxinit_corebootfb_noblobs_nomicrocode.rom
seabios_e6400_4mb_libgfxinit_corebootfb_noblobs.rom
seabios_withgrub_hp8300usdt_16mb_libgfxinit_corebootfb_colemak_nomicrocode.rom
seabios_withgrub_hp8300usdt_16mb_libgfxinit_corebootfb_colemak.rom
uboot_payload_gru_kevin_libgfxinit_corebootfb_noblobs_nomicrocode.rom
A vocal minority of people were not happy with some of the changes
made in Libreboot last year, including on existing supported
hardware from before those changes were made. I did this before the
last release, out of respect:
https://libreboot.org/news/gm45microcode.html
(re-add mitigations for no-microcode setup on GM45)
This new change is done as an further, extended courtesy. Tested
and works fine. (testing using cbfstool-print)
Actual Libreboot policy about binary blobs is nuanced. See:
https://libreboot.org/news/policy.html (reduction policy) and:
https://libreboot.org/freedom-status.html (implementation)
Well, the status page talks about descriptor vs non-descriptor
on Intel platforms, and where me_cleaner is used (on platforms
that need Intel ME firmware), it regards the descriptored setups
to be blob-free if coreboot does not require binary blobs.
In this paradigm, microcode updates are not considered to be
binary blobs, because they aren't technically software, they're
more like config files that just turn certain features on or off
within the CPU.
However, for lbmk purposes, "noblobs" means that, after the ROM
is fully ready to flash on the chip, there will be no blobs in
it (except microcode). So for example, an X200 that does not
require ME firmware is considered blob-free under this paradigm,
even though Libreboot policy regards X230 as equally libre when
me_cleaner is used; in this setup, ROMs will not contain "blobfree"
in the filename, for X230 (as one example).
Signed-off-by: Leah Rowe <leah@libreboot.org>
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Still on Gerrit. ME downloader failed with HP update file, so let's just
use Lenovo's instead. Both contain identical ME8_5M_Production.bin files.
Tested and working:
* Native raminit with both DIMMs
* Libgfxinit textmode and framebuffer on both DisplayPorts and VGA
* External USB2 and USB3 ports: they all work
* USB 3.0 SuperSpeed (rear, 4 ports)
* Ethernet
* Mini-PCIe WLAN
* SATA: 2.5" SSD and optical drive bay
* SeaBIOS and GRUB (boot to linux)
* PS/2 keyboard and mouse
* S3 suspend and resume, wake using USB keyboard
* Headphone output, line out, internal speaker
* Wake on LAN
* Rebooting
* CMOS options & nvramcui
Untested:
* Line in, mic input
* MXM graphics card
* EHCI debug
Not working:
* Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so
maybe it just isn't present
* PS/2 keyboard wake from S3
* mSATA (I have no mSATA drives)
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Tested with Johan Ehnberg (johan@molnix.com)
The following is tested and confirmed working:
- backlight control
- touchpad
- USB (external, smart card, fingerprint, bluetooth, webcam, WWAN)
- touchpad
- Wi-Fi
- 2,5" SATA
- USB 3.0
- SD card
- Memory: 2+2 (matched or unmatched), 8+2, 8+8
- internal flashing from libreboot
- SeaBIOS and GRUB payloads
- Boots Devuan and Ubuntu
Untested:
- ExpressCard
- DVD
- dock
- external displays
- eSATA
- trackpoint (not present on this aftermarket keyboard)
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This fixes the PCI interrupt routing tables for the E6400 so that the SD
card works. It is already merged in upstream but libreboot has not yet
updated coreboot.
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This is useful for internally flashing Libreboot from OEM BIOS
since the top ~3MB is write-protected by vendor firmware.
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I added this in upstream to prevent people from accidentally flashing
roms without a payload resulting in a no boot situation, but in
libreboot lbmk handles the payload and thus this warning always comes
up. This has caused confusion and concern so just patch it out.
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users reported it doesn't boot in recent releases, with the
february 2023 coreboot revision update
i have one in the lab, i'll just re-test it and fix whatever's
wrong for a future release
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python 3 is default now, in all the distros
specifically calling "python3" often doesn't work anymore
python2 is obsolete
let python2 die
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nobody will bother to upgrade the flash on those machines
not much point maintaining the 8/16mb versions
might aswell do just the _4mb version
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This reverts commit fe2b72035fb58d2c0792daa62aa346da710f04a3.
The GRUB patch to fix the E6400 broke other systems and has been
reverted. As a result, GRUB needs to be disabled again on the E6400
until a better fix has been created.
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This reverts commit 1497ae045104145de677fd151da4de6e92be4e5a.
The blanket GRUB patch seems to break PS/2 keyboard handling across
other platforms, so revert it.
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This reverts commit 7bc4dc32ac3e430e50ace3a2876cf501f647b89f.
The E6400 keyboard should work in GRUB now so we can reenable it.
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This introduces a patch to grub which disables the coreboot
specific handling, allowing PS/2 keyboards to be handled the
same as i386-pc. However this alone breaks the keyboard in
Linux, requiring coreboot to perform PS/2 initialization.
I think GRUB may be restoring the original configuration of
the PS/2 controller once it exits, and if coreboot doesn't
initialize the controller then it's restored to the default
state which Linux doesn't seem to like. I think the emulated
keyboard interface provided by the EC on the E6400 behaves
in a non-standard way that is incompatible with the old
coreboot specific handling.
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ps/2 internal keyboard faulty in grub target
i386-coreboot, according to nic3-14159
normal i386-pc grub (bios grub) is fine,
booted from seabios
it is being investigated
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Tested the 4MiB ROMs but not the 8 or 16 MiB ones. This uses the same
board.cfg as the GM45 ThinkPads with an IFD+GBE from ich9gen.
Known issues:
- The internal keyboard does not work properly in GRUB. It seems like
the keyboard controller is outputing set 1 (XT) scancodes, but GRUB
is interpreting them as set 2 (AT) scancodes. This may also have
something to do with scancode translation. However, the keyboard works
fine in SeaBIOS and Linux. USB keyboards also work properly.
- The subsystem IDs in the GBE region are hardcoded for a Thinkpad in
ich9gen, though this doesn't seem to cause issues in Linux. The vendor
IFD and GBE region do have some differences from the generated
binaries, though they do not appear to be critical.
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libreboot will still include microcode updates
by default, but mitigations against broken speedstep
and reboot (when microcode updates are excluded) were
removed following the merge with osboot
this patch restores those mitigations; the patch
reverts coreboot to older smrr code (which works fine, it
isn't critical to use the new behaviour) and disables peci
(pointless feature)
i'll probably re-tool this later to apply the changes
conditionally to whether ucode is present
this is not a change in policy. policy says:
include cpu microcode updates by default
policy also says:
libreboot must be configurable
microcode removal via cbfstool remove -n, counts as
configuration, and in practise is not possible on
gm45 patches in current libreboot; this patch corrects
that problem, allowing the machines to work somewhat
well (same stability issues as before, like MCE errors
resulting in kernel panic on high CPU/memory usage,
but i digress)
happy... hacking
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bl1 bootloader blobs needed, and lbmk doesn't currently
auto-download these for insertion, so their presence in
the build system is problematic because people might build
these and think they work - they don't, due to the lack of
those bl1 blobs
notes about this are included in lbwww, on the compatibility
list. these can be re-added and tested later, when lbmk handles
those bl1 bootloader blobs
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u-boot is known broken on these, last revision
known working is 2021.01
can bisect and find the fix. i'm putting this on
the issue tracker (new one on codeberg)
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i overlooked this one. the normal one was removed,
due to boot issues with the board. i need to look
at this board before re-adding it to libreboot
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these boards are almost impossible to find, and have always been
buggy, it doesn't look like there will be any viable testing or
development on it
it's currently broken in master, on coreboot. if someone wants to
fix and re-add to lbmk, they can do that
use older libreboot releases to flash this board, if you wish
(i *am* adding te the issue tracker, a note about this commit,
with a view to re-adding it one day)
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rename board configs, and add to sources file the
t530/w530 boards
in some situations, the files weren't being downloaded
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MRC caches in a certain way, that Heads was able to work
around in their build system, for this board.
I've adapted the relevant config differences, from their project
as of heads revision 96440b928acb06de5b925ea12014c9c280b23165
The downside is that CBFS now has to be 8MB in size. The upside
is that the machine also boots much faster
See:
https://github.com/osresearch/heads/pull/1282/commits/f0792117efa177ded19878f652c5a28e8cc62a71
https://github.com/osresearch/heads/pull/1282#issuecomment-1400634600
I have not adapted their IFD changes, versus Libreboot, because theirs
simply has a different version string, and uses different read/write
permission bits for regions as defined in the IFD.
This affects:
t440p_12mb_mrc
w541_12mb_mrc
S3 suspend/resume still broken on these targets which use the libre
MRC init (replacement code by Angel Pons, recently merged in lbmk):
t440p_12mb
w541_12mb
With clever use of FMAP, the rest of the BIOS region might still be
used. However, for our purposes, 8MB CBFS will do just fine.
Heads's changes configure MRC so that caching is handled properly,
for when the machine returns from sleep. Setting CBFS to be any
higher will result in slower boot times, and broken S3 resume, due
to MRC cache misalignment (this is based on my understanding, reading
through the Heads project looking at their research on this).
At some point in the future, Angel's libre MRC code will probably
be finished, and merged, with more fine tuning possible to allow
bigger CBFS sizes.
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libre mrc on haswell is quite buggy for now, but works in
a limited fashion
this patch re-adds the old configs, but as _mrc for example
t440p_12mb_mrc instead of t440p_12mb
and t440p_12mb (without _mrc) still uses the libre mrc code
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i found that with libre mrc, usb was broken in grub
however, it worked nicely in seabios
for our purposes, doing seabios-only roms in text mode
is best for now
i'm going to re-add mrc.bin, but for t440p_12mb_mrc
and w541_12mb_mrc, as new config names. the regular
t440p_12mb and w541_12mb will continue to use libre
mrc, but the _mrc ones will use mrc.bin and retain the
grub payload in board.cfg
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untested. removing.
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courtesy of Angel Pons from the coreboot project
this uses the following patch set from gerrit, as yet
unmerged (in coreboot master) on this date:
https://review.coreboot.org/c/coreboot/+/64198/5
logic for downloading mrc blobs has been deleted from
lbmk, as this is now completely obsolete (for haswell
boards)
if other platforms are added later that need mrc.bin,
then logic will be re-added again for that
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they don't even boot in pcbox properly, and the real
hardware is not much to talk about
useless port
delete
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using the same method as the previous patch for t440p
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352MB VRAM causes stability issues, according to some reports
users can still set it to the higher level when building, if
they wish to
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