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Coreboot is enabling PECI on these CPUs which, according to Intel erratum, must
only be done after loading microcode updates, otherwise the CPUID feature set
becomes corrupted. That's my understanding, and I think this is why SpeedStep
is broken. To be specific, it could but but operating systems no longer detect
that the feature is supported. In any case, belgin on IRC found the commit in
coreboot, after a bisect, enabling PECI. This commit in Libreboot adds a patch,
reverting coreboot's PECI patch.
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tianocore is a liability for the libreboot project. it's a bloated mess, and
unreliable, broken on many boards, and basically impossible to audit.
i don't trust tianocore, so i'm removing it.
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See:
<https://lists.nongnu.org/archive/html/libreboot/2016-08/msg00063.html>
This enables all SATA ports, allowing full T400s compatibility. T400s already
works just fine, when flashing a T400 ROM, but not all SATA ports were usable.
The specific patch is here:
<https://lists.nongnu.org/archive/html/libreboot/2016-08/txtgT_L8DC94R.txt>
There was also this patch, which coreboot actually adapted upstream:
<https://lists.nongnu.org/archive/html/libreboot/2016-08/txtMXyws85Q_P.txt>
Yes, this patch was submitted in 2016. I overlooked it, during all this time.
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mitigate missing characters in unifont for border/arrow characters. this saves
space because now it is no longer necessary to add a custom font
the background added has the libreboot logo on it, and it's 10kb in size unlike
the old gnulove background that was hundreds of KB
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This fixes issue 3:
https://notabug.org/libreboot/lbmk/issues/3
In this issue, GM45 laptops such as X200/T400 will hang on reboot (normal boot
works, and shutting down works too).
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this is forked from the "libre" branch in osboot, which is itself a libre,
deblobbed fork of osboot, a blobbed up fork of libreboot
libreboot needed to be purged clean. this is the new libreboot development
repository. the old one has been abandoned
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