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libreboot will still include microcode updates
by default, but mitigations against broken speedstep
and reboot (when microcode updates are excluded) were
removed following the merge with osboot
this patch restores those mitigations; the patch
reverts coreboot to older smrr code (which works fine, it
isn't critical to use the new behaviour) and disables peci
(pointless feature)
i'll probably re-tool this later to apply the changes
conditionally to whether ucode is present
this is not a change in policy. policy says:
include cpu microcode updates by default
policy also says:
libreboot must be configurable
microcode removal via cbfstool remove -n, counts as
configuration, and in practise is not possible on
gm45 patches in current libreboot; this patch corrects
that problem, allowing the machines to work somewhat
well (same stability issues as before, like MCE errors
resulting in kernel panic on high CPU/memory usage,
but i digress)
happy... hacking
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352MB VRAM causes stability issues, according to some reports
users can still set it to the higher level when building, if
they wish to
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e.g.
./ifdtool --nuke me coreboot.rom
this will be used by rom release build scripts, to scrub
stuff like intel me from the rom
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New x230edp_12mb target uses the
https://review.coreboot.org/c/coreboot/+/28950 patchset to add an
X230_EDP target to the default coreboot branch.
Consequently the "fhd" coreboot branch is no longer needed and has
been safely removed.
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backported from newer coreboot revisions, see patch
coreboot/default/patches/0014-coreboot-default-fix-crossgcc-build.patch
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osboot is now part of libreboot, and will soon shut down.
libreboot now conforms to osboot policy.
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with this change, it's unlikely we'll hit errors again. previously,
some projects used were calling "python" which in context was
python3, but on some setups, the user only has python2 and python3
but no symlink for "python" (which if exists, we assumed linked to
python3)
now it's unambiguous. docs/build/ can probably be updated now, as
a result of this change, to remove the advice about that
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Coreboot is enabling PECI on these CPUs which, according to Intel erratum, must
only be done after loading microcode updates, otherwise the CPUID feature set
becomes corrupted. That's my understanding, and I think this is why SpeedStep
is broken. To be specific, it could but but operating systems no longer detect
that the feature is supported. In any case, belgin on IRC found the commit in
coreboot, after a bisect, enabling PECI. This commit in Libreboot adds a patch,
reverting coreboot's PECI patch.
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tianocore is a liability for the libreboot project. it's a bloated mess, and
unreliable, broken on many boards, and basically impossible to audit.
i don't trust tianocore, so i'm removing it.
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See:
<https://lists.nongnu.org/archive/html/libreboot/2016-08/msg00063.html>
This enables all SATA ports, allowing full T400s compatibility. T400s already
works just fine, when flashing a T400 ROM, but not all SATA ports were usable.
The specific patch is here:
<https://lists.nongnu.org/archive/html/libreboot/2016-08/txtgT_L8DC94R.txt>
There was also this patch, which coreboot actually adapted upstream:
<https://lists.nongnu.org/archive/html/libreboot/2016-08/txtMXyws85Q_P.txt>
Yes, this patch was submitted in 2016. I overlooked it, during all this time.
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mitigate missing characters in unifont for border/arrow characters. this saves
space because now it is no longer necessary to add a custom font
the background added has the libreboot logo on it, and it's 10kb in size unlike
the old gnulove background that was hundreds of KB
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This fixes issue 3:
https://notabug.org/libreboot/lbmk/issues/3
In this issue, GM45 laptops such as X200/T400 will hang on reboot (normal boot
works, and shutting down works too).
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this is forked from the "libre" branch in osboot, which is itself a libre,
deblobbed fork of osboot, a blobbed up fork of libreboot
libreboot needed to be purged clean. this is the new libreboot development
repository. the old one has been abandoned
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