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2024-02-12Add HP EliteBook 8560wRiku Viitanen
Iru Cai's port from Gerrit: https://review.coreboot.org/c/coreboot/+/39398 Now with the proper MXM structure, which removes the 30 second POST delay. Tested with i7-2670QM, Quadro 2000M and 32GB RAM. Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2024-02-07Merge pull request 'Add Latitude E6420, E6520, and E5530' (#183) from ↵Leah Rowe
nic3-14159/lbmk:latitude-ports into master Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/183
2024-02-06config: Add Dell Latitude E5530Nicholas Chin
Tested by Martin Dawson. Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-02-06config: Add Dell Latitude E6520Nicholas Chin
Tested by Martin Dawson. Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-02-06config: Add Dell Latitude E6420Nicholas Chin
Tested by Martin Dawson. Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-02-03import dell optiplex 7020/9020 patch from gerritLeah Rowe
coreboot gerrit patch 55232, patchset 31 the actual board will be enabled in a follow-up patch. merging the patch on its own first is better practise, to run ./update trees -u coreboot this way, there won't be a revision that breaks builds, due to the idiosyncratic nature of coreboot configuration. Signed-off-by: Leah Rowe <info@minifree.org>
2024-01-25dell/e6*30: use generic PS2K/PS2M EISAID stringsLeah Rowe
CONFIG_PS2M_EISAID. this is a a string used for the identifier on the mouse, in ACPI. CONFIG_PS2K_EISAID this is used for the keyboard. IASL comes back with this build error: dsdt.asl 1884: Name(_HID, EISAID("DLLK0534")) Error 6045 - ^ EISAID string must be of the form "UUUXXXX" (3 uppercase, 4 hex digits) (DLLK0534) Change DLLK0534 back to PNP0303 and change DLL0534 back to PNP0F13. These are generic identifiers for PS/2 keyboard and mouse. Any generic driver will work with the onboard mouse/keyboard on these machines. They do not need to be changed. These are the default values anyway. Just leave them explicitly defined to the default values, for now; if these options are not set, coreboot will default to these values. This shouldn't break anything for the users. I've reported this to Nicholas Chin, author of those patches. Libreboot imported the new versions of E6430/E6530 board patches in the coreboot revision update, but the new (technically correct) values broke IASL, so I've decided to use the old values for now. Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-01-25coreboot/default: update coreboot to January 2024Leah Rowe
Base revision changed to: commit b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a Author: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Date: Fri Jan 5 16:48:17 2024 +0800 mb/google/dedede/var/metaknight:Add fw_config probe for multi codec and amplifier Of note: Several out-of-tree ports have been adjusted to use the new SPD config style, where it is defined in devicetree. I manually updated the E6530 patch myself, based on the update that Nicholas did on E6430 (Nicholas will later update the E6530 patch himself, and I'll re-merge the patch). Several upstream patches now exist in this revision, that we were able to remove from lbmk. The heap size patch was reverted upstream, as we did, but see: https://review.coreboot.org/c/coreboot/+/80023 https://review.coreboot.org/c/coreboot/+/79525 Although we still disable the TSEG Stage Cache, ivy/sandy/haswell should be reliable on S3 now (leaving TSEG Stage Cache disabled, for now, anyway). Also included in upstream now: commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94 Author: Bill Xie <persmule@hardenedlinux.org> Date: Sat Oct 7 01:32:51 2023 +0800 drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume Further patches from upstream: commit 432e92688eca0e85cbaebca3232f65936b305a98 Author: Bill Xie <persmule@hardenedlinux.org> Date: Fri Nov 3 12:34:01 2023 +0800 drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum This should fix S3 on GM45 thinkpads. Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-01-21coreboot/*/target.cfg: don't define xarchLeah Rowe
it's defined per board Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-01-10NEW MAINBOARD: HP EliteBook 820 G2Leah Rowe
This is of Broadwell platform, one generation above Haswell. Of note: this uses HP Sure Start. Although the flash is 16MB, our CBFS section (and IFD configuration) assumes 12MB flash, so the final 4MB will be left unflashed on installation, after blanking the private flash. The coreboot documents have more information about this. Some minor design changes in lbmk were made, to accomodate this port: Support for extracting refcode binaries added (pulled from Google recovery images). The refcode file is an ELF that initialises the MRC and the PCH. It is also responsible for enabling or disabling the Intel GbE device, where Google does not enable it, but lbmk modifies it per the instructions on the coreboot documentation, so as to enable Intel GbE. Google's recovery image stores the refcode as a stage file, but coreboot changed the format (for CBFS files) after 4.13 so coreboot 4.13's cbfstool is used to extract refcode. This realisation made me also change the script logic to use a cbfstool and ifdtool version matching the coreboot tree, for all parts of lbmk, whereas lbmk previously used only the default tree for cbfstool/ifdtool, on insertion and deletion of vendor files - it was 81dc20e744 that broke extraction of refcode on google's recovery images, where google used an older version of cbfstool to insert the files in their coreboot ROMs. A further backported patch has been added, copying coreboot revision f22f408956 which is a build fix from Nico Huber. Iru Cai submitted an ACPI bugfix after the revision lbmk currently uses, for coreboot/default, and this fix is needed for rebooting to work on Linux 6.1 or higher. This patch has been backported to lbmk, while it still uses the same October 2023 revision of coreboot. Broadwell MRC is inserted at the same offset as Haswell, so I didn't need to tweak that. Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-12-27update/trees: further simplify crossgcc handlingLeah Rowe
arch no longer needs to be set, on multi-tree projects, and it has been renamed to xarch the new behaviour is: if xarch is set, treat it as a list of crossgcc targets and go through the list. set the first one as the target, for what lbmk builds, but build all of the defined crossgccc targets crossgcc_ada is now xlang, and defines which languages to build, rather than whether to build gcc-gnat Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-12-24Add HP 8300 CMT portRiku Viitanen
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2023-12-21build/roms: remove modify_coreboot_rom()Leah Rowe
don't handle "romtype" at all, in board target.cfg files add /dev/null as pike2008 rom on amd boards. this serves the same purpose, adding them as empty vga roms, to add an empty rom in cbfs. pike2008 cards cause seabios to hang, when their oproms are executed, so we insert a fake rom on i945 thinkpads, use the coreboot config option: CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK when set, this enables the same bootblock copy, for use with bucts. these two cases, namely pike2008 roms and i945 bootblock copies, no longer need to be handled in code Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-12-21update/trees: simplified crossgcc handlingLeah Rowe
only call crossgcc for coreboot and u-boot, but use hostcc for everything else. simplify the checking of which architecture to compile for. "arch" in target.cfg files has been modified, to allow further simplification. without this patch, the logic currently only *barely* avoids using crossgcc on things like utils, and only works in practise because, in practise, lbmk only works on x86_64 anyway. the new logic, as per this patch, is simpler and more robust. Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-12-19Add HP EliteBook 8460pRiku Viitanen
Inside the BIOS update, there's 68SCE and 68SCF variants. Based on Qubes HCL and browsing linux-hardware.org, these are Probook 6360b and Elitebook 8460p respectively. I checked the KBC1126 EC Firmwares within the update file, both use the exact same firmware images. Following-up will be a very similar but untested port for 6360b. Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2023-12-17added x220edp_8mbrisapav
2023-11-05Add Dell Latitude E6530 supportNicholas Chin
This is pretty much the same as the E6430 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-11-05use mirrorservice.org for gcc downloadsLeah Rowe
the gnu.org 302 redirect often fails Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-11-05Merge pull request 'Enable VBT for E6430' (#147) from ↵Leah Rowe
nic3-14159/lbmk:enable-e6430-vbt into master Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/147
2023-11-05coreboot/dell: move e6400 to new tree, dellLeah Rowe
the ddr2 fix broke *ddr3* on gm45 thinkpads in testing, depending on memory modules. this was established by removing patches, re-doing configs etc, on a user's X200 (testing gentoo and freebsd). the X200 kept randomly rebooting or having random glitches. the configs themselves (gm45 thinkpads) will also be re-done, because i found minor issues unrelated, but this patch moves dell e6400 to its own tree. the ddr2 fix is no longer present in coreboot/default, only coreboot/dell. i noticed minor differences in gm45 thinkpad configs, when re-doing the configs, versus what are currently in lbmk master; for instance, vbt was not enabled anymore, on thinkpad x200. modifications to these will be done separately. Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-11-05Dell E6430: use ME Soft Temporary DisableLeah Rowe
me_state=Disabled in cmos.default Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-11-04Enable VBT for E6430Nicholas Chin
The original E6430 patch included the Intel VBT file, but did not actually enable it in Kconfig. Update the patch to enable it and update the E6430 configs.
2023-10-31Revert "coreboot/default: use alternative heap size fix"Leah Rowe
This reverts commit 29e9c32e32f8e947f51a3efe375dab3ef8e1987e.
2023-10-31crank up vram allocation on more intel boardsLeah Rowe
it's preferable that the vram setting be as high as feasible, for users. we overlooked this on some newer platforms that were added, over several releases. these levels won't offend most users, and people who want less can always turn it down Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-10-31coreboot/default: use alternative heap size fixLeah Rowe
My previous fix to revert didn't fix S3 on GM45, one of the platforms reported fixed by 78263; I'm merging that instead, at patch set 10. It is referenced by 78815/1 which was split from it, so merge that too (restores overrides of higher values, on certain platforms that we don't use yet). https://review.coreboot.org/c/coreboot/+/78623/10 https://review.coreboot.org/c/coreboot/+/78815/1 Accordingly, update configs to match the new default. Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-10-29fix raminit/coldboot on dell e6400Leah Rowe
the patch included in this revision is pulled from: https://review.coreboot.org/c/coreboot/+/54024/2 contrary to hell's assertion of "not for merge", this does in fact work nicely on a dell e6400; nicholas chin tested on e6400 and found that those RCOMP values are the same nicholas was testing some errant modules that seemed to fail raminit in coreboot. in some cases, dell e6400 would regularly fail coldboot even though reboot was ok; this was therefore the cause of suspicioun for it being raminit-related with this patch from hell (Angel Pons, but knows as hell on IRC) it should fix boot issue on Dell Latitude E6400 Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-10-29add heci timeout for ibex peakLeah Rowe
patch courtesy of denis :) Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-10-29revert coreboot heap size patchLeah Rowe
the patch: https://review.coreboot.org/c/coreboot/+/78270 this has been reverted, because it caused s3 resume issues on most intel laptops in libreboot. i was going to merge this instead: https://review.coreboot.org/c/coreboot/+/78623 however, it's under review, and this doesn't change to the old behaviour; it keeps the new universal config, but changes the default we know the old logic works, so keep that for now. in fact, the offending patch was only merged to main in coreboot, one day before i recently updated coreboot revs in coreboot/default - i used a 12 october revision, the patch above is 11 october i then ran "./update trees -u coreboot" which updated the heap sizes back to the old defaults. this should fix s3 suspend/resume where it was broken, in the libreboot 20231021 release - a point release with this and a few other fixes is planned soon. Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-10-25use mirrorservice.org for acpica downloadsLeah Rowe
princeton was down today. kent is probably more reliable. Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-10-22coreboot/default: don't use github on acpica fetch20231021fix2Leah Rowe
github's httpd b0rked the fuck out and i didn't want to wait for them to fix it (ssl cert error) before i continued a build. i now host the relevant acpica tarball on libreboot rsync, mirrored to princeton. Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-10-14coreboot: gru: Use default coreboot treeAlper Nebi Yasak
We don't really need a custom coreboot tree for Chromebooks. I had added one, because at a cursory glance to the available config/coreboot/board subdirectories I had the impression that I should. But upstreams have one tree for every board and I think we should move towards that too. Move the one important BL31 makefile patch into the default coreboot patches, update the gru boards' configs by running savedefconfig in the cros tree and then running olddefconfig in the default tree. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2023-10-12coreboot/default bump: rev d862695f5f, 12 Oct 2023Leah Rowe
Riku's mSATA patch for HP8300USDT was merged upstream, so the patch has been dropped from lbmk because it is contained within this new coreboot revision. Signed-off-by: Leah Rowe <leah@libreboot.org>
2023-09-04merge config/ and resources/Leah Rowe
Signed-off-by: Leah Rowe <leah@libreboot.org>