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-rw-r--r--resources/coreboot/default/blobs.list22
-rw-r--r--resources/coreboot/default/board.cfg32
-rw-r--r--resources/coreboot/default/deblob-check.results.list849
-rw-r--r--resources/coreboot/default/patches/0001-hardcode-tianocore-revisions-and-don-t-automatically.patch128
-rw-r--r--resources/coreboot/default/patches/0002-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch23
-rw-r--r--resources/coreboot/default/patches/0003-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch22
-rw-r--r--resources/coreboot/default/patches/0004-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch23
-rw-r--r--resources/coreboot/default/patches/0005-util-cbfstool-Do-not-set-D_XOPEN_SOURCE-on-FreeBSD.patch46
-rw-r--r--resources/coreboot/default/patches/0006-src-security-intel-stm-Add-warning-for-non-reproduci.patch35
-rw-r--r--resources/coreboot/default/patches/0007-Makefile-Don-t-run-genbuild_h-if-not-doing-a-build.patch36
-rw-r--r--resources/coreboot/default/patches/0008-util-genbuild_h-Update-IASL-location-finding-code.patch74
-rw-r--r--resources/coreboot/default/patches/0009-util-crossgcc-Update-gmp-to-6.2.1.patch54
-rw-r--r--resources/coreboot/default/patches/0010-util-crossgcc-Update-mpc-to-1.2.1.patch48
-rw-r--r--resources/coreboot/default/patches/0011-tests-Enable-config-override-for-tests.patch76
-rw-r--r--resources/coreboot/default/patches/0012-src-Match-array-format-in-function-declarations-and-.patch193
-rw-r--r--resources/coreboot/default/patches/0013-src-security-tpm-Deal-with-zero-length-tlcl-writes.patch36
-rw-r--r--resources/coreboot/default/patches/0014-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch27
-rw-r--r--resources/coreboot/default/patches/0015-lenovo-x200-set-VRAM-to-352MiB-by-default.patch24
-rw-r--r--resources/coreboot/default/patches/0016-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch22
-rw-r--r--resources/coreboot/default/patches/0017-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch22
20 files changed, 1792 insertions, 0 deletions
diff --git a/resources/coreboot/default/blobs.list b/resources/coreboot/default/blobs.list
new file mode 100644
index 00000000..05d3ee48
--- /dev/null
+++ b/resources/coreboot/default/blobs.list
@@ -0,0 +1,22 @@
+src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
+3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
+3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
+3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
+3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
+3rdparty/chromeec/test/legacy_nvmem_dump.h
+3rdparty/vboot/tests/futility/data/bios_link_mp.bin
+3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
+src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
+src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
+src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
+src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
+src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
+src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
+src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
+src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
+src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
+src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
+src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
+src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
+src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h
+3rdparty/chromeec/third_party/bmi260/accelgyro_bmi260_config_tbin.h
diff --git a/resources/coreboot/default/board.cfg b/resources/coreboot/default/board.cfg
new file mode 100644
index 00000000..c20d085f
--- /dev/null
+++ b/resources/coreboot/default/board.cfg
@@ -0,0 +1,32 @@
+cbtree="default"
+romtype="normal"
+cbrevision="a0aee78c8261804e498b3c31bf4b855fb7e7d1cd"
+arch="x86_64"
+payload_grub="n"
+payload_grub_withseabios="n"
+payload_grub_withtianocore="n"
+payload_seabios="n"
+payload_tianocore="n"
+
+# NOTE: 1b242b6618d4cbb80d5b4268ba2b39ae363d96f9 is the last revision checked.
+# Right now, coreboot 4.14 is being used, and specific patches being
+# Backported. Check commits after the above commit ID
+
+# NOTE: for de-blob purposes, 4.14 was used. next time deblobbing, compare
+# files between 4.14 and whatever new version of coreboot is used
+
+# The following patches from coreboot are currently backported to 4.14:
+# 99973d29af774c54e8859d967b2b9617abebeeb0 <-- and this is the last one
+# 40b8f01697d6f26f86de7fbda1d0a160dcd4d5df
+# 5c3b05ecf4dbb89da3dd7bc514875b53e3a8ce1c
+# f963a0f8e5ac5d68b17bb1f703cab617260a3fa6
+# 0afb90a73ba007b3f6dc135ec8105def00182c5f
+# de0fd07ca7f5ca404d1a13c036766c561fd26cd8
+# 6318f1f500b69bbba156ec78598406cf30fd5e02 <-- then this, going all the way up
+# b403da65cddff557da67cabd1a66e1053b8967c7 <-- then this
+# 9a056013411a79ca7973c6a141d78e22949d4553 <-- this first
+
+# Watch this. It may cause some mayhem:
+# https://review.coreboot.org/c/coreboot/+/54301
+# https://review.coreboot.org/c/coreboot/+/54298
+# keep an eye on avph's changes to postcar stage (on various platforms)
diff --git a/resources/coreboot/default/deblob-check.results.list b/resources/coreboot/default/deblob-check.results.list
new file mode 100644
index 00000000..5f18d3c8
--- /dev/null
+++ b/resources/coreboot/default/deblob-check.results.list
@@ -0,0 +1,849 @@
+./3rdparty/arm-trusted-firmware/docs/components/secure-partition-manager.rst
+./3rdparty/arm-trusted-firmware/docs/design/firmware-design.rst
+./3rdparty/arm-trusted-firmware/docs/plat/arm/fvp/index.rst
+./3rdparty/arm-trusted-firmware/drivers/marvell/comphy/phy-comphy-3700.c
+./3rdparty/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+./3rdparty/arm-trusted-firmware/drivers/st/pmic/stpmic1.c
+./3rdparty/arm-trusted-firmware/lib/debugfs/blobs.h
+./3rdparty/arm-trusted-firmware/lib/debugfs/devfip.c
+./3rdparty/arm-trusted-firmware/lib/romlib/gen_combined_bl1_romlib.sh
+./3rdparty/arm-trusted-firmware/lib/zlib/crc32.h
+./3rdparty/arm-trusted-firmware/lib/zlib/inffixed.h
+./3rdparty/arm-trusted-firmware/lib/zlib/inftrees.c
+./3rdparty/arm-trusted-firmware/plat/arm/board/fvp/fvp_io_storage.c
+./3rdparty/arm-trusted-firmware/plat/arm/board/rde1edge/rde1edge_topology.c
+./3rdparty/arm-trusted-firmware/plat/common/plat_bl_common.c
+./3rdparty/arm-trusted-firmware/plat/hisilicon/hikey/hisi_dvfs.c
+./3rdparty/arm-trusted-firmware/plat/hisilicon/poplar/include/platform_def.h
+./3rdparty/arm-trusted-firmware/plat/hisilicon/poplar/include/poplar_layout.h
+./3rdparty/arm-trusted-firmware/plat/intel/soc/agilex/soc/agilex_pinmux.c
+./3rdparty/arm-trusted-firmware/plat/intel/soc/stratix10/soc/s10_pinmux.c
+./3rdparty/arm-trusted-firmware/plat/marvell/armada/a8k/a70x0/board/dram_port.c
+./3rdparty/arm-trusted-firmware/plat/marvell/armada/a8k/a70x0_amc/board/dram_port.c
+./3rdparty/arm-trusted-firmware/plat/marvell/armada/a8k/a80x0/board/dram_port.c
+./3rdparty/arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_mcbin/board/dram_port.c
+./3rdparty/arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c
+./3rdparty/arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
+./3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
+./3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
+./3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
+./3rdparty/arm-trusted-firmware/plat/qemu/common/qemu_io_storage.c
+./3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c
+./3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
+./3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dfs.c
+./3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/startup.c
+./3rdparty/arm-trusted-firmware/plat/rpi/common/rpi3_io_storage.c
+./3rdparty/arm-trusted-firmware/plat/socionext/synquacer/sq_spm.c
+./3rdparty/arm-trusted-firmware/plat/st/stm32mp1/platform.mk
+./3rdparty/arm-trusted-firmware/tools/amlogic/doimage.c
+./3rdparty/arm-trusted-firmware/tools/fiptool/fiptool.c
+./3rdparty/arm-trusted-firmware/tools/sptool/sp_mk_generator.py
+./3rdparty/chromeec/board/bloog/board.c
+./3rdparty/chromeec/board/coffeecake/board.c
+./3rdparty/chromeec/board/cr50/tpm2/ecc.c
+./3rdparty/chromeec/board/cr50/tpm2/endorsement.c
+./3rdparty/chromeec/board/cr50/tpm2/rsa.c
+./3rdparty/chromeec/board/dingdong/board.c
+./3rdparty/chromeec/board/flapjack/battery.c
+./3rdparty/chromeec/board/hoho/board.c
+./3rdparty/chromeec/board/kukui_scp/update_scp
+./3rdparty/chromeec/board/meep/board.c
+./3rdparty/chromeec/chip/g/dcrypto/bn.c
+./3rdparty/chromeec/chip/g/dcrypto/hmac_drbg.c
+./3rdparty/chromeec/chip/mchp/util/pack_ec.py
+./3rdparty/chromeec/chip/mec1322/util/pack_ec.py
+./3rdparty/chromeec/chip/stm32/usb_hid_keyboard.c
+./3rdparty/chromeec/chip/stm32/usb_hid_touchpad.c
+./3rdparty/chromeec/common/crc.c
+./3rdparty/chromeec/common/ctz.c
+./3rdparty/chromeec/common/keyboard_8042_sharedlib.c
+./3rdparty/chromeec/common/lightbar.c
+./3rdparty/chromeec/common/mock/rollback_mock.c
+./3rdparty/chromeec/common/sha256.c
+./3rdparty/chromeec/core/riscv-rv32i/init.S
+./3rdparty/chromeec/driver/als_tcs3400.c
+./3rdparty/chromeec/driver/led/lm3509.c
+./3rdparty/chromeec/driver/regulator_ir357x.c
+./3rdparty/chromeec/driver/touchpad_elan.c
+./3rdparty/chromeec/extra/rma_reset/rma_reset.c
+./3rdparty/chromeec/extra/touchpad_updater/touchpad_updater.c
+./3rdparty/chromeec/extra/usb_updater/fw_update.py
+./3rdparty/chromeec/extra/usb_updater/servo_updater.py
+./3rdparty/chromeec/fuzz/nvmem_tpm2_mock.c
+./3rdparty/chromeec/setup.py
+./3rdparty/chromeec/test/aes.c
+./3rdparty/chromeec/test/fpsensor.c
+./3rdparty/chromeec/test/legacy_nvmem_dump.h
+./3rdparty/chromeec/test/nvmem_tpm2_mock.c
+./3rdparty/chromeec/test/pinweaver.c
+./3rdparty/chromeec/test/rsa2048-3.h
+./3rdparty/chromeec/test/rsa2048-F4.h
+./3rdparty/chromeec/test/sha256.c
+./3rdparty/chromeec/test/test_config.h
+./3rdparty/chromeec/test/thermal.c
+./3rdparty/chromeec/test/tpm_test/rsa_test.py
+./3rdparty/chromeec/test/usb_prl.c
+./3rdparty/chromeec/test/x25519.c
+./3rdparty/chromeec/third_party/boringssl/common/aes.c
+./3rdparty/chromeec/third_party/boringssl/core/cortex-m/aes.S
+./3rdparty/chromeec/util/ec_sb_firmware_update.c
+./3rdparty/chromeec/util/ectool_keyscan.c
+./3rdparty/chromeec/util/flash_ec
+./3rdparty/chromeec/util/flash_fp_mcu
+./3rdparty/chromeec/util/flash_pd.py
+./3rdparty/chromeec/util/signer/create_released_image.sh
+./3rdparty/chromeec/util/uut/lib_crc.c
+./3rdparty/intel-sec-tools/cmd/txt-prov/README.md
+./3rdparty/intel-sec-tools/pkg/hwapi/mock_pc.go
+./3rdparty/intel-sec-tools/pkg/provisioning/structures.go
+./3rdparty/intel-sec-tools/pkg/test/tpm.go
+./3rdparty/intel-sec-tools/pkg/tools/acm_test.go
+./3rdparty/intel-sec-tools/pkg/tools/lcp_test.go
+./3rdparty/libgfxinit/common/skylake/hw-gfx-gma-plls-dpll.adb
+./3rdparty/opensbi/Makefile
+./3rdparty/stm/Stm/StmPkg/Core/CMakeLists.txt
+./3rdparty/stm/Stm/StmPkg/EdkII/BaseTools/Source/Python/AutoGen/ValidCheckingInfoObject.py
+./3rdparty/stm/Stm/StmPkg/EdkII/BaseTools/Source/Python/Common/VpdInfoFile.py
+./3rdparty/vboot/cgpt/cgpt_wrapper.c
+./3rdparty/vboot/firmware/2lib/2sha256.c
+./3rdparty/vboot/firmware/2lib/2sha512.c
+./3rdparty/vboot/firmware/lib/cgptlib/crc32.c
+./3rdparty/vboot/firmware/lib/tpm_lite/include/tlcl_structures.h
+./3rdparty/vboot/futility/cmd_gbb_utility.c
+./3rdparty/vboot/futility/file_type_rwsig.c
+./3rdparty/vboot/futility/updater.c
+./3rdparty/vboot/futility/updater_archive.c
+./3rdparty/vboot/scripts/image_signing/make_dev_firmware.sh
+./3rdparty/vboot/scripts/image_signing/make_dev_ssd.sh
+./3rdparty/vboot/scripts/image_signing/sign_android_image.sh
+./3rdparty/vboot/scripts/image_signing/sign_cr50_firmware.sh
+./3rdparty/vboot/scripts/image_signing/sign_official_build.sh
+./3rdparty/vboot/scripts/image_signing/strip_boot_from_image.sh
+./3rdparty/vboot/scripts/image_signing/tag_image.sh
+./3rdparty/vboot/tests/cgptlib_test.c
+./3rdparty/vboot/tests/crc32_test.c
+./3rdparty/vboot/tests/futility/data/bios_link_mp.bin
+./3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
+./3rdparty/vboot/tests/futility/link_bios.manifest.json
+./3rdparty/vboot/tests/futility/link_image.manifest.json
+./3rdparty/vboot/tests/futility/models/link/setvars.sh
+./3rdparty/vboot/tests/futility/models/peppy/setvars.sh
+./3rdparty/vboot/tests/futility/models/whitetip/setvars.sh
+./3rdparty/vboot/tests/futility/test_dump_fmap.sh
+./3rdparty/vboot/tests/futility/test_file_types.c
+./3rdparty/vboot/tests/futility/test_file_types.sh
+./3rdparty/vboot/tests/futility/test_rwsig.sh
+./3rdparty/vboot/tests/futility/test_sign_firmware.sh
+./3rdparty/vboot/tests/futility/test_update.sh
+./3rdparty/vboot/tests/gen_preamble_testdata.sh
+./3rdparty/vboot/tests/load_kernel_tests.sh
+./3rdparty/vboot/tests/rsa_padding_test.h
+./3rdparty/vboot/tests/run_vbutil_kernel_arg_tests.sh
+./3rdparty/vboot/tests/sha_test_vectors.h
+./3rdparty/vboot/tests/testcases/padding_test_vectors.inc
+./3rdparty/vboot/tests/tlcl_tests.c
+./3rdparty/vboot/tests/vb21_host_misc_tests.c
+./3rdparty/vboot/tests/vb2_api_tests.c
+./3rdparty/vboot/tests/vb2_sha_tests.c
+./3rdparty/vboot/utility/chromeos-tpm-recovery
+./3rdparty/vboot/utility/vbutil_what_keys
+./Documentation/Intel/SoC/soc.html
+./Documentation/releases/coreboot-4.13-relnotes.md
+./Documentation/releases/coreboot-4.2-relnotes.md
+./Documentation/soc/intel/fit.md
+./Documentation/soc/intel/index.md
+./Documentation/soc/intel/microcode.md
+./Documentation/tutorial/part1.md
+./Documentation/codeflow.svg
+./Documentation/hypertransport.svg
+./configs/builder/config.intel.cpx.crb
+./configs/builder/config.lenovo_t420
+./configs/builder/config.lenovo_t420s
+./configs/builder/config.lenovo_t430s
+./configs/builder/config.lenovo_t520
+./configs/builder/config.lenovo_t530
+./configs/builder/config.lenovo_x220
+./configs/builder/config.lenovo_x220i
+./configs/builder/config.lenovo_x230
+./configs/builder/config.ocp.deltalake
+./configs/builder/config.ocp.tiogapass
+./configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms
+./configs/config.intel_coffeelake_rvp11.fsp_car
+./configs/config.purism_librem15_v4.txt_build_test
+./payloads/external/BOOTBOOT/Kconfig
+./payloads/external/FILO/Kconfig
+./payloads/external/GRUB2/Kconfig
+./payloads/external/SeaBIOS/Kconfig
+./payloads/external/U-Boot/Kconfig
+./payloads/external/Yabits/Kconfig
+./payloads/external/depthcharge/Kconfig
+./payloads/libpayload/curses/PDCurses/demos/worm.c
+./payloads/libpayload/curses/PDCurses/sdl1/deffont.h
+./payloads/libpayload/curses/PDCurses/sdl1/deficon.h
+./payloads/libpayload/curses/PDCurses/win32/pdckbd.c
+./payloads/libpayload/curses/PDCurses/x11/big_icon.xbm
+./payloads/libpayload/curses/PDCurses/x11/little_icon.xbm
+./payloads/libpayload/curses/pdcurses-backend/pdcdisp.c
+./payloads/libpayload/curses/tinycurses.c
+./payloads/libpayload/drivers/i8042/keyboard.c
+./payloads/libpayload/drivers/usb/usbmsc.c
+./payloads/libpayload/libc/fpmath.c
+./payloads/libpayload/tests/cbfs-x86-test.c
+./payloads/nvramcui/payload.sh
+./payloads/Kconfig
+./src/cpu/amd/pi/00730F01/Makefile.inc
+./src/cpu/amd/pi/00730F01/model_16_init.c
+./src/cpu/amd/pi/00730F01/update_microcode.c
+./src/cpu/intel/car/non-evict/cache_as_ram.S
+./src/cpu/intel/car/p4-netburst/cache_as_ram.S
+./src/cpu/intel/haswell/acpi.c
+./src/cpu/intel/microcode/Kconfig
+./src/cpu/intel/microcode/microcode.c
+./src/cpu/intel/microcode/microcode_asm.S
+./src/cpu/intel/model_2065x/acpi.c
+./src/cpu/intel/model_206ax/acpi.c
+./src/cpu/intel/model_65x/model_65x_init.c
+./src/cpu/intel/model_67x/model_67x_init.c
+./src/cpu/intel/model_68x/model_68x_init.c
+./src/cpu/intel/model_6bx/model_6bx_init.c
+./src/cpu/intel/model_6xx/model_6xx_init.c
+./src/cpu/intel/model_f2x/model_f2x_init.c
+./src/cpu/intel/model_f3x/model_f3x_init.c
+./src/cpu/Kconfig
+./src/cpu/Makefile.inc
+./src/device/oprom/yabel/interrupt.c
+./src/device/Kconfig
+./src/drivers/aspeed/common/ast_dram_tables.h
+./src/drivers/aspeed/common/ast_tables.h
+./src/drivers/i2c/ww_ring/ww_ring_programs.c
+./src/drivers/intel/fsp1_1/cache_as_ram.S
+./src/drivers/intel/fsp1_1/car.c
+./src/drivers/intel/fsp1_1/ramstage.c
+./src/drivers/intel/fsp1_1/romstage.c
+./src/drivers/intel/fsp1_1/temp_ram_exit.c
+./src/drivers/intel/fsp2_0/Kconfig
+./src/drivers/intel/gma/opregion.c
+./src/drivers/intel/gma/opregion.h
+./src/drivers/pc80/rtc/option.c
+./src/drivers/pc80/vga/vga_palette.c
+./src/drivers/siemens/nc_fpga/nc_fpga.c
+./src/drivers/wifi/generic/Kconfig
+./src/ec/51nb/npce985la0dx/Kconfig
+./src/ec/hp/kbc1126/Kconfig
+./src/include/cpu/amd/microcode.h
+./src/include/cpu/intel/microcode.h
+./src/include/spd_bin.h
+./src/lib/coreboot_table.c
+./src/lib/jpeg.c
+./src/lib/spd_bin.c
+./src/mainboard/amd/gardenia/bootblock/OemCustomize.c
+./src/mainboard/amd/inagua/Kconfig
+./src/mainboard/amd/majolica/Kconfig
+./src/mainboard/amd/mandolin/Kconfig
+./src/mainboard/amd/olivehill/mptable.c
+./src/mainboard/amd/parmer/mptable.c
+./src/mainboard/amd/persimmon/Kconfig
+./src/mainboard/amd/south_station/Kconfig
+./src/mainboard/amd/south_station/mptable.c
+./src/mainboard/amd/thatcher/mptable.c
+./src/mainboard/amd/union_station/Kconfig
+./src/mainboard/amd/union_station/mptable.c
+./src/mainboard/apple/macbookair4_2/early_init.c
+./src/mainboard/asrock/b75pro3-m/early_init.c
+./src/mainboard/asrock/e350m1/mptable.c
+./src/mainboard/asrock/imb-a180/mptable.c
+./src/mainboard/asus/a88xm-e/mainboard.c
+./src/mainboard/asus/f2a85-m/mptable.c
+./src/mainboard/asus/h61m-cs/early_init.c
+./src/mainboard/asus/maximus_iv_gene-z/early_init.c
+./src/mainboard/asus/p8h61-m_lx/early_init.c
+./src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c
+./src/mainboard/asus/p8h61-m_pro/early_init.c
+./src/mainboard/asus/p8z77-v_lx2/early_init.c
+./src/mainboard/bap/ode_e20XX/spd/BAP_Q7_1066.spd.hex
+./src/mainboard/bap/ode_e20XX/spd/BAP_Q7_800.spd.hex
+./src/mainboard/biostar/a68n_5200/mptable.c
+./src/mainboard/biostar/th61-itx/early_init.c
+./src/mainboard/clevo/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex
+./src/mainboard/compulab/intense_pc/early_init.c
+./src/mainboard/dell/optiplex_9010/early_init.c
+./src/mainboard/dell/optiplex_9010/sch5545_ec.c
+./src/mainboard/dell/optiplex_9010/sch5545_ec_early.c
+./src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex
+./src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex
+./src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
+./src/mainboard/facebook/fbg1701/Kconfig
+./src/mainboard/facebook/fbg1701/board_mboot.h
+./src/mainboard/facebook/fbg1701/board_verified_boot.c
+./src/mainboard/facebook/fbg1701/board_verified_boot.h
+./src/mainboard/facebook/fbg1701/ramstage.c
+./src/mainboard/facebook/monolith/Kconfig
+./src/mainboard/gigabyte/ga-b75m-d3h/early_init.c
+./src/mainboard/gigabyte/ga-h61m-series/early_init.c
+./src/mainboard/gizmosphere/gizmo/mptable.c
+./src/mainboard/gizmosphere/gizmo2/spd/Micron_MT41J128M16JT.spd.hex
+./src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.hex
+./src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
+./src/mainboard/google/auron/variants/auron_paine/spd/Micron_4KTF25664HZ.spd.hex
+./src/mainboard/google/auron/variants/auron_paine/spd/empty.spd.hex
+./src/mainboard/google/auron/variants/auron_paine/spd/spd.c
+./src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6AFR6A.spd.hex
+./src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
+./src/mainboard/google/auron/variants/auron_yuna/spd/Micron_4KTF25664HZ.spd.hex
+./src/mainboard/google/auron/variants/auron_yuna/spd/empty.spd.hex
+./src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
+./src/mainboard/google/auron/variants/buddy/variant.c
+./src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6AFR6A.spd.hex
+./src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
+./src/mainboard/google/auron/variants/gandof/spd/Micron_4KTF25664HZ.spd.hex
+./src/mainboard/google/auron/variants/gandof/spd/Samsung_M471B5674EB0-YK0.spd.hex
+./src/mainboard/google/auron/variants/gandof/spd/empty.spd.hex
+./src/mainboard/google/auron/variants/gandof/spd/spd.c
+./src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex
+./src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
+./src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex
+./src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
+./src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex
+./src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
+./src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
+./src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex
+./src/mainboard/google/auron/variants/lulu/spd/spd.c
+./src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex
+./src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex
+./src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex
+./src/mainboard/google/auron/variants/samus/spd/empty.spd.hex
+./src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex
+./src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex
+./src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex
+./src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex
+./src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex
+./src/mainboard/google/auron/variants/samus/spd/spd.c
+./src/mainboard/google/beltino/lan.c
+./src/mainboard/google/butterfly/hda_verb.c
+./src/mainboard/google/butterfly/mainboard.c
+./src/mainboard/google/cyan/spd/empty.spd.hex
+./src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
+./src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD.spd.hex
+./src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
+./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex
+./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex
+./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
+./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex
+./src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex
+./src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-JD-F.spd.hex
+./src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex
+./src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex
+./src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF.spd.hex
+./src/mainboard/google/cyan/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex
+./src/mainboard/google/cyan/spd/nanya_dimm_NT6CL256T32CM-H1.spd.hex
+./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
+./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
+./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCE.spd.hex
+./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCF.spd.hex
+./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E324EB-EGCF.spd.hex
+./src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
+./src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex
+./src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
+./src/mainboard/google/cyan/spd/spd.c
+./src/mainboard/google/dedede/variants/drawcia/variant.c
+./src/mainboard/google/dedede/variants/madoo/variant.c
+./src/mainboard/google/dedede/variants/magolor/variant.c
+./src/mainboard/google/drallion/spd/empty_ddr4.spd.hex
+./src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex
+./src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex
+./src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex
+./src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex
+./src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex
+./src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex
+./src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex
+./src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex
+./src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex
+./src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex
+./src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex
+./src/mainboard/google/drallion/variants/drallion/devicetree.cb
+./src/mainboard/google/drallion/variants/drallion/memory.c
+./src/mainboard/google/eve/spd/empty.spd.hex
+./src/mainboard/google/eve/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex
+./src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex
+./src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex
+./src/mainboard/google/eve/spd/samsung_dimm_K4E6E304EB.spd.hex
+./src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex
+./src/mainboard/google/eve/spd/samsung_dimm_K4EBE304EB.spd.hex
+./src/mainboard/google/eve/spd/spd.c
+./src/mainboard/google/glados/spd/empty.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLGALAR.spd.hex
+./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex
+./src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex
+./src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex
+./src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex
+./src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex
+./src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex
+./src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex
+./src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex
+./src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex
+./src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
+./src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex
+./src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex
+./src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
+./src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCF.spd.hex
+./src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCG.spd.hex
+./src/mainboard/google/glados/spd/spd.c
+./src/mainboard/google/hatch/spd/16G_2400.spd.hex
+./src/mainboard/google/hatch/spd/16G_2666.spd.hex
+./src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex
+./src/mainboard/google/hatch/spd/16G_3200.spd.hex
+./src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex
+./src/mainboard/google/hatch/spd/4G_2400.spd.hex
+./src/mainboard/google/hatch/spd/8G_2400.spd.hex
+./src/mainboard/google/hatch/spd/8G_2666.spd.hex
+./src/mainboard/google/hatch/spd/8G_3200.spd.hex
+./src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex
+./src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex
+./src/mainboard/google/hatch/spd/LP_8G_2133.spd.hex
+./src/mainboard/google/hatch/spd/empty_ddr4.spd.hex
+./src/mainboard/google/hatch/variants/dratini/variant.c
+./src/mainboard/google/hatch/variants/kindred/variant.c
+./src/mainboard/google/hatch/variants/nightfury/variant.c
+./src/mainboard/google/jecht/lan.c
+./src/mainboard/google/kahlee/spd/empty.spd.hex
+./src/mainboard/google/kahlee/spd/hynix-H5AN8G6NAFR-UH.spd.hex
+./src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-VKC.spd.hex
+./src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex
+./src/mainboard/google/kahlee/spd/hynix-H5ANAG6NAMR-UH.spd.hex
+./src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-VKC.spd.hex
+./src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-XNC.spd.hex
+./src/mainboard/google/kahlee/spd/micron-MT40A1G16KNR-075-E.spd.hex
+./src/mainboard/google/kahlee/spd/micron-MT40A1G16RC-062E-B.spd.hex
+./src/mainboard/google/kahlee/spd/micron-MT40A512M16JY-083E-B.spd.hex
+./src/mainboard/google/kahlee/spd/micron-MT40A512M16LY-075-E.spd.hex
+./src/mainboard/google/kahlee/spd/micron-MT40A512M16TB-062E-J.spd.hex
+./src/mainboard/google/kahlee/spd/samsung-K4A8G165WB-BCRC.spd.hex
+./src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCTD.spd.hex
+./src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex
+./src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCTD.spd.hex
+./src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCWE.spd.hex
+./src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCRC.spd.hex
+./src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCTD.spd.hex
+./src/mainboard/google/kahlee/variants/baseboard/mainboard.c
+./src/mainboard/google/kahlee/variants/nuwani/mainboard.c
+./src/mainboard/google/kahlee/variants/treeya/mainboard.c
+./src/mainboard/google/kahlee/Kconfig
+./src/mainboard/google/link/spd/elpida_4Gb_1600_x16.spd.hex
+./src/mainboard/google/link/spd/micron_4Gb_1600_1.35v_x16.spd.hex
+./src/mainboard/google/link/spd/samsung_4Gb_1600_1.35v_x16.spd.hex
+./src/mainboard/google/link/early_init.c
+./src/mainboard/google/link/hda_verb.c
+./src/mainboard/google/octopus/variants/bloog/variant.c
+./src/mainboard/google/octopus/variants/bobba/variant.c
+./src/mainboard/google/octopus/variants/casta/variant.c
+./src/mainboard/google/octopus/variants/fleex/variant.c
+./src/mainboard/google/octopus/variants/foob/variant.c
+./src/mainboard/google/octopus/variants/garg/variant.c
+./src/mainboard/google/octopus/variants/meep/variant.c
+./src/mainboard/google/octopus/variants/phaser/mainboard.c
+./src/mainboard/google/peach_pit/mainboard.c
+./src/mainboard/google/poppy/spd/empty.spd.hex
+./src/mainboard/google/poppy/spd/empty_ddr4.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H5AN4G6NAFR-UHC.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H5AN4G6NBJR-UHC.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NAFR-UHC.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAMR-UHC.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBJTALAR-NUD.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBKTALBR-NUD.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NUD.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex
+./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT40A256M16GE-083E.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT40A256M16LY-075F.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16LY-075E.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-093.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT52L256M64D2PP-107.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-093.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex
+./src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex
+./src/mainboard/google/poppy/spd/nayna_dimm_NT6CL256T32CM-H1.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K3QF3F30BM-AGCF.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K3QF4F40BM-AGCF.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K3QFAFA0CM-AGCF.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4A4G165WE-BCRC.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4A8G165WB-BCRC.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4AAG165WB-MCRC.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304EC-EGCF.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EB-EGCG.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EC-EGCF.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EC-EGCG.spd.hex
+./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex
+./src/mainboard/google/poppy/variants/nami/mainboard.c
+./src/mainboard/google/poppy/romstage.c
+./src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex
+./src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
+./src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex
+./src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex
+./src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex
+./src/mainboard/google/rambi/spd/empty.spd.hex
+./src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
+./src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
+./src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex
+./src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex
+./src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
+./src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
+./src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex
+./src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex
+./src/mainboard/google/rambi/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex
+./src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
+./src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
+./src/mainboard/google/rambi/variants/ninja/lan.c
+./src/mainboard/google/rambi/variants/sumo/lan.c
+./src/mainboard/google/rambi/romstage.c
+./src/mainboard/google/reef/variants/coral/mainboard.c
+./src/mainboard/google/sarien/variants/arcada/devicetree.cb
+./src/mainboard/google/slippy/variants/falco/spd/Elpida_EDJ4216EFBG.spd.hex
+./src/mainboard/google/slippy/variants/falco/spd/Hynix_HMT425S6AFR6A.spd.hex
+./src/mainboard/google/slippy/variants/falco/spd/Micron_4KTF25664HZ.spd.hex
+./src/mainboard/google/slippy/variants/falco/spd/Samsung_M471B5674QH0.spd.hex
+./src/mainboard/google/slippy/variants/falco/romstage.c
+./src/mainboard/google/slippy/variants/leon/spd/Hynix_HMT425S6AFR6A.spd.hex
+./src/mainboard/google/slippy/variants/leon/spd/Micron_4KTF25664HZ.spd.hex
+./src/mainboard/google/slippy/variants/leon/spd/Samsung_K4B4G1646Q.spd.hex
+./src/mainboard/google/slippy/variants/leon/romstage.c
+./src/mainboard/google/slippy/variants/peppy/spd/Elpida_EDJ4216EFBG.spd.hex
+./src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6AFR6A.spd.hex
+./src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6CFR6A.spd.hex
+./src/mainboard/google/slippy/variants/peppy/spd/Micron_4KTF25664HZ.spd.hex
+./src/mainboard/google/slippy/variants/peppy/romstage.c
+./src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex
+./src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex
+./src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex
+./src/mainboard/google/slippy/variants/wolf/romstage.c
+./src/mainboard/google/zork/spd/ddr4-spd-1.hex
+./src/mainboard/google/zork/spd/ddr4-spd-2.hex
+./src/mainboard/google/zork/spd/ddr4-spd-3.hex
+./src/mainboard/google/zork/spd/ddr4-spd-4.hex
+./src/mainboard/google/zork/spd/ddr4-spd-5.hex
+./src/mainboard/google/zork/spd/ddr4-spd-6.hex
+./src/mainboard/google/zork/spd/ddr4-spd-7.hex
+./src/mainboard/google/zork/spd/ddr4-spd-8.hex
+./src/mainboard/google/zork/spd/ddr4-spd-9.hex
+./src/mainboard/google/zork/spd/ddr4-spd-empty.hex
+./src/mainboard/hp/abm/mptable.c
+./src/mainboard/hp/folio_9480m/hda_verb.c
+./src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+./src/mainboard/hp/snb_ivb_laptops/spd/hynix_4g.spd.hex
+./src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c
+./src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c
+./src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c
+./src/mainboard/hp/z220_sff_workstation/early_init.c
+./src/mainboard/ibase/mb899/cmos.layout
+./src/mainboard/ibase/mb899/superio_hwm.c
+./src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex
+./src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex
+./src/mainboard/intel/adlrvp/spd/empty.spd.hex
+./src/mainboard/intel/adlrvp/memory.c
+./src/mainboard/intel/apollolake_rvp/romstage.c
+./src/mainboard/intel/coffeelake_rvp/variants/cml_u/hda_verb.c
+./src/mainboard/intel/coffeelake_rvp/variants/whl_u/hda_verb.c
+./src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex
+./src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex
+./src/mainboard/intel/glkrvp/romstage.c
+./src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
+./src/mainboard/intel/harcuvar/spd/spd.c
+./src/mainboard/intel/icelake_rvp/spd/empty.spd.hex
+./src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex
+./src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h
+./src/mainboard/intel/jasperlake_rvp/spd/empty.spd.hex
+./src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex
+./src/mainboard/intel/kblrvp/spd/empty.spd.hex
+./src/mainboard/intel/kblrvp/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex
+./src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
+./src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h
+./src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h
+./src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h
+./src/mainboard/intel/kblrvp/Kconfig
+./src/mainboard/intel/kunimitsu/spd/empty.spd.hex
+./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866.spd.hex
+./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
+./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTALAR-NUD-2G-1866.spd.hex
+./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
+./src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex
+./src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E6E304EE-EGCF-2G-1866.spd.hex
+./src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
+./src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCF-1G-1866.spd.hex
+./src/mainboard/intel/kunimitsu/spd/spd_util.c
+./src/mainboard/intel/leafhill/Kconfig
+./src/mainboard/intel/leafhill/romstage.c
+./src/mainboard/intel/minnow3/Kconfig
+./src/mainboard/intel/minnow3/romstage.c
+./src/mainboard/intel/strago/Kconfig
+./src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
+./src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex
+./src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex
+./src/mainboard/intel/tglrvp/spd/empty.spd.hex
+./src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+./src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+./src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex
+./src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex
+./src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex
+./src/mainboard/jetway/nf81-t56n-lf/Kconfig
+./src/mainboard/kontron/986lcd-m/cmos.layout
+./src/mainboard/kontron/986lcd-m/mainboard.c
+./src/mainboard/lenovo/g505s/mptable.c
+./src/mainboard/lenovo/s230u/spd/elpida_2gb.spd.hex
+./src/mainboard/lenovo/s230u/spd/elpida_4gb.spd.hex
+./src/mainboard/lenovo/s230u/spd/elpida_8gb.spd.hex
+./src/mainboard/lenovo/s230u/spd/hynix_2gb.spd.hex
+./src/mainboard/lenovo/s230u/spd/hynix_4gb.spd.hex
+./src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.hex
+./src/mainboard/lenovo/s230u/spd/samsung_4gb.spd.hex
+./src/mainboard/lenovo/s230u/early_init.c
+./src/mainboard/lenovo/t430s/variants/t431s/spd/samsung_4gb.spd.hex
+./src/mainboard/lenovo/t430s/variants/t431s/romstage.c
+./src/mainboard/lenovo/t440p/hda_verb.c
+./src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.spd.hex
+./src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.spd.hex
+./src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.spd.hex
+./src/mainboard/lenovo/x1_carbon_gen1/early_init.c
+./src/mainboard/lenovo/x220/variants/x1/romstage.c
+./src/mainboard/lenovo/x220/early_init.c
+./src/mainboard/lippert/frontrunner-af/mptable.c
+./src/mainboard/msi/ms7707/early_init.c
+./src/mainboard/msi/ms7721/mptable.c
+./src/mainboard/opencellular/elgon/gbcv2.dts
+./src/mainboard/packardbell/ms2290/mainboard.c
+./src/mainboard/pcengines/apu1/Kconfig
+./src/mainboard/pcengines/apu2/Kconfig
+./src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex
+./src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex
+./src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
+./src/mainboard/protectli/vault_bsw/Kconfig
+./src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex
+./src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex
+./src/mainboard/samsung/lumpy/spd/lumpy.spd.hex
+./src/mainboard/samsung/lumpy/early_init.c
+./src/mainboard/sapphire/pureplatinumh61/early_init.c
+./src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c
+./src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c
+./src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c
+./src/mainboard/siemens/mc_apl1/mainboard.c
+./src/mainboard/siemens/mc_apl1/romstage.c
+./src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex
+./src/mainboard/up/squared/romstage.c
+./src/northbridge/amd/pi/00630F01/Kconfig
+./src/northbridge/amd/pi/00730F01/Kconfig
+./src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+./src/northbridge/intel/gm45/raminit_read_write_training.c
+./src/northbridge/intel/haswell/Kconfig
+./src/northbridge/intel/haswell/raminit.c
+./src/northbridge/intel/i945/raminit.c
+./src/northbridge/intel/ironlake/raminit.c
+./src/northbridge/intel/ironlake/raminit_tables.c
+./src/northbridge/intel/pineview/raminit.c
+./src/northbridge/intel/sandybridge/Kconfig
+./src/northbridge/intel/sandybridge/gma.c
+./src/northbridge/intel/sandybridge/raminit.c
+./src/northbridge/intel/sandybridge/raminit_mrc.c
+./src/northbridge/intel/sandybridge/raminit_tables.c
+./src/northbridge/intel/x4x/dq_dqs.c
+./src/northbridge/intel/x4x/raminit_ddr23.c
+./src/northbridge/intel/x4x/raminit_tables.c
+./src/security/intel/stm/Kconfig
+./src/security/intel/stm/StmPlatformSmm.c
+./src/security/intel/txt/Kconfig
+./src/security/tpm/tss/tcg-1.2/tss_commands.h
+./src/security/vboot/secdata_tpm.c
+./src/soc/amd/picasso/Kconfig
+./src/soc/amd/picasso/Makefile.inc
+./src/soc/amd/picasso/cpu.c
+./src/soc/amd/picasso/update_microcode.c
+./src/soc/amd/stoneyridge/Kconfig
+./src/soc/cavium/cn81xx/Kconfig
+./src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex
+./src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex
+./src/soc/intel/apollolake/Kconfig
+./src/soc/intel/apollolake/nhlt.c
+./src/soc/intel/baytrail/romstage/raminit.c
+./src/soc/intel/baytrail/Kconfig
+./src/soc/intel/baytrail/acpi.c
+./src/soc/intel/baytrail/modphy_table.c
+./src/soc/intel/braswell/acpi.c
+./src/soc/intel/braswell/gpio.c
+./src/soc/intel/broadwell/Kconfig
+./src/soc/intel/broadwell/cpu/acpi.c
+./src/soc/intel/broadwell/raminit.c
+./src/soc/intel/cannonlake/nhlt.c
+./src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+./src/soc/intel/common/block/cse/cse_rw_metadata.c
+./src/soc/intel/common/mma.c
+./src/soc/intel/denverton_ns/acpi.c
+./src/soc/intel/denverton_ns/chip.c
+./src/soc/intel/jasperlake/spd/lp4x-spd-1.hex
+./src/soc/intel/jasperlake/spd/lp4x-spd-2.hex
+./src/soc/intel/jasperlake/spd/lp4x-spd-3.hex
+./src/soc/intel/jasperlake/spd/lp4x-spd-4.hex
+./src/soc/intel/jasperlake/spd/lp4x-spd-5.hex
+./src/soc/intel/jasperlake/spd/lp4x-spd-6.hex
+./src/soc/intel/jasperlake/spd/lp4x-spd-7.hex
+./src/soc/intel/jasperlake/spd/placeholder.spd.hex
+./src/soc/intel/quark/romstage/romstage.c
+./src/soc/intel/quark/Kconfig
+./src/soc/intel/skylake/nhlt/da7219.c
+./src/soc/intel/skylake/nhlt/dmic.c
+./src/soc/intel/skylake/nhlt/max98357.c
+./src/soc/intel/skylake/nhlt/max98373.c
+./src/soc/intel/skylake/nhlt/max98927.c
+./src/soc/intel/skylake/nhlt/nau88l25.c
+./src/soc/intel/skylake/nhlt/rt5514.c
+./src/soc/intel/skylake/nhlt/rt5663.c
+./src/soc/intel/skylake/nhlt/ssm4567.c
+./src/soc/intel/tigerlake/spd/ddr4-spd-1.hex
+./src/soc/intel/tigerlake/spd/ddr4-spd-2.hex
+./src/soc/intel/tigerlake/spd/ddr4-spd-3.hex
+./src/soc/intel/tigerlake/spd/ddr4-spd-4.hex
+./src/soc/intel/tigerlake/spd/ddr4-spd-5.hex
+./src/soc/intel/tigerlake/spd/ddr4-spd-6.hex
+./src/soc/intel/tigerlake/spd/ddr4-spd-7.hex
+./src/soc/intel/tigerlake/spd/ddr4-spd-8.hex
+./src/soc/intel/tigerlake/spd/ddr4-spd-9.hex
+./src/soc/intel/tigerlake/spd/ddr4-spd-empty.hex
+./src/soc/intel/tigerlake/spd/lp4x-spd-1.hex
+./src/soc/intel/tigerlake/spd/lp4x-spd-2.hex
+./src/soc/intel/tigerlake/spd/lp4x-spd-3.hex
+./src/soc/intel/tigerlake/spd/lp4x-spd-4.hex
+./src/soc/intel/tigerlake/spd/lp4x-spd-5.hex
+./src/soc/intel/tigerlake/spd/placeholder.spd.hex
+./src/soc/intel/xeon_sp/skx/chip.c
+./src/soc/mediatek/mt8183/Kconfig
+./src/soc/mediatek/mt8183/spm.c
+./src/soc/mediatek/mt8192/Kconfig
+./src/soc/mediatek/mt8192/mt6315.c
+./src/soc/mediatek/mt8192/mt6359p.c
+./src/soc/nvidia/tegra210/Kconfig
+./src/soc/nvidia/tegra210/mtc.c
+./src/soc/qualcomm/ipq40xx/Kconfig
+./src/soc/qualcomm/ipq40xx/lcc.c
+./src/soc/qualcomm/ipq806x/Kconfig
+./src/soc/qualcomm/ipq806x/blobs_init.c
+./src/soc/qualcomm/ipq806x/lcc.c
+./src/soc/qualcomm/sc7180/display/dsi_phy.c
+./src/soc/samsung/exynos5250/clock.c
+./src/soc/samsung/exynos5420/clock.c
+./src/southbridge/amd/agesa/hudson/Kconfig
+./src/southbridge/amd/cimx/sb800/Kconfig
+./src/southbridge/amd/pi/hudson/Kconfig
+./src/southbridge/intel/bd82x6x/lpc.c
+./src/southbridge/intel/common/firmware/Kconfig
+./src/southbridge/intel/i82801ix/dmi_setup.c
+./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
+./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
+./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
+./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
+./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
+./src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c
+./src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
+./src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
+./src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c
+./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
+./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
+./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
+./src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c
+./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
+./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
+./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h
+./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
+./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
+./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
+./src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c
+./src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mptn3.c
+./src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c
+./src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
+./src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c
+./src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c
+./src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c
+./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c
+./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
+./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c
+./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
+./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h
+./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h
+./src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c
+./src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpkb3.c
+./src/vendorcode/amd/cimx/sb800/SATA.c
+./src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S
+./src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_header.inc
+./src/vendorcode/amd/pi/Kconfig
+./src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c
+./src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c
+./src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse.c
+./src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c
+./src/vendorcode/eltan/security/verified_boot/vboot_check.c
+./src/vendorcode/google/chromeos/build-snow.sh
+./src/vendorcode/google/chromeos/sar.c
+./src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm12.h
+./src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiConfigAccess.h
+./src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm12.h
+./src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiConfigAccess.h
+./src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
+./src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
+./util/amdtools/example_input/lspci-cb-48G-667MHz-18.2-20090909e
+./util/amdtools/example_input/lspci-prop-48G-667MHz-18.2
+./util/autoport/readme.md
+./util/bincfg/bincfg.lex.c_shipped
+./util/bincfg/bincfg.tab.c_shipped
+./util/cbfstool/lz4/lib/lz4.c
+./util/cbfstool/fit.c
+./util/cbfstool/fmd_parser.c_shipped
+./util/cbfstool/fmd_scanner.c_shipped
+./util/cbfstool/linux_trampoline.c
+./util/ifdtool/ifdtool.c
+./util/intelmetool/intelmetool.c
+./util/kbc1126/kbc1126_ec_dump.c
+./util/kconfig/zconf.hash.c_shipped
+./util/kconfig/zconf.lex.c_shipped
+./util/kconfig/zconf.tab.c_shipped
+./util/mma/mma_automated_test.sh
+./util/mtkheader/gen-bl-img.py
+./util/nvidia/cbootimage/samples/sign.sh
+./util/nvidia/cbootimage/src/aes_ref.c
+./util/nvramtool/accessors/layout-bin.c
+./util/qualcomm/scripts/cmm/debug_cb_common.cmm
+./util/qualcomm/scripts/cmm/debug_chroot_common.cmm
+./util/qualcomm/createxbl.py
+./util/riscv/make-spike-elf.sh
+./util/riscv/sifive-gpt.py
+./util/rockchip/make_idb.py
+./util/sconfig/lex.yy.c_shipped
+./util/sconfig/sconfig.tab.c_shipped
+./util/spd_tools/ddr4/gen_part_id.go
+./util/spd_tools/ddr4/gen_spd.go
+./util/spd_tools/lp4x/gen_spd.go
+./util/spdtool/spdtool.py
+./util/superiotool/fintek.c
+./util/superiotool/ite.c
+./util/superiotool/nuvoton.c
+./util/superiotool/smsc.c
+./util/superiotool/winbond.c
+./util/xcompile/xcompile
+./Makefile.inc
diff --git a/resources/coreboot/default/patches/0001-hardcode-tianocore-revisions-and-don-t-automatically.patch b/resources/coreboot/default/patches/0001-hardcode-tianocore-revisions-and-don-t-automatically.patch
new file mode 100644
index 00000000..d05eb306
--- /dev/null
+++ b/resources/coreboot/default/patches/0001-hardcode-tianocore-revisions-and-don-t-automatically.patch
@@ -0,0 +1,128 @@
+From 91b073efaca57d455e2f25370918b9796cbc1a15 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Thu, 13 May 2021 23:52:08 +0100
+Subject: [PATCH 01/17] hardcode tianocore revisions, and don't automatically
+ download
+
+---
+ Makefile | 2 +-
+ payloads/external/tianocore/Makefile | 57 ++++++++--------------------
+ 2 files changed, 17 insertions(+), 42 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index 02c6288f15..8290b45e89 100644
+--- a/Makefile
++++ b/Makefile
+@@ -486,7 +486,7 @@ distclean-utils:
+ $(MAKE) -C util/$(tool) distclean MFLAGS= MAKEFLAGS= ; \
+ rm -f /util/$(tool)/junit.xml;)
+
+-distclean: clean clean-ctags clean-cscope distclean-payloads distclean-utils
++distclean: clean clean-ctags clean-cscope distclean-utils
+ rm -f .config .config.old ..config.tmp* .kconfig.d .tmpconfig* .ccwrap .xcompile
+ rm -rf coreboot-builds coreboot-builds-chromeos
+ rm -f abuild*.xml junit.xml* util/lint/junit.xml
+diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
+index 7cd34f1732..3527b7a2ad 100644
+--- a/payloads/external/tianocore/Makefile
++++ b/payloads/external/tianocore/Makefile
+@@ -1,5 +1,8 @@
+ ## SPDX-License-Identifier: GPL-2.0-only
+
++# This file has been modified for libreboot/osboot/osboot-libre.
++# The tianocore repo/branch/revision has been hardcoded, as have some options
++
+ # force the shell to bash - the edksetup.sh script doesn't work with dash
+ export SHELL := env bash
+
+@@ -9,51 +12,31 @@ project_git_repo=https://github.com/mrchromebox/edk2
+ project_git_branch=coreboot_fb
+ upstream_git_repo=https://github.com/tianocore/edk2
+
+-ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y)
+-bootloader=UefiPayloadPkg
+-logo_pkg=MdeModulePkg
+-build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
+-TAG=upstream/master
+-else
+ bootloader=CorebootPayloadPkg
+ logo_pkg=CorebootPayloadPkg
+ # STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch
+-TAG=origin/$(project_git_branch)
+-endif
+-
+-ifneq ($(CONFIG_TIANOCORE_REVISION_ID),)
+-TAG=$(CONFIG_TIANOCORE_REVISION_ID)
+-endif
++TAG=ca08920ded1649921a12105d1959df423733431f
++# above is a commit ID in MrChromebox's coreboot_fb branch
+
+ export EDK_TOOLS_PATH=$(project_dir)/BaseTools
+
+-ifeq ($(CONFIG_TIANOCORE_DEBUG),y)
+-BUILD_TYPE=DEBUG
+-else
+ BUILD_TYPE=RELEASE
+-endif
+
+-ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y)
+ TIMER=-DUSE_HPET_TIMER
+-endif
+
+-TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
++# see coreboot 61a3c8a005922d46425c84f847c0ad26e9c3cdca
++# "2 seconds for board with internal display"
++# "5 seconds for board without internal display"
++# libreboot takes the shotgun approach. 5 seconds for all
++TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=5
+
+-ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
+-ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y)
+-ARCH=-a IA32 -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+-else
+ ARCH=-a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+-endif
+-else
+-ARCH=-a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc
+-endif
+
+-BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor)
++BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT)
+
+ all: clean build
+
+-$(project_dir):
++download:
+ echo " Cloning $(project_name) from Git"
+ git clone --branch $(project_git_branch) $(project_git_repo) $(project_dir); \
+ cd $(project_dir); \
+@@ -76,17 +59,9 @@ update: $(project_dir)
+ git submodule update --init
+
+ checktools:
+- echo "Checking uuid-dev..."
+- echo "#include <uuid/uuid.h>" > libtest.c
+- echo "int main(int argc, char **argv) { (void) argc; (void) argv; return 0; }" >> libtest.c
+- $(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo " found uuid-dev." || \
+- ( echo " Not found."; echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 )
+- rm -rf libtest.c libtest
+- echo "Checking nasm..."
+- type nasm > /dev/null 2>&1 && echo " found nasm." || \
+- ( echo " Not found."; echo "Error: Please install nasm."; exit 1 )
+-
+-build: update checktools
++ echo "tianocore tool check disabled"
++
++build: checktools
+ unset CC; $(MAKE) -C $(project_dir)/BaseTools
+ echo " build $(project_name) $(TAG)"
+ if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \
+@@ -116,4 +91,4 @@ clean:
+ distclean:
+ rm -rf $(project_dir)
+
+-.PHONY: all update checktools config build clean distclean
++.PHONY: all update checktools config build clean distclean download
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0002-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/resources/coreboot/default/patches/0002-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
new file mode 100644
index 00000000..c3df0afa
--- /dev/null
+++ b/resources/coreboot/default/patches/0002-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
@@ -0,0 +1,23 @@
+From 2ca1b655f0421fb9ed971f6e815bdd9dadc61a32 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Sun, 3 Jan 2021 03:34:01 +0000
+Subject: [PATCH 02/17] lenovo/x60: 64MiB Video RAM changed to default
+ (previously it was 8MiB)
+
+---
+ src/mainboard/lenovo/x60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
+index 5c3576d1f3..88170a1aab 100644
+--- a/src/mainboard/lenovo/x60/cmos.default
++++ b/src/mainboard/lenovo/x60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0003-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/resources/coreboot/default/patches/0003-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
new file mode 100644
index 00000000..01f97cd0
--- /dev/null
+++ b/resources/coreboot/default/patches/0003-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
@@ -0,0 +1,22 @@
+From 86bf61b803e116e9037d74a1166e64c7b6d85c7a Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Mon, 22 Feb 2021 22:16:59 +0000
+Subject: [PATCH 03/17] lenovo/t60: make 64MiB VRAM the default in cmos.default
+
+---
+ src/mainboard/lenovo/t60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
+index af865f16da..7f03157df7 100644
+--- a/src/mainboard/lenovo/t60/cmos.default
++++ b/src/mainboard/lenovo/t60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0004-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/resources/coreboot/default/patches/0004-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
new file mode 100644
index 00000000..6458a800
--- /dev/null
+++ b/resources/coreboot/default/patches/0004-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
@@ -0,0 +1,23 @@
+From d2da9e70f608016c20976623a6ca9916da13e647 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@retroboot.org>
+Date: Fri, 19 Mar 2021 05:54:58 +0000
+Subject: [PATCH 04/17] apple/macbook21: Set default VRAM to 64MiB instead of
+ 8MiB
+
+---
+ src/mainboard/apple/macbook21/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
+index cf1bc4566e..dc0df3b6d6 100644
+--- a/src/mainboard/apple/macbook21/cmos.default
++++ b/src/mainboard/apple/macbook21/cmos.default
+@@ -5,4 +5,4 @@ boot_devices=''
+ boot_default=0x40
+ cmos_defaults_loaded=Yes
+ lpt=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0005-util-cbfstool-Do-not-set-D_XOPEN_SOURCE-on-FreeBSD.patch b/resources/coreboot/default/patches/0005-util-cbfstool-Do-not-set-D_XOPEN_SOURCE-on-FreeBSD.patch
new file mode 100644
index 00000000..1cc7aa17
--- /dev/null
+++ b/resources/coreboot/default/patches/0005-util-cbfstool-Do-not-set-D_XOPEN_SOURCE-on-FreeBSD.patch
@@ -0,0 +1,46 @@
+From f0c8276fe364d4773f9f305f2678a0b8e8f84830 Mon Sep 17 00:00:00 2001
+From: Idwer Vollering <vidwer@gmail.com>
+Date: Sun, 9 May 2021 18:16:26 +0200
+Subject: [PATCH 05/17] util/cbfstool: Do not set -D_XOPEN_SOURCE on FreeBSD
+
+Fixes compilation on FreeBSD CURRENT, and possibly other releases.
+
+The compiler, clang, complained about:
+util/cbfstool/cbfstool.c:181:40: error: implicit declaration of function 'memmem' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
+util/cbfstool/cbfstool.c:181:31: error: incompatible integer to pointer conversion initializing 'struct metadata_hash_anchor *' with an expression of type 'int' [-Werror,-Wint-conversion]
+
+Signed-off-by: Idwer Vollering <vidwer@gmail.com>
+Change-Id: I45c02a21709160df44fc8da329f6c4a9bad24478
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/53996
+Reviewed-by: Angel Pons <th3fanbus@gmail.com>
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+---
+ util/cbfstool/Makefile.inc | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
+index 5b49fe80ad..47b89e57b0 100644
+--- a/util/cbfstool/Makefile.inc
++++ b/util/cbfstool/Makefile.inc
+@@ -95,7 +95,6 @@ TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings
+ TOOLCFLAGS += -O2
+ TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h
+ TOOLCPPFLAGS += -D_BSD_SOURCE -D_SVID_SOURCE # _DEFAULT_SOURCE for older glibc
+-TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
+ TOOLCPPFLAGS += -D_GNU_SOURCE # memmem() from string.h
+ TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
+ TOOLCPPFLAGS += -I$(top)/util/cbfstool
+@@ -113,6 +112,10 @@ TOOLCPPFLAGS += -I$(top)/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
+ TOOLLDFLAGS ?=
+ HOSTCFLAGS += -fms-extensions
+
++ifneq ($(shell uname -o 2>/dev/null), FreeBSD)
++TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
++endif
++
+ ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
+ TOOLCFLAGS += -mno-ms-bitfields
+ endif
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0006-src-security-intel-stm-Add-warning-for-non-reproduci.patch b/resources/coreboot/default/patches/0006-src-security-intel-stm-Add-warning-for-non-reproduci.patch
new file mode 100644
index 00000000..e03418dd
--- /dev/null
+++ b/resources/coreboot/default/patches/0006-src-security-intel-stm-Add-warning-for-non-reproduci.patch
@@ -0,0 +1,35 @@
+From 8a687e2efd7199a06cd6bdd85fa1a1b17bca53cc Mon Sep 17 00:00:00 2001
+From: Martin Roth <martin@coreboot.org>
+Date: Mon, 10 May 2021 11:28:45 -0600
+Subject: [PATCH 06/17] src/security/intel/stm: Add warning for
+ non-reproducible build
+
+Because the STM build doesn't use the coreboot toolchain it's not
+reproducible. Make sure that's displayed during the build.
+
+Signed-off-by: Martin Roth <martin@coreboot.org>
+Change-Id: I3f0101400dc221eca09c928705f30d30492f171f
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/54020
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Angel Pons <th3fanbus@gmail.com>
+Reviewed-by: Patrick Georgi <pgeorgi@google.com>
+---
+ src/security/intel/stm/Makefile | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/src/security/intel/stm/Makefile b/src/security/intel/stm/Makefile
+index 1493869e80..31e5bdd88a 100644
+--- a/src/security/intel/stm/Makefile
++++ b/src/security/intel/stm/Makefile
+@@ -18,6 +18,8 @@ all: build
+
+ build:
+ echo "STM - Build"
++ echo "-- WARNING: This uses the system toolchain instead of"
++ echo " the coreboot toolchain, so is not reproducible."
+ cd $(project_dir)/Stm; \
+ mkdir -p build; \
+ cd build; \
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0007-Makefile-Don-t-run-genbuild_h-if-not-doing-a-build.patch b/resources/coreboot/default/patches/0007-Makefile-Don-t-run-genbuild_h-if-not-doing-a-build.patch
new file mode 100644
index 00000000..b0a09f15
--- /dev/null
+++ b/resources/coreboot/default/patches/0007-Makefile-Don-t-run-genbuild_h-if-not-doing-a-build.patch
@@ -0,0 +1,36 @@
+From 710301b4e80325012e86cdec3c0c4bcca03be551 Mon Sep 17 00:00:00 2001
+From: Martin Roth <martin@coreboot.org>
+Date: Sun, 9 May 2021 10:26:10 -0600
+Subject: [PATCH 07/17] Makefile: Don't run genbuild_h if not doing a build
+
+genbuild_h was being run on every make invocation - clean, distclean,
+etc. to get the source date epoch value. This value isn't used unless
+a build is being done, so don't run it on non-compile make invocations.
+
+Signed-off-by: Martin Roth <martin@coreboot.org>
+Change-Id: I2afc0affc17116e0db849ea968474bc19dbb0ae1
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/53997
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Angel Pons <th3fanbus@gmail.com>
+Reviewed-by: Patrick Georgi <pgeorgi@google.com>
+---
+ Makefile | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Makefile b/Makefile
+index 8290b45e89..1e6cca44b3 100644
+--- a/Makefile
++++ b/Makefile
+@@ -24,7 +24,9 @@ COREBOOT_EXPORTS += top src srck obj objutil objk
+ LANG:=C
+ LC_ALL:=C
+ TZ:=UTC0
++ifneq ($(NOCOMPILE),1)
+ SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"\(.*\)".*/\1/p')
++endif
+ # don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system
+ # are reproducible
+ export LANG LC_ALL TZ SOURCE_DATE_EPOCH
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0008-util-genbuild_h-Update-IASL-location-finding-code.patch b/resources/coreboot/default/patches/0008-util-genbuild_h-Update-IASL-location-finding-code.patch
new file mode 100644
index 00000000..79a35fcf
--- /dev/null
+++ b/resources/coreboot/default/patches/0008-util-genbuild_h-Update-IASL-location-finding-code.patch
@@ -0,0 +1,74 @@
+From 5c4c5cdc3110bf02b93be9d5eb744235c8f49e33 Mon Sep 17 00:00:00 2001
+From: Martin Roth <martin@coreboot.org>
+Date: Sun, 9 May 2021 11:44:15 -0600
+Subject: [PATCH 08/17] util/genbuild_h: Update IASL location finding code
+
+Update the iasl path finding code to use XGCCPATH if it's set, and to
+look for iasl on the path if it's not set and not under util/crossgcc.
+
+On the jenkins builders, iasl is in the path, not in util/crossgcc/xgcc.
+
+On the systems of people who have multiple copies of coreboot, it makes
+sense to just have a single copy of the toolchain and define XGCCPATH in
+the environment to point to it.
+
+Previously, either of these situations resulted in a warning from the
+genbuild_h tool that iasl was not found under util/crossgcc, which was
+true, but not particularly relevant, and generated confusion.
+
+If xcompile already existed before make was run, the correct path would
+be found, but on an initial build, this check couldn't find iasl.
+
+BUG=None
+TEST=Build with iasl in /util/crossgcc/xgcc/bin, in the path and in a
+directory pointed to with XGCCPATH.
+
+Signed-off-by: Martin Roth <martin@coreboot.org>
+Change-Id: Ic2f8dca0be8bfb54d3c672fab6cf6f005bb394c3
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/54001
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Angel Pons <th3fanbus@gmail.com>
+Reviewed-by: Patrick Georgi <pgeorgi@google.com>
+---
+ util/genbuild_h/genbuild_h.sh | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh
+index 10ca0c5fa3..c898fb6e3f 100755
+--- a/util/genbuild_h/genbuild_h.sh
++++ b/util/genbuild_h/genbuild_h.sh
+@@ -5,6 +5,7 @@
+ DATE=""
+ GITREV=""
+ TIMESOURCE=""
++XGCCPATH="${XGCCPATH:-util/crossgcc/xgcc/bin/}"
+
+ export LANG=C
+ export LC_ALL=C
+@@ -47,8 +48,15 @@ NetBSD|OpenBSD|DragonFly|FreeBSD|Darwin)
+ esac
+ }
+
+-IASL=util/crossgcc/xgcc/bin/iasl
++# Look for IASL in XGCCPATH and xcompile. Unfortunately,
++# xcompile isn't available on the first build.
++# If neither of those gives a valid iasl, check the path.
++IASL="${XGCCPATH}iasl"
+ eval $(grep ^IASL:= "$XCOMPILE" 2>/dev/null | sed s,:=,=,)
++if [ ! -x "${IASL}" ]; then
++ IASL=$(command -v iasl)
++fi
++IASLVERSION="$(${IASL} -v | grep version | sed 's/.*version //')" >/dev/null
+
+ #Print out the information that goes into build.h
+ printf "/* build system definitions (autogenerated) */\n"
+@@ -72,5 +80,5 @@ printf "#define COREBOOT_BUILD_EPOCH \"$(our_date "$DATE" +%s)\"\n"
+ printf "#define COREBOOT_DMI_DATE \"$(our_date "$DATE" +%m/%d/%Y)\"\n"
+ printf "\n"
+ printf "#define COREBOOT_COMPILE_TIME \"$(our_date "$DATE" +%T)\"\n"
+-printf "#define ASL_VERSION 0x%d\n" `$IASL -v | grep version | sed 's/.*version //'`
++printf "#define ASL_VERSION 0x%d\n" "${IASLVERSION}"
+ printf "#endif\n"
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0009-util-crossgcc-Update-gmp-to-6.2.1.patch b/resources/coreboot/default/patches/0009-util-crossgcc-Update-gmp-to-6.2.1.patch
new file mode 100644
index 00000000..b7899899
--- /dev/null
+++ b/resources/coreboot/default/patches/0009-util-crossgcc-Update-gmp-to-6.2.1.patch
@@ -0,0 +1,54 @@
+From 86af2659583125b2891ad57bde30a33adff91c03 Mon Sep 17 00:00:00 2001
+From: Patrick Georgi <pgeorgi@google.com>
+Date: Mon, 10 May 2021 23:34:18 +0200
+Subject: [PATCH 09/17] util/crossgcc: Update gmp to 6.2.1
+
+Change-Id: I871942f66e8fc496ebe523fdab539ea20950a202
+Signed-off-by: Patrick Georgi <pgeorgi@google.com>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/54047
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
+---
+ util/crossgcc/buildgcc | 2 +-
+ ...-6.2.0_generic-build.patch => gmp-6.2.1_generic-build.patch} | 0
+ util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum | 1 -
+ util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum | 1 +
+ 4 files changed, 2 insertions(+), 2 deletions(-)
+ rename util/crossgcc/patches/{gmp-6.2.0_generic-build.patch => gmp-6.2.1_generic-build.patch} (100%)
+ delete mode 100644 util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum
+ create mode 100644 util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index c947dd45ab..d8f25dbbb8 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -32,7 +32,7 @@ BOOTSTRAP=0
+ THREADS=1
+
+ # GCC toolchain version numbers
+-GMP_VERSION=6.2.0
++GMP_VERSION=6.2.1
+ MPFR_VERSION=4.1.0
+ MPC_VERSION=1.2.0
+ GCC_VERSION=8.3.0
+diff --git a/util/crossgcc/patches/gmp-6.2.0_generic-build.patch b/util/crossgcc/patches/gmp-6.2.1_generic-build.patch
+similarity index 100%
+rename from util/crossgcc/patches/gmp-6.2.0_generic-build.patch
+rename to util/crossgcc/patches/gmp-6.2.1_generic-build.patch
+diff --git a/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum
+deleted file mode 100644
+index b00b669fe7..0000000000
+--- a/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum
++++ /dev/null
+@@ -1 +0,0 @@
+-052a5411dc74054240eec58132d2cf41211d0ff6 tarballs/gmp-6.2.0.tar.xz
+diff --git a/util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum b/util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum
+new file mode 100644
+index 0000000000..3ea4232e59
+--- /dev/null
++++ b/util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum
+@@ -0,0 +1 @@
++0578d48607ec0e272177d175fd1807c30b00fdf2 tarballs/gmp-6.2.1.tar.xz
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0010-util-crossgcc-Update-mpc-to-1.2.1.patch b/resources/coreboot/default/patches/0010-util-crossgcc-Update-mpc-to-1.2.1.patch
new file mode 100644
index 00000000..0bd330d4
--- /dev/null
+++ b/resources/coreboot/default/patches/0010-util-crossgcc-Update-mpc-to-1.2.1.patch
@@ -0,0 +1,48 @@
+From b1533d4dca6b9c88f9e0418d5a93dd9a3c4cd7f3 Mon Sep 17 00:00:00 2001
+From: Patrick Georgi <pgeorgi@google.com>
+Date: Mon, 10 May 2021 23:35:51 +0200
+Subject: [PATCH 10/17] util/crossgcc: Update mpc to 1.2.1
+
+Change-Id: Ic1422464d0a95c9cba1c417aaa05e4f1fe799d26
+Signed-off-by: Patrick Georgi <pgeorgi@google.com>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/54048
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
+---
+ util/crossgcc/buildgcc | 2 +-
+ util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum | 1 -
+ util/crossgcc/sum/mpc-1.2.1.tar.gz.cksum | 1 +
+ 3 files changed, 2 insertions(+), 2 deletions(-)
+ delete mode 100644 util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum
+ create mode 100644 util/crossgcc/sum/mpc-1.2.1.tar.gz.cksum
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index d8f25dbbb8..abe602c821 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -34,7 +34,7 @@ THREADS=1
+ # GCC toolchain version numbers
+ GMP_VERSION=6.2.1
+ MPFR_VERSION=4.1.0
+-MPC_VERSION=1.2.0
++MPC_VERSION=1.2.1
+ GCC_VERSION=8.3.0
+ GCC_AUTOCONF_VERSION=2.69
+ BINUTILS_VERSION=2.35.1
+diff --git a/util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum b/util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum
+deleted file mode 100644
+index ed98cc0298..0000000000
+--- a/util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum
++++ /dev/null
+@@ -1 +0,0 @@
+-0abdc94acab0c9bfdaa391347cdfd7bbdb1cf017 tarballs/mpc-1.2.0.tar.gz
+diff --git a/util/crossgcc/sum/mpc-1.2.1.tar.gz.cksum b/util/crossgcc/sum/mpc-1.2.1.tar.gz.cksum
+new file mode 100644
+index 0000000000..84254eb5af
+--- /dev/null
++++ b/util/crossgcc/sum/mpc-1.2.1.tar.gz.cksum
+@@ -0,0 +1 @@
++2a4919abf445c6eda4e120cd669b8733ce337227 tarballs/mpc-1.2.1.tar.gz
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0011-tests-Enable-config-override-for-tests.patch b/resources/coreboot/default/patches/0011-tests-Enable-config-override-for-tests.patch
new file mode 100644
index 00000000..2aca94d5
--- /dev/null
+++ b/resources/coreboot/default/patches/0011-tests-Enable-config-override-for-tests.patch
@@ -0,0 +1,76 @@
+From 89236c7c44797cd8306d9509552bf0115ffe928a Mon Sep 17 00:00:00 2001
+From: Jakub Czapiga <jacz@semihalf.com>
+Date: Wed, 28 Apr 2021 16:50:51 +0200
+Subject: [PATCH 11/17] tests: Enable config override for tests
+
+Some tests require to change kconfig symbols values to cover the code.
+This patch enables one to set these vaues using <test-name>-config
+variable.
+
+Example for integer values.
+timestamp-test-config += CONFIG_HAVE_MONOTONIC_TIMER=1
+
+Example for string values. Notice escaped quotes.
+spd_cache-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"SPD_CACHE_FMAP_NAME\"
+
+Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
+Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/52937
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
+Reviewed-by: Julius Werner <jwerner@chromium.org>
+---
+ tests/Makefile.inc | 22 ++++++++++++++++++----
+ 1 file changed, 18 insertions(+), 4 deletions(-)
+
+diff --git a/tests/Makefile.inc b/tests/Makefile.inc
+index 44e3c69618..cd25e0f809 100644
+--- a/tests/Makefile.inc
++++ b/tests/Makefile.inc
+@@ -11,7 +11,7 @@ CMAKE:= cmake
+
+ TEST_DEFAULT_CONFIG = $(top)/configs/config.emulation_qemu_x86_i440fx
+ TEST_DOTCONFIG = $(testobj)/.config
+-TEST_KCONFIG_AUTOHEADER := $(testobj)/config.h
++TEST_KCONFIG_AUTOHEADER := $(testobj)/config.src.h
+ TEST_KCONFIG_AUTOCONFIG := $(testobj)/auto.conf
+ TEST_KCONFIG_DEPENDENCIES := $(testobj)/auto.conf.cmd
+ TEST_KCONFIG_SPLITCONFIG := $(testobj)/config
+@@ -52,7 +52,7 @@ TEST_CFLAGS += -fno-pie -fno-pic
+ TEST_LDFLAGS += -no-pie
+
+ # Extra attributes for unit tests, declared per test
+-attributes:= srcs cflags mocks stage
++attributes:= srcs cflags config mocks stage
+
+ stages:= decompressor bootblock romstage smm verstage
+ stages+= ramstage rmodule postcar libagesa
+@@ -83,9 +83,23 @@ $(call evaluate_subdirs)
+ # Create actual targets for unit test binaries
+ # $1 - test name
+ define TEST_CC_template
+-$($(1)-objs): TEST_CFLAGS+= \
++
++# Generate custom config.h redefining given symbols
++$(1)-config-file := $(obj)/$(1)/config.h
++$$($(1)-config-file): $(TEST_KCONFIG_AUTOHEADER)
++ mkdir -p $$(dir $$@)
++ printf '// File generated by tests/Makefile.inc\n// Do not change\n' > $$@
++ printf '#include <%s>\n\n' "$(notdir $(TEST_KCONFIG_AUTOHEADER))" >> $$@
++ for kv in $$($(1)-config); do \
++ key="`echo $$$$kv | cut -d '=' -f -1`"; \
++ value="`echo $$$$kv | cut -d '=' -f 2-`"; \
++ printf '#undef %s\n' "$$$$key" >> $$@; \
++ printf '#define %s %s\n\n' "$$$$key" "$$$$value" >> $$@; \
++ done
++
++$($(1)-objs): TEST_CFLAGS += -I$$(dir $$($(1)-config-file)) \
+ -D__$$(shell echo $$($(1)-stage) | tr '[:lower:]' '[:upper:]')__
+-$($(1)-objs): $(obj)/$(1)/%.o: $$$$*.c $(TEST_KCONFIG_AUTOHEADER)
++$($(1)-objs): $(obj)/$(1)/%.o: $$$$*.c $$($(1)-config-file)
+ mkdir -p $$(dir $$@)
+ $(HOSTCC) $(HOSTCFLAGS) $$(TEST_CFLAGS) $($(1)-cflags) -MMD \
+ -MT $$@ -c $$< -o $$@
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0012-src-Match-array-format-in-function-declarations-and-.patch b/resources/coreboot/default/patches/0012-src-Match-array-format-in-function-declarations-and-.patch
new file mode 100644
index 00000000..574e2e95
--- /dev/null
+++ b/resources/coreboot/default/patches/0012-src-Match-array-format-in-function-declarations-and-.patch
@@ -0,0 +1,193 @@
+From 7413a445b51db0adb9faf1bb21d8f6d2311a35d0 Mon Sep 17 00:00:00 2001
+From: Patrick Georgi <pgeorgi@google.com>
+Date: Wed, 12 May 2021 14:52:12 +0200
+Subject: [PATCH 12/17] src: Match array format in function declarations and
+ definitions
+
+gcc 11.1 complains when we're passing a type* into a function that was
+declared to get a type[], even if the ABI has identical parameter
+passing for both.
+
+To prepare for newer compilers, adapt to this added constraint.
+
+Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f
+Signed-off-by: Patrick Georgi <pgeorgi@google.com>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
+Reviewed-by: Felix Singer <felixsinger@posteo.net>
+Reviewed-by: Angel Pons <th3fanbus@gmail.com>
+---
+ src/mainboard/lenovo/t400/romstage.c | 2 +-
+ src/mainboard/lenovo/x200/romstage.c | 2 +-
+ src/mainboard/roda/rk9/romstage.c | 2 +-
+ src/soc/intel/alderlake/espi.c | 2 +-
+ src/soc/intel/cannonlake/lpc.c | 2 +-
+ src/soc/intel/elkhartlake/espi.c | 2 +-
+ src/soc/intel/icelake/espi.c | 2 +-
+ src/soc/intel/jasperlake/espi.c | 2 +-
+ src/soc/intel/skylake/lpc.c | 2 +-
+ src/soc/intel/tigerlake/espi.c | 2 +-
+ src/soc/intel/xeon_sp/lpc.c | 2 +-
+ src/vendorcode/mediatek/mt8192/dramc/dramc_top.c | 2 +-
+ 12 files changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
+index b4766ed737..aa3462a901 100644
+--- a/src/mainboard/lenovo/t400/romstage.c
++++ b/src/mainboard/lenovo/t400/romstage.c
+@@ -15,7 +15,7 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo)
+ sysinfo->enable_peg = peg;
+ }
+
+-void get_mb_spd_addrmap(u8 *spd_addrmap)
++void get_mb_spd_addrmap(u8 spd_addrmap[4])
+ {
+ spd_addrmap[0] = 0x50;
+ spd_addrmap[2] = 0x51;
+diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
+index 46cedfb07f..6764644274 100644
+--- a/src/mainboard/lenovo/x200/romstage.c
++++ b/src/mainboard/lenovo/x200/romstage.c
+@@ -3,7 +3,7 @@
+ #include <southbridge/intel/common/gpio.h>
+ #include <northbridge/intel/gm45/gm45.h>
+
+-void get_mb_spd_addrmap(u8 *spd_addrmap)
++void get_mb_spd_addrmap(u8 spd_addrmap[4])
+ {
+ spd_addrmap[0] = 0x50;
+ spd_addrmap[2] = 0x51;
+diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
+index be8ba5dbb3..dabef34707 100644
+--- a/src/mainboard/roda/rk9/romstage.c
++++ b/src/mainboard/roda/rk9/romstage.c
+@@ -2,7 +2,7 @@
+
+ #include <northbridge/intel/gm45/gm45.h>
+
+-void get_mb_spd_addrmap(u8 *spd_addrmap)
++void get_mb_spd_addrmap(u8 spd_addrmap[4])
+ {
+ spd_addrmap[0] = 0x50;
+ spd_addrmap[2] = 0x52;
+diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c
+index feec465a92..dd0edcde2c 100644
+--- a/src/soc/intel/alderlake/espi.c
++++ b/src/soc/intel/alderlake/espi.c
+@@ -20,7 +20,7 @@
+ #include <soc/pcr_ids.h>
+ #include <soc/soc_chip.h>
+
+-void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
++void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
+ {
+ const config_t *config = config_of_soc();
+
+diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
+index 20704e5bc6..0e63e0dc97 100644
+--- a/src/soc/intel/cannonlake/lpc.c
++++ b/src/soc/intel/cannonlake/lpc.c
+@@ -17,7 +17,7 @@
+
+ #include "chip.h"
+
+-void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
++void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
+ {
+ const config_t *config = config_of_soc();
+
+diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c
+index 1737a474ac..46646d8485 100644
+--- a/src/soc/intel/elkhartlake/espi.c
++++ b/src/soc/intel/elkhartlake/espi.c
+@@ -16,7 +16,7 @@
+ #include <soc/pcr_ids.h>
+ #include <soc/soc_chip.h>
+
+-void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
++void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
+ {
+ const config_t *config = config_of_soc();
+
+diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c
+index 489fe34223..d634cf8943 100644
+--- a/src/soc/intel/icelake/espi.c
++++ b/src/soc/intel/icelake/espi.c
+@@ -16,7 +16,7 @@
+ #include <soc/pcr_ids.h>
+ #include <soc/soc_chip.h>
+
+-void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
++void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
+ {
+ const config_t *config = config_of_soc();
+
+diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
+index c3b50de8f0..1d1f94e328 100644
+--- a/src/soc/intel/jasperlake/espi.c
++++ b/src/soc/intel/jasperlake/espi.c
+@@ -16,7 +16,7 @@
+ #include <soc/pcr_ids.h>
+ #include <soc/soc_chip.h>
+
+-void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
++void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
+ {
+ const config_t *config = config_of_soc();
+
+diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
+index 5abae765c9..5d38bb8683 100644
+--- a/src/soc/intel/skylake/lpc.c
++++ b/src/soc/intel/skylake/lpc.c
+@@ -14,7 +14,7 @@
+
+ #include "chip.h"
+
+-void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
++void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
+ {
+ const config_t *config = config_of_soc();
+
+diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
+index 8386cd9df1..427867622b 100644
+--- a/src/soc/intel/tigerlake/espi.c
++++ b/src/soc/intel/tigerlake/espi.c
+@@ -22,7 +22,7 @@
+ #include <soc/pcr_ids.h>
+ #include <soc/soc_chip.h>
+
+-void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
++void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
+ {
+ const config_t *config = config_of_soc();
+
+diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c
+index f0cb6db63d..dad0a4914d 100644
+--- a/src/soc/intel/xeon_sp/lpc.c
++++ b/src/soc/intel/xeon_sp/lpc.c
+@@ -8,7 +8,7 @@
+
+ #include <chip.h>
+
+-void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
++void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
+ {
+ const config_t *config = config_of_soc();
+
+diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
+index 8af6a36851..04fd62a27f 100644
+--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
++++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
+@@ -475,7 +475,7 @@ int get_dram_freq_cnt(void)
+ #if (FOR_DV_SIMULATION_USED==0)
+ #if !__FLASH_TOOL_DA__ && !__ETT__
+
+-void get_dram_rank_size(u64 dram_rank_size[DRAMC_MAX_RK])
++void get_dram_rank_size(u64 dram_rank_size[])
+ {
+ #ifdef COMBO_MCP
+ int index, rank_nr, i;
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0013-src-security-tpm-Deal-with-zero-length-tlcl-writes.patch b/resources/coreboot/default/patches/0013-src-security-tpm-Deal-with-zero-length-tlcl-writes.patch
new file mode 100644
index 00000000..183c6026
--- /dev/null
+++ b/resources/coreboot/default/patches/0013-src-security-tpm-Deal-with-zero-length-tlcl-writes.patch
@@ -0,0 +1,36 @@
+From 37589dc0c9c0bb78904b0b2b9aae0ba519eb6e04 Mon Sep 17 00:00:00 2001
+From: Patrick Georgi <pgeorgi@google.com>
+Date: Wed, 12 May 2021 14:54:49 +0200
+Subject: [PATCH 13/17] src/security/tpm: Deal with zero length tlcl writes
+
+While memcpy(foo, bar, 0) should be a no-op, that's hard to prove for a
+compiler and so gcc 11.1 complains about the use of an uninitialized
+"bar" even though it's harmless in this case.
+
+Change-Id: Idbffa508c2cd68790efbc0b4ab97ae1b4d85ad51
+Signed-off-by: Patrick Georgi <pgeorgi@google.com>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/54095
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
+Reviewed-by: Angel Pons <th3fanbus@gmail.com>
+---
+ src/security/tpm/tss/tcg-1.2/tss.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c
+index 8b7778ddb2..413b68193f 100644
+--- a/src/security/tpm/tss/tcg-1.2/tss.c
++++ b/src/security/tpm/tss/tcg-1.2/tss.c
+@@ -215,7 +215,8 @@ uint32_t tlcl_write(uint32_t index, const void *data, uint32_t length)
+
+ to_tpm_uint32(cmd.buffer + tpm_nv_write_cmd.index, index);
+ to_tpm_uint32(cmd.buffer + tpm_nv_write_cmd.length, length);
+- memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length);
++ if (length > 0)
++ memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length);
+
+ return tlcl_send_receive(cmd.buffer, response, sizeof(response));
+ }
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0014-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch b/resources/coreboot/default/patches/0014-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch
new file mode 100644
index 00000000..d2feee40
--- /dev/null
+++ b/resources/coreboot/default/patches/0014-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch
@@ -0,0 +1,27 @@
+From cff1ab192e04ca9c90b03bf4aa74d54db078d4d2 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:10:33 +0100
+Subject: [PATCH 14/17] lenovo/t400: set VRAM to 352MiB VRAM by default
+
+In the past, this caused stability issues so we set it to 256MiB. Nowadays,
+coreboot has fixed the issue preventing this. See:
+https://review.coreboot.org/c/coreboot/+/16831
+
+So, set the VRAM to 352MiB
+---
+ src/mainboard/lenovo/t400/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
+index a326e315b1..e74d15d030 100644
+--- a/src/mainboard/lenovo/t400/cmos.default
++++ b/src/mainboard/lenovo/t400/cmos.default
+@@ -13,4 +13,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ hybrid_graphics_mode=Integrated Only
+-gfx_uma_size=32M
++gfx_uma_size=352M
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0015-lenovo-x200-set-VRAM-to-352MiB-by-default.patch b/resources/coreboot/default/patches/0015-lenovo-x200-set-VRAM-to-352MiB-by-default.patch
new file mode 100644
index 00000000..7f0ac99e
--- /dev/null
+++ b/resources/coreboot/default/patches/0015-lenovo-x200-set-VRAM-to-352MiB-by-default.patch
@@ -0,0 +1,24 @@
+From 0daea37502732d3cc19404c2be7cb5b7be095456 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:11:59 +0100
+Subject: [PATCH 15/17] lenovo/x200: set VRAM to 352MiB by default
+
+This fix makes it possible:
+https://review.coreboot.org/c/coreboot/+/16831
+---
+ src/mainboard/lenovo/x200/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
+index bb4323836e..33a6a69f59 100644
+--- a/src/mainboard/lenovo/x200/cmos.default
++++ b/src/mainboard/lenovo/x200/cmos.default
+@@ -12,4 +12,4 @@ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=352M
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0016-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch b/resources/coreboot/default/patches/0016-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch
new file mode 100644
index 00000000..fb3d2ec3
--- /dev/null
+++ b/resources/coreboot/default/patches/0016-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch
@@ -0,0 +1,22 @@
+From 264ea6cfabe553059c888dea09046e6eac393d1b Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:18:26 +0100
+Subject: [PATCH 16/17] gigabyte/ga-g41m-es2l: set VRAM to 352MiB by default
+
+---
+ src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+index 8372032119..3a9a8e2d72 100644
+--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
++++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+-gfx_uma_size=64M
++gfx_uma_size=352M
+--
+2.25.1
+
diff --git a/resources/coreboot/default/patches/0017-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch b/resources/coreboot/default/patches/0017-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch
new file mode 100644
index 00000000..672f9776
--- /dev/null
+++ b/resources/coreboot/default/patches/0017-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch
@@ -0,0 +1,22 @@
+From a40d461be382e3897b4365f34b5e5872baf72334 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:21:39 +0100
+Subject: [PATCH 17/17] acer/g43t-am3: set VRAM to 352MiB by default
+
+---
+ src/mainboard/acer/g43t-am3/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
+index 706f5dd551..98899e8bf5 100644
+--- a/src/mainboard/acer/g43t-am3/cmos.default
++++ b/src/mainboard/acer/g43t-am3/cmos.default
+@@ -3,4 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=64M
++gfx_uma_size=352M
+--
+2.25.1
+