diff options
Diffstat (limited to 'config')
219 files changed, 19554 insertions, 5397 deletions
diff --git a/config/coreboot/d510mo/target.cfg b/config/coreboot/d510mo/target.cfg index 69c1db41..f07fee9a 100644 --- a/config/coreboot/d510mo/target.cfg +++ b/config/coreboot/d510mo/target.cfg @@ -4,3 +4,4 @@ payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" payload_memtest="y" +status="untested" diff --git a/config/coreboot/d510mo_16mb/target.cfg b/config/coreboot/d510mo_16mb/target.cfg index 1e7b56ca..a99b11f0 100644 --- a/config/coreboot/d510mo_16mb/target.cfg +++ b/config/coreboot/d510mo_16mb/target.cfg @@ -3,3 +3,4 @@ xarch="i386-elf" payload_seabios="y" payload_seabios_withgrub="y" payload_memtest="y" +status="untested" diff --git a/config/coreboot/d945gclf_512kb/target.cfg b/config/coreboot/d945gclf_512kb/target.cfg index cfae0b2c..5899fae2 100644 --- a/config/coreboot/d945gclf_512kb/target.cfg +++ b/config/coreboot/d945gclf_512kb/target.cfg @@ -4,3 +4,4 @@ payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" payload_memtest="n" +status="untested" diff --git a/config/coreboot/d945gclf_8mb/target.cfg b/config/coreboot/d945gclf_8mb/target.cfg index cfae0b2c..5899fae2 100644 --- a/config/coreboot/d945gclf_8mb/target.cfg +++ b/config/coreboot/d945gclf_8mb/target.cfg @@ -4,3 +4,4 @@ payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" payload_memtest="n" +status="untested" diff --git a/config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch b/config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch new file mode 100644 index 00000000..11f95a63 --- /dev/null +++ b/config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch @@ -0,0 +1,774 @@ +From 7dd58c8b301404a8bafee25a1e97a8a5d614b3d6 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Mon, 4 Mar 2024 18:05:43 -0700 +Subject: [PATCH] mb/dell: Add Latitude E5420 (Sandy Bridge) + +--- + src/mainboard/dell/e5420/Kconfig | 37 ++++ + src/mainboard/dell/e5420/Kconfig.name | 2 + + src/mainboard/dell/e5420/Makefile.mk | 5 + + src/mainboard/dell/e5420/acpi/ec.asl | 9 + + src/mainboard/dell/e5420/acpi/platform.asl | 12 ++ + src/mainboard/dell/e5420/acpi/superio.asl | 3 + + src/mainboard/dell/e5420/acpi_tables.c | 16 ++ + src/mainboard/dell/e5420/board_info.txt | 6 + + src/mainboard/dell/e5420/cmos.default | 9 + + src/mainboard/dell/e5420/cmos.layout | 88 ++++++++++ + src/mainboard/dell/e5420/data.vbt | Bin 0 -> 6144 bytes + src/mainboard/dell/e5420/devicetree.cb | 66 +++++++ + src/mainboard/dell/e5420/dsdt.asl | 30 ++++ + src/mainboard/dell/e5420/early_init.c | 32 ++++ + src/mainboard/dell/e5420/gma-mainboard.ads | 20 +++ + src/mainboard/dell/e5420/gpio.c | 195 +++++++++++++++++++++ + src/mainboard/dell/e5420/hda_verb.c | 33 ++++ + src/mainboard/dell/e5420/mainboard.c | 21 +++ + 18 files changed, 584 insertions(+) + create mode 100644 src/mainboard/dell/e5420/Kconfig + create mode 100644 src/mainboard/dell/e5420/Kconfig.name + create mode 100644 src/mainboard/dell/e5420/Makefile.mk + create mode 100644 src/mainboard/dell/e5420/acpi/ec.asl + create mode 100644 src/mainboard/dell/e5420/acpi/platform.asl + create mode 100644 src/mainboard/dell/e5420/acpi/superio.asl + create mode 100644 src/mainboard/dell/e5420/acpi_tables.c + create mode 100644 src/mainboard/dell/e5420/board_info.txt + create mode 100644 src/mainboard/dell/e5420/cmos.default + create mode 100644 src/mainboard/dell/e5420/cmos.layout + create mode 100755 src/mainboard/dell/e5420/data.vbt + create mode 100644 src/mainboard/dell/e5420/devicetree.cb + create mode 100644 src/mainboard/dell/e5420/dsdt.asl + create mode 100644 src/mainboard/dell/e5420/early_init.c + create mode 100644 src/mainboard/dell/e5420/gma-mainboard.ads + create mode 100644 src/mainboard/dell/e5420/gpio.c + create mode 100644 src/mainboard/dell/e5420/hda_verb.c + create mode 100644 src/mainboard/dell/e5420/mainboard.c + +diff --git a/src/mainboard/dell/e5420/Kconfig b/src/mainboard/dell/e5420/Kconfig +new file mode 100644 +index 0000000000..f4385045ae +--- /dev/null ++++ b/src/mainboard/dell/e5420/Kconfig +@@ -0,0 +1,37 @@ ++if BOARD_DELL_LATITUDE_E5420 ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select BOARD_ROMSIZE_KB_6144 ++ select EC_ACPI ++ select EC_DELL_MEC5035 ++ select GFX_GMA_PANEL_1_ON_LVDS ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT ++ select INTEL_INT15 ++ select MAINBOARD_HAS_LIBGFXINIT ++ select NORTHBRIDGE_INTEL_SANDYBRIDGE ++ select SERIRQ_CONTINUOUS_MODE ++ select SOUTHBRIDGE_INTEL_BD82X6X ++ select SYSTEM_TYPE_LAPTOP ++ select USE_NATIVE_RAMINIT ++ ++config DRAM_RESET_GATE_GPIO ++ default 60 ++ ++config MAINBOARD_DIR ++ default "dell/e5420" ++ ++config MAINBOARD_PART_NUMBER ++ default "Latitude E5420" ++ ++config USBDEBUG_HCD_INDEX ++ default 2 ++ ++config VGA_BIOS_ID ++ default "8086,0116" ++ ++endif # BOARD_DELL_LATITUDE_E5420 +diff --git a/src/mainboard/dell/e5420/Kconfig.name b/src/mainboard/dell/e5420/Kconfig.name +new file mode 100644 +index 0000000000..eb495fb705 +--- /dev/null ++++ b/src/mainboard/dell/e5420/Kconfig.name +@@ -0,0 +1,2 @@ ++config BOARD_DELL_LATITUDE_E5420 ++ bool "Latitude E5420" +diff --git a/src/mainboard/dell/e5420/Makefile.mk b/src/mainboard/dell/e5420/Makefile.mk +new file mode 100644 +index 0000000000..18391d8b18 +--- /dev/null ++++ b/src/mainboard/dell/e5420/Makefile.mk +@@ -0,0 +1,5 @@ ++bootblock-y += early_init.c ++bootblock-y += gpio.c ++romstage-y += early_init.c ++romstage-y += gpio.c ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/dell/e5420/acpi/ec.asl b/src/mainboard/dell/e5420/acpi/ec.asl +new file mode 100644 +index 0000000000..0d429410a9 +--- /dev/null ++++ b/src/mainboard/dell/e5420/acpi/ec.asl +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++Device(EC) ++{ ++ Name (_HID, EISAID("PNP0C09")) ++ Name (_UID, 0) ++ Name (_GPE, 16) ++/* FIXME: EC support */ ++} +diff --git a/src/mainboard/dell/e5420/acpi/platform.asl b/src/mainboard/dell/e5420/acpi/platform.asl +new file mode 100644 +index 0000000000..2d24bbd9b9 +--- /dev/null ++++ b/src/mainboard/dell/e5420/acpi/platform.asl +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++Method(_WAK, 1) ++{ ++ /* FIXME: EC support */ ++ Return(Package() {0, 0}) ++} ++ ++Method(_PTS,1) ++{ ++ /* FIXME: EC support */ ++} +diff --git a/src/mainboard/dell/e5420/acpi/superio.asl b/src/mainboard/dell/e5420/acpi/superio.asl +new file mode 100644 +index 0000000000..55b1db5b11 +--- /dev/null ++++ b/src/mainboard/dell/e5420/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <drivers/pc80/pc/ps2_controller.asl> +diff --git a/src/mainboard/dell/e5420/acpi_tables.c b/src/mainboard/dell/e5420/acpi_tables.c +new file mode 100644 +index 0000000000..e2759659bf +--- /dev/null ++++ b/src/mainboard/dell/e5420/acpi_tables.c +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <acpi/acpi_gnvs.h> ++#include <soc/nvs.h> ++ ++/* FIXME: check this function. */ ++void mainboard_fill_gnvs(struct global_nvs *gnvs) ++{ ++ /* The lid is open by default. */ ++ gnvs->lids = 1; ++ ++ /* Temperature at which OS will shutdown */ ++ gnvs->tcrt = 100; ++ /* Temperature at which OS will throttle CPU */ ++ gnvs->tpsv = 90; ++} +diff --git a/src/mainboard/dell/e5420/board_info.txt b/src/mainboard/dell/e5420/board_info.txt +new file mode 100644 +index 0000000000..34d5ad9e0b +--- /dev/null ++++ b/src/mainboard/dell/e5420/board_info.txt +@@ -0,0 +1,6 @@ ++Category: laptop ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2011 +diff --git a/src/mainboard/dell/e5420/cmos.default b/src/mainboard/dell/e5420/cmos.default +new file mode 100644 +index 0000000000..279415dfd1 +--- /dev/null ++++ b/src/mainboard/dell/e5420/cmos.default +@@ -0,0 +1,9 @@ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++bluetooth=Enable ++wwan=Enable ++wlan=Enable ++sata_mode=AHCI ++me_state=Disabled +diff --git a/src/mainboard/dell/e5420/cmos.layout b/src/mainboard/dell/e5420/cmos.layout +new file mode 100644 +index 0000000000..1aa7e77bce +--- /dev/null ++++ b/src/mainboard/dell/e5420/cmos.layout +@@ -0,0 +1,88 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++#400 8 r 0 reserved for century byte ++ ++# coreboot config options: southbridge ++408 1 e 1 nmi ++409 2 e 7 power_on_after_fail ++411 1 e 9 sata_mode ++ ++# coreboot config options: EC ++412 1 e 1 bluetooth ++413 1 e 1 wwan ++414 1 e 1 wlan ++ ++# coreboot config options: ME ++424 1 e 14 me_state ++425 2 h 0 me_state_prev ++ ++# coreboot config options: northbridge ++432 3 e 11 gfx_uma_size ++435 2 e 12 hybrid_graphics_mode ++440 8 h 0 volume ++ ++# VBOOT ++448 128 r 0 vbnv ++ ++# SandyBridge MRC Scrambler Seed values ++896 32 r 0 mrc_scrambler_seed ++928 32 r 0 mrc_scrambler_seed_s3 ++960 16 r 0 mrc_scrambler_seed_chk ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++9 0 AHCI ++9 1 Compatible ++11 0 32M ++11 1 64M ++11 2 96M ++11 3 128M ++11 4 160M ++11 5 192M ++11 6 224M ++14 0 Normal ++14 1 Disabled ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 447 984 +diff --git a/src/mainboard/dell/e5420/data.vbt b/src/mainboard/dell/e5420/data.vbt +new file mode 100755 +index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57 +GIT binary patch +literal 6144 +zcmeHKeQZ-z6hE);wSBvNZ!2$ObQ^;MgV6zl*Rhp}BXnCCMZU^_r7jRwT!kfLo8?3H +zk9)u(7?cb(hChhTM57@QFfmbMB!G!dNsO6BW5OSp5EGF^jHnTTdhUBI+h`e+1ft1q +z^SfW?+;h)4_uO+|XEfEV$91)<gOArWE)OnSTD}Ug6?8a~vz+SmQn!4~y3N7b^|hPp +zR<5aEfv-b8M00Lk251!oO|8(YA6XaeXzkt-Z)@Ee!_{@z#Fro^?DqN4SGjRIu8KYp +zZEufuU@5MM@7jv%h;75FS}ezKv?JDzCH}d%tE)A-GuDb*+B%}~w%88r>}c;!*XQ5O +z)OU7u$J@4U+lk)#GSW%c%c)v`%R6?`w)LIyu6bD7-j0o&X9qUMcEsYlW3BU4rZRvt +zqAUpjf*qXuLCCsU0YM2I5@gB1WKd)f1+Yt?%HWd0DZxYumP(K<LxTif8A39+!KMl} +z31FHG)7?qk5g>e?=ER{f^&}W<0k@mxff(?6+Stw+s6y%k1mM$cLk#^FWWI*9bE1GY +z&VY9?WC1u#23^3^UYw5?H0x2S2gN`x18Fko6_x(#MKyuCU_<D!mEp$qO_An}#@>DV +zdkf*li41yW3p$*0Oo3+63kO6S91*KwP#l2i4jnc)JkUirL^$k}VbH0;CBh#BS=OLf +zW-yE3BRon75gG{_2~QIC5cUzCC%i)FCmbidM>tIwAPf>N5Pl?FC0r*+Sq!oXj!keQ +zVKcyK>TL+gc7oLco$28+FpeeXkEP}_Sea=mk#IWUR^m$!BogvszLPu83FJm0k6K<l +z$#$~YiXtY*GpHp#@FvHJ1UnBD*H%d+{_j24XE4nmBa*?5mOWiold28s3}>*}<HaeO +z+1|-8g2)FCfkDZIdb-Ub);z0#;XEbPfGe?A72!{DAUg|$m+Z~(i@h9j4gtm611ni( +z#u>ACcP}M4exU`*MKVwl5+t6JBpTkmm}xWflKUe~7}`!#%z#gAo{NxUrpDAndYktu +zI0}VLU`J7^xmF1AFiz5S^uzp*DPI$%$qq!(ikh0kP+(GKzF|@N?Y%_#Vp@M+xHr$F +z=%+18z`-fT%z)9-TS$~Dh@2yeN7!UIt0h`fWxUu`JvA_ra*8P48l%7KR0&c1;0R75 +z4f0oz(xQ3MWqz5>qW5M4tZWExHs8<H(e1G@4km@5wEzOOP^x<l`YmA|eKs6j3wl8B +z%C%;uygh%<#kGZ{fymL+OlV0!-*T!V5IB>X@p!@CBU=7e{5^Jl{s7by`po-AJqM2l +znk(=^0bHkF0rUw7)^7j;$=_UIs8`6P6b-;vPDZ#U9L)W1_PAYRDP9k~;5$stt5ZiV +zD0>;i-?OlYY2}P9WVnfGos4xee2r=EGWHR}ADH$VV>cO=xU?!4TjIi)OMBYI_PX#b +zm-eBHed5BOT-x6*W>;{IqAga~G6lCQT93k>Q}CpsomJR*1%FjEkv?fuT%c-8RklXO +zU8;6KWk*zeU)4TW+1D!mrE0EhHZfbBeN{4S7X@Pig%};A99QTdA~wZruL*8y?K!jP +zG5R*k=);S}Zn<T;W!Mxt`(!+z7_r@3LVpf|FESauM&4}+wqzXfba-zG>A}on(uzNF +zyu>BcjA})C@bg%<;+Eh2;Sz4heFFCbZ@C{FrXMIbYzu>?Bi-|vZ}JSFU%JA>7$7et +z0Yo%CnOVZm#ZA}4kWZOn15};h5*#OM3b+6vHzgruMP>=5MNJK1y42{YgveP-!j%#( +z0rGe@8t%!=66Ti%K4|Gx=o7gFp83wQ;+s3H7+r^SKlpp3KKcr!3@|n;NCH_=qL=3T +zq3WH?en`b+W-HR-fnrhw*9aZ%M}lHX7@H?E>!6wv_&YQFEHdA$%Z1R--yub>=c@p? +z6@7Fc$&>sAxwiz{BE$1kb$K9Co=ozlA973y^i(^BM|EZ$$^y`0KyHiMJ%O*XbfEX1 +ziZaH>W(1pWL0bo|T!x__N$^$DpmxI=bL6WUK3JGyn?rw-qC4ZA$yGjIB}N(=ldD2O +zAJ@bxp<qR-3lIv<!P~SE8r*#_Ckl?$0|1fZ>2>n}u*mUIYFd>}O_wuwBD^r9<#=!0 +X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/e5420/devicetree.cb b/src/mainboard/dell/e5420/devicetree.cb +new file mode 100644 +index 0000000000..f26413557d +--- /dev/null ++++ b/src/mainboard/dell/e5420/devicetree.cb +@@ -0,0 +1,66 @@ ++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. ++ register "gfx" = "GMA_STATIC_DISPLAYS(1)" ++ register "gpu_cpu_backlight" = "0x00000c31" ++ register "gpu_dp_b_hotplug" = "4" ++ register "gpu_dp_c_hotplug" = "4" ++ register "gpu_dp_d_hotplug" = "4" ++ register "gpu_panel_port_select" = "0" ++ register "gpu_panel_power_backlight_off_delay" = "2300" ++ register "gpu_panel_power_backlight_on_delay" = "2300" ++ register "gpu_panel_power_cycle_delay" = "6" ++ register "gpu_panel_power_down_delay" = "400" ++ register "gpu_panel_power_up_delay" = "400" ++ register "gpu_pch_backlight" = "0x13121312" ++ ++ register "spd_addresses" = "{0x50, 0, 0x52, 0}" ++ ++ device domain 0x0 on ++ subsystemid 0x1028 0x049b inherit ++ ++ device ref host_bridge on end # Host bridge ++ device ref peg10 on end # PEG ++ device ref igd on end # iGPU ++ ++ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH ++ register "docking_supported" = "1" ++ register "gen1_dec" = "0x007c0681" ++ register "gen2_dec" = "0x007c0901" ++ register "gen3_dec" = "0x003c07e1" ++ register "gen4_dec" = "0x001c0901" ++ register "gpi0_routing" = "2" ++ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }" ++ register "pcie_port_coalesce" = "1" ++ register "sata_interface_speed_support" = "0x3" ++ register "sata_port_map" = "0x3b" ++ register "spi_lvscc" = "0x2005" ++ register "spi_uvscc" = "0x2005" ++ ++ device ref mei1 off end ++ device ref mei2 off end ++ device ref me_ide_r off end ++ device ref me_kt off end ++ device ref gbe off end ++ device ref ehci2 on end ++ device ref hda on end ++ device ref pcie_rp1 on end ++ device ref pcie_rp2 on end ++ device ref pcie_rp3 on end ++ device ref pcie_rp4 off end ++ device ref pcie_rp5 on end ++ device ref pcie_rp6 on end ++ device ref pcie_rp7 on end ++ device ref pcie_rp8 off end ++ device ref ehci1 on end ++ device ref pci_bridge off end ++ device ref lpc on ++ chip ec/dell/mec5035 ++ device pnp ff.0 on end ++ end ++ end ++ device ref sata1 on end ++ device ref smbus on end ++ device ref sata2 off end ++ device ref thermal off end ++ end ++ end ++end +diff --git a/src/mainboard/dell/e5420/dsdt.asl b/src/mainboard/dell/e5420/dsdt.asl +new file mode 100644 +index 0000000000..7d13c55b08 +--- /dev/null ++++ b/src/mainboard/dell/e5420/dsdt.asl +@@ -0,0 +1,30 @@ ++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB ++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++ ++#include <acpi/acpi.h> ++ ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20141018 /* OEM revision */ ++) ++{ ++ #include <acpi/dsdt_top.asl> ++ #include "acpi/platform.asl" ++ #include <cpu/intel/common/acpi/cpu.asl> ++ #include <southbridge/intel/common/acpi/platform.asl> ++ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> ++ #include <southbridge/intel/common/acpi/sleepstates.asl> ++ ++ Device (\_SB.PCI0) ++ { ++ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> ++ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> ++ #include <southbridge/intel/bd82x6x/acpi/pch.asl> ++ } ++} +diff --git a/src/mainboard/dell/e5420/early_init.c b/src/mainboard/dell/e5420/early_init.c +new file mode 100644 +index 0000000000..7297921546 +--- /dev/null ++++ b/src/mainboard/dell/e5420/early_init.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++ ++#include <bootblock_common.h> ++#include <device/pci_ops.h> ++#include <ec/dell/mec5035/mec5035.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++ ++const struct southbridge_usb_port mainboard_usb_ports[] = { ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 1, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 1, 3 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 1, 7 }, ++ { 1, 1, 6 }, ++ { 1, 1, 6 }, ++ { 1, 1, 7 }, ++}; ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/e5420/gma-mainboard.ads b/src/mainboard/dell/e5420/gma-mainboard.ads +new file mode 100644 +index 0000000000..2a16f44360 +--- /dev/null ++++ b/src/mainboard/dell/e5420/gma-mainboard.ads +@@ -0,0 +1,20 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ ( ++ HDMI1, -- mainboard HDMI ++ DP2, -- dock DP ++ DP3, -- dock DP ++ Analog, -- mainboard VGA ++ LVDS, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/e5420/gpio.c b/src/mainboard/dell/e5420/gpio.c +new file mode 100644 +index 0000000000..f76b93d9f0 +--- /dev/null ++++ b/src/mainboard/dell/e5420/gpio.c +@@ -0,0 +1,195 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <southbridge/intel/common/gpio.h> ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_GPIO, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_NATIVE, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio12 = GPIO_DIR_OUTPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio12 = GPIO_LEVEL_HIGH, ++ .gpio30 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_GPIO, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_NATIVE, ++ .gpio50 = GPIO_MODE_GPIO, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_GPIO, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_GPIO, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_OUTPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio46 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio50 = GPIO_DIR_OUTPUT, ++ .gpio51 = GPIO_DIR_OUTPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio53 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio55 = GPIO_DIR_OUTPUT, ++ .gpio56 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_LOW, ++ .gpio37 = GPIO_LEVEL_LOW, ++ .gpio46 = GPIO_LEVEL_HIGH, ++ .gpio50 = GPIO_LEVEL_HIGH, ++ .gpio51 = GPIO_LEVEL_LOW, ++ .gpio55 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_NATIVE, ++ .gpio69 = GPIO_MODE_NATIVE, ++ .gpio70 = GPIO_MODE_NATIVE, ++ .gpio71 = GPIO_MODE_NATIVE, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_GPIO, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio74 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/e5420/hda_verb.c b/src/mainboard/dell/e5420/hda_verb.c +new file mode 100644 +index 0000000000..70e7c2e79a +--- /dev/null ++++ b/src/mainboard/dell/e5420/hda_verb.c +@@ -0,0 +1,33 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/azalia_device.h> ++ ++const u32 cim_verb_data[] = { ++ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ ++ 0x1028049b, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x1028049b), ++ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0xd5a30130), ++ ++ 0x80862805, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++ ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/e5420/mainboard.c b/src/mainboard/dell/e5420/mainboard.c +new file mode 100644 +index 0000000000..31e49802fc +--- /dev/null ++++ b/src/mainboard/dell/e5420/mainboard.c +@@ -0,0 +1,21 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <device/device.h> ++#include <drivers/intel/gma/int15.h> ++#include <southbridge/intel/bd82x6x/pch.h> ++#include <ec/acpi/ec.h> ++#include <console/console.h> ++#include <pc80/keyboard.h> ++ ++static void mainboard_enable(struct device *dev) ++{ ++ ++ /* FIXME: fix these values. */ ++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, ++ GMA_INT15_PANEL_FIT_DEFAULT, ++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++}; +-- +2.44.0 + diff --git a/config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch b/config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch new file mode 100644 index 00000000..f4c3939c --- /dev/null +++ b/config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch @@ -0,0 +1,66 @@ +From 4889f08306f1530211dcc6f6a4e999c6cc72f3ac Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Sat, 30 Mar 2024 05:57:54 +0000 +Subject: [PATCH 1/1] fix sata ports on dell 9020 sff and mt + +mate kukri has a patch under review on coreboot that sets +sata port map to 0x7 on sff and 0xf on mt. + +see: intel 8 series pch datasheet, section 13.1.35 + +basically, the 6 least significant bits enable the sata +slots; 1 for enable and 0 for disable. there can be up +to 6 ports. least significant bit is port 0, then next +is port 1, and so on. + +coreboot currently enables ports 0, 1, 4 and 5, making this +value 0x33 (converted to binary: 00110011). sff has ports +0, 1 and 2 wired, so mate changed that to 0x7 (00000111). + +on mt, the blue ports are ports 0 and 1, but the two white +ports don't work, but coreboot enables 4 and 5; it is +likely that the blue ports are in fact 0 and 1, and the +white ports are 2 and 3, but we've not tested this! + +it could be that the blue ports are ports 4 and 5, and +the white ports are 2 and 3! we have not yet determined +this, but mate set it to 0xf, meaning ports 0 1 2 and 3 +are enabled, in his patch under review. the chance that +it's 2, 3, 4 and 5 on the board is unlikely, but it is +theoretically possible and has not been confirmed. + +therefore, for now, i will set the value to 0x3f, which +in binary is 00111111, thus enabling all 6 slots. the two +that aren't physically wired don't really matter. enabling +ports (from the pch) that electrically aren't there and +then powering on is electrically equivalent to those ports +being actually being wired, but with no devices plugged +into them. therefore, 0x3f is an effective shotgun fix. + +i'll remove this patch and use mate's fix when the latter +has been tested on MT; it has already been tested on SFF. + +this patch fixes the 3rd sata slot on 9020 sff, and the 3rd +and 4th sata slots on 9020 MT + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/mainboard/dell/optiplex_9020/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb +index c0b17a15ff..7bfa6736a6 100644 +--- a/src/mainboard/dell/optiplex_9020/devicetree.cb ++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb +@@ -23,7 +23,7 @@ chip northbridge/intel/haswell + register "gen2_dec" = "0x007c0901" + register "gen3_dec" = "0x003c07e1" + register "gen4_dec" = "0x001c0901" +- register "sata_port_map" = "0x33" ++ register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # Management Engine interface 1 +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch new file mode 100644 index 00000000..7a02d902 --- /dev/null +++ b/config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch @@ -0,0 +1,54 @@ +From c6ce9c635e6576c86c546177c3d770dec2f3c9ae Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Fri, 23 Feb 2024 13:33:31 +0000 +Subject: [PATCH 1/1] nb/haswell: Disable iGPU when dGPU is used + +This is usually is handled by Haswell mrc.bin, disabling VGA +decode on the iGPU when a dGPU is installed. However, Broadwell +mrc.bin does not, so the iGPU and dGPU are both enabled. + +This patch disables legacy VGA cycles for iGPU, under such +conditions. It has been tested on Broadwell mrc.bin when +using a graphics card on Dell OptiPlex 9020 SFF (currently +under review at this time of writing, submitted by Mate +Kukri). + +This patch has also been tested when Haswell mrc.bin is used, +and there are seemingly no breaking changes caused by it. + +Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b +Signed-off-by: Leah Rowe <info@minifree.org> +Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717 +Tested-by: build bot (Jenkins) <no-reply@coreboot.org> +Reviewed-by: Nico Huber <nico.h@gmx.de> +--- + src/northbridge/intel/haswell/gma.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c +index 6e6948b70f..48a0ba54c7 100644 +--- a/src/northbridge/intel/haswell/gma.c ++++ b/src/northbridge/intel/haswell/gma.c +@@ -461,12 +461,19 @@ static void gma_generate_ssdt(const struct device *dev) + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); + } + ++static void gma_func0_disable(struct device *dev) ++{ ++ /* Disable VGA decode */ ++ pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); ++} ++ + static struct device_operations gma_func0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, + .acpi_fill_ssdt = gma_generate_ssdt, ++ .vga_disable = gma_func0_disable, + .ops_pci = &pci_dev_ops_pci, + }; + +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch new file mode 100644 index 00000000..bc8fd55c --- /dev/null +++ b/config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -0,0 +1,51 @@ +From 0801b3ba8a0ce0109e30d27f405c912d5d705e9c Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Sat, 6 Apr 2024 01:22:47 +0100 +Subject: [PATCH 1/1] nb/haswell: Fully disable iGPU when dGPU is used + +My earlier patch disabled decode *and* disabled the iGPU itself, but +a subsequent revision disabled only VGA decode. Upon revisiting, I +found that, actually, yes, you also need to disable the iGPU entirely. + +Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU. +With this patch, the iGPU is completely disabled when you install a +graphics card, but the iGPU is available to use when no graphics card +is present. + +For more context, see: + +Author: Leah Rowe <info@minifree.org> +Date: Fri Feb 23 13:33:31 2024 +0000 + + nb/haswell: Disable iGPU when dGPU is used + +And look at the Gerrit comments: + +https://review.coreboot.org/c/coreboot/+/80717/ + +So, my original submission on change 80717 was actually correct. +This patch fixes the issue. I tested on iGPU and dGPU, with both +broadwell and haswell mrc.bin. + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/northbridge/intel/haswell/gma.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c +index 48a0ba54c7..f0b848852d 100644 +--- a/src/northbridge/intel/haswell/gma.c ++++ b/src/northbridge/intel/haswell/gma.c +@@ -465,6 +465,9 @@ static void gma_func0_disable(struct device *dev) + { + /* Disable VGA decode */ + pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); ++ ++ /* Required or else the graphics card doesn't work */ ++ dev->enabled = 0; + } + + static struct device_operations gma_func0_ops = { +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch b/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch new file mode 100644 index 00000000..37353e20 --- /dev/null +++ b/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch @@ -0,0 +1,602 @@ +From c58e0fea2a4e591e5ecd8a1f376c3b3af0fbb306 Mon Sep 17 00:00:00 2001 +From: Mate Kukri <kukri.mate@gmail.com> +Date: Thu, 18 Apr 2024 20:28:45 +0100 +Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization + +There are 4 different chassis types specified by vendor firmware, each +with a slightly different HWM configuration. + +The chassis type to use is determined at runtime by reading a set of +4 PCH GPIOs: 70, 38, 17, and 1. + +Additionally vendor firmware also provides an option to run the fans at +full speed. This is substituted with a coreboot nvram option in this +implementation. + +This was tested to make fan control work on my OptiPlex 7020 SFF. + +NOTE: This is superficially similar to the OptiPlex 9010's SCH5545 +however the OptiPlex 9020's SCH5555 does not use externally +programmed EC firmware. + +Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 +Signed-off-by: Mate Kukri <kukri.mate@gmail.com> +--- + src/mainboard/dell/optiplex_9020/Makefile.inc | 3 +- + src/mainboard/dell/optiplex_9020/bootblock.c | 25 +- + src/mainboard/dell/optiplex_9020/cmos.default | 1 + + src/mainboard/dell/optiplex_9020/cmos.layout | 5 +- + src/mainboard/dell/optiplex_9020/mainboard.c | 387 ++++++++++++++++++ + src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++ + src/mainboard/dell/optiplex_9020/sch5555_ec.h | 10 + + 7 files changed, 463 insertions(+), 22 deletions(-) + create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c + create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h + +diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc +index 6ca2f2afaa..08e2e53577 100644 +--- a/src/mainboard/dell/optiplex_9020/Makefile.inc ++++ b/src/mainboard/dell/optiplex_9020/Makefile.inc +@@ -2,4 +2,5 @@ + + romstage-y += gpio.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +-bootblock-y += bootblock.c ++ramstage-y += sch5555_ec.c ++bootblock-y += bootblock.c sch5555_ec.c +diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c +index 2837cf9cf1..e5e759273e 100644 +--- a/src/mainboard/dell/optiplex_9020/bootblock.c ++++ b/src/mainboard/dell/optiplex_9020/bootblock.c +@@ -4,29 +4,14 @@ + #include <device/pnp_ops.h> + #include <superio/smsc/sch555x/sch555x.h> + #include <southbridge/intel/lynxpoint/pch.h> +- +-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) +-{ +- // Clear EC-to-Host mailbox +- uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); +- outb(tmp, SCH555x_EMI_IOBASE + 1); +- +- // Send address and value to the EC +- sch555x_emi_write16(0, (addr1 * 2) | 0x101); +- sch555x_emi_write32(4, val | (addr2 << 16)); +- +- // Wait for acknowledgement message from EC +- outb(1, SCH555x_EMI_IOBASE); +- size_t timeout = 0; +- do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0); +-} ++#include "sch5555_ec.h" + + struct ec_init_entry { + uint16_t addr; + uint8_t val; + }; + +-static void ec_init(void) ++static void bootblock_ec_init(void) + { + /* + * Tables from CORE_PEI +@@ -108,9 +93,9 @@ void mainboard_config_superio(void) + outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); + outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); + +- // Magic EC init +- ec_init(); ++ // Perform bootblock EC initialization ++ bootblock_ec_init(); + +- // Magic EC init is needed for UART1 initialization to work ++ // Bootblock EC initialization is required for UART1 to work + sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + } +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index 7bccc80e51..1909abcb9f 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -3,3 +3,4 @@ debug_level=Debug + nmi=Disable + power_on_after_fail=Disable + iommu=Disable ++fan_full_speed=Disable +diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout +index 72ff9c4bee..4a1496a878 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.layout ++++ b/src/mainboard/dell/optiplex_9020/cmos.layout +@@ -22,7 +22,10 @@ entries + 409 2 e 5 power_on_after_fail + + # turn iommu on or off +-412 1 e 6 iommu ++411 1 e 6 iommu ++ ++# coreboot config options: EC ++412 1 e 1 fan_full_speed + + # coreboot config options: check sums + 984 16 h 0 check_sum +diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c +index c834fea5d3..0b7829c736 100644 +--- a/src/mainboard/dell/optiplex_9020/mainboard.c ++++ b/src/mainboard/dell/optiplex_9020/mainboard.c +@@ -1,7 +1,12 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + ++#include <bootstate.h> ++#include <cpu/x86/msr.h> + #include <device/device.h> + #include <drivers/intel/gma/int15.h> ++#include <option.h> ++#include <southbridge/intel/common/gpio.h> ++#include "sch5555_ec.h" + + static void mainboard_enable(struct device *dev) + { +@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev) + struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + }; ++ ++#define HWM_TAB_ADD_TEMP_TARGET 1 ++#define HWM_TAB_PKG_POWER_ANY 0xffff ++#define CHASSIS_TYPE_UNKNOWN 0xff ++ ++struct hwm_tab_entry { ++ uint16_t addr; ++ uint8_t val; ++ uint8_t flags; ++ uint16_t pkg_power; ++}; ++ ++struct hwm_tab_entry HWM_TAB3[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x8a, 0, 0x0010 }, ++ { 0x086, 0x4c, 0, 0x0010 }, ++ { 0x08a, 0x66, 0, 0x0010 }, ++ { 0x08b, 0x5b, 0, 0x0010 }, ++ { 0x090, 0x65, 0, 0xffff }, ++ { 0x091, 0x70, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0e, 0, 0xffff }, ++ { 0x0a1, 0x0e, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x86, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x9a, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x99, 0, 0xffff }, ++ { 0x280, 0xa0, 0, 0x0010 }, ++ { 0x281, 0x0f, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x68, 0, 0x0010 }, ++ { 0x289, 0x10, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB4[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x99, 0, 0x0020 }, ++ { 0x085, 0xad, 0, 0x0010 }, ++ { 0x086, 0x1c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x41, 0, 0x0010 }, ++ { 0x08b, 0x76, 0, 0x0020 }, ++ { 0x08b, 0x8b, 0, 0x0010 }, ++ { 0x090, 0x5e, 0, 0xffff }, ++ { 0x091, 0x5e, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0a, 0, 0xffff }, ++ { 0x0a1, 0x0a, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x90, 0, 0xffff }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x28, 0, 0x0020 }, ++ { 0x289, 0x0a, 0, 0x0020 }, ++ { 0x288, 0x28, 0, 0x0010 }, ++ { 0x289, 0x0a, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB5[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x66, 0, 0x0020 }, ++ { 0x085, 0x5d, 0, 0x0010 }, ++ { 0x086, 0x1c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x41, 0, 0x0010 }, ++ { 0x08b, 0x76, 0, 0x0020 }, ++ { 0x08b, 0x80, 0, 0x0010 }, ++ { 0x090, 0x5d, 0, 0x0020 }, ++ { 0x090, 0x5e, 0, 0x0010 }, ++ { 0x091, 0x5e, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa3, 0, 0x0020 }, ++ { 0x098, 0xa4, 0, 0x0010 }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x08, 0, 0xffff }, ++ { 0x0a1, 0x0a, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x98, 0, 0x0020 }, ++ { 0x1be, 0x90, 0, 0x0010 }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x28, 0, 0x0020 }, ++ { 0x289, 0x0a, 0, 0x0020 }, ++ { 0x288, 0x28, 0, 0x0010 }, ++ { 0x289, 0x0a, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB6[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x98, 0, 0xffff }, ++ { 0x086, 0x3c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x3d, 0, 0x0010 }, ++ { 0x08b, 0x44, 0, 0x0020 }, ++ { 0x08b, 0x51, 0, 0x0010 }, ++ { 0x090, 0x61, 0, 0xffff }, ++ { 0x091, 0x6d, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0x9f, 0, 0x0020 }, ++ { 0x098, 0xa4, 0, 0x0010 }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0e, 0, 0xffff }, ++ { 0x0a1, 0x0e, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9b, 0, 0x0020 }, ++ { 0x0b0, 0x98, 0, 0x0010 }, ++ { 0x0b3, 0x9a, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x9a, 0, 0x0020 }, ++ { 0x1be, 0x96, 0, 0x0010 }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x94, 0, 0x0020 }, ++ { 0x289, 0x11, 0, 0x0020 }, ++ { 0x288, 0x94, 0, 0x0010 }, ++ { 0x289, 0x11, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++static uint8_t get_chassis_type(void) ++{ ++ uint8_t gpio_chassis_type; ++ ++ // Read chassis type from GPIO ++ gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 | ++ get_gpio(17) << 1 | get_gpio(1); ++ ++ printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type); ++ ++ // Turn it into internal chassis index ++ switch (gpio_chassis_type) { ++ case 0x08: ++ case 0x0a: ++ return 4; ++ case 0x0b: ++ return 3; ++ case 0x0c: ++ return 5; ++ case 0x0d: // SFF ++ case 0x0e: ++ case 0x0f: ++ return 6; ++ default: ++ return CHASSIS_TYPE_UNKNOWN; ++ } ++ ++} ++ ++static uint8_t get_temp_target(void) ++{ ++ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; ++ if (!val) ++ val = 20; ++ return 0x95 - val; ++} ++ ++static uint16_t get_pkg_power(void) ++{ ++ uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf; ++ if (rapl_power_unit) ++ rapl_power_unit = 2 << (rapl_power_unit - 1); ++ uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff; ++ if (pkg_power_info / rapl_power_unit > 0x41) ++ return 32; ++ else ++ return 16; ++} ++ ++static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size) ++{ ++ uint8_t temp_target = get_temp_target(); ++ uint16_t pkg_power = get_pkg_power(); ++ ++ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); ++ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); ++ ++ for (size_t i = 0; i < size; ++i) { ++ // Skip entry if it doesn't apply for this package power ++ if (arr[i].pkg_power != pkg_power && ++ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) ++ continue; ++ ++ uint8_t val = arr[i].val; ++ ++ // Add temp target to value if requested (current tables never do) ++ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) ++ val += temp_target; ++ ++ // Perform write ++ ec_write(1, arr[i].addr, val); ++ ++ } ++} ++ ++static void sch5555_ec_hwm_init(void *arg) ++{ ++ uint8_t chassis_type, saved_2fc; ++ ++ printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n"); ++ ++ saved_2fc = ec_read(1, 0x2fc); ++ ec_write(1, 0x2fc, 0xa0); ++ ec_write(1, 0x2fd, 0x32); ++ ++ chassis_type = get_chassis_type(); ++ ++ if (chassis_type != CHASSIS_TYPE_UNKNOWN) { ++ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); ++ } else { ++ printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n"); ++ } ++ ++ // Apply HWM table based on chassis type ++ switch (chassis_type) { ++ case 3: ++ apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3)); ++ break; ++ case 4: ++ apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4)); ++ break; ++ case 5: ++ apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5)); ++ break; ++ case 6: ++ apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6)); ++ break; ++ } ++ ++ // NOTE: vendor firmware applies these when "max core address" > 2 ++ // i think this is always the case ++ ec_write(1, 0x9e, 0x30); ++ ec_write(1, 0xeb, ec_read(1, 0xea)); ++ ++ ec_write(1, 0x2fc, saved_2fc); ++ ++ // Apply full speed fan config if requested or if the chassis type is unknown ++ if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) { ++ printk(BIOS_DEBUG, "Setting full fan speed\n"); ++ ec_write(1, 0x80, 0x60 | ec_read(1, 0x80)); ++ ec_write(1, 0x81, 0x60 | ec_read(1, 0x81)); ++ } ++ ++ ec_read(1, 0xb8); ++ ++ if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) { ++ ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb); ++ ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb); ++ ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb); ++ ec_write(1, 0x8a, 0x99); ++ ec_write(1, 0x8b, 0x47); ++ ec_write(1, 0x8c, 0x91); ++ } ++} ++ ++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); +diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c +new file mode 100644 +index 0000000000..a1067ac063 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c +@@ -0,0 +1,54 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <arch/io.h> ++#include <device/pnp_ops.h> ++#include <superio/smsc/sch555x/sch555x.h> ++#include "sch5555_ec.h" ++ ++uint8_t ec_read(uint8_t addr1, uint16_t addr2) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++ ++ // read result ++ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); ++ return inb(SCH555x_EMI_IOBASE + 4); ++} ++ ++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address and value ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++} +diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h +new file mode 100644 +index 0000000000..7e399e8e74 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h +@@ -0,0 +1,10 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __SCH5555_EC_H__ ++#define __SCH5555_EC_H__ ++ ++uint8_t ec_read(uint8_t addr1, uint16_t addr2); ++ ++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val); ++ ++#endif +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch b/config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch new file mode 100644 index 00000000..556e8e07 --- /dev/null +++ b/config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch @@ -0,0 +1,49 @@ +From cd3c553a313a26494e5dc31ff8323c3a919f190a Mon Sep 17 00:00:00 2001 +From: Mate Kukri <kukri.mate@gmail.com> +Date: Wed, 10 Apr 2024 20:31:35 +0100 +Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device + +These machines come with a TPM1.2 device by default. It is somewhat +obsolete these days, but there is no harm in enabling it. + +Change-Id: Iec05321862aed58695c256b00494e5953219786d +Signed-off-by: Mate Kukri <kukri.mate@gmail.com> +Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827 +Reviewed-by: Angel Pons <th3fanbus@gmail.com> +Tested-by: build bot (Jenkins) <no-reply@coreboot.org> +--- + src/mainboard/dell/optiplex_9020/Kconfig | 2 ++ + src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++ + 2 files changed, 5 insertions(+) + +diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig +index 774a72f161..296938aa8d 100644 +--- a/src/mainboard/dell/optiplex_9020/Kconfig ++++ b/src/mainboard/dell/optiplex_9020/Kconfig +@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION ++ select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT +diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb +index 7bfa6736a6..e5cbd64127 100644 +--- a/src/mainboard/dell/optiplex_9020/devicetree.cb ++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb +@@ -70,6 +70,9 @@ chip northbridge/intel/haswell + device pnp 2e.b off end # Floppy Controller + device pnp 2e.11 off end # Parallel Port + end ++ chip drivers/pc80/tpm ++ device pnp 0c31.0 on end ++ end + end + device pci 1f.2 on end # SATA controller 1 + device pci 1f.3 on end # SMBus +-- +2.39.2 + diff --git a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..509e784e --- /dev/null +++ b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,640 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +CONFIG_UTIL_GENPARSER=y +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..428bed87 --- /dev/null +++ b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode @@ -0,0 +1,637 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +CONFIG_UTIL_GENPARSER=y +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020mt-nri_12mb/target.cfg b/config/coreboot/dell9020mt-nri_12mb/target.cfg new file mode 100644 index 00000000..bc4053d4 --- /dev/null +++ b/config/coreboot/dell9020mt-nri_12mb/target.cfg @@ -0,0 +1,8 @@ +tree="haswell" +xarch="i386-elf" +payload_seabios="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +payload_memtest="y" +grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb index 1925ed68..2fbd5982 100644 --- a/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb @@ -135,6 +135,8 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set @@ -183,6 +185,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -427,6 +430,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -457,6 +462,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers @@ -479,7 +486,13 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 @@ -494,6 +507,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode index ffca5b39..c92a7c7c 100644 --- a/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode @@ -133,6 +133,8 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set @@ -181,6 +183,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -423,6 +426,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -453,6 +458,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y @@ -476,7 +483,13 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 @@ -491,6 +504,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020mt_12mb/target.cfg b/config/coreboot/dell9020mt_12mb/target.cfg index e6d3bec6..a3acd5fb 100644 --- a/config/coreboot/dell9020mt_12mb/target.cfg +++ b/config/coreboot/dell9020mt_12mb/target.cfg @@ -5,3 +5,5 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" +status="stable" diff --git a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..2878f894 --- /dev/null +++ b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,649 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT" +CONFIG_HAVE_IFD_BIN=y +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..35bbcf5b --- /dev/null +++ b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode @@ -0,0 +1,646 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT" +CONFIG_HAVE_IFD_BIN=y +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020mtbmrc_12mb/target.cfg b/config/coreboot/dell9020mtbmrc_12mb/target.cfg new file mode 100644 index 00000000..a3acd5fb --- /dev/null +++ b/config/coreboot/dell9020mtbmrc_12mb/target.cfg @@ -0,0 +1,9 @@ +tree="default" +xarch="i386-elf" +payload_seabios="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +payload_memtest="y" +grub_scan_disk="ahci" +release="n" +status="stable" diff --git a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..ac1d9f16 --- /dev/null +++ b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,640 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_E6400 is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..179af9cc --- /dev/null +++ b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode @@ -0,0 +1,637 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_E6400 is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020sff-nri_12mb/target.cfg b/config/coreboot/dell9020sff-nri_12mb/target.cfg new file mode 100644 index 00000000..bc4053d4 --- /dev/null +++ b/config/coreboot/dell9020sff-nri_12mb/target.cfg @@ -0,0 +1,8 @@ +tree="haswell" +xarch="i386-elf" +payload_seabios="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +payload_memtest="y" +grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb index ada13b04..65d9ddf2 100644 --- a/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb @@ -135,6 +135,8 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set @@ -183,6 +185,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -427,6 +430,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -457,6 +462,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers @@ -479,7 +486,13 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 @@ -494,6 +507,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode index d6279c26..127c034d 100644 --- a/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode @@ -133,6 +133,8 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set @@ -181,6 +183,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -423,6 +426,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -453,6 +458,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y @@ -476,7 +483,13 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 @@ -491,6 +504,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020sff_12mb/target.cfg b/config/coreboot/dell9020sff_12mb/target.cfg index e6d3bec6..a3acd5fb 100644 --- a/config/coreboot/dell9020sff_12mb/target.cfg +++ b/config/coreboot/dell9020sff_12mb/target.cfg @@ -5,3 +5,5 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" +status="stable" diff --git a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..f544407a --- /dev/null +++ b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,649 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF" +CONFIG_HAVE_IFD_BIN=y +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..0586764c --- /dev/null +++ b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode @@ -0,0 +1,646 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF" +CONFIG_HAVE_IFD_BIN=y +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020sffbmrc_12mb/target.cfg b/config/coreboot/dell9020sffbmrc_12mb/target.cfg new file mode 100644 index 00000000..a3acd5fb --- /dev/null +++ b/config/coreboot/dell9020sffbmrc_12mb/target.cfg @@ -0,0 +1,9 @@ +tree="default" +xarch="i386-elf" +payload_seabios="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +payload_memtest="y" +grub_scan_disk="ahci" +release="n" +status="stable" diff --git a/config/coreboot/e5420_6mb/config/libgfxinit_corebootfb b/config/coreboot/e5420_6mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..9abe57a3 --- /dev/null +++ b/config/coreboot/e5420_6mb/config/libgfxinit_corebootfb @@ -0,0 +1,620 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="Latitude E5420" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/e5420" +CONFIG_VGA_BIOS_ID="8086,0116" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x5ea000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_DRAM_RESET_GATE_GPIO=60 +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_BOARD_DELL_LATITUDE_E5420=y +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xfefe0000 +CONFIG_DCACHE_RAM_SIZE=0x20000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe" +CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5420" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_GFX_GMA_PANEL_1_PORT="LVDS" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_6144=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +CONFIG_COREBOOT_ROMSIZE_KB_6144=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=6144 +CONFIG_ROM_SIZE=0x00600000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +# CONFIG_USE_EXP_X86_64_SUPPORT is not set +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_MODEL_206AX=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_USE_NATIVE_RAMINIT=y +CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y +# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set +# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set +# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set +# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set +CONFIG_RAMINIT_ENABLE_ECC=y + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y +# CONFIG_HIDE_MEI_ON_ERROR is not set +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_DELL_MEC5035=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_HAVE_EXP_X86_64_SUPPORT=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x800 +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Ironlake" +CONFIG_GFX_GMA_PCH="Cougar_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/e5420_6mb/config/libgfxinit_txtmode b/config/coreboot/e5420_6mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..5606a017 --- /dev/null +++ b/config/coreboot/e5420_6mb/config/libgfxinit_txtmode @@ -0,0 +1,617 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="Latitude E5420" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/e5420" +CONFIG_VGA_BIOS_ID="8086,0116" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x5ea000 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_DRAM_RESET_GATE_GPIO=60 +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_BOARD_DELL_LATITUDE_E5420=y +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xfefe0000 +CONFIG_DCACHE_RAM_SIZE=0x20000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe" +CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5420" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_GFX_GMA_PANEL_1_PORT="LVDS" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_6144=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +CONFIG_COREBOOT_ROMSIZE_KB_6144=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=6144 +CONFIG_ROM_SIZE=0x00600000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +# CONFIG_USE_EXP_X86_64_SUPPORT is not set +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_MODEL_206AX=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_USE_NATIVE_RAMINIT=y +CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y +# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set +# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set +# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set +# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set +CONFIG_RAMINIT_ENABLE_ECC=y + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y +# CONFIG_HIDE_MEI_ON_ERROR is not set +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_DELL_MEC5035=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_HAVE_EXP_X86_64_SUPPORT=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x800 +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Ironlake" +CONFIG_GFX_GMA_PCH="Cougar_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/e5420_6mb/target.cfg b/config/coreboot/e5420_6mb/target.cfg new file mode 100644 index 00000000..70be0ab9 --- /dev/null +++ b/config/coreboot/e5420_6mb/target.cfg @@ -0,0 +1,12 @@ +tree="default" +romtype="normal" +arch="x86_64" +payload_grub="n" +payload_grub_withseabios="n" +payload_seabios="y" +payload_memtest="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +grub_scan_disk="ahci" +microcode_required="n" +status="untested" diff --git a/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb b/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb index 5276c108..e57da732 100644 --- a/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set CONFIG_BOARD_DELL_LATITUDE_E5520=y # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e5520_6mb/config/libgfxinit_txtmode b/config/coreboot/e5520_6mb/config/libgfxinit_txtmode index 29148416..b9c2cd0a 100644 --- a/config/coreboot/e5520_6mb/config/libgfxinit_txtmode +++ b/config/coreboot/e5520_6mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set CONFIG_BOARD_DELL_LATITUDE_E5520=y # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e5520_6mb/target.cfg b/config/coreboot/e5520_6mb/target.cfg index 1cf0792e..70be0ab9 100644 --- a/config/coreboot/e5520_6mb/target.cfg +++ b/config/coreboot/e5520_6mb/target.cfg @@ -9,3 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" +status="untested" diff --git a/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb b/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb index a93401db..7f4cdc8b 100644 --- a/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set CONFIG_BOARD_DELL_LATITUDE_E5530=y # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e5530_12mb/config/libgfxinit_txtmode b/config/coreboot/e5530_12mb/config/libgfxinit_txtmode index e42a9972..4e1303a4 100644 --- a/config/coreboot/e5530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e5530_12mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set CONFIG_BOARD_DELL_LATITUDE_E5530=y # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e5530_12mb/target.cfg b/config/coreboot/e5530_12mb/target.cfg index 03fd230b..e2375ad4 100644 --- a/config/coreboot/e5530_12mb/target.cfg +++ b/config/coreboot/e5530_12mb/target.cfg @@ -7,3 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/e6400_4mb/target.cfg b/config/coreboot/e6400_4mb/target.cfg index 3a458ee4..d1ea26ad 100644 --- a/config/coreboot/e6400_4mb/target.cfg +++ b/config/coreboot/e6400_4mb/target.cfg @@ -7,3 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" +status="unstable" # broken s3 diff --git a/config/coreboot/e6400_4mb/warn.txt b/config/coreboot/e6400_4mb/warn.txt new file mode 100644 index 00000000..95b8ebbf --- /dev/null +++ b/config/coreboot/e6400_4mb/warn.txt @@ -0,0 +1 @@ +broken s3 resume/suspend, no battery indicator/status diff --git a/config/coreboot/e6400nvidia_4mb/target.cfg b/config/coreboot/e6400nvidia_4mb/target.cfg index 3a458ee4..d1026eed 100644 --- a/config/coreboot/e6400nvidia_4mb/target.cfg +++ b/config/coreboot/e6400nvidia_4mb/target.cfg @@ -7,3 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" +status="unstable" # s3, nvidia+nouveau diff --git a/config/coreboot/e6400nvidia_4mb/warn.txt b/config/coreboot/e6400nvidia_4mb/warn.txt new file mode 100644 index 00000000..a604fc87 --- /dev/null +++ b/config/coreboot/e6400nvidia_4mb/warn.txt @@ -0,0 +1,2 @@ +broken s3 resume/suspend, no battery indicator/status. +nouveau crashes xorg under linux (can use nomodeset) diff --git a/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb b/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb index d3cc4360..5bdd1843 100644 --- a/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6420_10mb/config/libgfxinit_txtmode b/config/coreboot/e6420_10mb/config/libgfxinit_txtmode index 5766398d..b7aafbaa 100644 --- a/config/coreboot/e6420_10mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6420_10mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6420_10mb/target.cfg b/config/coreboot/e6420_10mb/target.cfg index 1cf0792e..70be0ab9 100644 --- a/config/coreboot/e6420_10mb/target.cfg +++ b/config/coreboot/e6420_10mb/target.cfg @@ -9,3 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" +status="untested" diff --git a/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb b/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb index b7a11ae9..7d1fd1ed 100644 --- a/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6430_12mb/config/libgfxinit_txtmode b/config/coreboot/e6430_12mb/config/libgfxinit_txtmode index 694f1eab..fe8d8105 100644 --- a/config/coreboot/e6430_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6430_12mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6430_12mb/target.cfg b/config/coreboot/e6430_12mb/target.cfg index 03fd230b..e2375ad4 100644 --- a/config/coreboot/e6430_12mb/target.cfg +++ b/config/coreboot/e6430_12mb/target.cfg @@ -7,3 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb b/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb index 28214b76..7b3385ff 100644 --- a/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6520_10mb/config/libgfxinit_txtmode b/config/coreboot/e6520_10mb/config/libgfxinit_txtmode index 31c9df68..c5195de0 100644 --- a/config/coreboot/e6520_10mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6520_10mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6520_10mb/target.cfg b/config/coreboot/e6520_10mb/target.cfg index 1cf0792e..70be0ab9 100644 --- a/config/coreboot/e6520_10mb/target.cfg +++ b/config/coreboot/e6520_10mb/target.cfg @@ -9,3 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" +status="untested" diff --git a/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb b/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb index 6344db92..3824cd7e 100644 --- a/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6530_12mb/config/libgfxinit_txtmode b/config/coreboot/e6530_12mb/config/libgfxinit_txtmode index 59f22da1..7bcc0d08 100644 --- a/config/coreboot/e6530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6530_12mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6530_12mb/target.cfg b/config/coreboot/e6530_12mb/target.cfg index 03fd230b..e2375ad4 100644 --- a/config/coreboot/e6530_12mb/target.cfg +++ b/config/coreboot/e6530_12mb/target.cfg @@ -7,3 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/g43t-am3/target.cfg b/config/coreboot/g43t-am3/target.cfg index 13f2a260..af80482f 100644 --- a/config/coreboot/g43t-am3/target.cfg +++ b/config/coreboot/g43t-am3/target.cfg @@ -3,3 +3,4 @@ xarch="i386-elf" payload_seabios="y" payload_memtest="y" grub_timeout=10 +status="untested" diff --git a/config/coreboot/g43t-am3_16mb/target.cfg b/config/coreboot/g43t-am3_16mb/target.cfg index 13f2a260..af80482f 100644 --- a/config/coreboot/g43t-am3_16mb/target.cfg +++ b/config/coreboot/g43t-am3_16mb/target.cfg @@ -3,3 +3,4 @@ xarch="i386-elf" payload_seabios="y" payload_memtest="y" grub_timeout=10 +status="untested" diff --git a/config/coreboot/ga-g41m-es2l/target.cfg b/config/coreboot/ga-g41m-es2l/target.cfg index ef85da4b..9fc566d8 100644 --- a/config/coreboot/ga-g41m-es2l/target.cfg +++ b/config/coreboot/ga-g41m-es2l/target.cfg @@ -4,3 +4,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ata" grub_timeout=10 +status="untested" diff --git a/config/coreboot/gru_bob/target.cfg b/config/coreboot/gru_bob/target.cfg index a7c36159..3ff37611 100644 --- a/config/coreboot/gru_bob/target.cfg +++ b/config/coreboot/gru_bob/target.cfg @@ -1,3 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" +status="untested" diff --git a/config/coreboot/gru_kevin/target.cfg b/config/coreboot/gru_kevin/target.cfg index a7c36159..3ff37611 100644 --- a/config/coreboot/gru_kevin/target.cfg +++ b/config/coreboot/gru_kevin/target.cfg @@ -1,3 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" +status="untested" diff --git a/config/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch b/config/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch deleted file mode 100644 index 96e4c14d..00000000 --- a/config/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch +++ /dev/null @@ -1,54 +0,0 @@ -From dd58f5e9108bc596c93071705d2b53233d13ade6 Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Sat, 7 May 2022 20:36:10 +0200 -Subject: [PATCH 01/26] commonlib/clamp.h: Add more clamping functions - -Add more clamping functions that work with different types. - -Change-Id: I14cf335d5a54f769f8fd9184450957e876affd6b -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - src/commonlib/include/commonlib/clamp.h | 26 +++++++++++++++++-------- - 1 file changed, 18 insertions(+), 8 deletions(-) - -diff --git a/src/commonlib/include/commonlib/clamp.h b/src/commonlib/include/commonlib/clamp.h -index e01a107ed4..526185195c 100644 ---- a/src/commonlib/include/commonlib/clamp.h -+++ b/src/commonlib/include/commonlib/clamp.h -@@ -8,15 +8,25 @@ - /* - * Clamp a value, so that it is between a lower and an upper bound. - */ --static inline u32 clamp_u32(const u32 min, const u32 val, const u32 max) --{ -- if (val > max) -- return max; -+#define __MAKE_CLAMP_FUNC(type) \ -+ static inline type clamp_##type(const type min, const type val, const type max) \ -+ { \ -+ if (val > max) \ -+ return max; \ -+ if (val < min) \ -+ return min; \ -+ return val; \ -+ } \ - -- if (val < min) -- return min; -+__MAKE_CLAMP_FUNC(s8) /* clamp_s8 */ -+__MAKE_CLAMP_FUNC(u8) /* clamp_u8 */ -+__MAKE_CLAMP_FUNC(s16) /* clamp_s16 */ -+__MAKE_CLAMP_FUNC(u16) /* clamp_u16 */ -+__MAKE_CLAMP_FUNC(s32) /* clamp_s32 */ -+__MAKE_CLAMP_FUNC(u32) /* clamp_u32 */ -+__MAKE_CLAMP_FUNC(s64) /* clamp_s64 */ -+__MAKE_CLAMP_FUNC(u64) /* clamp_u64 */ - -- return val; --} -+#undef __MAKE_CLAMP_FUNC - - #endif /* COMMONLIB_CLAMP_H */ --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0011-haswell-NRI-Initialise-MPLL.patch b/config/coreboot/haswell/patches/0001-haswell-NRI-Initialise-MPLL.patch index 1fec2e38..0de1a4ec 100644 --- a/config/coreboot/haswell/patches/0011-haswell-NRI-Initialise-MPLL.patch +++ b/config/coreboot/haswell/patches/0001-haswell-NRI-Initialise-MPLL.patch @@ -1,7 +1,7 @@ -From 77a89d55ab7a715dc20c34a6edacaaf781b56087 Mon Sep 17 00:00:00 2001 +From cce5392f272b0acc493f47f9b5ca3cf90ce901e8 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> -Date: Sat, 7 May 2022 14:36:10 +0200 -Subject: [PATCH 11/26] haswell NRI: Initialise MPLL +Date: Thu, 11 Apr 2024 17:25:07 +0200 +Subject: [PATCH 01/20] haswell NRI: Initialise MPLL Add code to initialise the MPLL (Memory PLL). The procedure is similar to the one for Sandy/Ivy Bridge, but it is not worth factoring out. @@ -9,20 +9,20 @@ to the one for Sandy/Ivy Bridge, but it is not worth factoring out. Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 2 + + .../intel/haswell/native_raminit/Makefile.mk | 2 + .../intel/haswell/native_raminit/init_mpll.c | 210 ++++++++++++++++++ .../haswell/native_raminit/io_comp_control.c | 22 ++ - .../haswell/native_raminit/raminit_main.c | 1 + + .../haswell/native_raminit/raminit_main.c | 3 +- .../haswell/native_raminit/raminit_native.h | 11 + .../intel/haswell/registers/mchbar.h | 3 + - 6 files changed, 249 insertions(+) + 6 files changed, 250 insertions(+), 1 deletion(-) create mode 100644 src/northbridge/intel/haswell/native_raminit/init_mpll.c create mode 100644 src/northbridge/intel/haswell/native_raminit/io_comp_control.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index ebf7abc6ec..c125d84f0b 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -33,13 +33,13 @@ index ebf7abc6ec..c125d84f0b 100644 romstage-y += spd_bitmunching.c diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c new file mode 100644 -index 0000000000..2faa183724 +index 0000000000..1f3f2c29a9 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + -+#include <commonlib/clamp.h> ++#include <commonlib/bsd/clamp.h> +#include <console/console.h> +#include <delay.h> +#include <device/pci_ops.h> @@ -249,13 +249,13 @@ index 0000000000..2faa183724 +} diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c new file mode 100644 -index 0000000000..7e96c08938 +index 0000000000..d45b608dd3 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + -+#include <commonlib/clamp.h> ++#include <commonlib/bsd/clamp.h> +#include <console/console.h> +#include <northbridge/intel/haswell/haswell.h> +#include <timer.h> @@ -276,13 +276,15 @@ index 0000000000..7e96c08938 + return RAMINIT_STATUS_POLL_TIMEOUT; +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 2d2cfa48bb..09545422c0 100644 +index 19ec5859ac..bf745e943f 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -21,6 +21,7 @@ struct task_entry { +@@ -19,7 +19,8 @@ struct task_entry { + }; static const struct task_entry cold_boot[] = { - { collect_spd_info, true, "PROCSPD", }, +- { collect_spd_info, true, "PROCSPD", }, ++ { collect_spd_info, true, "PROCSPD", }, + { initialise_mpll, true, "INITMPLL", }, }; diff --git a/config/coreboot/haswell/patches/0012-haswell-NRI-Post-process-selected-timings.patch b/config/coreboot/haswell/patches/0002-haswell-NRI-Post-process-selected-timings.patch index e38f8e57..0cc95cdd 100644 --- a/config/coreboot/haswell/patches/0012-haswell-NRI-Post-process-selected-timings.patch +++ b/config/coreboot/haswell/patches/0002-haswell-NRI-Post-process-selected-timings.patch @@ -1,7 +1,7 @@ -From faabed9ca8974b2e7192c55b59a9d28d75e72df6 Mon Sep 17 00:00:00 2001 +From 42b21fdce8c8bade53d9d86515f88b0665a4c1b1 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 16:29:55 +0200 -Subject: [PATCH 12/26] haswell NRI: Post-process selected timings +Subject: [PATCH 02/20] haswell NRI: Post-process selected timings Once the MPLL has been initialised, convert the timings from the SPD to be in DCLKs, which is what the hardware expects. In addition, calculate @@ -10,7 +10,7 @@ the values for tREFI and tXP. Change-Id: Id02caf858f75b9e08016762b3aefda282b274386 Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/lookup_timings.c | 62 +++++++++++ .../haswell/native_raminit/raminit_main.c | 1 + .../haswell/native_raminit/raminit_native.h | 8 ++ @@ -18,10 +18,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> 5 files changed, 172 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/lookup_timings.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index c125d84f0b..2769e0bbb4 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -31,13 +31,13 @@ index c125d84f0b..2769e0bbb4 100644 romstage-y += raminit_main.c diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c new file mode 100644 -index 0000000000..038686c844 +index 0000000000..8b81c7c341 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + -+#include <commonlib/clamp.h> ++#include <commonlib/bsd/clamp.h> +#include <types.h> + +#include "raminit_native.h" @@ -98,10 +98,10 @@ index 0000000000..038686c844 + return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut)); +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 09545422c0..5f2be980d4 100644 +index bf745e943f..2fea658415 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -22,6 +22,7 @@ struct task_entry { +@@ -21,6 +21,7 @@ struct task_entry { static const struct task_entry cold_boot[] = { { collect_spd_info, true, "PROCSPD", }, { initialise_mpll, true, "INITMPLL", }, @@ -137,7 +137,7 @@ index a54581abc7..01e5ed1bd6 100644 + #endif diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c -index dbe02c72d0..becbea0725 100644 +index 2dab8504c4..7d98341a7e 100644 --- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c +++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c @@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl) @@ -221,7 +221,7 @@ index dbe02c72d0..becbea0725 100644 + */ + + /* tCK is special */ -+ printk(BIOS_DEBUG, "Selected tCK : %u ns\n", ctrl->tCK / 256); ++ printk(BIOS_DEBUG, "Selected tCK : %u ps\n", ctrl->tCK * 1000 / 256); + + /* Primary timings */ + printk(BIOS_DEBUG, "Selected tAA : %uT\n", ctrl->tAA); diff --git a/config/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch b/config/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch deleted file mode 100644 index 35d5c89e..00000000 --- a/config/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch +++ /dev/null @@ -1,143 +0,0 @@ -From c07391821c32cafea950574b85468f5b3284b6df Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Fri, 6 May 2022 21:12:14 +0200 -Subject: [PATCH 02/26] nb/intel/haswell: Introduce option to not use MRC.bin - -Introduce the `USE_NATIVE_RAMINIT` Kconfig option, which should allow -booting coreboot on Haswell mainboards without the need of the closed -source MRC.bin. For now, this option does not work at all; the needed -magic will be implemented in subsequent commits. Add a config file to -make sure the newly-introduced option gets build-tested. - -Change-Id: I46c77586f9b5771624082e07c60c205e578edd8e -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - configs/config.asrock_b85m_pro4.native_raminit | 5 +++++ - src/northbridge/intel/haswell/Kconfig | 13 +++++++++++++ - src/northbridge/intel/haswell/Makefile.inc | 7 ++++++- - .../intel/haswell/native_raminit/Makefile.inc | 3 +++ - .../intel/haswell/native_raminit/raminit_native.c | 15 +++++++++++++++ - 5 files changed, 42 insertions(+), 1 deletion(-) - create mode 100644 configs/config.asrock_b85m_pro4.native_raminit - create mode 100644 src/northbridge/intel/haswell/native_raminit/Makefile.inc - create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.c - -diff --git a/configs/config.asrock_b85m_pro4.native_raminit b/configs/config.asrock_b85m_pro4.native_raminit -new file mode 100644 -index 0000000000..2de538926f ---- /dev/null -+++ b/configs/config.asrock_b85m_pro4.native_raminit -@@ -0,0 +1,5 @@ -+# Configuration used to build-test native raminit -+CONFIG_VENDOR_ASROCK=y -+CONFIG_BOARD_ASROCK_B85M_PRO4=y -+CONFIG_USE_NATIVE_RAMINIT=y -+CONFIG_DEBUG_RAM_SETUP=y -diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig -index 50acb09a91..b659bf6d98 100644 ---- a/src/northbridge/intel/haswell/Kconfig -+++ b/src/northbridge/intel/haswell/Kconfig -@@ -9,6 +9,14 @@ config NORTHBRIDGE_INTEL_HASWELL - - if NORTHBRIDGE_INTEL_HASWELL - -+config USE_NATIVE_RAMINIT -+ bool "[NOT WORKING] Use native raminit" -+ default n -+ select HAVE_DEBUG_RAM_SETUP -+ help -+ Select if you want to use coreboot implementation of raminit rather than -+ MRC.bin. Currently incomplete and does not boot. -+ - config HASWELL_VBOOT_IN_BOOTBLOCK - depends on VBOOT - bool "Start verstage in bootblock" -@@ -45,6 +53,7 @@ config DCACHE_RAM_BASE - - config DCACHE_RAM_SIZE - hex -+ default 0x40000 if USE_NATIVE_RAMINIT - default 0x10000 - help - The size of the cache-as-ram region required during bootblock -@@ -53,12 +62,14 @@ config DCACHE_RAM_SIZE - - config DCACHE_RAM_MRC_VAR_SIZE - hex -+ default 0x0 if USE_NATIVE_RAMINIT - default 0x30000 - help - The amount of cache-as-ram region required by the reference code. - - config DCACHE_BSP_STACK_SIZE - hex -+ default 0x20000 if USE_NATIVE_RAMINIT - default 0x2000 - help - The amount of anticipated stack usage in CAR by bootblock and -@@ -66,6 +77,7 @@ config DCACHE_BSP_STACK_SIZE - - config HAVE_MRC - bool "Add a System Agent binary" -+ depends on !USE_NATIVE_RAMINIT - help - Select this option to add a System Agent binary to - the resulting coreboot image. -@@ -82,6 +94,7 @@ config MRC_FILE - - config HASWELL_HIDE_PEG_FROM_MRC - bool "Hide PEG devices from MRC to work around hardcoded MRC behavior" -+ depends on !USE_NATIVE_RAMINIT - default y - help - If set, hides all PEG devices from MRC. This allows the iGPU -diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc -index 2d1532be05..329f1f7ffe 100644 ---- a/src/northbridge/intel/haswell/Makefile.inc -+++ b/src/northbridge/intel/haswell/Makefile.inc -@@ -19,6 +19,11 @@ romstage-y += report_platform.c - - postcar-y += memmap.c - --subdirs-y += haswell_mrc -+ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) -+subdirs-y += native_raminit -+ -+else -+subdirs-y += haswell_mrc -+endif - - endif -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -new file mode 100644 -index 0000000000..8cfb4fb33e ---- /dev/null -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -@@ -0,0 +1,3 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+romstage-y += raminit_native.c -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -new file mode 100644 -index 0000000000..1aafdf8659 ---- /dev/null -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <console/console.h> -+#include <northbridge/intel/haswell/raminit.h> -+ -+void perform_raminit(const int s3resume) -+{ -+ /* -+ * See, this function's name is a lie. There are more things to -+ * do that memory initialisation, but they are relatively easy. -+ */ -+ -+ /** TODO: Implement the required magic **/ -+ die("NATIVE RAMINIT: More Magic (tm) required.\n"); -+} --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0013-haswell-NRI-Configure-initial-MC-settings.patch b/config/coreboot/haswell/patches/0003-haswell-NRI-Configure-initial-MC-settings.patch index b1c33328..f44eb029 100644 --- a/config/coreboot/haswell/patches/0013-haswell-NRI-Configure-initial-MC-settings.patch +++ b/config/coreboot/haswell/patches/0003-haswell-NRI-Configure-initial-MC-settings.patch @@ -1,7 +1,7 @@ -From 1b0b17d85256193de825fa7ff0e04767c818f2fc Mon Sep 17 00:00:00 2001 +From 574f4965976b56f98a825dea71e919fefb2c8547 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 17:22:07 +0200 -Subject: [PATCH 13/26] haswell NRI: Configure initial MC settings +Subject: [PATCH 03/20] haswell NRI: Configure initial MC settings Program initial memory controller settings. Many of these values will be adjusted later during training. @@ -9,7 +9,7 @@ adjusted later during training. Change-Id: If33846b51cb1bab5d0458fe626e13afb1bdc900e Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 2 + + .../intel/haswell/native_raminit/Makefile.mk | 2 + .../haswell/native_raminit/configure_mc.c | 822 ++++++++++++++++++ .../haswell/native_raminit/raminit_main.c | 2 + .../haswell/native_raminit/raminit_native.h | 101 +++ @@ -21,10 +21,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> create mode 100644 src/northbridge/intel/haswell/native_raminit/reg_structs.h create mode 100644 src/northbridge/intel/haswell/native_raminit/timings_refresh.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 2769e0bbb4..fc55277a65 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,8 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -38,14 +38,14 @@ index 2769e0bbb4..fc55277a65 100644 +romstage-y += timings_refresh.c diff --git a/src/northbridge/intel/haswell/native_raminit/configure_mc.c b/src/northbridge/intel/haswell/native_raminit/configure_mc.c new file mode 100644 -index 0000000000..2a667b075b +index 0000000000..88249725a7 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/configure_mc.c @@ -0,0 +1,822 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <assert.h> -+#include <commonlib/clamp.h> ++#include <commonlib/bsd/clamp.h> +#include <console/console.h> +#include <delay.h> +#include <lib.h> @@ -131,22 +131,22 @@ index 0000000000..2a667b075b + +static const uint8_t rxb_trad[2][5][4] = { + { /* Vdd low */ -+ /* 1067 MHz, 1333 MHz, 1600 MHz, 1867 MHz, 2133 MHz, */ ++ /* 1067 MT/s, 1333 MT/s, 1600 MT/s, 1867 MT/s, 2133 MT/s, */ + {4, 3, 3, 2}, {4, 4, 3, 2}, {5, 4, 3, 3}, {5, 4, 4, 3}, {5, 4, 4, 3}, + }, + { /* Vdd hi */ -+ /* 1067 MHz, 1333 MHz, 1600 MHz, 1867 MHz, 2133 MHz, */ ++ /* 1067 MT/s, 1333 MT/s, 1600 MT/s, 1867 MT/s, 2133 MT/s, */ + {4, 3, 3, 2}, {4, 4, 3, 2}, {5, 4, 3, 3}, {5, 4, 4, 3}, {4, 4, 3, 3}, + }, +}; + +static const uint8_t rxb_ultx[2][3][4] = { + { /* Vdd low */ -+ /* 1067 MHz, 1333 MHz, 1600 MHz, */ ++ /* 1067 MT/s, 1333 MT/s, 1600 MT/s, */ + {5, 6, 6, 5}, {5, 6, 6, 5}, {4, 6, 6, 6}, + }, + { /* Vdd hi */ -+ /* 1067 MHz, 1333 MHz, 1600 MHz, */ ++ /* 1067 MT/s, 1333 MT/s, 1600 MT/s, */ + {7, 6, 6, 5}, {7, 6, 6, 5}, {7, 6, 6, 6}, + }, +}; @@ -277,7 +277,7 @@ index 0000000000..2a667b075b + const int16_t coding[] = {0, -125, -62, -31, 250, 125, 62, 31}; + *best_a = 0; + *best_b = 0; -+ int16_t best_err = slope; ++ int16_t best_err = slope; + for (uint8_t b = 0; b < ARRAY_SIZE(coding); b++) { + for (uint8_t a = b; a < ARRAY_SIZE(coding); a++) { + int16_t error = slope - (coding[a] + coding[b]); @@ -865,10 +865,10 @@ index 0000000000..2a667b075b + return RAMINIT_STATUS_SUCCESS; +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 5f2be980d4..3a773cfa19 100644 +index 2fea658415..fcc981ad04 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -23,6 +23,7 @@ static const struct task_entry cold_boot[] = { +@@ -22,6 +22,7 @@ static const struct task_entry cold_boot[] = { { collect_spd_info, true, "PROCSPD", }, { initialise_mpll, true, "INITMPLL", }, { convert_timings, true, "CONVTIM", }, @@ -876,7 +876,7 @@ index 5f2be980d4..3a773cfa19 100644 }; /* Return a generic stepping value to make stepping checks simpler */ -@@ -54,6 +55,7 @@ static void initialize_ctrl(struct sysinfo *ctrl) +@@ -53,6 +54,7 @@ static void initialize_ctrl(struct sysinfo *ctrl) ctrl->cpu = cpu_get_cpuid(); ctrl->stepping = get_stepping(ctrl->cpu); diff --git a/config/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch b/config/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch deleted file mode 100644 index 4e70407c..00000000 --- a/config/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch +++ /dev/null @@ -1,615 +0,0 @@ -From 6ec71c6df97eded010e96c4ea2bd37cc6a13849d Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Fri, 6 May 2022 21:56:48 +0200 -Subject: [PATCH 03/26] haswell/lynxpoint: Add native DMI init - -Implement native DMI init for Haswell and Lynx Point. This is only -needed on non-ULT platforms, and only when MRC.bin is not used. - -TEST=Verify DMI initialises correctly on Asrock B85M Pro4. - -Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - src/northbridge/intel/haswell/Makefile.inc | 1 + - src/northbridge/intel/haswell/early_dmi.c | 96 ++++++++++++ - src/northbridge/intel/haswell/early_pcie.c | 121 ++++++++++++++ - src/northbridge/intel/haswell/haswell.h | 3 + - .../haswell/native_raminit/raminit_native.c | 15 ++ - src/northbridge/intel/haswell/vcu_mailbox.c | 147 ++++++++++++++++++ - src/northbridge/intel/haswell/vcu_mailbox.h | 16 ++ - src/southbridge/intel/lynxpoint/Makefile.inc | 2 + - .../intel/lynxpoint/early_pch_native.c | 52 +++++++ - src/southbridge/intel/lynxpoint/pch.h | 20 ++- - 10 files changed, 472 insertions(+), 1 deletion(-) - create mode 100644 src/northbridge/intel/haswell/early_dmi.c - create mode 100644 src/northbridge/intel/haswell/early_pcie.c - create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.c - create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.h - create mode 100644 src/southbridge/intel/lynxpoint/early_pch_native.c - -diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc -index 329f1f7ffe..df0b097296 100644 ---- a/src/northbridge/intel/haswell/Makefile.inc -+++ b/src/northbridge/intel/haswell/Makefile.inc -@@ -20,6 +20,7 @@ romstage-y += report_platform.c - postcar-y += memmap.c - - ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) -+romstage-y += early_dmi.c early_pcie.c vcu_mailbox.c - subdirs-y += native_raminit - - else -diff --git a/src/northbridge/intel/haswell/early_dmi.c b/src/northbridge/intel/haswell/early_dmi.c -new file mode 100644 -index 0000000000..9941242fd5 ---- /dev/null -+++ b/src/northbridge/intel/haswell/early_dmi.c -@@ -0,0 +1,96 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <console/console.h> -+#include <northbridge/intel/haswell/haswell.h> -+#include <southbridge/intel/lynxpoint/pch.h> -+#include <types.h> -+ -+static void dmi_print_link_status(int loglevel) -+{ -+ const uint16_t dmilsts = dmibar_read16(DMILSTS); -+ printk(loglevel, "DMI: Running at Gen%u x%u\n", dmilsts & 0xf, dmilsts >> 4 & 0x1f); -+} -+ -+#define RETRAIN (1 << 5) -+ -+#define LTRN (1 << 11) -+ -+static void dmi_setup_physical_layer(void) -+{ -+ /* Program DMI AFE settings, which are needed for DMI to work */ -+ peg_dmi_recipe(false, 0); -+ -+ /* Additional DMI programming steps */ -+ dmibar_setbits32(0x258, 1 << 29); -+ dmibar_clrsetbits32(0x208, 0x7ff, 0x6b5); -+ dmibar_clrsetbits32(0x22c, 0xffff, 0x2020); -+ -+ /* Write SA reference code version */ -+ dmibar_write32(0x71c, 0x0000000f); -+ dmibar_write32(0x720, 0x01060200); -+ -+ /* We also have to bring up the PCH side of the DMI link */ -+ pch_dmi_setup_physical_layer(); -+ -+ /* Write-once settings */ -+ dmibar_clrsetbits32(DMILCAP, 0x3f00f, 2 << 0); -+ -+ printk(BIOS_DEBUG, "Retraining DMI at Gen2 speeds...\n"); -+ dmi_print_link_status(BIOS_DEBUG); -+ -+ /* Retrain link */ -+ dmibar_setbits16(DMILCTL, RETRAIN); -+ do {} while (dmibar_read16(DMILSTS) & LTRN); -+ dmi_print_link_status(BIOS_DEBUG); -+ -+ /* Retrain link again for DMI Gen2 speeds */ -+ dmibar_setbits16(DMILCTL, RETRAIN); -+ do {} while (dmibar_read16(DMILSTS) & LTRN); -+ dmi_print_link_status(BIOS_INFO); -+} -+ -+#define VC_ACTIVE (1U << 31) -+ -+#define VCNEGPND (1 << 1) -+ -+#define DMI_VC_CFG(vcid, tcmap) (VC_ACTIVE | ((vcid) << 24) | (tcmap)) -+ -+static void dmi_tc_vc_mapping(void) -+{ -+ printk(BIOS_DEBUG, "Programming SA DMI VC/TC mappings...\n"); -+ -+ if (CONFIG(INTEL_LYNXPOINT_LP)) -+ dmibar_setbits8(0xa78, 1 << 1); -+ -+ /* Each TC is mapped to one and only one VC */ -+ const u32 vc0 = DMI_VC_CFG(0, (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 0)); -+ const u32 vc1 = DMI_VC_CFG(1, (1 << 1)); -+ const u32 vcp = DMI_VC_CFG(2, (1 << 2)); -+ const u32 vcm = DMI_VC_CFG(7, (1 << 7)); -+ dmibar_write32(DMIVC0RCTL, vc0); -+ dmibar_write32(DMIVC1RCTL, vc1); -+ dmibar_write32(DMIVCPRCTL, vcp); -+ dmibar_write32(DMIVCMRCTL, vcm); -+ -+ /* Set Extended VC Count (EVCC) to 1 if VC1 is active */ -+ dmibar_clrsetbits8(DMIPVCCAP1, 7, !!(vc1 & VC_ACTIVE)); -+ -+ /* -+ * We also have to program the PCH side of the DMI link. Since both ends -+ * must use the same Virtual Channel settings, we pass them as arguments. -+ */ -+ pch_dmi_tc_vc_mapping(vc0, vc1, vcp, vcm); -+ -+ printk(BIOS_DEBUG, "Waiting for SA DMI VC negotiation... "); -+ do {} while (dmibar_read16(DMIVC0RSTS) & VCNEGPND); -+ do {} while (dmibar_read16(DMIVC1RSTS) & VCNEGPND); -+ do {} while (dmibar_read16(DMIVCPRSTS) & VCNEGPND); -+ do {} while (dmibar_read16(DMIVCMRSTS) & VCNEGPND); -+ printk(BIOS_DEBUG, "done!\n"); -+} -+ -+void dmi_early_init(void) -+{ -+ dmi_setup_physical_layer(); -+ dmi_tc_vc_mapping(); -+} -diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c -new file mode 100644 -index 0000000000..d3940e3fac ---- /dev/null -+++ b/src/northbridge/intel/haswell/early_pcie.c -@@ -0,0 +1,121 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <console/console.h> -+#include <device/pci_def.h> -+#include <device/pci_mmio_cfg.h> -+#include <device/pci_ops.h> -+#include <northbridge/intel/haswell/haswell.h> -+#include <northbridge/intel/haswell/vcu_mailbox.h> -+#include <types.h> -+ -+#define PEG_DEV(func) PCI_DEV(0, 1, func) -+ -+#define MAX_PEG_FUNC 3 -+ -+static void peg_dmi_unset_and_set_mask_pcicfg( -+ volatile union pci_bank *const bank, -+ const uint32_t offset, -+ const uint32_t unset_mask, -+ const uint32_t set_mask, -+ const uint32_t shift, -+ const bool valid) -+{ -+ if (!valid) -+ return; -+ -+ volatile uint32_t *const addr = &bank->reg32[offset / sizeof(uint32_t)]; -+ clrsetbits32(addr, unset_mask << shift, set_mask << shift); -+} -+ -+static void peg_dmi_unset_and_set_mask_common( -+ const bool is_peg, -+ const uint32_t offset, -+ const uint32_t unset, -+ const uint32_t set, -+ const uint32_t shift, -+ const bool valid) -+{ -+ const uint32_t unset_mask = unset << shift; -+ const uint32_t set_mask = set << shift; -+ if (is_peg) { -+ for (uint8_t i = 0; i < MAX_PEG_FUNC; i++) -+ pci_update_config32(PEG_DEV(i), offset, ~unset_mask, set_mask); -+ } else { -+ dmibar_clrsetbits32(offset, unset_mask, set_mask); -+ } -+} -+ -+static void peg_dmi_unset_and_set_mask_vcu_mmio( -+ const uint32_t addr, -+ const uint32_t unset_mask, -+ const uint32_t set_mask, -+ const uint32_t shift, -+ const bool valid) -+{ -+ if (!valid) -+ return; -+ -+ vcu_update_mmio(addr, ~(unset_mask << shift), set_mask << shift); -+} -+ -+#define BUNDLE_STEP 0x20 -+ -+static void *const dmibar = (void *)(uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE; -+ -+void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev) -+{ -+ const bool always = true; -+ const bool is_dmi = !is_peg; -+ -+ /* Treat DMIBAR and PEG devices the same way */ -+ volatile union pci_bank *const bank = is_peg ? pci_map_bus(dev) : dmibar; -+ -+ const size_t bundles = (is_peg ? 8 : 2) * BUNDLE_STEP; -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) { -+ /* These are actually per-lane */ -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa00 + i, 0x1f, 0x0c, 0, always); -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa10 + i, 0x1f, 0x0c, 0, always); -+ } -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x02, 0, is_peg); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x03, 5, is_peg); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x3f, 0x09, 5, always); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x0f, 0x05, 21, is_peg); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x08, 6, is_peg); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x00, 10, always); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x07, 0x00, 18, always); -+ -+ peg_dmi_unset_and_set_mask_vcu_mmio(0x0c008001, 0x1f, 0x03, 25, is_peg); -+ peg_dmi_unset_and_set_mask_vcu_mmio(0x0c0c8001, 0x3f, 0x00, 23, is_dmi); -+ -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0xc28, 0x1f, 0x13, 18, always); -+ -+ peg_dmi_unset_and_set_mask_common(is_peg, 0xc38, 0x01, 0x00, 6, always); -+ peg_dmi_unset_and_set_mask_common(is_peg, 0x260, 0x03, 0x02, 0, always); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x900 + i, 0x03, 0x00, 26, always); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x03, 0x03, 10, always); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x1f, 0x07, 25, is_peg); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x91c + i, 0x07, 0x05, 27, is_peg); -+} -diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h -index 1b29f6baf0..30b4abd0a7 100644 ---- a/src/northbridge/intel/haswell/haswell.h -+++ b/src/northbridge/intel/haswell/haswell.h -@@ -34,6 +34,9 @@ void haswell_early_initialization(void); - void haswell_late_initialization(void); - void haswell_unhide_peg(void); - -+void dmi_early_init(void); -+void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev); -+ - void report_platform_info(void); - - struct acpi_rsdp; -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index 1aafdf8659..0938e026e3 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -1,7 +1,19 @@ - /* SPDX-License-Identifier: GPL-2.0-or-later */ - - #include <console/console.h> -+#include <northbridge/intel/haswell/haswell.h> - #include <northbridge/intel/haswell/raminit.h> -+#include <types.h> -+ -+static bool early_init_native(int s3resume) -+{ -+ printk(BIOS_DEBUG, "Starting native platform initialisation\n"); -+ -+ if (!CONFIG(INTEL_LYNXPOINT_LP)) -+ dmi_early_init(); -+ -+ return false; -+} - - void perform_raminit(const int s3resume) - { -@@ -9,6 +21,9 @@ void perform_raminit(const int s3resume) - * See, this function's name is a lie. There are more things to - * do that memory initialisation, but they are relatively easy. - */ -+ const bool cpu_replaced = early_init_native(s3resume); -+ -+ (void)cpu_replaced; - - /** TODO: Implement the required magic **/ - die("NATIVE RAMINIT: More Magic (tm) required.\n"); -diff --git a/src/northbridge/intel/haswell/vcu_mailbox.c b/src/northbridge/intel/haswell/vcu_mailbox.c -new file mode 100644 -index 0000000000..aead144023 ---- /dev/null -+++ b/src/northbridge/intel/haswell/vcu_mailbox.c -@@ -0,0 +1,147 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <assert.h> -+#include <console/console.h> -+#include <delay.h> -+#include <northbridge/intel/haswell/haswell.h> -+#include <northbridge/intel/haswell/vcu_mailbox.h> -+#include <stdint.h> -+ -+/* -+ * This is a library for the VCU (Validation Control Unit) mailbox. This -+ * mailbox is primarily used to adjust some magic PCIe tuning parameters. -+ * -+ * There are two revisions of the VCU mailbox. Rev1 is specific to Haswell -+ * stepping A0, and all other steppings use Rev2. Haswell stepping A0 CPUs -+ * are early Engineering Samples with undocumented errata, and most likely -+ * need special microcode updates to boot. Thus, the code does not support -+ * VCU mailbox Rev1, because no one should need it anymore. -+ */ -+ -+#define VCU_MAILBOX_INTERFACE 0x6c00 -+#define VCU_MAILBOX_DATA 0x6c04 -+ -+#define VCU_RUN_BUSY (1 << 31) -+ -+enum vcu_opcode { -+ VCU_OPCODE_READ_VCU_API_VER_ID = 0x01, -+ VCU_OPCODE_OPEN_SEQ = 0x02, -+ VCU_OPCODE_CLOSE_SEQ = 0x03, -+ VCU_OPCODE_READ_DATA = 0x07, -+ VCU_OPCODE_WRITE_DATA = 0x08, -+ VCU_OPCODE_READ_CSR = 0x13, -+ VCU_OPCODE_WRITE_CSR = 0x14, -+ VCU_OPCODE_READ_MMIO = 0x15, -+ VCU_OPCODE_WRITE_MMIO = 0x16, -+}; -+ -+enum vcu_sequence { -+ SEQ_ID_READ_CSR = 0x1, -+ SEQ_ID_WRITE_CSR = 0x2, -+ SEQ_ID_READ_MMIO = 0x3, -+ SEQ_ID_WRITE_MMIO = 0x4, -+}; -+ -+#define VCU_RESPONSE_MASK 0xffff -+#define VCU_RESPONSE_SUCCESS 0x40 -+#define VCU_RESPONSE_BUSY 0x80 -+#define VCU_RESPONSE_THREAD_UNAVAILABLE 0x82 -+#define VCU_RESPONSE_ILLEGAL 0x90 -+ -+/* FIXME: Use timer API */ -+static void send_vcu_command(const enum vcu_opcode opcode, const uint32_t data) -+{ -+ for (unsigned int i = 0; i < 10; i++) { -+ mchbar_write32(VCU_MAILBOX_DATA, data); -+ mchbar_write32(VCU_MAILBOX_INTERFACE, opcode | VCU_RUN_BUSY); -+ uint32_t vcu_interface; -+ for (unsigned int j = 0; j < 100; j++) { -+ vcu_interface = mchbar_read32(VCU_MAILBOX_INTERFACE); -+ if (!(vcu_interface & VCU_RUN_BUSY)) -+ break; -+ -+ udelay(10); -+ } -+ if (vcu_interface & VCU_RUN_BUSY) -+ continue; -+ -+ if ((vcu_interface & VCU_RESPONSE_MASK) == VCU_RESPONSE_SUCCESS) -+ return; -+ } -+ printk(BIOS_ERR, "VCU: Failed to send command\n"); -+} -+ -+static enum vcu_opcode get_register_opcode(enum vcu_sequence seq) -+{ -+ switch (seq) { -+ case SEQ_ID_READ_CSR: -+ return VCU_OPCODE_READ_CSR; -+ case SEQ_ID_WRITE_CSR: -+ return VCU_OPCODE_WRITE_CSR; -+ case SEQ_ID_READ_MMIO: -+ return VCU_OPCODE_READ_MMIO; -+ case SEQ_ID_WRITE_MMIO: -+ return VCU_OPCODE_WRITE_MMIO; -+ default: -+ return dead_code_t(enum vcu_opcode); -+ } -+} -+ -+static enum vcu_opcode get_data_opcode(enum vcu_sequence seq) -+{ -+ switch (seq) { -+ case SEQ_ID_READ_CSR: -+ case SEQ_ID_READ_MMIO: -+ return VCU_OPCODE_READ_DATA; -+ case SEQ_ID_WRITE_CSR: -+ case SEQ_ID_WRITE_MMIO: -+ return VCU_OPCODE_WRITE_DATA; -+ default: -+ return dead_code_t(enum vcu_opcode); -+ } -+} -+ -+static uint32_t send_vcu_sequence(uint32_t addr, enum vcu_sequence seq, uint32_t wr_data) -+{ -+ send_vcu_command(VCU_OPCODE_OPEN_SEQ, seq); -+ -+ send_vcu_command(get_register_opcode(seq), addr); -+ -+ send_vcu_command(get_data_opcode(seq), wr_data); -+ -+ const uint32_t rd_data = mchbar_read32(VCU_MAILBOX_DATA); -+ -+ send_vcu_command(VCU_OPCODE_CLOSE_SEQ, seq); -+ -+ return rd_data; -+} -+ -+uint32_t vcu_read_csr(uint32_t addr) -+{ -+ return send_vcu_sequence(addr, SEQ_ID_READ_CSR, 0); -+} -+ -+void vcu_write_csr(uint32_t addr, uint32_t data) -+{ -+ send_vcu_sequence(addr, SEQ_ID_WRITE_CSR, data); -+} -+ -+void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue) -+{ -+ vcu_write_csr(addr, (vcu_read_csr(addr) & andvalue) | orvalue); -+} -+ -+uint32_t vcu_read_mmio(uint32_t addr) -+{ -+ return send_vcu_sequence(addr, SEQ_ID_READ_MMIO, 0); -+} -+ -+void vcu_write_mmio(uint32_t addr, uint32_t data) -+{ -+ send_vcu_sequence(addr, SEQ_ID_WRITE_MMIO, data); -+} -+ -+void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue) -+{ -+ vcu_write_mmio(addr, (vcu_read_mmio(addr) & andvalue) | orvalue); -+} -diff --git a/src/northbridge/intel/haswell/vcu_mailbox.h b/src/northbridge/intel/haswell/vcu_mailbox.h -new file mode 100644 -index 0000000000..ba0a62e486 ---- /dev/null -+++ b/src/northbridge/intel/haswell/vcu_mailbox.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#ifndef HASWELL_VCU_MAILBOX_H -+#define HASWELL_VCU_MAILBOX_H -+ -+#include <stdint.h> -+ -+uint32_t vcu_read_csr(uint32_t addr); -+void vcu_write_csr(uint32_t addr, uint32_t data); -+void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue); -+ -+uint32_t vcu_read_mmio(uint32_t addr); -+void vcu_write_mmio(uint32_t addr, uint32_t data); -+void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue); -+ -+#endif /* HASWELL_VCU_MAILBOX_H */ -diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc -index 02022d348d..b8503ac8bc 100644 ---- a/src/southbridge/intel/lynxpoint/Makefile.inc -+++ b/src/southbridge/intel/lynxpoint/Makefile.inc -@@ -37,6 +37,8 @@ bootblock-y += early_pch.c - romstage-y += early_usb.c early_me.c me_status.c early_pch.c - romstage-y += pmutil.c - -+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c -+ - ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) - romstage-y += lp_gpio.c - ramstage-y += lp_gpio.c -diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c -new file mode 100644 -index 0000000000..c28ddfcf5d ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c -@@ -0,0 +1,52 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <console/console.h> -+#include <device/pci_ops.h> -+#include <southbridge/intel/lynxpoint/pch.h> -+#include <types.h> -+ -+void pch_dmi_setup_physical_layer(void) -+{ -+ /* FIXME: We need to make sure the SA supports Gen2 as well */ -+ if ((RCBA32(0x21a4) & 0x0f) == 0x02) { -+ /* Set Gen 2 Common Clock N_FTS */ -+ RCBA32_AND_OR(0x2340, ~0x00ff0000, 0x3a << 16); -+ -+ /* Set Target Link Speed to DMI Gen2 */ -+ RCBA8_AND_OR(DLCTL2, ~0x07, 0x02); -+ } -+} -+ -+#define VC_ACTIVE (1U << 31) -+ -+#define VCNEGPND (1 << 1) -+ -+void pch_dmi_tc_vc_mapping(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm) -+{ -+ printk(BIOS_DEBUG, "Programming PCH DMI VC/TC mappings...\n"); -+ -+ RCBA32_AND_OR(CIR0050, ~(0xf << 20), 2 << 20); -+ if (vcp & VC_ACTIVE) -+ RCBA32_OR(CIR0050, 1 << 19 | 1 << 17); -+ -+ RCBA32(CIR0050); /* Posted Write */ -+ -+ /* Use the same virtual channel mapping on both ends of the DMI link */ -+ RCBA32(V0CTL) = vc0; -+ RCBA32(V1CTL) = vc1; -+ RCBA32(V1CTL); /* Posted Write */ -+ RCBA32(VPCTL) = vcp; -+ RCBA32(VPCTL); /* Posted Write */ -+ RCBA32(VMCTL) = vcm; -+ -+ /* Lock the registers */ -+ RCBA32_OR(CIR0050, 1U << 31); -+ RCBA32(CIR0050); /* Posted Write */ -+ -+ printk(BIOS_DEBUG, "Waiting for PCH DMI VC negotiation... "); -+ do {} while (RCBA16(V0STS) & VCNEGPND); -+ do {} while (RCBA16(V1STS) & VCNEGPND); -+ do {} while (RCBA16(VPSTS) & VCNEGPND); -+ do {} while (RCBA16(VMSTS) & VCNEGPND); -+ printk(BIOS_DEBUG, "done!\n"); -+} -diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h -index 7d9fc6d6af..b5e0c2a830 100644 ---- a/src/southbridge/intel/lynxpoint/pch.h -+++ b/src/southbridge/intel/lynxpoint/pch.h -@@ -113,6 +113,9 @@ enum pch_platform_type { - PCH_TYPE_ULT = 5, - }; - -+void pch_dmi_setup_physical_layer(void); -+void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); -+ - void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); - void usb_ehci_disable(pci_devfn_t dev); - void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); -@@ -406,9 +409,10 @@ void mainboard_config_rcba(void); - - /* Southbridge IO BARs */ - -+#define PMBASE 0x40 - #define GPIOBASE 0x48 - --#define PMBASE 0x40 -+#define CIR0050 0x0050 /* 32bit */ - - #define RPC 0x0400 /* 32bit */ - #define RPFN 0x0404 /* 32bit */ -@@ -431,6 +435,20 @@ void mainboard_config_rcba(void); - #define IOTR2 0x1e90 /* 64bit */ - #define IOTR3 0x1e98 /* 64bit */ - -+#define V0CTL 0x2014 /* 32bit */ -+#define V0STS 0x201a /* 16bit */ -+ -+#define V1CTL 0x2020 /* 32bit */ -+#define V1STS 0x2026 /* 16bit */ -+ -+#define VPCTL 0x2030 /* 32bit */ -+#define VPSTS 0x2038 /* 16bit */ -+ -+#define VMCTL 0x2040 /* 32bit */ -+#define VMSTS 0x2048 /* 16bit */ -+ -+#define DLCTL2 0x21b0 -+ - #define TCTL 0x3000 /* 8bit */ - - #define NOINT 0 --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0014-haswell-NRI-Add-timings-refresh-programming.patch b/config/coreboot/haswell/patches/0004-haswell-NRI-Add-timings-refresh-programming.patch index 1b88f350..74c21227 100644 --- a/config/coreboot/haswell/patches/0014-haswell-NRI-Add-timings-refresh-programming.patch +++ b/config/coreboot/haswell/patches/0004-haswell-NRI-Add-timings-refresh-programming.patch @@ -1,7 +1,7 @@ -From b64d728bfe7c8ee44af252338257e95d87864659 Mon Sep 17 00:00:00 2001 +From d94843c7c0e25cb6da4040b845556034fdb0e2c3 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 20:59:58 +0200 -Subject: [PATCH 14/26] haswell NRI: Add timings/refresh programming +Subject: [PATCH 04/20] haswell NRI: Add timings/refresh programming Program the registers with timing and refresh parameters. @@ -16,7 +16,7 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> 5 files changed, 452 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c -index 038686c844..afe2c615d2 100644 +index 8b81c7c341..b8d6c1ef40 100644 --- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c +++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c @@ -60,3 +60,105 @@ uint32_t get_tXP(const uint32_t mem_clock_mhz) @@ -262,14 +262,14 @@ index d11cda4b3d..70487e1640 100644 struct __packed { uint32_t enable_cmd_limit : 1; // Bits 0:0 diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c -index a9d960f31b..20a05b359b 100644 +index a9d960f31b..54fee0121d 100644 --- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c +++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c @@ -1,13 +1,242 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <assert.h> -+#include <commonlib/clamp.h> ++#include <commonlib/bsd/clamp.h> +#include <console/console.h> +#include <delay.h> +#include <device/pci_ops.h> @@ -458,7 +458,7 @@ index a9d960f31b..20a05b359b 100644 { - /** TODO: Stub **/ + if (ctrl->lpddr) -+ die("%s: Missing support for LPDDR\n"); ++ die("%s: Missing support for LPDDR\n", __func__); + + const uint8_t odt_stretch = get_odt_stretch(ctrl); + const union tc_bank_reg tc_bank = make_tc_bank(ctrl); diff --git a/config/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch b/config/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch deleted file mode 100644 index 28dbc02a..00000000 --- a/config/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch +++ /dev/null @@ -1,148 +0,0 @@ -From 98142e01fc8ebb3b762974e9e4de75e7f5c073b4 Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Fri, 6 May 2022 22:18:21 +0200 -Subject: [PATCH 04/26] haswell/lynxpoint: Add native early ME init - -Implement native early ME init for Lynx Point. This is only needed when -MRC.bin is not used. - -Change-Id: If416e2078f139f26b4742c564b70e018725bf003 -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - .../haswell/native_raminit/raminit_native.c | 17 ++++++++++- - src/southbridge/intel/lynxpoint/early_me.c | 30 ++++++++++++++++++- - src/southbridge/intel/lynxpoint/me.h | 7 +++-- - 3 files changed, 50 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index 0938e026e3..6a002548c1 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -1,18 +1,24 @@ - /* SPDX-License-Identifier: GPL-2.0-or-later */ - - #include <console/console.h> -+#include <delay.h> - #include <northbridge/intel/haswell/haswell.h> - #include <northbridge/intel/haswell/raminit.h> -+#include <southbridge/intel/lynxpoint/me.h> - #include <types.h> - - static bool early_init_native(int s3resume) - { - printk(BIOS_DEBUG, "Starting native platform initialisation\n"); - -+ intel_early_me_init(); -+ /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ -+ const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); -+ - if (!CONFIG(INTEL_LYNXPOINT_LP)) - dmi_early_init(); - -- return false; -+ return cpu_replaced; - } - - void perform_raminit(const int s3resume) -@@ -25,6 +31,15 @@ void perform_raminit(const int s3resume) - - (void)cpu_replaced; - -+ /** TODO: Move after raminit */ -+ if (intel_early_me_uma_size() > 0) { -+ /** TODO: Update status once raminit is implemented **/ -+ uint8_t me_status = ME_INIT_STATUS_ERROR; -+ intel_early_me_init_done(me_status); -+ } -+ -+ intel_early_me_status(); -+ - /** TODO: Implement the required magic **/ - die("NATIVE RAMINIT: More Magic (tm) required.\n"); - } -diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c -index 947c570e16..07013c5539 100644 ---- a/src/southbridge/intel/lynxpoint/early_me.c -+++ b/src/southbridge/intel/lynxpoint/early_me.c -@@ -1,11 +1,12 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ - - #include <arch/io.h> -+#include <cf9_reset.h> - #include <device/pci_ops.h> - #include <console/console.h> - #include <delay.h> - #include <halt.h> -- -+#include <timer.h> - #include "me.h" - #include "pch.h" - -@@ -60,6 +61,33 @@ int intel_early_me_init(void) - return 0; - } - -+bool intel_early_me_cpu_replacement_check(void) -+{ -+ printk(BIOS_DEBUG, "ME: Checking whether CPU was replaced... "); -+ -+ struct stopwatch timer; -+ stopwatch_init_msecs_expire(&timer, 50); -+ -+ union me_hfs2 hfs2; -+ do { -+ hfs2.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2); -+ if (stopwatch_expired(&timer)) { -+ /* Assume CPU was replaced just in case */ -+ printk(BIOS_DEBUG, "timed out, assuming CPU was replaced\n"); -+ return true; -+ } -+ udelay(ME_DELAY); -+ } while (!hfs2.cpu_replaced_valid); -+ -+ if (hfs2.warm_reset_request) { -+ printk(BIOS_DEBUG, "warm reset needed for dynamic fusing\n"); -+ system_reset(); -+ } -+ -+ printk(BIOS_DEBUG, "%sreplaced\n", hfs2.cpu_replaced_sts ? "" : "not "); -+ return hfs2.cpu_replaced_sts; -+} -+ - int intel_early_me_uma_size(void) - { - union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) }; -diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h -index fe8b0260c4..6990322651 100644 ---- a/src/southbridge/intel/lynxpoint/me.h -+++ b/src/southbridge/intel/lynxpoint/me.h -@@ -177,14 +177,16 @@ union me_did { - union me_hfs2 { - struct __packed { - u32 bist_in_progress: 1; -- u32 reserved1: 2; -+ u32 icc_prog_sts: 2; - u32 invoke_mebx: 1; - u32 cpu_replaced_sts: 1; - u32 mbp_rdy: 1; - u32 mfs_failure: 1; - u32 warm_reset_request: 1; - u32 cpu_replaced_valid: 1; -- u32 reserved2: 4; -+ u32 reserved: 2; -+ u32 fw_upd_ipu: 1; -+ u32 reserved2: 1; - u32 mbp_cleared: 1; - u32 reserved3: 2; - u32 current_state: 8; -@@ -338,6 +340,7 @@ void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2); - - void intel_early_me_status(void); - int intel_early_me_init(void); -+bool intel_early_me_cpu_replacement_check(void); - int intel_early_me_uma_size(void); - int intel_early_me_init_done(u8 status); - --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0015-haswell-NRI-Program-memory-map.patch b/config/coreboot/haswell/patches/0005-haswell-NRI-Program-memory-map.patch index ad8527b2..e095417c 100644 --- a/config/coreboot/haswell/patches/0015-haswell-NRI-Program-memory-map.patch +++ b/config/coreboot/haswell/patches/0005-haswell-NRI-Program-memory-map.patch @@ -1,7 +1,7 @@ -From 89ff35083af68d1b24c1633886202ecc153af67d Mon Sep 17 00:00:00 2001 +From b872fb9fc10d1789989072b8533b797152e6cb54 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 21:24:50 +0200 -Subject: [PATCH 15/26] haswell NRI: Program memory map +Subject: [PATCH 05/20] haswell NRI: Program memory map This is very similar to Sandy/Ivy Bridge, except that there's several registers to program in GDXCBAR. One of these GDXCBAR registers has a @@ -12,7 +12,7 @@ bit was the only reason why native raminit did not work. Change-Id: I3af73a018a7ba948701a542e661e7fefd57591fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../intel/haswell/native_raminit/memory_map.c | 183 ++++++++++++++++++ .../haswell/native_raminit/raminit_main.c | 1 + .../haswell/native_raminit/raminit_native.h | 1 + @@ -20,10 +20,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> 5 files changed, 188 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/memory_map.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index fc55277a65..37d527e972 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -4,6 +4,7 @@ romstage-y += configure_mc.c romstage-y += lookup_timings.c romstage-y += init_mpll.c @@ -222,10 +222,10 @@ index 0000000000..e3aded2b37 + return 0; +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 3a773cfa19..136a8ba989 100644 +index fcc981ad04..559dfc3a4e 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -24,6 +24,7 @@ static const struct task_entry cold_boot[] = { +@@ -23,6 +23,7 @@ static const struct task_entry cold_boot[] = { { initialise_mpll, true, "INITMPLL", }, { convert_timings, true, "CONVTIM", }, { configure_mc, true, "CONFMC", }, diff --git a/config/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch b/config/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch deleted file mode 100644 index d9c2570b..00000000 --- a/config/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch +++ /dev/null @@ -1,783 +0,0 @@ -From 9bfb8614dbf1d9800ef8251cb3d839bcdbe5577f Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Fri, 6 May 2022 23:17:39 +0200 -Subject: [PATCH 05/26] sb/intel/lynxpoint: Add native USB init - -Implement native USB initialisation for Lynx Point. This is only needed -when MRC.bin is not used. - -TO DO: Figure out how to deal with the FIXME's and TODO's lying around. - -Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373 -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - .../haswell/native_raminit/raminit_native.c | 3 + - src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- - src/southbridge/intel/lynxpoint/early_usb.c | 11 - - .../intel/lynxpoint/early_usb_native.c | 584 ++++++++++++++++++ - src/southbridge/intel/lynxpoint/pch.h | 49 ++ - 5 files changed, 637 insertions(+), 12 deletions(-) - create mode 100644 src/southbridge/intel/lynxpoint/early_usb_native.c - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index 6a002548c1..ef61d4ee09 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -5,6 +5,7 @@ - #include <northbridge/intel/haswell/haswell.h> - #include <northbridge/intel/haswell/raminit.h> - #include <southbridge/intel/lynxpoint/me.h> -+#include <southbridge/intel/lynxpoint/pch.h> - #include <types.h> - - static bool early_init_native(int s3resume) -@@ -15,6 +16,8 @@ static bool early_init_native(int s3resume) - /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ - const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); - -+ early_usb_init(); -+ - if (!CONFIG(INTEL_LYNXPOINT_LP)) - dmi_early_init(); - -diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc -index b8503ac8bc..0e1f2fe4eb 100644 ---- a/src/southbridge/intel/lynxpoint/Makefile.inc -+++ b/src/southbridge/intel/lynxpoint/Makefile.inc -@@ -37,7 +37,7 @@ bootblock-y += early_pch.c - romstage-y += early_usb.c early_me.c me_status.c early_pch.c - romstage-y += pmutil.c - --romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c -+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c - - ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) - romstage-y += lp_gpio.c -diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c -index a753681ce0..52e8ac17f8 100644 ---- a/src/southbridge/intel/lynxpoint/early_usb.c -+++ b/src/southbridge/intel/lynxpoint/early_usb.c -@@ -4,17 +4,6 @@ - #include <device/pci_def.h> - #include "pch.h" - --/* HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index -- * selects 0:1d.0 (PCH_EHCI1) for usbdebug use. -- */ --#if CONFIG_USBDEBUG_HCD_INDEX != 2 --#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR --#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400) --#else --#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR --#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400) --#endif -- - /* - * Setup USB controller MMIO BAR to prevent the - * reference code from resetting the controller. -diff --git a/src/southbridge/intel/lynxpoint/early_usb_native.c b/src/southbridge/intel/lynxpoint/early_usb_native.c -new file mode 100644 -index 0000000000..cb6f6ee8e6 ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/early_usb_native.c -@@ -0,0 +1,584 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <console/console.h> -+#include <delay.h> -+#include <device/mmio.h> -+#include <device/pci_def.h> -+#include <device/pci_ops.h> -+#include <northbridge/intel/haswell/haswell.h> -+#include <northbridge/intel/haswell/raminit.h> -+#include <southbridge/intel/lynxpoint/iobp.h> -+#include <southbridge/intel/lynxpoint/pch.h> -+#include <timer.h> -+#include <types.h> -+ -+static unsigned int is_usbr_enabled(void) -+{ -+ return !!(pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) & BIT(5)); -+} -+ -+static char *const xhci_bar = (char *)PCH_XHCI_TEMP_BAR0; -+ -+static void ehci_hcs_init(const pci_devfn_t dev, const uintptr_t ehci_bar) -+{ -+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, ehci_bar); -+ -+ /** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/ -+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); -+ -+ char *const mem_bar = (char *)ehci_bar; -+ -+ /** -+ * Shared EHCI/XHCI ports w/a. -+ * This step is required when some of the ports are routed to EHCI -+ * and other ports are routed XHCI at the same time. -+ * -+ * FIXME: Under which conditions should this be done? -+ */ -+ pci_and_config16(dev, 0x78, ~0x03); -+ -+ /* Skip reset if usbdebug is enabled */ -+ if (!CONFIG(USBDEBUG_IN_PRE_RAM)) -+ setbits32(mem_bar + EHCI_USB_CMD, EHCI_USB_CMD_HCRESET); -+ -+ /* 2: Configure number of controllers and ports */ -+ pci_or_config16(dev, EHCI_ACCESS_CNTL, ACCESS_CNTL_ENABLE); -+ clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf << 12, 0); -+ clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf << 0, 2 + is_usbr_enabled()); -+ pci_and_config16(dev, EHCI_ACCESS_CNTL, ~ACCESS_CNTL_ENABLE); -+ -+ pci_or_config16(dev, 0x78, BIT(2)); -+ pci_or_config16(dev, 0x7c, BIT(14) | BIT(7)); -+ pci_update_config32(dev, 0x8c, ~(0xf << 8), (4 << 8)); -+ pci_update_config32(dev, 0x8c, ~BIT(26), BIT(17)); -+} -+ -+static inline unsigned int physical_port_count(void) -+{ -+ return MAX_USB2_PORTS; -+} -+ -+static unsigned int hs_port_count(void) -+{ -+ /** TODO: Apparently, WPT-LP has 10 USB2 ports **/ -+ if (CONFIG(INTEL_LYNXPOINT_LP)) -+ return 8; -+ -+ switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 1) & 3) { -+ case 3: -+ return 8; -+ case 2: -+ return 10; -+ case 1: -+ return 12; -+ case 0: -+ default: -+ return 14; -+ } -+} -+ -+static unsigned int ss_port_count(void) -+{ -+ if (CONFIG(INTEL_LYNXPOINT_LP)) -+ return 4; -+ -+ switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 3) & 3) { -+ case 3: -+ return 0; -+ case 2: -+ return 2; -+ case 1: -+ return 4; -+ case 0: -+ default: -+ return 6; -+ } -+} -+ -+static void common_ehci_hcs_init(void) -+{ -+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP); -+ -+ ehci_hcs_init(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0); -+ if (!is_lp) -+ ehci_hcs_init(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0); -+ -+ pch_iobp_update(0xe5007f04, 0, 0x00004481); -+ -+ for (unsigned int port = 0; port < physical_port_count(); port++) -+ pch_iobp_update(0xe500400f + port * 0x100, ~(1 << 0), 0 << 0); -+ -+ pch_iobp_update(0xe5007f14, ~(3 << 19), (3 << 19)); -+ -+ if (is_lp) -+ pch_iobp_update(0xe5007f02, ~(3 << 22), (0 << 22)); -+} -+ -+static void xhci_open_memory_space(void) -+{ -+ /** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/ -+ pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, (uintptr_t)xhci_bar); -+ pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); -+} -+ -+static void xhci_close_memory_space(void) -+{ -+ pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); -+ pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, 0); -+} -+ -+static void common_xhci_hc_init(void) -+{ -+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP); -+ -+ if (!is_lp) { -+ const unsigned int max_ports = 15 + ss_port_count(); -+ clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_1, 0xf << 28, max_ports << 28); -+ } -+ -+ clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_3, 0xffff << 16 | 0xff, 0x200 << 16 | 0x0a); -+ clrsetbits32(xhci_bar + XHCI_HCC_PARAMS, BIT(5), BIT(10) | BIT(9)); -+ -+ if (!is_lp) -+ clrsetbits32(xhci_bar + 0x8008, BIT(19), 0); -+ -+ if (is_lp) -+ clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16)); -+ else -+ clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16) | BIT(20)); -+ -+ clrsetbits32(xhci_bar + 0x8060, 0, BIT(25) | BIT(18)); -+ clrsetbits32(xhci_bar + 0x8090, 0, BIT(14) | BIT(8)); -+ clrsetbits32(xhci_bar + 0x8094, 0, BIT(23) | BIT(21) | BIT(14)); -+ clrsetbits32(xhci_bar + 0x80e0, BIT(16), BIT(6)); -+ clrsetbits32(xhci_bar + 0x80ec, (7 << 12) | (7 << 9), (0 << 12) | (6 << 9)); -+ clrsetbits32(xhci_bar + 0x80f0, BIT(20), 0); -+ -+ if (is_lp) -+ clrsetbits32(xhci_bar + 0x80fc, 0, BIT(25)); -+ -+ if (is_lp) -+ clrsetbits32(xhci_bar + 0x8110, BIT(8) | BIT(2), BIT(20) | BIT(11)); -+ else -+ clrsetbits32(xhci_bar + 0x8110, BIT(2), BIT(20) | BIT(11)); -+ -+ if (is_lp) -+ write32(xhci_bar + 0x8140, 0xff00f03c); -+ else -+ write32(xhci_bar + 0x8140, 0xff03c132); -+ -+ if (is_lp) -+ clrsetbits32(xhci_bar + 0x8154, BIT(21), BIT(13)); -+ else -+ clrsetbits32(xhci_bar + 0x8154, BIT(21) | BIT(13), 0); -+ -+ clrsetbits32(xhci_bar + 0x8154, BIT(3), 0); -+ -+ if (is_lp) { -+ clrsetbits32(xhci_bar + 0x8164, 0, BIT(1) | BIT(0)); -+ write32(xhci_bar + 0x8174, 0x01400c0a); -+ write32(xhci_bar + 0x817c, 0x033200a3); -+ write32(xhci_bar + 0x8180, 0x00cb0028); -+ write32(xhci_bar + 0x8184, 0x0064001e); -+ } -+ -+ /* -+ * Note: Register at offset 0x44 is 32-bit, but bit 31 is write-once. -+ * We use these weird partial accesses here to avoid locking bit 31. -+ */ -+ pci_or_config16(PCH_XHCI_DEV, 0x44, BIT(15) | BIT(14) | BIT(10) | BIT(0)); -+ pci_or_config8(PCH_XHCI_DEV, 0x44 + 2, 0x0f); -+ -+ /* LPT-LP >= B0 */ -+ if (is_lp) -+ clrsetbits32(xhci_bar + 0x8188, 0, BIT(26) | BIT(24)); -+ -+ /* LPT-H >= C0 */ -+ if (!is_lp) -+ clrsetbits32(xhci_bar + 0x8188, 0, BIT(24)); -+} -+ -+static inline bool is_mem_sr(void) -+{ -+ return pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2) & GEN_PMCON_2_MEM_SR; -+} -+ -+static bool should_restore_xhci_smart_auto(void) -+{ -+ if (!is_mem_sr()) -+ return false; -+ -+ return pci_read_config32(PCH_LPC_DEV, PMIR) & PMIR_XHCI_SMART_AUTO; -+} -+ -+enum usb_port_route { -+ ROUTE_TO_EHCI, -+ ROUTE_TO_XHCI, -+}; -+ -+/* Returns whether port reset was successful */ -+static bool reset_usb2_ports(const unsigned int ehci_ports) -+{ -+ for (unsigned int port = 0; port < ehci_ports; port++) { -+ /* Initiate port reset for all USB2 ports */ -+ clrsetbits32( -+ xhci_bar + XHCI_USB2_PORTSC(port), -+ XHCI_USB2_PORTSC_PED, -+ XHCI_USB2_PORTSC_PR); -+ } -+ /* Poll for port reset bit to be cleared or time out at 100ms */ -+ struct stopwatch timer; -+ stopwatch_init_msecs_expire(&timer, 100); -+ uint32_t reg32; -+ do { -+ reg32 = 0; -+ for (unsigned int port = 0; port < ehci_ports; port++) -+ reg32 |= read32(xhci_bar + XHCI_USB2_PORTSC(port)); -+ -+ reg32 &= XHCI_USB2_PORTSC_PR; -+ if (!reg32) { -+ const long elapsed_time = stopwatch_duration_usecs(&timer); -+ printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time); -+ return true; -+ } -+ /* Reference code has a 10 ms delay here, but a smaller delay works too */ -+ udelay(100); -+ } while (!stopwatch_expired(&timer)); -+ printk(BIOS_ERR, "%s: timed out\n", __func__); -+ return !reg32; -+} -+ -+/* Returns whether warm reset was successful */ -+static bool warm_reset_usb3_ports(const unsigned int xhci_ports) -+{ -+ for (unsigned int port = 0; port < xhci_ports; port++) { -+ /* Initiate warm reset for all USB3 ports */ -+ clrsetbits32( -+ xhci_bar + XHCI_USB3_PORTSC(port), -+ XHCI_USB3_PORTSC_PED, -+ XHCI_USB3_PORTSC_WPR); -+ } -+ /* Poll for port reset bit to be cleared or time out at 100ms */ -+ struct stopwatch timer; -+ stopwatch_init_msecs_expire(&timer, 100); -+ uint32_t reg32; -+ do { -+ reg32 = 0; -+ for (unsigned int port = 0; port < xhci_ports; port++) -+ reg32 |= read32(xhci_bar + XHCI_USB3_PORTSC(port)); -+ -+ reg32 &= XHCI_USB3_PORTSC_PR; -+ if (!reg32) { -+ const long elapsed_time = stopwatch_duration_usecs(&timer); -+ printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time); -+ return true; -+ } -+ /* Reference code has a 10 ms delay here, but a smaller delay works too */ -+ udelay(100); -+ } while (!stopwatch_expired(&timer)); -+ printk(BIOS_ERR, "%s: timed out\n", __func__); -+ return !reg32; -+} -+ -+static void perform_xhci_ehci_switching_flow(const enum usb_port_route usb_route) -+{ -+ const pci_devfn_t dev = PCH_XHCI_DEV; -+ -+ const unsigned int ehci_ports = hs_port_count() + is_usbr_enabled(); -+ const unsigned int xhci_ports = ss_port_count(); -+ -+ const uint32_t ehci_mask = BIT(ehci_ports) - 1; -+ const uint32_t xhci_mask = BIT(xhci_ports) - 1; -+ -+ /** TODO: Handle USBr port? How, though? **/ -+ pci_update_config32(dev, XHCI_USB2PRM, ~XHCI_USB2PR_HCSEL, ehci_mask); -+ pci_update_config32(dev, XHCI_USB3PRM, ~XHCI_USB3PR_SSEN, xhci_mask); -+ -+ /* -+ * Workaround for USB2PR / USB3PR value not surviving warm reset. -+ * Restore USB Port Routing registers if OS HC Switch driver has been executed. -+ */ -+ if (should_restore_xhci_smart_auto()) { -+ /** FIXME: Derive values from mainboard code instead? **/ -+ pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_mask); -+ pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN, xhci_mask); -+ } -+ -+ /* Later stages shouldn't need the value of this bit */ -+ pci_and_config32(PCH_LPC_DEV, PMIR, ~PMIR_XHCI_SMART_AUTO); -+ -+ /** -+ * FIXME: Things here depend on the chosen routing mode. -+ * For now, implement both functions. -+ */ -+ -+ /* Route to EHCI if xHCI disabled or auto mode */ -+ if (usb_route == ROUTE_TO_EHCI) { -+ if (!reset_usb2_ports(ehci_ports)) -+ printk(BIOS_ERR, "USB2 port reset timed out\n"); -+ -+ pci_and_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL); -+ -+ for (unsigned int port = 0; port < ehci_ports; port++) { -+ clrsetbits32( -+ xhci_bar + XHCI_USB2_PORTSC(port), -+ XHCI_USB2_PORTSC_PED, -+ XHCI_USB2_PORTSC_CHST); -+ } -+ -+ if (!warm_reset_usb3_ports(xhci_ports)) -+ printk(BIOS_ERR, "USB3 warm reset timed out\n"); -+ -+ /* FIXME: BWG says this should be inside the warm reset function */ -+ pci_and_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN); -+ -+ for (unsigned int port = 0; port < ehci_ports; port++) { -+ clrsetbits32( -+ xhci_bar + XHCI_USB3_PORTSC(port), -+ XHCI_USB3_PORTSC_PED, -+ XHCI_USB3_PORTSC_CHST); -+ } -+ -+ setbits32(xhci_bar + XHCI_USBCMD, BIT(0)); -+ clrbits32(xhci_bar + XHCI_USBCMD, BIT(0)); -+ } -+ -+ /* Route to xHCI if xHCI enabled */ -+ if (usb_route == ROUTE_TO_XHCI) { -+ if (is_mem_sr()) { -+ if (!warm_reset_usb3_ports(xhci_ports)) -+ printk(BIOS_ERR, "USB3 warm reset timed out\n"); -+ } -+ -+ const uint32_t xhci_port_mask = pci_read_config32(dev, XHCI_USB3PRM) & 0x3f; -+ pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN, xhci_port_mask); -+ -+ const uint32_t ehci_port_mask = pci_read_config32(dev, XHCI_USB2PRM) & 0x7fff; -+ pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_port_mask); -+ } -+} -+ -+/* Do not shift in this macro, as it can cause undefined behaviour for bad port/oc values */ -+#define PORT_TO_OC_SHIFT(port, oc) ((oc) * 8 + (port)) -+ -+/* Avoid shifting into undefined behaviour */ -+static inline bool shift_ok(const int shift) -+{ -+ return shift >= 0 && shift < 32; -+} -+ -+static void usb_overcurrent_mapping(void) -+{ -+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP); -+ -+ uint32_t ehci_1_ocmap = 0; -+ uint32_t ehci_2_ocmap = 0; -+ uint32_t xhci_1_ocmap = 0; -+ uint32_t xhci_2_ocmap = 0; -+ -+ /* -+ * EHCI -+ */ -+ for (unsigned int idx = 0; idx < physical_port_count(); idx++) { -+ const struct usb2_port_config *const port = &mainboard_usb2_ports[idx]; -+ printk(BIOS_DEBUG, "USB2 port %u => ", idx); -+ if (!port->enable) { -+ printk(BIOS_DEBUG, "disabled\n"); -+ continue; -+ } -+ const unsigned short oc_pin = port->oc_pin; -+ if (oc_pin == USB_OC_PIN_SKIP) { -+ printk(BIOS_DEBUG, "not mapped to OC pin\n"); -+ continue; -+ } -+ /* Ports 0 .. 7 => OC 0 .. 3 */ -+ if (idx < 8 && oc_pin <= 3) { -+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin); -+ if (shift_ok(shift)) { -+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin); -+ ehci_1_ocmap |= 1 << shift; -+ continue; -+ } -+ } -+ /* Ports 8 .. 13 => OC 4 .. 7 (LPT-H only) */ -+ if (!is_lp && idx >= 8 && oc_pin >= 4) { -+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4); -+ if (shift_ok(shift)) { -+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin); -+ ehci_2_ocmap |= 1 << shift; -+ continue; -+ } -+ } -+ printk(BIOS_ERR, "Invalid OC pin %u for USB2 port %u\n", oc_pin, idx); -+ } -+ printk(BIOS_DEBUG, "\n"); -+ pci_write_config32(PCH_EHCI1_DEV, EHCI_OCMAP, ehci_1_ocmap); -+ if (!is_lp) -+ pci_write_config32(PCH_EHCI2_DEV, EHCI_OCMAP, ehci_2_ocmap); -+ -+ /* -+ * xHCI -+ */ -+ for (unsigned int idx = 0; idx < ss_port_count(); idx++) { -+ const struct usb3_port_config *const port = &mainboard_usb3_ports[idx]; -+ printk(BIOS_DEBUG, "USB3 port %u => ", idx); -+ if (!port->enable) { -+ printk(BIOS_DEBUG, "disabled\n"); -+ continue; -+ } -+ const unsigned short oc_pin = port->oc_pin; -+ if (oc_pin == USB_OC_PIN_SKIP) { -+ printk(BIOS_DEBUG, "not mapped to OC pin\n"); -+ continue; -+ } -+ /* Ports 0 .. 5 => OC 0 .. 3 */ -+ if (oc_pin <= 3) { -+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin); -+ if (shift_ok(shift)) { -+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin); -+ xhci_1_ocmap |= 1 << shift; -+ continue; -+ } -+ } -+ /* Ports 0 .. 5 => OC 4 .. 7 (LPT-H only) */ -+ if (!is_lp && oc_pin >= 4) { -+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4); -+ if (shift_ok(shift)) { -+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin); -+ xhci_2_ocmap |= 1 << shift; -+ continue; -+ } -+ } -+ printk(BIOS_ERR, "Invalid OC pin %u for USB3 port %u\n", oc_pin, idx); -+ } -+ printk(BIOS_DEBUG, "\n"); -+ pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM1, ehci_1_ocmap); -+ pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM1, xhci_1_ocmap); -+ if (!is_lp) { -+ pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM2, ehci_2_ocmap); -+ pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM2, xhci_2_ocmap); -+ } -+} -+ -+static uint8_t get_ehci_tune_param_1(const struct usb2_port_config *const port) -+{ -+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP); -+ -+ const enum pch_platform_type plat_type = get_pch_platform_type(); -+ const enum usb2_port_location location = port->location; -+ const uint16_t length = port->length; -+ if (!is_lp) { -+ if (plat_type == PCH_TYPE_DESKTOP) { -+ if (location == USB_PORT_BACK_PANEL) -+ return 4; /* Back Panel */ -+ else -+ return 3; /* Front Panel */ -+ -+ } else if (plat_type == PCH_TYPE_MOBILE) { -+ if (location == USB_PORT_INTERNAL) -+ return 5; /* Internal Topology */ -+ else if (location == USB_PORT_DOCK) -+ return 4; /* Dock */ -+ else if (length < 0x70) -+ return 5; /* Back Panel, less than 7" */ -+ else -+ return 6; /* Back Panel, 7" or more */ -+ } -+ } else { -+ if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) { -+ if (length < 0x70) -+ return 5; /* Back Panel, less than 7" */ -+ else -+ return 6; /* Back Panel, 7" or more */ -+ } else if (location == USB_PORT_DOCK) { -+ return 4; /* Dock */ -+ } else { -+ return 5; /* Internal Topology */ -+ } -+ } -+ printk(BIOS_ERR, "%s: Unhandled case\n", __func__); -+ return 0; -+} -+ -+static uint8_t get_ehci_tune_param_2(const struct usb2_port_config *const port) -+{ -+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP); -+ -+ const enum pch_platform_type plat_type = get_pch_platform_type(); -+ const enum usb2_port_location location = port->location; -+ const uint16_t length = port->length; -+ if (!is_lp) { -+ if (plat_type == PCH_TYPE_DESKTOP) { -+ if (location == USB_PORT_BACK_PANEL) { -+ if (length < 0x80) -+ return 2; /* Back Panel, less than 8" */ -+ else if (length < 0x130) -+ return 3; /* Back Panel, 8"-13" */ -+ else -+ return 4; /* Back Panel, 13" or more */ -+ } else { -+ return 2; /* Front Panel */ -+ } -+ -+ } else if (plat_type == PCH_TYPE_MOBILE) { -+ if (location == USB_PORT_INTERNAL) { -+ return 2; /* Internal Topology */ -+ } else if (location == USB_PORT_DOCK) { -+ if (length < 0x50) -+ return 1; /* Dock, less than 5" */ -+ else -+ return 2; /* Dock, 5" or more */ -+ } else { -+ if (length < 0x100) -+ return 2; /* Back Panel, less than 10" */ -+ else -+ return 3; /* Back Panel, 10" or more */ -+ } -+ } -+ } else { -+ if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) { -+ if (length < 0x100) -+ return 2; /* Back Panel, less than 10" */ -+ else -+ return 3; /* Back Panel, 10" or more */ -+ } else if (location == USB_PORT_DOCK) { -+ if (length < 0x50) -+ return 1; /* Dock, less than 5" */ -+ else -+ return 2; /* Dock, 5" or more */ -+ } else { -+ return 2; /* Internal Topology */ -+ } -+ } -+ printk(BIOS_ERR, "%s: Unhandled case\n", __func__); -+ return 0; -+} -+ -+static void program_ehci_port_length(void) -+{ -+ for (unsigned int port = 0; port < physical_port_count(); port++) { -+ if (!mainboard_usb2_ports[port].enable) -+ continue; -+ const uint32_t addr = 0xe5004000 + (port + 1) * 0x100; -+ const uint8_t param_1 = get_ehci_tune_param_1(&mainboard_usb2_ports[port]); -+ const uint8_t param_2 = get_ehci_tune_param_2(&mainboard_usb2_ports[port]); -+ pch_iobp_update(addr, ~0x7f00, param_2 << 11 | param_1 << 8); -+ } -+} -+ -+void early_usb_init(void) -+{ -+ /** TODO: Make this configurable? How do the modes affect usbdebug? **/ -+ const enum usb_port_route usb_route = ROUTE_TO_XHCI; -+ ///(pd->boot_mode == 2 && pd->usb_xhci_on_resume) ? ROUTE_TO_XHCI : ROUTE_TO_EHCI; -+ -+ common_ehci_hcs_init(); -+ xhci_open_memory_space(); -+ common_xhci_hc_init(); -+ perform_xhci_ehci_switching_flow(usb_route); -+ usb_overcurrent_mapping(); -+ program_ehci_port_length(); -+ /** FIXME: USB per port control is missing, is it needed? **/ -+ xhci_close_memory_space(); -+ /** TODO: Close EHCI memory space? **/ -+} -diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h -index b5e0c2a830..ad983d86cf 100644 ---- a/src/southbridge/intel/lynxpoint/pch.h -+++ b/src/southbridge/intel/lynxpoint/pch.h -@@ -115,6 +115,7 @@ enum pch_platform_type { - - void pch_dmi_setup_physical_layer(void); - void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); -+void early_usb_init(void); - - void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); - void usb_ehci_disable(pci_devfn_t dev); -@@ -202,6 +203,8 @@ void mainboard_config_rcba(void); - #define GEN_PMCON_1 0xa0 - #define SMI_LOCK (1 << 4) - #define GEN_PMCON_2 0xa2 -+#define GEN_PMCON_2_DISB (1 << 7) -+#define GEN_PMCON_2_MEM_SR (1 << 5) - #define SYSTEM_RESET_STS (1 << 4) - #define THERMTRIP_STS (1 << 3) - #define SYSPWR_FLR (1 << 1) -@@ -215,6 +218,7 @@ void mainboard_config_rcba(void); - #define PMIR 0xac - #define PMIR_CF9LOCK (1 << 31) - #define PMIR_CF9GR (1 << 20) -+#define PMIR_XHCI_SMART_AUTO (1 << 16) /* c.f. LPT BWG or WPT-LP BIOS spec */ - - /* GEN_PMCON_3 bits */ - #define RTC_BATTERY_DEAD (1 << 2) -@@ -282,6 +286,20 @@ void mainboard_config_rcba(void); - #define SATA_DTLE_DATA_SHIFT 24 - #define SATA_DTLE_EDGE_SHIFT 16 - -+/* -+ * HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index -+ * selects 0:1d.0 (PCH_EHCI1) for usbdebug use. -+ */ -+#if CONFIG_USBDEBUG_HCD_INDEX != 2 -+#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR -+#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400) -+#else -+#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR -+#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400) -+#endif -+ -+#define PCH_XHCI_TEMP_BAR0 0xe8100000 -+ - /* EHCI PCI Registers */ - #define EHCI_PWR_CTL_STS 0x54 - #define PWR_CTL_SET_MASK 0x3 -@@ -289,10 +307,15 @@ void mainboard_config_rcba(void); - #define PWR_CTL_SET_D3 0x3 - #define PWR_CTL_ENABLE_PME (1 << 8) - #define PWR_CTL_STATUS_PME (1 << 15) -+#define EHCI_OCMAP 0x74 -+#define EHCI_ACCESS_CNTL 0x80 -+#define ACCESS_CNTL_ENABLE (1 << 0) - - /* EHCI Memory Registers */ -+#define EHCI_HCS_PARAMS 0x04 - #define EHCI_USB_CMD 0x20 - #define EHCI_USB_CMD_RUN (1 << 0) -+#define EHCI_USB_CMD_HCRESET (1 << 1) - #define EHCI_USB_CMD_PSE (1 << 4) - #define EHCI_USB_CMD_ASE (1 << 5) - #define EHCI_PORTSC(port) (0x64 + (port) * 4) -@@ -301,6 +324,10 @@ void mainboard_config_rcba(void); - - /* XHCI PCI Registers */ - #define XHCI_PWR_CTL_STS 0x74 -+#define XHCI_U2OCM1 0xc0 -+#define XHCI_U2OCM2 0xc4 -+#define XHCI_U3OCM1 0xc8 -+#define XHCI_U3OCM2 0xcc - #define XHCI_USB2PR 0xd0 - #define XHCI_USB2PRM 0xd4 - #define XHCI_USB2PR_HCSEL 0x7fff -@@ -313,6 +340,27 @@ void mainboard_config_rcba(void); - #define XHCI_USB3PDO 0xe8 - - /* XHCI Memory Registers */ -+#define XHCI_HCS_PARAMS_1 0x04 -+#define XHCI_HCS_PARAMS_2 0x08 -+#define XHCI_HCS_PARAMS_3 0x0c -+#define XHCI_HCC_PARAMS 0x10 -+#define XHCI_USBCMD 0x80 -+#define XHCI_USB2_PORTSC(port) (0x480 + ((port) * 0x10)) -+#define XHCI_USB2_PORTSC_WPR (1 << 31) /* Warm Port Reset */ -+#define XHCI_USB2_PORTSC_CEC (1 << 23) /* Port Config Error Change */ -+#define XHCI_USB2_PORTSC_PLC (1 << 22) /* Port Link State Change */ -+#define XHCI_USB2_PORTSC_PRC (1 << 21) /* Port Reset Change */ -+#define XHCI_USB2_PORTSC_OCC (1 << 20) /* Over-current Change */ -+#define XHCI_USB2_PORTSC_WRC (1 << 19) /* Warm Port Reset Change */ -+#define XHCI_USB2_PORTSC_PEC (1 << 18) /* Port Enabled Disabled Change */ -+#define XHCI_USB2_PORTSC_CSC (1 << 17) /* Connect Status Change */ -+#define XHCI_USB2_PORTSC_CHST (0x7f << 17) -+#define XHCI_USB2_PORTSC_LWS (1 << 16) /* Port Link State Write Strobe */ -+#define XHCI_USB2_PORTSC_PP (1 << 9) -+#define XHCI_USB2_PORTSC_PR (1 << 4) /* Port Reset */ -+#define XHCI_USB2_PORTSC_PED (1 << 1) /* Port Enable/Disabled */ -+#define XHCI_USB2_PORTSC_CCS (1 << 0) /* Current Connect Status */ -+ - #define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + ((port) * 0x10)) - #define XHCI_USB3_PORTSC_CHST (0x7f << 17) - #define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ -@@ -320,6 +368,7 @@ void mainboard_config_rcba(void); - #define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ - #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ - #define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -+#define XHCI_USB3_PORTSC_PR (1 << 4) /* Port Reset */ - #define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ - #define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ - #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0016-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch b/config/coreboot/haswell/patches/0006-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch index c321d239..ea46364f 100644 --- a/config/coreboot/haswell/patches/0016-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch +++ b/config/coreboot/haswell/patches/0006-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch @@ -1,7 +1,7 @@ -From d24def01ec15f41a48331ef1e236270b2df90b84 Mon Sep 17 00:00:00 2001 +From 1ea9b05694da7ee61d49d9cd2b7e533a98e42321 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 21:49:40 +0200 -Subject: [PATCH 16/26] haswell NRI: Add DDR3 JEDEC reset and init +Subject: [PATCH 06/20] haswell NRI: Add DDR3 JEDEC reset and init Implement JEDEC reset and init sequence for DDR3. The MRS commands are issued through the REUT (Robust Electrical Unified Testing) hardware. @@ -9,25 +9,25 @@ issued through the REUT (Robust Electrical Unified Testing) hardware. Change-Id: I2a0c066537021b587599228086727cb1e041bff5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 3 + + .../intel/haswell/native_raminit/Makefile.mk | 3 + .../intel/haswell/native_raminit/ddr3.c | 217 ++++++++++++++++++ .../haswell/native_raminit/io_comp_control.c | 19 ++ .../haswell/native_raminit/jedec_reset.c | 120 ++++++++++ .../haswell/native_raminit/raminit_main.c | 2 + - .../haswell/native_raminit/raminit_native.h | 101 ++++++++ + .../haswell/native_raminit/raminit_native.h | 99 ++++++++ .../haswell/native_raminit/reg_structs.h | 154 +++++++++++++ .../intel/haswell/native_raminit/reut.c | 196 ++++++++++++++++ .../intel/haswell/registers/mchbar.h | 21 ++ src/southbridge/intel/lynxpoint/pch.h | 2 + - 10 files changed, 835 insertions(+) + 10 files changed, 833 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/ddr3.c create mode 100644 src/northbridge/intel/haswell/native_raminit/jedec_reset.c create mode 100644 src/northbridge/intel/haswell/native_raminit/reut.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 37d527e972..e9212df9e6 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,11 +1,14 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -267,7 +267,7 @@ index 0000000000..6ddb11488b + return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT); +} diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c -index 7e96c08938..ad8c848e57 100644 +index d45b608dd3..8a55fd81b2 100644 --- a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c +++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c @@ -8,6 +8,25 @@ @@ -423,10 +423,10 @@ index 0000000000..de0f676758 + return status; +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 136a8ba989..73ff180b8c 100644 +index 559dfc3a4e..94b268468c 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -25,6 +25,7 @@ static const struct task_entry cold_boot[] = { +@@ -24,6 +24,7 @@ static const struct task_entry cold_boot[] = { { convert_timings, true, "CONVTIM", }, { configure_mc, true, "CONFMC", }, { configure_memory_map, true, "MEMMAP", }, @@ -434,7 +434,7 @@ index 136a8ba989..73ff180b8c 100644 }; /* Return a generic stepping value to make stepping checks simpler */ -@@ -58,6 +59,7 @@ static void initialize_ctrl(struct sysinfo *ctrl) +@@ -57,6 +58,7 @@ static void initialize_ctrl(struct sysinfo *ctrl) ctrl->stepping = get_stepping(ctrl->cpu); ctrl->vdd_mv = is_hsw_ult() ? 1350 : 1500; /** FIXME: Hardcoded, does it matter? **/ ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved; @@ -443,7 +443,7 @@ index 136a8ba989..73ff180b8c 100644 } diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 4763b25e8d..e3cf4254a0 100644 +index 4763b25e8d..4bc2a4955f 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -27,6 +27,30 @@ @@ -498,25 +498,23 @@ index 4763b25e8d..e3cf4254a0 100644 union tc_bank_rank_c_reg tc_bankrank_c[NUM_CHANNELS]; union tc_bank_rank_d_reg tc_bankrank_d[NUM_CHANNELS]; + -+ uint16_t mr0[NUM_CHANNELS][NUM_SLOTRANKS]; -+ uint16_t mr1[NUM_CHANNELS][NUM_SLOTRANKS]; -+ uint16_t mr2[NUM_CHANNELS][NUM_SLOTRANKS]; -+ uint16_t mr3[NUM_CHANNELS][NUM_SLOTRANKS]; ++ uint16_t mr0[NUM_CHANNELS][NUM_SLOTS]; ++ uint16_t mr1[NUM_CHANNELS][NUM_SLOTS]; ++ uint16_t mr2[NUM_CHANNELS][NUM_SLOTS]; ++ uint16_t mr3[NUM_CHANNELS][NUM_SLOTS]; }; static inline bool is_hsw_ult(void) -@@ -196,6 +227,55 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl) +@@ -196,6 +227,53 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl) memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train)); } +/* Number of ticks to wait in units of 69.841279 ns (citation needed) */ +static inline void tick_delay(const uint32_t delay) +{ -+ volatile uint32_t junk; -+ + /* Just perform reads to a random register */ + for (uint32_t start = 0; start <= delay; start++) -+ junk = mchbar_read32(REUT_ERR_DATA_STATUS); ++ mchbar_read32(REUT_ERR_DATA_STATUS); +} + +/* @@ -561,7 +559,7 @@ index 4763b25e8d..e3cf4254a0 100644 void raminit_main(enum raminit_boot_mode bootmode); enum raminit_status collect_spd_info(struct sysinfo *ctrl); -@@ -203,6 +283,7 @@ enum raminit_status initialise_mpll(struct sysinfo *ctrl); +@@ -203,6 +281,7 @@ enum raminit_status initialise_mpll(struct sysinfo *ctrl); enum raminit_status convert_timings(struct sysinfo *ctrl); enum raminit_status configure_mc(struct sysinfo *ctrl); enum raminit_status configure_memory_map(struct sysinfo *ctrl); @@ -569,7 +567,7 @@ index 4763b25e8d..e3cf4254a0 100644 void configure_timings(struct sysinfo *ctrl); void configure_refresh(struct sysinfo *ctrl); -@@ -215,8 +296,28 @@ uint32_t get_tXS_offset(uint32_t mem_clock_mhz); +@@ -215,8 +294,28 @@ uint32_t get_tXS_offset(uint32_t mem_clock_mhz); uint32_t get_tZQOPER(uint32_t mem_clock_mhz, bool lpddr); uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr); @@ -779,7 +777,7 @@ index 70487e1640..9929f617fe 100644 struct __packed { diff --git a/src/northbridge/intel/haswell/native_raminit/reut.c b/src/northbridge/intel/haswell/native_raminit/reut.c new file mode 100644 -index 0000000000..c55cdd9c7e +index 0000000000..31019f74a1 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/reut.c @@ -0,0 +1,196 @@ @@ -938,9 +936,9 @@ index 0000000000..c55cdd9c7e +{ + /** TODO: Issuing ZQ commands differs for LPDDR **/ + if (ctrl->lpddr) -+ die("%s: LPDDR not yet supported in ZQ calibration\n"); ++ die("%s: LPDDR not yet supported in ZQ calibration\n", __func__); + -+ uint8_t opcode; /* NOTE: Only used for LPDDR */ ++ __maybe_unused uint8_t opcode; /* NOTE: Only used for LPDDR */ + uint16_t zq = 0; + switch (zq_type) { + case ZQ_INIT: @@ -958,7 +956,7 @@ index 0000000000..c55cdd9c7e + opcode = 0xc3; + break; + default: -+ die("%s: ZQ type %u is invalid\n", zq_type); ++ die("%s: ZQ type %u is invalid\n", __func__, zq_type); + } + + /* ZQCS on single-channel needs a longer delay */ @@ -1021,7 +1019,7 @@ index 2acc5cbbc8..4fc78a7f43 100644 /* MCDECS */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h -index 74b4d50017..16bef5032a 100644 +index 07f4b9dc16..5b3696347c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -586,6 +586,8 @@ void mainboard_config_rcba(void); diff --git a/config/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch b/config/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch deleted file mode 100644 index 157d2999..00000000 --- a/config/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch +++ /dev/null @@ -1,128 +0,0 @@ -From 92be49d8422b4bc1c89bb49535f4dc6a01d47295 Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Fri, 6 May 2022 23:22:11 +0200 -Subject: [PATCH 06/26] sb/intel/lynxpoint: Add native thermal init - -Implement native thermal initialisation for Lynx Point. This is only -needed when MRC.bin is not used. - -Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - .../haswell/native_raminit/raminit_native.c | 1 + - src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- - src/southbridge/intel/lynxpoint/pch.h | 1 + - src/southbridge/intel/lynxpoint/thermal.c | 64 +++++++++++++++++++ - 4 files changed, 67 insertions(+), 1 deletion(-) - create mode 100644 src/southbridge/intel/lynxpoint/thermal.c - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index ef61d4ee09..dd1f1ec14e 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -16,6 +16,7 @@ static bool early_init_native(int s3resume) - /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ - const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); - -+ early_thermal_init(); - early_usb_init(); - - if (!CONFIG(INTEL_LYNXPOINT_LP)) -diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc -index 0e1f2fe4eb..a9a9b153d6 100644 ---- a/src/southbridge/intel/lynxpoint/Makefile.inc -+++ b/src/southbridge/intel/lynxpoint/Makefile.inc -@@ -37,7 +37,7 @@ bootblock-y += early_pch.c - romstage-y += early_usb.c early_me.c me_status.c early_pch.c - romstage-y += pmutil.c - --romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c -+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c - - ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) - romstage-y += lp_gpio.c -diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h -index ad983d86cf..38a9349220 100644 ---- a/src/southbridge/intel/lynxpoint/pch.h -+++ b/src/southbridge/intel/lynxpoint/pch.h -@@ -116,6 +116,7 @@ enum pch_platform_type { - void pch_dmi_setup_physical_layer(void); - void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); - void early_usb_init(void); -+void early_thermal_init(void); - - void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); - void usb_ehci_disable(pci_devfn_t dev); -diff --git a/src/southbridge/intel/lynxpoint/thermal.c b/src/southbridge/intel/lynxpoint/thermal.c -new file mode 100644 -index 0000000000..e71969ea0c ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/thermal.c -@@ -0,0 +1,64 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <device/mmio.h> -+#include <device/pci_ops.h> -+#include <southbridge/intel/lynxpoint/pch.h> -+#include <types.h> -+ -+#define TBARB_TEMP 0x40000000 -+ -+#define THERMAL_DEV PCI_DEV(0, 0x1f, 6) -+ -+/* Early thermal init, it may need to be done prior to giving ME its memory */ -+void early_thermal_init(void) -+{ -+ /* Program address for temporary BAR */ -+ pci_write_config32(THERMAL_DEV, 0x40, TBARB_TEMP); -+ pci_write_config32(THERMAL_DEV, 0x44, 0); -+ -+ /* Activate temporary BAR */ -+ pci_or_config32(THERMAL_DEV, 0x40, 1); -+ -+ /* -+ * BWG section 17.3.1 says: -+ * -+ * ### Initializing Lynx Point Thermal Sensors ### -+ * -+ * The System BIOS must perform the following steps to initialize the Lynx -+ * Point thermal subsystem device, D31:F6. The System BIOS is required to -+ * repeat this process on a resume from Sx. BIOS may enable any or all of -+ * the registers below based on OEM's platform configuration. Intel does -+ * not recommend a value on some of the registers, since each platform has -+ * different temperature trip points and one may enable a trip to cause an -+ * SMI while another platform would cause an interrupt instead. -+ * -+ * The recommended flow for enabling thermal sensor is by setting up various -+ * temperature trip points first, followed by enabling the desired trip -+ * alert method and then enable the actual sensors from TSEL registers. -+ * If this flow is not followed, software will need to take special care -+ * to handle false events during setting up those registers. -+ */ -+ -+ /* Step 1: Program CTT */ -+ write16p(TBARB_TEMP + 0x10, 0x0154); -+ -+ /* Step 2: Clear trip status from TSS and TAS */ -+ write8p(TBARB_TEMP + 0x06, 0xff); -+ write8p(TBARB_TEMP + 0x80, 0xff); -+ -+ /* Step 3: Program TSGPEN and TSPIEN to zero */ -+ write8p(TBARB_TEMP + 0x84, 0x00); -+ write8p(TBARB_TEMP + 0x82, 0x00); -+ -+ /* -+ * Step 4: If thermal reporting to an EC over SMBus is supported, -+ * then write 0x01 to TSREL, else leave at default. -+ */ -+ write8p(TBARB_TEMP + 0x0a, 0x01); -+ -+ /* Disable temporary BAR */ -+ pci_and_config32(THERMAL_DEV, 0x40, ~1); -+ -+ /* Clear temporary BAR address */ -+ pci_write_config32(THERMAL_DEV, 0x40, 0); -+} --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0017-haswell-NRI-Add-pre-training-steps.patch b/config/coreboot/haswell/patches/0007-haswell-NRI-Add-pre-training-steps.patch index e4cea123..8b73df88 100644 --- a/config/coreboot/haswell/patches/0017-haswell-NRI-Add-pre-training-steps.patch +++ b/config/coreboot/haswell/patches/0007-haswell-NRI-Add-pre-training-steps.patch @@ -1,7 +1,7 @@ -From 42e43eb210bbb172af8e5ad064326c4570be8654 Mon Sep 17 00:00:00 2001 +From 936d432822fcd9aa2f018444cdc89e48e6d257d5 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 23:12:18 +0200 -Subject: [PATCH 17/26] haswell NRI: Add pre-training steps +Subject: [PATCH 07/20] haswell NRI: Add pre-training steps Implement pre-training steps, which consist of enabling ECC I/O and filling the WDB (Write Data Buffer, stores test patterns) through a @@ -10,19 +10,19 @@ magic LDAT port. Change-Id: Ie2e09e3b218c4569ed8de5c5e1b05d491032e0f1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + - .../haswell/native_raminit/raminit_main.c | 34 ++++ + .../intel/haswell/native_raminit/Makefile.mk | 1 + + .../haswell/native_raminit/raminit_main.c | 35 ++++ .../haswell/native_raminit/raminit_native.h | 24 +++ .../haswell/native_raminit/reg_structs.h | 45 +++++ .../intel/haswell/native_raminit/setup_wdb.c | 159 ++++++++++++++++++ .../intel/haswell/registers/mchbar.h | 9 + - 6 files changed, 272 insertions(+) + 6 files changed, 273 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/setup_wdb.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index e9212df9e6..8d7d4e4db0 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -10,5 +10,6 @@ romstage-y += memory_map.c romstage-y += raminit_main.c romstage-y += raminit_native.c @@ -31,10 +31,18 @@ index e9212df9e6..8d7d4e4db0 100644 romstage-y += spd_bitmunching.c romstage-y += timings_refresh.c diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 73ff180b8c..5e4674957d 100644 +index 94b268468c..5e4674957d 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -13,6 +13,39 @@ +@@ -3,6 +3,7 @@ + #include <assert.h> + #include <console/console.h> + #include <cpu/intel/haswell/haswell.h> ++#include <delay.h> + #include <device/pci_ops.h> + #include <northbridge/intel/haswell/chip.h> + #include <northbridge/intel/haswell/haswell.h> +@@ -12,6 +13,39 @@ #include "raminit_native.h" @@ -74,7 +82,7 @@ index 73ff180b8c..5e4674957d 100644 struct task_entry { enum raminit_status (*task)(struct sysinfo *); bool is_enabled; -@@ -26,6 +59,7 @@ static const struct task_entry cold_boot[] = { +@@ -25,6 +59,7 @@ static const struct task_entry cold_boot[] = { { configure_mc, true, "CONFMC", }, { configure_memory_map, true, "MEMMAP", }, { do_jedec_init, true, "JEDECINIT", }, @@ -83,7 +91,7 @@ index 73ff180b8c..5e4674957d 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index e3cf4254a0..f29c2ec366 100644 +index 4bc2a4955f..1971b44b66 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -35,6 +35,13 @@ @@ -100,7 +108,7 @@ index e3cf4254a0..f29c2ec366 100644 /* ZQ calibration types */ enum { ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */ -@@ -318,6 +325,23 @@ void reut_issue_mrs_all( +@@ -316,6 +323,23 @@ void reut_issue_mrs_all( enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type); diff --git a/config/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch b/config/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch deleted file mode 100644 index 74427f5d..00000000 --- a/config/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch +++ /dev/null @@ -1,785 +0,0 @@ -From 7378cb4fefc87b9a096bb14820a44f26f3a628f5 Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Fri, 6 May 2022 23:43:46 +0200 -Subject: [PATCH 07/26] sb/intel/lynxpoint: Add native PCH init - -Implement native PCH initialisation for Lynx Point. This is only needed -when MRC.bin is not used. - -Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561 -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - .../haswell/native_raminit/raminit_native.c | 3 +- - src/southbridge/intel/lynxpoint/Makefile.inc | 1 + - .../intel/lynxpoint/early_pch_native.c | 123 +++++++++ - .../intel/lynxpoint/hsio/Makefile.inc | 8 + - src/southbridge/intel/lynxpoint/hsio/common.c | 52 ++++ - src/southbridge/intel/lynxpoint/hsio/hsio.h | 46 ++++ - .../intel/lynxpoint/hsio/lpt_h_cx.c | 244 ++++++++++++++++++ - .../intel/lynxpoint/hsio/lpt_lp_bx.c | 180 +++++++++++++ - src/southbridge/intel/lynxpoint/pch.h | 6 + - 9 files changed, 661 insertions(+), 2 deletions(-) - create mode 100644 src/southbridge/intel/lynxpoint/hsio/Makefile.inc - create mode 100644 src/southbridge/intel/lynxpoint/hsio/common.c - create mode 100644 src/southbridge/intel/lynxpoint/hsio/hsio.h - create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c - create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index dd1f1ec14e..b6efb6b40d 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -16,8 +16,7 @@ static bool early_init_native(int s3resume) - /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ - const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); - -- early_thermal_init(); -- early_usb_init(); -+ early_pch_init_native(s3resume); - - if (!CONFIG(INTEL_LYNXPOINT_LP)) - dmi_early_init(); -diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc -index a9a9b153d6..63243ecc86 100644 ---- a/src/southbridge/intel/lynxpoint/Makefile.inc -+++ b/src/southbridge/intel/lynxpoint/Makefile.inc -@@ -38,6 +38,7 @@ romstage-y += early_usb.c early_me.c me_status.c early_pch.c - romstage-y += pmutil.c - - romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c -+subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio - - ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) - romstage-y += lp_gpio.c -diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c -index c28ddfcf5d..421821fa5d 100644 ---- a/src/southbridge/intel/lynxpoint/early_pch_native.c -+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c -@@ -1,10 +1,133 @@ - /* SPDX-License-Identifier: GPL-2.0-or-later */ - - #include <console/console.h> -+#include <device/pci_def.h> - #include <device/pci_ops.h> -+#include <southbridge/intel/lynxpoint/hsio/hsio.h> - #include <southbridge/intel/lynxpoint/pch.h> - #include <types.h> - -+static void early_sata_init(const uint8_t pch_revision) -+{ -+ const bool is_mobile = get_pch_platform_type() != PCH_TYPE_DESKTOP; -+ -+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410); -+ printk(BIOS_DEBUG, "HSIO lane owner: 0x%02x\n", lane_owner); -+ -+ /* BWG Step 2 */ -+ pci_update_config32(PCH_SATA_DEV, SATA_SCLKG, ~0x1ff, 0x183); -+ -+ /* BWG Step 3: Set OOB Retry Mode */ -+ pci_or_config16(PCH_SATA_DEV, SATA_PCS, 1 << 15); -+ -+ /* BWG Step 4: Program the SATA mPHY tables */ -+ if (pch_is_lp()) { -+ if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) { -+ program_hsio_sata_lpt_lp_bx(is_mobile); -+ } else { -+ printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision); -+ } -+ } else { -+ if (pch_revision >= LPT_H_STEP_C0) { -+ program_hsio_sata_lpt_h_cx(is_mobile); -+ } else { -+ printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision); -+ } -+ } -+ -+ /** FIXME: Program SATA RxEq tables **/ -+ -+ /* BWG Step 5 */ -+ /** FIXME: Only for desktop and mobile (skip this on workstation and server) **/ -+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(22)); -+ -+ /* BWG Step 6 */ -+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(19)); -+ -+ /* BWG Step 7 */ -+ pci_update_config32(PCH_SATA_DEV, 0x98, ~(0x3f << 7), 0x04 << 7); -+ -+ /* BWG Step 8 */ -+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(20)); -+ -+ /* BWG Step 9 */ -+ pci_update_config32(PCH_SATA_DEV, 0x98, ~(3 << 5), 1 << 5); -+ -+ /* BWG Step 10 */ -+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(18)); -+ -+ /* Enable SATA ports */ -+ uint8_t sata_pcs = 0; -+ if (CONFIG(INTEL_LYNXPOINT_LP)) { -+ for (uint8_t i = 0; i < 4; i++) { -+ if ((lane_owner & BIT(7 - i)) == 0) { -+ sata_pcs |= BIT(i); -+ } -+ } -+ } else { -+ sata_pcs |= 0x0f; -+ for (uint8_t i = 4; i < 6; i++) { -+ if ((lane_owner & BIT(i)) == 0) { -+ sata_pcs |= BIT(i); -+ } -+ } -+ } -+ printk(BIOS_DEBUG, "SATA port enables: 0x%02x\n", sata_pcs); -+ pci_or_config8(PCH_SATA_DEV, SATA_PCS, sata_pcs); -+} -+ -+void early_pch_init_native(int s3resume) -+{ -+ const uint8_t pch_revision = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID); -+ -+ RCBA16(DISPBDF) = 0x0010; -+ RCBA32_OR(FD2, PCH_ENABLE_DBDF); -+ -+ /** FIXME: Check GEN_PMCON_3 and handle RTC failure? **/ -+ -+ RCBA32(PRSTS) = BIT(4); -+ -+ early_sata_init(pch_revision); -+ -+ pci_or_config8(PCH_LPC_DEV, 0xa6, 1 << 1); -+ pci_and_config8(PCH_LPC_DEV, 0xdc, ~(1 << 5 | 1 << 1)); -+ -+ /** TODO: Send GET HSIO VER and update ChipsetInit table? Is it needed? **/ -+ -+ /** FIXME: GbE handling? **/ -+ -+ pci_update_config32(PCH_LPC_DEV, 0xac, ~(1 << 20), 0); -+ -+ for (uint8_t i = 0; i < 8; i++) -+ pci_update_config32(PCI_DEV(0, 0x1c, i), 0x338, ~(1 << 26), 0); -+ -+ pci_update_config8(PCI_DEV(0, 0x1c, 0), 0xf4, ~(3 << 5), 1 << 7); -+ -+ pci_update_config8(PCI_DEV(0, 26, 0), 0x88, ~(1 << 2), 0); -+ pci_update_config8(PCI_DEV(0, 29, 0), 0x88, ~(1 << 2), 0); -+ -+ /** FIXME: Disable SATA2 device? **/ -+ -+ if (pch_is_lp()) { -+ if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) { -+ program_hsio_xhci_lpt_lp_bx(); -+ program_hsio_igbe_lpt_lp_bx(); -+ } else { -+ printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision); -+ } -+ } else { -+ if (pch_revision >= LPT_H_STEP_C0) { -+ program_hsio_xhci_lpt_h_cx(); -+ program_hsio_igbe_lpt_h_cx(); -+ } else { -+ printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision); -+ } -+ } -+ -+ early_thermal_init(); -+ early_usb_init(); -+} -+ - void pch_dmi_setup_physical_layer(void) - { - /* FIXME: We need to make sure the SA supports Gen2 as well */ -diff --git a/src/southbridge/intel/lynxpoint/hsio/Makefile.inc b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc -new file mode 100644 -index 0000000000..6b74997511 ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc -@@ -0,0 +1,8 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+romstage-y += common.c -+ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) -+romstage-y += lpt_lp_bx.c -+else -+romstage-y += lpt_h_cx.c -+endif -diff --git a/src/southbridge/intel/lynxpoint/hsio/common.c b/src/southbridge/intel/lynxpoint/hsio/common.c -new file mode 100644 -index 0000000000..9935ca347a ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/hsio/common.c -@@ -0,0 +1,52 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <device/pci_ops.h> -+#include <southbridge/intel/lynxpoint/hsio/hsio.h> -+#include <types.h> -+ -+/* -+ * FIXME: Ask Intel whether all lanes need to be programmed as specified -+ * in the PCH BWG. If not, make separate tables and only check this once. -+ */ -+void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or) -+{ -+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410); -+ -+ if ((addr & 0xfe00) == 0x2000 && (lane_owner & (1 << 4))) -+ return; -+ -+ if ((addr & 0xfe00) == 0x2200 && (lane_owner & (1 << 5))) -+ return; -+ -+ if (CONFIG(INTEL_LYNXPOINT_LP)) { -+ if ((addr & 0xfe00) == 0x2400 && (lane_owner & (1 << 6))) -+ return; -+ -+ if ((addr & 0xfe00) == 0x2600 && (lane_owner & (1 << 7))) -+ return; -+ } -+ hsio_update(addr, and, or); -+} -+ -+/* -+ * FIXME: Ask Intel whether all lanes need to be programmed as specified -+ * in the PCH BWG. If not, make separate tables and only check this once. -+ */ -+void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or) -+{ -+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410); -+ if (CONFIG(INTEL_LYNXPOINT_LP)) { -+ if ((addr & 0xfe00) == 0x2400 && ((lane_owner >> 0) & 3) != 2) -+ return; -+ -+ if ((addr & 0xfe00) == 0x2600 && ((lane_owner >> 2) & 3) != 2) -+ return; -+ } else { -+ if ((addr & 0xfe00) == 0x2c00 && ((lane_owner >> 2) & 3) != 2) -+ return; -+ -+ if ((addr & 0xfe00) == 0x2e00 && ((lane_owner >> 0) & 3) != 2) -+ return; -+ } -+ hsio_update(addr, and, or); -+} -diff --git a/src/southbridge/intel/lynxpoint/hsio/hsio.h b/src/southbridge/intel/lynxpoint/hsio/hsio.h -new file mode 100644 -index 0000000000..689ef4a05b ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/hsio/hsio.h -@@ -0,0 +1,46 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H -+#define SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H -+ -+#include <southbridge/intel/lynxpoint/iobp.h> -+#include <types.h> -+ -+struct hsio_table_row { -+ uint32_t addr; -+ uint32_t and; -+ uint32_t or; -+}; -+ -+static inline void hsio_update(const uint32_t addr, const uint32_t and, const uint32_t or) -+{ -+ pch_iobp_update(addr, and, or); -+} -+ -+static inline void hsio_update_row(const struct hsio_table_row row) -+{ -+ hsio_update(row.addr, row.and, row.or); -+} -+ -+void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or); -+void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or); -+ -+static inline void hsio_sata_shared_update_row(const struct hsio_table_row row) -+{ -+ hsio_sata_shared_update(row.addr, row.and, row.or); -+} -+ -+static inline void hsio_xhci_shared_update_row(const struct hsio_table_row row) -+{ -+ hsio_xhci_shared_update(row.addr, row.and, row.or); -+} -+ -+void program_hsio_sata_lpt_h_cx(const bool is_mobile); -+void program_hsio_xhci_lpt_h_cx(void); -+void program_hsio_igbe_lpt_h_cx(void); -+ -+void program_hsio_sata_lpt_lp_bx(const bool is_mobile); -+void program_hsio_xhci_lpt_lp_bx(void); -+void program_hsio_igbe_lpt_lp_bx(void); -+ -+#endif -diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c -new file mode 100644 -index 0000000000..b5dd402742 ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c -@@ -0,0 +1,244 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <device/pci_ops.h> -+#include <southbridge/intel/lynxpoint/hsio/hsio.h> -+#include <types.h> -+ -+const struct hsio_table_row hsio_sata_shared_lpt_h_cx[] = { -+ { 0xea002008, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002208, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002038, ~0x3f00000f, 0x0700000d }, -+ { 0xea002238, ~0x3f00000f, 0x0700000d }, -+ { 0xea00202c, ~0x00020f00, 0x00020100 }, -+ { 0xea00222c, ~0x00020f00, 0x00020100 }, -+ { 0xea002040, ~0x1f000000, 0x01000000 }, -+ { 0xea002240, ~0x1f000000, 0x01000000 }, -+ { 0xea002010, ~0xffff0000, 0x0d510000 }, -+ { 0xea002210, ~0xffff0000, 0x0d510000 }, -+ { 0xea002018, ~0xffff0300, 0x38250100 }, -+ { 0xea002218, ~0xffff0300, 0x38250100 }, -+ { 0xea002000, ~0xcf030000, 0xcf030000 }, -+ { 0xea002200, ~0xcf030000, 0xcf030000 }, -+ { 0xea002028, ~0xff1f0000, 0x580e0000 }, -+ { 0xea002228, ~0xff1f0000, 0x580e0000 }, -+ { 0xea00201c, ~0x00007c00, 0x00002400 }, -+ { 0xea00221c, ~0x00007c00, 0x00002400 }, -+ { 0xea00208c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00228c, ~0x00ff0000, 0x00800000 }, -+ { 0xea0020a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0022a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0020ac, ~0x00000030, 0x00000020 }, -+ { 0xea0022ac, ~0x00000030, 0x00000020 }, -+ { 0xea002140, ~0x00ffffff, 0x00140718 }, -+ { 0xea002340, ~0x00ffffff, 0x00140718 }, -+ { 0xea002144, ~0x00ffffff, 0x00140998 }, -+ { 0xea002344, ~0x00ffffff, 0x00140998 }, -+ { 0xea002148, ~0x00ffffff, 0x00140998 }, -+ { 0xea002348, ~0x00ffffff, 0x00140998 }, -+ { 0xea00217c, ~0x03000000, 0x03000000 }, -+ { 0xea00237c, ~0x03000000, 0x03000000 }, -+ { 0xea002178, ~0x00001f00, 0x00001800 }, -+ { 0xea002378, ~0x00001f00, 0x00001800 }, -+ { 0xea00210c, ~0x0038000f, 0x00000005 }, -+ { 0xea00230c, ~0x0038000f, 0x00000005 }, -+}; -+ -+const struct hsio_table_row hsio_sata_lpt_h_cx[] = { -+ { 0xea008008, ~0xff000000, 0x1c000000 }, -+ { 0xea002408, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002608, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea000808, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea000a08, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002438, ~0x3f00000f, 0x0700000d }, -+ { 0xea002638, ~0x3f00000f, 0x0700000d }, -+ { 0xea000838, ~0x3f00000f, 0x0700000d }, -+ { 0xea000a38, ~0x3f00000f, 0x0700000d }, -+ { 0xea002440, ~0x1f000000, 0x01000000 }, -+ { 0xea002640, ~0x1f000000, 0x01000000 }, -+ { 0xea000840, ~0x1f000000, 0x01000000 }, -+ { 0xea000a40, ~0x1f000000, 0x01000000 }, -+ { 0xea002410, ~0xffff0000, 0x0d510000 }, -+ { 0xea002610, ~0xffff0000, 0x0d510000 }, -+ { 0xea000810, ~0xffff0000, 0x0d510000 }, -+ { 0xea000a10, ~0xffff0000, 0x0d510000 }, -+ { 0xea00242c, ~0x00020800, 0x00020000 }, -+ { 0xea00262c, ~0x00020800, 0x00020000 }, -+ { 0xea00082c, ~0x00020800, 0x00020000 }, -+ { 0xea000a2c, ~0x00020800, 0x00020000 }, -+ { 0xea002418, ~0xffff0300, 0x38250100 }, -+ { 0xea002618, ~0xffff0300, 0x38250100 }, -+ { 0xea000818, ~0xffff0300, 0x38250100 }, -+ { 0xea000a18, ~0xffff0300, 0x38250100 }, -+ { 0xea002400, ~0xcf030000, 0xcf030000 }, -+ { 0xea002600, ~0xcf030000, 0xcf030000 }, -+ { 0xea000800, ~0xcf030000, 0xcf030000 }, -+ { 0xea000a00, ~0xcf030000, 0xcf030000 }, -+ { 0xea002428, ~0xff1f0000, 0x580e0000 }, -+ { 0xea002628, ~0xff1f0000, 0x580e0000 }, -+ { 0xea000828, ~0xff1f0000, 0x580e0000 }, -+ { 0xea000a28, ~0xff1f0000, 0x580e0000 }, -+ { 0xea00241c, ~0x00007c00, 0x00002400 }, -+ { 0xea00261c, ~0x00007c00, 0x00002400 }, -+ { 0xea00081c, ~0x00007c00, 0x00002400 }, -+ { 0xea000a1c, ~0x00007c00, 0x00002400 }, -+ { 0xea00248c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00268c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00088c, ~0x00ff0000, 0x00800000 }, -+ { 0xea000a8c, ~0x00ff0000, 0x00800000 }, -+ { 0xea0024a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0026a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0008a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea000aa4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0024ac, ~0x00000030, 0x00000020 }, -+ { 0xea0026ac, ~0x00000030, 0x00000020 }, -+ { 0xea0008ac, ~0x00000030, 0x00000020 }, -+ { 0xea000aac, ~0x00000030, 0x00000020 }, -+ { 0xea002540, ~0x00ffffff, 0x00140718 }, -+ { 0xea002740, ~0x00ffffff, 0x00140718 }, -+ { 0xea000940, ~0x00ffffff, 0x00140718 }, -+ { 0xea000b40, ~0x00ffffff, 0x00140718 }, -+ { 0xea002544, ~0x00ffffff, 0x00140998 }, -+ { 0xea002744, ~0x00ffffff, 0x00140998 }, -+ { 0xea000944, ~0x00ffffff, 0x00140998 }, -+ { 0xea000b44, ~0x00ffffff, 0x00140998 }, -+ { 0xea002548, ~0x00ffffff, 0x00140998 }, -+ { 0xea002748, ~0x00ffffff, 0x00140998 }, -+ { 0xea000948, ~0x00ffffff, 0x00140998 }, -+ { 0xea000b48, ~0x00ffffff, 0x00140998 }, -+ { 0xea00257c, ~0x03000000, 0x03000000 }, -+ { 0xea00277c, ~0x03000000, 0x03000000 }, -+ { 0xea00097c, ~0x03000000, 0x03000000 }, -+ { 0xea000b7c, ~0x03000000, 0x03000000 }, -+ { 0xea002578, ~0x00001f00, 0x00001800 }, -+ { 0xea002778, ~0x00001f00, 0x00001800 }, -+ { 0xea000978, ~0x00001f00, 0x00001800 }, -+ { 0xea000b78, ~0x00001f00, 0x00001800 }, -+ { 0xea00250c, ~0x0038000f, 0x00000005 }, -+ { 0xea00270c, ~0x0038000f, 0x00000005 }, -+ { 0xea00090c, ~0x0038000f, 0x00000005 }, -+ { 0xea000b0c, ~0x0038000f, 0x00000005 }, -+}; -+ -+const struct hsio_table_row hsio_xhci_shared_lpt_h_cx[] = { -+ { 0xe9002c2c, ~0x00000700, 0x00000100 }, -+ { 0xe9002e2c, ~0x00000700, 0x00000100 }, -+ { 0xe9002dcc, ~0x00001407, 0x00001407 }, -+ { 0xe9002fcc, ~0x00001407, 0x00001407 }, -+ { 0xe9002d68, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9002f68, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9002d6c, ~0x000000ff, 0x0000003f }, -+ { 0xe9002f6c, ~0x000000ff, 0x0000003f }, -+ { 0xe9002d4c, ~0x00ffff00, 0x00120500 }, -+ { 0xe9002f4c, ~0x00ffff00, 0x00120500 }, -+ { 0xe9002d14, ~0x38000700, 0x00000100 }, -+ { 0xe9002f14, ~0x38000700, 0x00000100 }, -+ { 0xe9002d64, ~0x0000f000, 0x00005000 }, -+ { 0xe9002f64, ~0x0000f000, 0x00005000 }, -+ { 0xe9002d70, ~0x00000018, 0x00000000 }, -+ { 0xe9002f70, ~0x00000018, 0x00000000 }, -+ { 0xe9002c38, ~0x3f00000f, 0x0700000b }, -+ { 0xe9002e38, ~0x3f00000f, 0x0700000b }, -+ { 0xe9002d40, ~0x00800000, 0x00000000 }, -+ { 0xe9002f40, ~0x00800000, 0x00000000 }, -+}; -+ -+const struct hsio_table_row hsio_xhci_lpt_h_cx[] = { -+ { 0xe90031cc, ~0x00001407, 0x00001407 }, -+ { 0xe90033cc, ~0x00001407, 0x00001407 }, -+ { 0xe90015cc, ~0x00001407, 0x00001407 }, -+ { 0xe90017cc, ~0x00001407, 0x00001407 }, -+ { 0xe9003168, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9003368, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9001568, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9001768, ~0x01000f3c, 0x00000a28 }, -+ { 0xe900316c, ~0x000000ff, 0x0000003f }, -+ { 0xe900336c, ~0x000000ff, 0x0000003f }, -+ { 0xe900156c, ~0x000000ff, 0x0000003f }, -+ { 0xe900176c, ~0x000000ff, 0x0000003f }, -+ { 0xe900314c, ~0x00ffff00, 0x00120500 }, -+ { 0xe900334c, ~0x00ffff00, 0x00120500 }, -+ { 0xe900154c, ~0x00ffff00, 0x00120500 }, -+ { 0xe900174c, ~0x00ffff00, 0x00120500 }, -+ { 0xe9003114, ~0x38000700, 0x00000100 }, -+ { 0xe9003314, ~0x38000700, 0x00000100 }, -+ { 0xe9001514, ~0x38000700, 0x00000100 }, -+ { 0xe9001714, ~0x38000700, 0x00000100 }, -+ { 0xe9003164, ~0x0000f000, 0x00005000 }, -+ { 0xe9003364, ~0x0000f000, 0x00005000 }, -+ { 0xe9001564, ~0x0000f000, 0x00005000 }, -+ { 0xe9001764, ~0x0000f000, 0x00005000 }, -+ { 0xe9003170, ~0x00000018, 0x00000000 }, -+ { 0xe9003370, ~0x00000018, 0x00000000 }, -+ { 0xe9001570, ~0x00000018, 0x00000000 }, -+ { 0xe9001770, ~0x00000018, 0x00000000 }, -+ { 0xe9003038, ~0x3f00000f, 0x0700000b }, -+ { 0xe9003238, ~0x3f00000f, 0x0700000b }, -+ { 0xe9001438, ~0x3f00000f, 0x0700000b }, -+ { 0xe9001638, ~0x3f00000f, 0x0700000b }, -+ { 0xe9003140, ~0x00800000, 0x00000000 }, -+ { 0xe9003340, ~0x00800000, 0x00000000 }, -+ { 0xe9001540, ~0x00800000, 0x00000000 }, -+ { 0xe9001740, ~0x00800000, 0x00000000 }, -+}; -+ -+void program_hsio_sata_lpt_h_cx(const bool is_mobile) -+{ -+ const struct hsio_table_row *pch_hsio_table; -+ size_t len; -+ -+ pch_hsio_table = hsio_sata_lpt_h_cx; -+ len = ARRAY_SIZE(hsio_sata_lpt_h_cx); -+ for (size_t i = 0; i < len; i++) -+ hsio_update_row(pch_hsio_table[i]); -+ -+ pch_hsio_table = hsio_sata_shared_lpt_h_cx; -+ len = ARRAY_SIZE(hsio_sata_shared_lpt_h_cx); -+ for (size_t i = 0; i < len; i++) -+ hsio_sata_shared_update_row(pch_hsio_table[i]); -+ -+ const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67; -+ -+ hsio_update(0xea002490, ~0x0000ffff, hsio_sata_value); -+ hsio_update(0xea002690, ~0x0000ffff, hsio_sata_value); -+ hsio_update(0xea000890, ~0x0000ffff, hsio_sata_value); -+ hsio_update(0xea000a90, ~0x0000ffff, hsio_sata_value); -+ -+ hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value); -+ hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value); -+} -+ -+void program_hsio_xhci_lpt_h_cx(void) -+{ -+ const struct hsio_table_row *pch_hsio_table; -+ size_t len; -+ -+ pch_hsio_table = hsio_xhci_lpt_h_cx; -+ len = ARRAY_SIZE(hsio_xhci_lpt_h_cx); -+ -+ for (size_t i = 0; i < len; i++) -+ hsio_update_row(pch_hsio_table[i]); -+ -+ pch_hsio_table = hsio_xhci_shared_lpt_h_cx; -+ len = ARRAY_SIZE(hsio_xhci_shared_lpt_h_cx); -+ -+ for (size_t i = 0; i < len; i++) -+ hsio_xhci_shared_update_row(pch_hsio_table[i]); -+} -+ -+void program_hsio_igbe_lpt_h_cx(void) -+{ -+ const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc); -+ if (!(strpfusecfg1 & (1 << 19))) -+ return; -+ -+ const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7; -+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410); -+ if (gbe_port == 0 && ((lane_owner >> 0) & 3) != 1) -+ return; -+ -+ if (gbe_port == 1 && ((lane_owner >> 2) & 3) != 1) -+ return; -+ -+ const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x2e - 2 * gbe_port) << 8; -+ hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100); -+} -diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c -new file mode 100644 -index 0000000000..24679e791a ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c -@@ -0,0 +1,180 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <device/pci_ops.h> -+#include <southbridge/intel/lynxpoint/iobp.h> -+#include <southbridge/intel/lynxpoint/hsio/hsio.h> -+#include <types.h> -+ -+const struct hsio_table_row hsio_sata_shared_lpt_lp_bx[] = { -+ { 0xea008008, ~0xff000000, 0x1c000000 }, -+ { 0xea002008, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002208, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002408, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002608, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002038, ~0x0000000f, 0x0000000d }, -+ { 0xea002238, ~0x0000000f, 0x0000000d }, -+ { 0xea002438, ~0x0000000f, 0x0000000d }, -+ { 0xea002638, ~0x0000000f, 0x0000000d }, -+ { 0xea00202c, ~0x00020f00, 0x00020100 }, -+ { 0xea00222c, ~0x00020f00, 0x00020100 }, -+ { 0xea00242c, ~0x00020f00, 0x00020100 }, -+ { 0xea00262c, ~0x00020f00, 0x00020100 }, -+ { 0xea002040, ~0x1f000000, 0x01000000 }, -+ { 0xea002240, ~0x1f000000, 0x01000000 }, -+ { 0xea002440, ~0x1f000000, 0x01000000 }, -+ { 0xea002640, ~0x1f000000, 0x01000000 }, -+ { 0xea002010, ~0xffff0000, 0x55510000 }, -+ { 0xea002210, ~0xffff0000, 0x55510000 }, -+ { 0xea002410, ~0xffff0000, 0x55510000 }, -+ { 0xea002610, ~0xffff0000, 0x55510000 }, -+ { 0xea002140, ~0x00ffffff, 0x00140718 }, -+ { 0xea002340, ~0x00ffffff, 0x00140718 }, -+ { 0xea002540, ~0x00ffffff, 0x00140718 }, -+ { 0xea002740, ~0x00ffffff, 0x00140718 }, -+ { 0xea002144, ~0x00ffffff, 0x00140998 }, -+ { 0xea002344, ~0x00ffffff, 0x00140998 }, -+ { 0xea002544, ~0x00ffffff, 0x00140998 }, -+ { 0xea002744, ~0x00ffffff, 0x00140998 }, -+ { 0xea002148, ~0x00ffffff, 0x00140998 }, -+ { 0xea002348, ~0x00ffffff, 0x00140998 }, -+ { 0xea002548, ~0x00ffffff, 0x00140998 }, -+ { 0xea002748, ~0x00ffffff, 0x00140998 }, -+ { 0xea00217c, ~0x03000000, 0x03000000 }, -+ { 0xea00237c, ~0x03000000, 0x03000000 }, -+ { 0xea00257c, ~0x03000000, 0x03000000 }, -+ { 0xea00277c, ~0x03000000, 0x03000000 }, -+ { 0xea00208c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00228c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00248c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00268c, ~0x00ff0000, 0x00800000 }, -+ { 0xea0020a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0022a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0024a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0026a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0020ac, ~0x00000030, 0x00000020 }, -+ { 0xea0022ac, ~0x00000030, 0x00000020 }, -+ { 0xea0024ac, ~0x00000030, 0x00000020 }, -+ { 0xea0026ac, ~0x00000030, 0x00000020 }, -+ { 0xea002018, ~0xffff0300, 0x38250100 }, -+ { 0xea002218, ~0xffff0300, 0x38250100 }, -+ { 0xea002418, ~0xffff0300, 0x38250100 }, -+ { 0xea002618, ~0xffff0300, 0x38250100 }, -+ { 0xea002000, ~0xcf030000, 0xcf030000 }, -+ { 0xea002200, ~0xcf030000, 0xcf030000 }, -+ { 0xea002400, ~0xcf030000, 0xcf030000 }, -+ { 0xea002600, ~0xcf030000, 0xcf030000 }, -+ { 0xea002028, ~0xff1f0000, 0x580e0000 }, -+ { 0xea002228, ~0xff1f0000, 0x580e0000 }, -+ { 0xea002428, ~0xff1f0000, 0x580e0000 }, -+ { 0xea002628, ~0xff1f0000, 0x580e0000 }, -+ { 0xea00201c, ~0x00007c00, 0x00002400 }, -+ { 0xea00221c, ~0x00007c00, 0x00002400 }, -+ { 0xea00241c, ~0x00007c00, 0x00002400 }, -+ { 0xea00261c, ~0x00007c00, 0x00002400 }, -+ { 0xea002178, ~0x00001f00, 0x00001800 }, -+ { 0xea002378, ~0x00001f00, 0x00001800 }, -+ { 0xea002578, ~0x00001f00, 0x00001800 }, -+ { 0xea002778, ~0x00001f00, 0x00001800 }, -+ { 0xea00210c, ~0x0038000f, 0x00000005 }, -+ { 0xea00230c, ~0x0038000f, 0x00000005 }, -+ { 0xea00250c, ~0x0038000f, 0x00000005 }, -+ { 0xea00270c, ~0x0038000f, 0x00000005 }, -+}; -+ -+const struct hsio_table_row hsio_xhci_shared_lpt_lp_bx[] = { -+ { 0xe90025cc, ~0x00001407, 0x00001407 }, -+ { 0xe90027cc, ~0x00001407, 0x00001407 }, -+ { 0xe9002568, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9002768, ~0x01000f3c, 0x00000a28 }, -+ { 0xe900242c, ~0x00000700, 0x00000100 }, -+ { 0xe900262c, ~0x00000700, 0x00000100 }, -+ { 0xe900256c, ~0x000000ff, 0x0000003f }, -+ { 0xe900276c, ~0x000000ff, 0x0000003f }, -+ { 0xe900254c, ~0x00ffff00, 0x00120500 }, -+ { 0xe900274c, ~0x00ffff00, 0x00120500 }, -+ { 0xe9002564, ~0x0000f000, 0x00005000 }, -+ { 0xe9002764, ~0x0000f000, 0x00005000 }, -+ { 0xe9002570, ~0x00000018, 0x00000000 }, -+ { 0xe9002770, ~0x00000018, 0x00000000 }, -+ { 0xe9002514, ~0x38000700, 0x00000100 }, -+ { 0xe9002714, ~0x38000700, 0x00000100 }, -+ { 0xe9002438, ~0x0000000f, 0x0000000b }, -+ { 0xe9002638, ~0x0000000f, 0x0000000b }, -+ { 0xe9002414, ~0x0000fe00, 0x00006600 }, -+ { 0xe9002614, ~0x0000fe00, 0x00006600 }, -+ { 0xe9002540, ~0x00800000, 0x00000000 }, -+ { 0xe9002740, ~0x00800000, 0x00000000 }, -+}; -+ -+const struct hsio_table_row hsio_xhci_lpt_lp_bx[] = { -+ { 0xe90021cc, ~0x00001407, 0x00001407 }, -+ { 0xe90023cc, ~0x00001407, 0x00001407 }, -+ { 0xe9002168, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9002368, ~0x01000f3c, 0x00000a28 }, -+ { 0xe900216c, ~0x000000ff, 0x0000003f }, -+ { 0xe900236c, ~0x000000ff, 0x0000003f }, -+ { 0xe900214c, ~0x00ffff00, 0x00120500 }, -+ { 0xe900234c, ~0x00ffff00, 0x00120500 }, -+ { 0xe9002164, ~0x0000f000, 0x00005000 }, -+ { 0xe9002364, ~0x0000f000, 0x00005000 }, -+ { 0xe9002170, ~0x00000018, 0x00000000 }, -+ { 0xe9002370, ~0x00000018, 0x00000000 }, -+ { 0xe9002114, ~0x38000700, 0x00000100 }, -+ { 0xe9002314, ~0x38000700, 0x00000100 }, -+ { 0xe9002038, ~0x0000000f, 0x0000000b }, -+ { 0xe9002238, ~0x0000000f, 0x0000000b }, -+ { 0xe9002014, ~0x0000fe00, 0x00006600 }, -+ { 0xe9002214, ~0x0000fe00, 0x00006600 }, -+ { 0xe9002140, ~0x00800000, 0x00000000 }, -+ { 0xe9002340, ~0x00800000, 0x00000000 }, -+}; -+ -+void program_hsio_sata_lpt_lp_bx(const bool is_mobile) -+{ -+ const struct hsio_table_row *pch_hsio_table; -+ size_t len; -+ -+ pch_hsio_table = hsio_sata_shared_lpt_lp_bx; -+ len = ARRAY_SIZE(hsio_sata_shared_lpt_lp_bx); -+ for (size_t i = 0; i < len; i++) -+ hsio_sata_shared_update_row(pch_hsio_table[i]); -+ -+ const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67; -+ -+ hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value); -+ hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value); -+ hsio_sata_shared_update(0xea002490, ~0x0000ffff, hsio_sata_value); -+ hsio_sata_shared_update(0xea002690, ~0x0000ffff, hsio_sata_value); -+} -+ -+void program_hsio_xhci_lpt_lp_bx(void) -+{ -+ const struct hsio_table_row *pch_hsio_table; -+ size_t len; -+ -+ pch_hsio_table = hsio_xhci_lpt_lp_bx; -+ len = ARRAY_SIZE(hsio_xhci_lpt_lp_bx); -+ -+ for (size_t i = 0; i < len; i++) -+ hsio_update_row(pch_hsio_table[i]); -+ -+ pch_hsio_table = hsio_xhci_shared_lpt_lp_bx; -+ len = ARRAY_SIZE(hsio_xhci_shared_lpt_lp_bx); -+ -+ for (size_t i = 0; i < len; i++) -+ hsio_xhci_shared_update_row(pch_hsio_table[i]); -+} -+ -+void program_hsio_igbe_lpt_lp_bx(void) -+{ -+ const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc); -+ if (!(strpfusecfg1 & (1 << 19))) -+ return; -+ -+ const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7; -+ if (gbe_port > 5) -+ return; -+ -+ const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x08 + 2 * gbe_port) << 8; -+ hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100); -+} -diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h -index 38a9349220..74b4d50017 100644 ---- a/src/southbridge/intel/lynxpoint/pch.h -+++ b/src/southbridge/intel/lynxpoint/pch.h -@@ -117,6 +117,7 @@ void pch_dmi_setup_physical_layer(void); - void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); - void early_usb_init(void); - void early_thermal_init(void); -+void early_pch_init_native(int s3resume); - - void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); - void usb_ehci_disable(pci_devfn_t dev); -@@ -271,6 +272,10 @@ void mainboard_config_rcba(void); - #define IDE_DECODE_ENABLE (1 << 15) - #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ - -+#define SATA_MAP 0x90 -+#define SATA_PCS 0x92 -+#define SATA_SCLKG 0x94 -+ - #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ - #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ - #define SATA_SP 0xd0 /* Scratchpad */ -@@ -580,6 +585,7 @@ void mainboard_config_rcba(void); - #define D19IR 0x3168 /* 16bit */ - #define ACPIIRQEN 0x31e0 /* 32bit */ - #define OIC 0x31fe /* 16bit */ -+#define PRSTS 0x3310 /* 32bit */ - #define PMSYNC_CONFIG 0x33c4 /* 32bit */ - #define PMSYNC_CONFIG2 0x33cc /* 32bit */ - #define SOFT_RESET_CTRL 0x38f4 --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0018-haswell-NRI-Add-REUT-I-O-test-library.patch b/config/coreboot/haswell/patches/0008-haswell-NRI-Add-REUT-I-O-test-library.patch index 5df22ed3..2225f18c 100644 --- a/config/coreboot/haswell/patches/0018-haswell-NRI-Add-REUT-I-O-test-library.patch +++ b/config/coreboot/haswell/patches/0008-haswell-NRI-Add-REUT-I-O-test-library.patch @@ -1,25 +1,25 @@ -From f4dd460d609276de7cb7db91f145a404451a2301 Mon Sep 17 00:00:00 2001 +From 49a7ef2401922a8492ba577a43235bcfba7ea822 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 00:11:29 +0200 -Subject: [PATCH 18/26] haswell NRI: Add REUT I/O test library +Subject: [PATCH 08/20] haswell NRI: Add REUT I/O test library Implement a library to run I/O tests using the REUT hardware. Change-Id: Id7b207cd0a3989ddd23c88c6b1f0cfa79d2c861f Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/raminit_native.h | 110 +++ .../haswell/native_raminit/reg_structs.h | 121 +++ - .../intel/haswell/native_raminit/testing_io.c | 742 ++++++++++++++++++ + .../intel/haswell/native_raminit/testing_io.c | 744 ++++++++++++++++++ .../intel/haswell/registers/mchbar.h | 30 + - 5 files changed, 1004 insertions(+) + 5 files changed, 1006 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/testing_io.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 8d7d4e4db0..6e1b365602 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -12,4 +12,5 @@ romstage-y += raminit_native.c romstage-y += reut.c romstage-y += setup_wdb.c @@ -27,7 +27,7 @@ index 8d7d4e4db0..6e1b365602 100644 +romstage-y += testing_io.c romstage-y += timings_refresh.c diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index f29c2ec366..56df36ca8d 100644 +index 1971b44b66..7f19fde4cc 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -58,6 +58,88 @@ enum { @@ -120,9 +120,9 @@ index f29c2ec366..56df36ca8d 100644 CT_ITERATION_CLOCK = 0, CT_ITERATION_CMD_NORTH, @@ -199,6 +281,10 @@ struct sysinfo { - uint16_t mr1[NUM_CHANNELS][NUM_SLOTRANKS]; - uint16_t mr2[NUM_CHANNELS][NUM_SLOTRANKS]; - uint16_t mr3[NUM_CHANNELS][NUM_SLOTRANKS]; + uint16_t mr1[NUM_CHANNELS][NUM_SLOTS]; + uint16_t mr2[NUM_CHANNELS][NUM_SLOTS]; + uint16_t mr3[NUM_CHANNELS][NUM_SLOTS]; + + uint8_t dq_pat; + @@ -130,7 +130,7 @@ index f29c2ec366..56df36ca8d 100644 }; static inline bool is_hsw_ult(void) -@@ -342,6 +428,30 @@ void write_wdb_va_pat( +@@ -340,6 +426,30 @@ void write_wdb_va_pat( void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup); void setup_wdb(const struct sysinfo *ctrl); @@ -309,10 +309,10 @@ index 7aa8d8c8b2..b943259b91 100644 uint32_t start_test : 1; // Bits 0:0 diff --git a/src/northbridge/intel/haswell/native_raminit/testing_io.c b/src/northbridge/intel/haswell/native_raminit/testing_io.c new file mode 100644 -index 0000000000..7716fc4285 +index 0000000000..2632c238f8 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/testing_io.c -@@ -0,0 +1,742 @@ +@@ -0,0 +1,744 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> @@ -535,8 +535,10 @@ index 0000000000..7716fc4285 + const uint8_t en_cadb, + const uint8_t subseq_wait) +{ -+ if (!chanmask) -+ die("\n%s: invalid chanmask\n", __func__, chanmask); ++ if (!chanmask) { ++ printk(BIOS_ERR, "\n%s: chanmask is invalid\n", __func__); ++ return; ++ } + + /* + * Prepare variables needed for both channels. diff --git a/config/coreboot/haswell/patches/0008-nb-intel-haswell-Add-native-raminit-scaffolding.patch b/config/coreboot/haswell/patches/0008-nb-intel-haswell-Add-native-raminit-scaffolding.patch deleted file mode 100644 index 6df828eb..00000000 --- a/config/coreboot/haswell/patches/0008-nb-intel-haswell-Add-native-raminit-scaffolding.patch +++ /dev/null @@ -1,407 +0,0 @@ -From 46cdec8cbce15ca11ad9a49a3ee415a78f781997 Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Sat, 7 May 2022 00:26:10 +0200 -Subject: [PATCH 08/26] nb/intel/haswell: Add native raminit scaffolding - -Implement some scaffolding for Haswell native raminit, like bootmode -selection, handling of MRC cache and CPU detection. - -Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - .../intel/haswell/native_raminit/Makefile.inc | 1 + - .../haswell/native_raminit/raminit_main.c | 104 ++++++++++ - .../haswell/native_raminit/raminit_native.c | 189 +++++++++++++++++- - .../haswell/native_raminit/raminit_native.h | 34 ++++ - 4 files changed, 322 insertions(+), 6 deletions(-) - create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_main.c - create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.h - -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -index 8cfb4fb33e..90af951c5a 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -@@ -1,3 +1,4 @@ - ## SPDX-License-Identifier: GPL-2.0-or-later - -+romstage-y += raminit_main.c - romstage-y += raminit_native.c -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -new file mode 100644 -index 0000000000..9b42c25b40 ---- /dev/null -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -0,0 +1,104 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <assert.h> -+#include <console/console.h> -+#include <cpu/intel/haswell/haswell.h> -+#include <delay.h> -+#include <device/pci_ops.h> -+#include <northbridge/intel/haswell/chip.h> -+#include <northbridge/intel/haswell/haswell.h> -+#include <northbridge/intel/haswell/raminit.h> -+#include <string.h> -+#include <types.h> -+ -+#include "raminit_native.h" -+ -+struct task_entry { -+ enum raminit_status (*task)(struct sysinfo *); -+ bool is_enabled; -+ const char *name; -+}; -+ -+static const struct task_entry cold_boot[] = { -+}; -+ -+/* Return a generic stepping value to make stepping checks simpler */ -+static enum generic_stepping get_stepping(const uint32_t cpuid) -+{ -+ switch (cpuid) { -+ case CPUID_HASWELL_A0: -+ die("Haswell stepping A0 is not supported\n"); -+ case CPUID_HASWELL_B0: -+ case CPUID_HASWELL_ULT_B0: -+ case CPUID_CRYSTALWELL_B0: -+ return STEPPING_B0; -+ case CPUID_HASWELL_C0: -+ case CPUID_HASWELL_ULT_C0: -+ case CPUID_CRYSTALWELL_C0: -+ return STEPPING_C0; -+ default: -+ /** TODO: Add Broadwell support someday **/ -+ die("Unknown CPUID 0x%x\n", cpuid); -+ } -+} -+ -+static void initialize_ctrl(struct sysinfo *ctrl) -+{ -+ const struct northbridge_intel_haswell_config *cfg = config_of_soc(); -+ const enum raminit_boot_mode bootmode = ctrl->bootmode; -+ -+ memset(ctrl, 0, sizeof(*ctrl)); -+ -+ ctrl->cpu = cpu_get_cpuid(); -+ ctrl->stepping = get_stepping(ctrl->cpu); -+ ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved; -+ ctrl->bootmode = bootmode; -+} -+ -+static enum raminit_status try_raminit(struct sysinfo *ctrl) -+{ -+ const struct task_entry *const schedule = cold_boot; -+ const size_t length = ARRAY_SIZE(cold_boot); -+ -+ enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR; -+ -+ for (size_t i = 0; i < length; i++) { -+ const struct task_entry *const entry = &schedule[i]; -+ assert(entry); -+ assert(entry->name); -+ if (!entry->is_enabled) -+ continue; -+ -+ assert(entry->task); -+ printk(RAM_DEBUG, "\nExecuting raminit task %s\n", entry->name); -+ status = entry->task(ctrl); -+ printk(RAM_DEBUG, "\n"); -+ if (status) { -+ printk(BIOS_ERR, "raminit failed on step %s\n", entry->name); -+ break; -+ } -+ } -+ -+ return status; -+} -+ -+void raminit_main(const enum raminit_boot_mode bootmode) -+{ -+ /* -+ * The mighty_ctrl struct. Will happily nuke the pre-RAM stack -+ * if left unattended. Make it static and pass pointers to it. -+ */ -+ static struct sysinfo mighty_ctrl; -+ -+ mighty_ctrl.bootmode = bootmode; -+ initialize_ctrl(&mighty_ctrl); -+ -+ /** TODO: Try more than once **/ -+ enum raminit_status status = try_raminit(&mighty_ctrl); -+ -+ if (status != RAMINIT_STATUS_SUCCESS) -+ die("Memory initialization was met with utmost failure and misery\n"); -+ -+ /** TODO: Implement the required magic **/ -+ die("NATIVE RAMINIT: More Magic (tm) required.\n"); -+} -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index b6efb6b40d..0869db3902 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -1,13 +1,45 @@ - /* SPDX-License-Identifier: GPL-2.0-or-later */ - -+#include <arch/cpu.h> -+#include <assert.h> -+#include <cbmem.h> -+#include <cf9_reset.h> - #include <console/console.h> -+#include <cpu/x86/msr.h> - #include <delay.h> -+#include <device/pci_ops.h> -+#include <mrc_cache.h> - #include <northbridge/intel/haswell/haswell.h> - #include <northbridge/intel/haswell/raminit.h> - #include <southbridge/intel/lynxpoint/me.h> - #include <southbridge/intel/lynxpoint/pch.h> - #include <types.h> - -+#include "raminit_native.h" -+ -+static void wait_txt_clear(void) -+{ -+ const struct cpuid_result cpuid = cpuid_ext(1, 0); -+ -+ /* Check if TXT is supported */ -+ if (!(cpuid.ecx & BIT(6))) -+ return; -+ -+ /* Some TXT public bit */ -+ if (!(read32p(0xfed30010) & 1)) -+ return; -+ -+ /* Wait for TXT clear */ -+ do {} while (!(read8p(0xfed40000) & (1 << 7))); -+} -+ -+static enum raminit_boot_mode get_boot_mode(void) -+{ -+ const uint16_t pmcon_2 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2); -+ const uint16_t bitmask = GEN_PMCON_2_DISB | GEN_PMCON_2_MEM_SR; -+ return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD; -+} -+ - static bool early_init_native(int s3resume) - { - printk(BIOS_DEBUG, "Starting native platform initialisation\n"); -@@ -24,6 +56,120 @@ static bool early_init_native(int s3resume) - return cpu_replaced; - } - -+#define MRC_CACHE_VERSION 1 -+ -+struct mrc_data { -+ const void *buffer; -+ size_t buffer_len; -+}; -+ -+static void save_mrc_data(struct mrc_data *md) -+{ -+ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len); -+} -+ -+static struct mrc_data prepare_mrc_cache(void) -+{ -+ struct mrc_data md = {0}; -+ md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, -+ MRC_CACHE_VERSION, -+ &md.buffer_len); -+ return md; -+} -+ -+static const char *const bm_names[] = { -+ "BOOTMODE_COLD", -+ "BOOTMODE_WARM", -+ "BOOTMODE_S3", -+ "BOOTMODE_FAST", -+}; -+ -+static void clear_disb(void) -+{ -+ pci_and_config16(PCH_LPC_DEV, GEN_PMCON_2, ~GEN_PMCON_2_DISB); -+} -+ -+static void raminit_reset(void) -+{ -+ clear_disb(); -+ system_reset(); -+} -+ -+static enum raminit_boot_mode do_actual_raminit( -+ struct mrc_data *md, -+ const bool s3resume, -+ const bool cpu_replaced, -+ const enum raminit_boot_mode orig_bootmode) -+{ -+ enum raminit_boot_mode bootmode = orig_bootmode; -+ -+ bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/ -+ -+ if (s3resume) { -+ if (bootmode == BOOTMODE_COLD) { -+ printk(BIOS_EMERG, "Memory may not be in self-refresh for S3 resume\n"); -+ printk(BIOS_EMERG, "S3 resume and cold boot are mutually exclusive\n"); -+ raminit_reset(); -+ } -+ /* Only a true mad hatter would replace a CPU in S3 */ -+ if (cpu_replaced) { -+ printk(BIOS_EMERG, "Oh no, CPU was replaced during S3\n"); -+ /* -+ * No reason to continue, memory consistency is most likely lost -+ * and ME will probably request a reset through DID response too. -+ */ -+ /** TODO: Figure out why past self commented this out **/ -+ //raminit_reset(); -+ } -+ bootmode = BOOTMODE_S3; -+ if (!save_data_valid) { -+ printk(BIOS_EMERG, "No training data, S3 resume is impossible\n"); -+ /* Failed S3 resume, reset to come up cleanly */ -+ raminit_reset(); -+ } -+ } -+ if (!s3resume && cpu_replaced) { -+ printk(BIOS_NOTICE, "CPU was replaced, forcing a cold boot\n"); -+ /* -+ * Looks like the ME will get angry if raminit takes too long. -+ * It will report that the CPU has been replaced on next boot. -+ * Try to continue anyway. This should not happen in most cases. -+ */ -+ /** TODO: Figure out why past self commented this out **/ -+ //save_data_valid = false; -+ } -+ if (bootmode == BOOTMODE_COLD) { -+ /* If possible, promote to a fast boot */ -+ if (save_data_valid) -+ bootmode = BOOTMODE_FAST; -+ -+ clear_disb(); -+ } else if (bootmode == BOOTMODE_WARM) { -+ /* If a warm reset happened before raminit is done, force a cold boot */ -+ if (mchbar_read32(SSKPD) == 0 && mchbar_read32(SSKPD + 4) == 0) { -+ printk(BIOS_NOTICE, "Warm reset occurred early in cold boot\n"); -+ save_data_valid = false; -+ } -+ if (!save_data_valid) -+ bootmode = BOOTMODE_COLD; -+ } -+ assert(save_data_valid != (bootmode == BOOTMODE_COLD)); -+ if (save_data_valid) { -+ printk(BIOS_INFO, "Using cached memory parameters\n"); -+ die("RAMINIT: Fast boot is not yet implemented\n"); -+ } -+ printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]); -+ printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]); -+ -+ /* -+ * And now, the actual memory initialization thing. -+ */ -+ printk(RAM_DEBUG, "\nStarting native raminit\n"); -+ raminit_main(bootmode); -+ -+ return bootmode; -+} -+ - void perform_raminit(const int s3resume) - { - /* -@@ -32,17 +178,48 @@ void perform_raminit(const int s3resume) - */ - const bool cpu_replaced = early_init_native(s3resume); - -- (void)cpu_replaced; -+ wait_txt_clear(); -+ wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); -+ -+ const enum raminit_boot_mode orig_bootmode = get_boot_mode(); -+ -+ struct mrc_data md = prepare_mrc_cache(); -+ -+ const enum raminit_boot_mode bootmode = -+ do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode); -+ -+ /** TODO: report_memory_config **/ - -- /** TODO: Move after raminit */ - if (intel_early_me_uma_size() > 0) { -- /** TODO: Update status once raminit is implemented **/ -- uint8_t me_status = ME_INIT_STATUS_ERROR; -+ /* -+ * The 'other' success value is to report loss of memory -+ * consistency to ME if warm boot was downgraded to cold. -+ */ -+ uint8_t me_status; -+ if (BOOTMODE_WARM == orig_bootmode && BOOTMODE_COLD == bootmode) -+ me_status = ME_INIT_STATUS_SUCCESS_OTHER; -+ else -+ me_status = ME_INIT_STATUS_SUCCESS; -+ -+ /** TODO: Remove this once raminit is implemented **/ -+ me_status = ME_INIT_STATUS_ERROR; - intel_early_me_init_done(me_status); - } - -+ post_code(0x3b); -+ - intel_early_me_status(); - -- /** TODO: Implement the required magic **/ -- die("NATIVE RAMINIT: More Magic (tm) required.\n"); -+ const bool cbmem_was_initted = !cbmem_recovery(s3resume); -+ if (s3resume && !cbmem_was_initted) { -+ /* Failed S3 resume, reset to come up cleanly */ -+ printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); -+ system_reset(); -+ } -+ -+ /* Save training data on non-S3 resumes */ -+ if (!s3resume) -+ save_mrc_data(&md); -+ -+ /** TODO: setup_sdram_meminfo **/ - } -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -new file mode 100644 -index 0000000000..885f0184f4 ---- /dev/null -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -0,0 +1,34 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#ifndef HASWELL_RAMINIT_NATIVE_H -+#define HASWELL_RAMINIT_NATIVE_H -+ -+enum raminit_boot_mode { -+ BOOTMODE_COLD, -+ BOOTMODE_WARM, -+ BOOTMODE_S3, -+ BOOTMODE_FAST, -+}; -+ -+enum raminit_status { -+ RAMINIT_STATUS_SUCCESS = 0, -+ RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ -+}; -+ -+enum generic_stepping { -+ STEPPING_A0 = 1, -+ STEPPING_B0 = 2, -+ STEPPING_C0 = 3, -+}; -+ -+struct sysinfo { -+ enum raminit_boot_mode bootmode; -+ enum generic_stepping stepping; -+ uint32_t cpu; /* CPUID value */ -+ -+ bool dq_pins_interleaved; -+}; -+ -+void raminit_main(enum raminit_boot_mode bootmode); -+ -+#endif --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0019-haswell-NRI-Add-range-tracking-library.patch b/config/coreboot/haswell/patches/0009-haswell-NRI-Add-range-tracking-library.patch index f433b043..9c3fe1c9 100644 --- a/config/coreboot/haswell/patches/0019-haswell-NRI-Add-range-tracking-library.patch +++ b/config/coreboot/haswell/patches/0009-haswell-NRI-Add-range-tracking-library.patch @@ -1,7 +1,7 @@ -From 9fba0468e75877cbda62f5eaeef1946d6489a8f9 Mon Sep 17 00:00:00 2001 +From 7f5c3f8c6c8960d1c374b9c95821c19f230fa34f Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 00:56:00 +0200 -Subject: [PATCH 19/26] haswell NRI: Add range tracking library +Subject: [PATCH 09/20] haswell NRI: Add range tracking library Implement a small library used to keep track of passing ranges. This will be used by 1D training algorithms when margining some parameter. @@ -9,17 +9,17 @@ will be used by 1D training algorithms when margining some parameter. Change-Id: I8718e85165160afd7c0c8e730b5ce6c9c00f8a60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../intel/haswell/native_raminit/ranges.c | 109 ++++++++++++++++++ .../intel/haswell/native_raminit/ranges.h | 68 +++++++++++ 3 files changed, 178 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.c create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.h -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 6e1b365602..2da950771d 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -9,6 +9,7 @@ romstage-y += io_comp_control.c romstage-y += memory_map.c romstage-y += raminit_main.c diff --git a/config/coreboot/haswell/patches/0009-nb-intel-haswell-nri-Only-do-CPU-replacement-check-o.patch b/config/coreboot/haswell/patches/0009-nb-intel-haswell-nri-Only-do-CPU-replacement-check-o.patch deleted file mode 100644 index 07525d18..00000000 --- a/config/coreboot/haswell/patches/0009-nb-intel-haswell-nri-Only-do-CPU-replacement-check-o.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 731216aef3129ae27ad5adc7266cb8a58090c9fc Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Sun, 26 Jun 2022 10:32:12 +0200 -Subject: [PATCH 09/26] nb/intel/haswell/nri: Only do CPU replacement check on - cold boots - -CPU replacement check should only be done on cold boots. - -Change-Id: I98efa105f4df755b23febe12dd7b356787847852 -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - .../intel/haswell/native_raminit/raminit_native.c | 13 ++++++------- - 1 file changed, 6 insertions(+), 7 deletions(-) - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index 0869db3902..bd9bc8e692 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -40,15 +40,14 @@ static enum raminit_boot_mode get_boot_mode(void) - return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD; - } - --static bool early_init_native(int s3resume) -+static bool early_init_native(enum raminit_boot_mode bootmode) - { - printk(BIOS_DEBUG, "Starting native platform initialisation\n"); - - intel_early_me_init(); -- /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ -- const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); -+ bool cpu_replaced = bootmode == BOOTMODE_COLD && intel_early_me_cpu_replacement_check(); - -- early_pch_init_native(s3resume); -+ early_pch_init_native(bootmode == BOOTMODE_S3); - - if (!CONFIG(INTEL_LYNXPOINT_LP)) - dmi_early_init(); -@@ -176,13 +175,13 @@ void perform_raminit(const int s3resume) - * See, this function's name is a lie. There are more things to - * do that memory initialisation, but they are relatively easy. - */ -- const bool cpu_replaced = early_init_native(s3resume); -+ const enum raminit_boot_mode orig_bootmode = get_boot_mode(); -+ -+ const bool cpu_replaced = early_init_native(s3resume ? BOOTMODE_S3 : orig_bootmode); - - wait_txt_clear(); - wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); - -- const enum raminit_boot_mode orig_bootmode = get_boot_mode(); -- - struct mrc_data md = prepare_mrc_cache(); - - const enum raminit_boot_mode bootmode = --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0020-haswell-NRI-Add-library-to-change-margins.patch b/config/coreboot/haswell/patches/0010-haswell-NRI-Add-library-to-change-margins.patch index 30926494..622fac5a 100644 --- a/config/coreboot/haswell/patches/0020-haswell-NRI-Add-library-to-change-margins.patch +++ b/config/coreboot/haswell/patches/0010-haswell-NRI-Add-library-to-change-margins.patch @@ -1,24 +1,24 @@ -From 54cfbe4cf53d16f747bfcfadd20445a0f5f1e5db Mon Sep 17 00:00:00 2001 +From 8ad18cc335f60a78f47ab9e5a7994f6075b6a176 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 01:11:03 +0200 -Subject: [PATCH 20/26] haswell NRI: Add library to change margins +Subject: [PATCH 10/20] haswell NRI: Add library to change margins Implement a library to change Rx/Tx margins. It will be expanded later. Change-Id: I0b55aba428d8b4d4e16d2fbdec57235ce3ce8adf Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/change_margin.c | 154 ++++++++++++++++++ .../haswell/native_raminit/raminit_native.h | 50 ++++++ .../intel/haswell/registers/mchbar.h | 9 + 4 files changed, 214 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/change_margin.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 2da950771d..ebe9e9b762 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -28,13 +28,13 @@ index 2da950771d..ebe9e9b762 100644 romstage-y += jedec_reset.c diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c new file mode 100644 -index 0000000000..12da59580f +index 0000000000..055c666eee --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + -+#include <commonlib/clamp.h> ++#include <commonlib/bsd/clamp.h> +#include <console/console.h> +#include <delay.h> +#include <northbridge/intel/haswell/haswell.h> @@ -187,7 +187,7 @@ index 0000000000..12da59580f + mchbar_write32(reg, ddr_data_control_0.raw); +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 56df36ca8d..7c1a786780 100644 +index 7f19fde4cc..906b3143b9 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -117,6 +117,30 @@ enum test_stop { @@ -221,7 +221,7 @@ index 56df36ca8d..7c1a786780 100644 struct wdb_pat { uint32_t start_ptr; /* Starting pointer in WDB */ uint32_t stop_ptr; /* Stopping pointer in WDB */ -@@ -452,6 +476,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas +@@ -450,6 +474,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas void run_mpr_io_test(bool clear_errors); uint8_t run_io_test(struct sysinfo *ctrl, uint8_t chanmask, uint8_t dq_pat, bool clear_errors); diff --git a/config/coreboot/haswell/patches/0010-haswell-NRI-Collect-SPD-info.patch b/config/coreboot/haswell/patches/0010-haswell-NRI-Collect-SPD-info.patch deleted file mode 100644 index 4c2a2670..00000000 --- a/config/coreboot/haswell/patches/0010-haswell-NRI-Collect-SPD-info.patch +++ /dev/null @@ -1,344 +0,0 @@ -From 354969af4361bcc7dc240ef5871d169728f7f0cc Mon Sep 17 00:00:00 2001 -From: Angel Pons <th3fanbus@gmail.com> -Date: Sat, 7 May 2022 13:48:53 +0200 -Subject: [PATCH 10/26] haswell NRI: Collect SPD info - -Collect SPD data from DIMMs and memory-down, and find the common -supported settings. - -Change-Id: I4e6a1408a638a463ecae37a447cfed1d6556e44a -Signed-off-by: Angel Pons <th3fanbus@gmail.com> ---- - .../intel/haswell/native_raminit/Makefile.inc | 1 + - .../haswell/native_raminit/raminit_main.c | 1 + - .../haswell/native_raminit/raminit_native.h | 57 +++++ - .../haswell/native_raminit/spd_bitmunching.c | 206 ++++++++++++++++++ - 4 files changed, 265 insertions(+) - create mode 100644 src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c - -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -index 90af951c5a..ebf7abc6ec 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -@@ -2,3 +2,4 @@ - - romstage-y += raminit_main.c - romstage-y += raminit_native.c -+romstage-y += spd_bitmunching.c -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 9b42c25b40..2d2cfa48bb 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -20,6 +20,7 @@ struct task_entry { - }; - - static const struct task_entry cold_boot[] = { -+ { collect_spd_info, true, "PROCSPD", }, - }; - - /* Return a generic stepping value to make stepping checks simpler */ -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 885f0184f4..1a0793947e 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -3,6 +3,15 @@ - #ifndef HASWELL_RAMINIT_NATIVE_H - #define HASWELL_RAMINIT_NATIVE_H - -+#include <device/dram/ddr3.h> -+#include <northbridge/intel/haswell/haswell.h> -+ -+#define SPD_LEN 256 -+ -+/* 8 data lanes + 1 ECC lane */ -+#define NUM_LANES 9 -+#define NUM_LANES_NO_ECC 8 -+ - enum raminit_boot_mode { - BOOTMODE_COLD, - BOOTMODE_WARM, -@@ -12,6 +21,8 @@ enum raminit_boot_mode { - - enum raminit_status { - RAMINIT_STATUS_SUCCESS = 0, -+ RAMINIT_STATUS_NO_MEMORY_INSTALLED, -+ RAMINIT_STATUS_UNSUPPORTED_MEMORY, - RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ - }; - -@@ -21,14 +32,60 @@ enum generic_stepping { - STEPPING_C0 = 3, - }; - -+struct raminit_dimm_info { -+ spd_raw_data raw_spd; -+ struct dimm_attr_ddr3_st data; -+ uint8_t spd_addr; -+ bool valid; -+}; -+ - struct sysinfo { - enum raminit_boot_mode bootmode; - enum generic_stepping stepping; - uint32_t cpu; /* CPUID value */ - - bool dq_pins_interleaved; -+ -+ /** TODO: ECC support untested **/ -+ bool is_ecc; -+ -+ /** -+ * FIXME: LPDDR support is incomplete. The largest chunks are missing, -+ * but some LPDDR-specific variations in algorithms have been handled. -+ * LPDDR-specific functions have stubs which will halt upon execution. -+ */ -+ bool lpddr; -+ -+ struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS]; -+ union dimm_flags_ddr3_st flags; -+ uint16_t cas_supported; -+ -+ /* Except for tCK, everything is eventually stored in DCLKs */ -+ uint32_t tCK; -+ uint32_t tAA; /* Also known as tCL */ -+ uint32_t tWR; -+ uint32_t tRCD; -+ uint32_t tRRD; -+ uint32_t tRP; -+ uint32_t tRAS; -+ uint32_t tRC; -+ uint32_t tRFC; -+ uint32_t tWTR; -+ uint32_t tRTP; -+ uint32_t tFAW; -+ uint32_t tCWL; -+ uint32_t tCMD; -+ -+ uint8_t lanes; /* 8 or 9 */ -+ uint8_t chanmap; -+ uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */ -+ uint8_t rankmap[NUM_CHANNELS]; -+ uint8_t rank_mirrored[NUM_CHANNELS]; -+ uint32_t channel_size_mb[NUM_CHANNELS]; - }; - - void raminit_main(enum raminit_boot_mode bootmode); - -+enum raminit_status collect_spd_info(struct sysinfo *ctrl); -+ - #endif -diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c -new file mode 100644 -index 0000000000..dbe02c72d0 ---- /dev/null -+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c -@@ -0,0 +1,206 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include <cbfs.h> -+#include <commonlib/clamp.h> -+#include <console/console.h> -+#include <device/dram/ddr3.h> -+#include <device/smbus_host.h> -+#include <northbridge/intel/haswell/haswell.h> -+#include <northbridge/intel/haswell/raminit.h> -+#include <string.h> -+#include <types.h> -+ -+#include "raminit_native.h" -+ -+static const uint8_t *get_spd_data_from_cbfs(struct spd_info *spdi) -+{ -+ if (!CONFIG(HAVE_SPD_IN_CBFS)) -+ return NULL; -+ -+ printk(RAM_DEBUG, "SPD index %u\n", spdi->spd_index); -+ -+ size_t spd_file_len; -+ uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len); -+ -+ if (!spd_file) { -+ printk(BIOS_ERR, "SPD data not found in CBFS\n"); -+ return NULL; -+ } -+ -+ if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) { -+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); -+ spdi->spd_index = 0; -+ } -+ -+ if (spd_file_len < SPD_LEN) { -+ printk(BIOS_ERR, "Invalid SPD data in CBFS\n"); -+ return NULL; -+ } -+ -+ return spd_file + (spdi->spd_index * SPD_LEN); -+} -+ -+static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t *cbfs_spd) -+{ -+ if (dimm->spd_addr == SPD_MEMORY_DOWN) { -+ if (cbfs_spd) { -+ memcpy(dimm->raw_spd, cbfs_spd, SPD_LEN); -+ dimm->valid = true; -+ printk(RAM_DEBUG, "memory-down\n"); -+ return; -+ } else { -+ printk(RAM_DEBUG, "memory-down but no CBFS SPD data, ignoring\n"); -+ return; -+ } -+ } -+ printk(RAM_DEBUG, "slotted "); -+ const uint8_t spd_mem_type = smbus_read_byte(dimm->spd_addr, SPD_MEMORY_TYPE); -+ if (spd_mem_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { -+ printk(RAM_DEBUG, "and not DDR3, ignoring\n"); -+ return; -+ } -+ printk(RAM_DEBUG, "and DDR3\n"); -+ if (i2c_eeprom_read(dimm->spd_addr, 0, SPD_LEN, dimm->raw_spd) != SPD_LEN) { -+ printk(BIOS_WARNING, "I2C block read failed, trying SMBus byte reads\n"); -+ for (uint32_t i = 0; i < SPD_LEN; i++) -+ dimm->raw_spd[i] = smbus_read_byte(dimm->spd_addr, i); -+ } -+ dimm->valid = true; -+} -+ -+static void get_spd_data(struct sysinfo *ctrl) -+{ -+ struct spd_info spdi = {0}; -+ mb_get_spd_map(&spdi); -+ const uint8_t *cbfs_spd = get_spd_data_from_cbfs(&spdi); -+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { -+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { -+ struct raminit_dimm_info *const dimm = &ctrl->dimms[channel][slot]; -+ dimm->spd_addr = spdi.addresses[channel + channel + slot]; -+ if (!dimm->spd_addr) -+ continue; -+ -+ printk(RAM_DEBUG, "CH%uS%u is ", channel, slot); -+ get_spd_for_dimm(dimm, cbfs_spd); -+ } -+ } -+} -+ -+static void decode_spd(struct raminit_dimm_info *const dimm) -+{ -+ /** TODO: Hook up somewhere, and handle lack of XMP data **/ -+ const bool enable_xmp = false; -+ memset(&dimm->data, 0, sizeof(dimm->data)); -+ if (enable_xmp) -+ spd_xmp_decode_ddr3(&dimm->data, dimm->raw_spd, DDR3_XMP_PROFILE_1); -+ else -+ spd_decode_ddr3(&dimm->data, dimm->raw_spd); -+ -+ if (CONFIG(DEBUG_RAM_SETUP)) -+ dram_print_spd_ddr3(&dimm->data); -+} -+ -+static enum raminit_status find_common_spd_parameters(struct sysinfo *ctrl) -+{ -+ ctrl->cas_supported = 0xffff; -+ ctrl->flags.raw = 0xffffffff; -+ -+ ctrl->tCK = 0; -+ ctrl->tAA = 0; -+ ctrl->tWR = 0; -+ ctrl->tRCD = 0; -+ ctrl->tRRD = 0; -+ ctrl->tRP = 0; -+ ctrl->tRAS = 0; -+ ctrl->tRC = 0; -+ ctrl->tRFC = 0; -+ ctrl->tWTR = 0; -+ ctrl->tRTP = 0; -+ ctrl->tFAW = 0; -+ ctrl->tCWL = 0; -+ ctrl->tCMD = 0; -+ ctrl->chanmap = 0; -+ -+ bool yes_ecc = false; -+ bool not_ecc = false; -+ -+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { -+ ctrl->dpc[channel] = 0; -+ ctrl->rankmap[channel] = 0; -+ ctrl->rank_mirrored[channel] = 0; -+ ctrl->channel_size_mb[channel] = 0; -+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { -+ struct raminit_dimm_info *const dimm = &ctrl->dimms[channel][slot]; -+ if (!dimm->valid) -+ continue; -+ -+ printk(RAM_DEBUG, "\nCH%uS%u SPD:\n", channel, slot); -+ decode_spd(dimm); -+ -+ ctrl->chanmap |= BIT(channel); -+ ctrl->dpc[channel]++; -+ ctrl->channel_size_mb[channel] += dimm->data.size_mb; -+ -+ /* The first rank of a populated slot is always present */ -+ const uint8_t rank = slot + slot; -+ assert(dimm->data.ranks); -+ ctrl->rankmap[channel] |= (BIT(dimm->data.ranks) - 1) << rank; -+ -+ if (dimm->data.flags.pins_mirrored) -+ ctrl->rank_mirrored[channel] |= BIT(rank + 1); -+ -+ /* Find common settings */ -+ ctrl->cas_supported &= dimm->data.cas_supported; -+ ctrl->flags.raw &= dimm->data.flags.raw; -+ ctrl->tCK = MAX(ctrl->tCK, dimm->data.tCK); -+ ctrl->tAA = MAX(ctrl->tAA, dimm->data.tAA); -+ ctrl->tWR = MAX(ctrl->tWR, dimm->data.tWR); -+ ctrl->tRCD = MAX(ctrl->tRCD, dimm->data.tRCD); -+ ctrl->tRRD = MAX(ctrl->tRRD, dimm->data.tRRD); -+ ctrl->tRP = MAX(ctrl->tRP, dimm->data.tRP); -+ ctrl->tRAS = MAX(ctrl->tRAS, dimm->data.tRAS); -+ ctrl->tRC = MAX(ctrl->tRC, dimm->data.tRC); -+ ctrl->tRFC = MAX(ctrl->tRFC, dimm->data.tRFC); -+ ctrl->tWTR = MAX(ctrl->tWTR, dimm->data.tWTR); -+ ctrl->tRTP = MAX(ctrl->tRTP, dimm->data.tRTP); -+ ctrl->tFAW = MAX(ctrl->tFAW, dimm->data.tFAW); -+ ctrl->tCWL = MAX(ctrl->tCWL, dimm->data.tCWL); -+ ctrl->tCMD = MAX(ctrl->tCMD, dimm->data.tCMD); -+ -+ yes_ecc |= dimm->data.flags.is_ecc; -+ not_ecc |= !dimm->data.flags.is_ecc; -+ } -+ } -+ -+ if (!ctrl->chanmap) { -+ printk(BIOS_ERR, "No DIMMs were found\n"); -+ return RAMINIT_STATUS_NO_MEMORY_INSTALLED; -+ } -+ if (!ctrl->cas_supported) { -+ printk(BIOS_ERR, "Could not resolve common CAS latency\n"); -+ return RAMINIT_STATUS_UNSUPPORTED_MEMORY; -+ } -+ /** TODO: Properly handle ECC support and ECC forced **/ -+ if (yes_ecc && not_ecc) { -+ /** TODO: Test if the ECC DIMMs can be operated as non-ECC DIMMs **/ -+ printk(BIOS_ERR, "Both ECC and non-ECC DIMMs present, this is unsupported\n"); -+ return RAMINIT_STATUS_UNSUPPORTED_MEMORY; -+ } -+ if (yes_ecc) -+ ctrl->lanes = NUM_LANES; -+ else -+ ctrl->lanes = NUM_LANES_NO_ECC; -+ -+ ctrl->is_ecc = yes_ecc; -+ -+ /** TODO: Complete LPDDR support **/ -+ ctrl->lpddr = false; -+ -+ return RAMINIT_STATUS_SUCCESS; -+} -+ -+enum raminit_status collect_spd_info(struct sysinfo *ctrl) -+{ -+ get_spd_data(ctrl); -+ return find_common_spd_parameters(ctrl); -+} --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0021-haswell-NRI-Add-RcvEn-training.patch b/config/coreboot/haswell/patches/0011-haswell-NRI-Add-RcvEn-training.patch index 9139a67e..4815be9a 100644 --- a/config/coreboot/haswell/patches/0021-haswell-NRI-Add-RcvEn-training.patch +++ b/config/coreboot/haswell/patches/0011-haswell-NRI-Add-RcvEn-training.patch @@ -1,14 +1,14 @@ -From ac8843553af34855d0331554c03280e66c4ea582 Mon Sep 17 00:00:00 2001 +From 4254a9ff03658d7a6f1a4e32cfe4c65dbfc072f8 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 00:05:41 +0200 -Subject: [PATCH 21/26] haswell NRI: Add RcvEn training +Subject: [PATCH 11/20] haswell NRI: Add RcvEn training Implement the RcvEn (Receive Enable) calibration procedure. Change-Id: Ifbfa520f3e0486c56d0988ce67af2ddb9cf29888 Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/raminit_main.c | 1 + .../haswell/native_raminit/raminit_native.h | 14 + .../haswell/native_raminit/reg_structs.h | 13 + @@ -17,10 +17,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> 6 files changed, 593 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/train_receive_enable.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index ebe9e9b762..e2fbfb4211 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -16,3 +16,4 @@ romstage-y += setup_wdb.c romstage-y += spd_bitmunching.c romstage-y += testing_io.c @@ -39,7 +39,7 @@ index 5e4674957d..7d444659c3 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 7c1a786780..a36ebfacd1 100644 +index 906b3143b9..b4e8c7de5a 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -42,6 +42,9 @@ @@ -83,7 +83,7 @@ index 7c1a786780..a36ebfacd1 100644 /* Number of ticks to wait in units of 69.841279 ns (citation needed) */ static inline void tick_delay(const uint32_t delay) { -@@ -401,6 +414,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl); +@@ -399,6 +412,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl); enum raminit_status configure_mc(struct sysinfo *ctrl); enum raminit_status configure_memory_map(struct sysinfo *ctrl); enum raminit_status do_jedec_init(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0022-haswell-NRI-Add-function-to-change-margins.patch b/config/coreboot/haswell/patches/0012-haswell-NRI-Add-function-to-change-margins.patch index 2e6de17c..f4f5161e 100644 --- a/config/coreboot/haswell/patches/0022-haswell-NRI-Add-function-to-change-margins.patch +++ b/config/coreboot/haswell/patches/0012-haswell-NRI-Add-function-to-change-margins.patch @@ -1,7 +1,7 @@ -From 8c3874195c0fc1af9d0b84611496689da1c19d8c Mon Sep 17 00:00:00 2001 +From c24b26594bfab47a8709ed7fb5cb77307fb73a53 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 11:58:59 +0200 -Subject: [PATCH 22/26] haswell NRI: Add function to change margins +Subject: [PATCH 12/20] haswell NRI: Add function to change margins Implement a function to change margin parameters. Haswell provides a register to apply an offset to margin parameters during training, so @@ -19,14 +19,14 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> 4 files changed, 188 insertions(+) diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c -index 12da59580f..4ba9cfa5c6 100644 +index 055c666eee..299c44a6b0 100644 --- a/src/northbridge/intel/haswell/native_raminit/change_margin.c +++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <assert.h> - #include <commonlib/clamp.h> + #include <commonlib/bsd/clamp.h> #include <console/console.h> #include <delay.h> @@ -152,3 +153,138 @@ void download_regfile( @@ -169,7 +169,7 @@ index 12da59580f..4ba9cfa5c6 100644 + change_margin(ctrl, param, value0, true, 0, rank, 0, update_ctrl, regfile); +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index a36ebfacd1..500fc28909 100644 +index b4e8c7de5a..5242b16f28 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -35,6 +35,18 @@ @@ -206,7 +206,7 @@ index a36ebfacd1..500fc28909 100644 /* ZQ calibration types */ enum { ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */ -@@ -516,6 +536,25 @@ void download_regfile( +@@ -514,6 +534,25 @@ void download_regfile( bool read_rf_rd, bool read_rf_wr); diff --git a/config/coreboot/haswell/patches/0023-haswell-NRI-Add-read-MPR-training.patch b/config/coreboot/haswell/patches/0013-haswell-NRI-Add-read-MPR-training.patch index b13eb2db..5f154bcc 100644 --- a/config/coreboot/haswell/patches/0023-haswell-NRI-Add-read-MPR-training.patch +++ b/config/coreboot/haswell/patches/0013-haswell-NRI-Add-read-MPR-training.patch @@ -1,25 +1,25 @@ -From 6781cec818501f7afd6ee26464fd4556ac3068cb Mon Sep 17 00:00:00 2001 +From e263f0d2e9d6d016d603342651da261bbcb6af1f Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 11:35:49 +0200 -Subject: [PATCH 23/26] haswell NRI: Add read MPR training +Subject: [PATCH 13/20] haswell NRI: Add read MPR training Implement read training using DDR3 MPR (Multi-Purpose Register). Change-Id: Id17cb2c4c399ac9bcc937b595b58f863c152461b Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/raminit_main.c | 1 + .../haswell/native_raminit/raminit_native.h | 4 + - .../haswell/native_raminit/train_read_mpr.c | 240 ++++++++++++++++++ + .../haswell/native_raminit/train_read_mpr.c | 241 ++++++++++++++++++ .../intel/haswell/registers/mchbar.h | 2 +- - 5 files changed, 247 insertions(+), 1 deletion(-) + 5 files changed, 248 insertions(+), 1 deletion(-) create mode 100644 src/northbridge/intel/haswell/native_raminit/train_read_mpr.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index e2fbfb4211..c442be0728 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -16,4 +16,5 @@ romstage-y += setup_wdb.c romstage-y += spd_bitmunching.c romstage-y += testing_io.c @@ -39,7 +39,7 @@ index 7d444659c3..264d1468f5 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 500fc28909..a7551ad63c 100644 +index 5242b16f28..49e9214656 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -27,6 +27,8 @@ @@ -59,7 +59,7 @@ index 500fc28909..a7551ad63c 100644 RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ }; -@@ -435,6 +438,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl); +@@ -433,6 +436,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl); enum raminit_status configure_memory_map(struct sysinfo *ctrl); enum raminit_status do_jedec_init(struct sysinfo *ctrl); enum raminit_status train_receive_enable(struct sysinfo *ctrl); @@ -69,13 +69,13 @@ index 500fc28909..a7551ad63c 100644 void configure_refresh(struct sysinfo *ctrl); diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c new file mode 100644 -index 0000000000..0225e1a384 +index 0000000000..ade1e36148 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c -@@ -0,0 +1,240 @@ +@@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + -+#include <commonlib/clamp.h> ++#include <commonlib/bsd/clamp.h> +#include <console/console.h> +#include <delay.h> +#include <northbridge/intel/haswell/haswell.h> @@ -206,7 +206,8 @@ index 0000000000..0225e1a384 + for (dqs_delay = RMPR_START; dqs_delay < RMPR_STOP; dqs_delay += RMPR_STEP) { + printk(RMPR_PLOT, "% 5d", dqs_delay); + const enum regfile_mode regfile = REG_FILE_USE_START; -+ change_1d_margin_multicast(ctrl, RdT, dqs_delay, 0, false, regfile); ++ /* Looks like MRC uses rank 0 here, but it feels wrong */ ++ change_1d_margin_multicast(ctrl, RdT, dqs_delay, rank, false, regfile); + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + if (!rank_in_ch(ctrl, rank, channel)) + continue; diff --git a/config/coreboot/haswell/patches/0024-haswell-NRI-Add-write-leveling.patch b/config/coreboot/haswell/patches/0014-haswell-NRI-Add-write-leveling.patch index 59e9af9d..5a96cd1f 100644 --- a/config/coreboot/haswell/patches/0024-haswell-NRI-Add-write-leveling.patch +++ b/config/coreboot/haswell/patches/0014-haswell-NRI-Add-write-leveling.patch @@ -1,7 +1,7 @@ -From 20fe4fa852d3e13851a01b51dc984ec5976c864e Mon Sep 17 00:00:00 2001 +From bebe0b74bede64b03aa1e3781310ef539465627b Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 12:56:04 +0200 -Subject: [PATCH 24/26] haswell NRI: Add write leveling +Subject: [PATCH 14/20] haswell NRI: Add write leveling Implement JEDEC write leveling, which is done in two steps. The first step uses the JEDEC procedure to do "fine" write leveling, i.e. align @@ -11,18 +11,18 @@ read-write test to correct "coarse" cycle errors. Change-Id: I27678523fe22c38173a688e2a4751c259a20f009 Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/raminit_main.c | 1 + .../haswell/native_raminit/raminit_native.h | 10 + - .../train_jedec_write_leveling.c | 580 ++++++++++++++++++ + .../train_jedec_write_leveling.c | 581 ++++++++++++++++++ .../intel/haswell/registers/mchbar.h | 2 + - 5 files changed, 594 insertions(+) + 5 files changed, 595 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index c442be0728..40c2f5e014 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -16,5 +16,6 @@ romstage-y += setup_wdb.c romstage-y += spd_bitmunching.c romstage-y += testing_io.c @@ -43,7 +43,7 @@ index 264d1468f5..1ff23be615 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index a7551ad63c..666b233c45 100644 +index 49e9214656..86d89f2120 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -59,6 +59,9 @@ @@ -76,7 +76,7 @@ index a7551ad63c..666b233c45 100644 /* Number of ticks to wait in units of 69.841279 ns (citation needed) */ static inline void tick_delay(const uint32_t delay) { -@@ -439,6 +448,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl); +@@ -437,6 +446,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl); enum raminit_status do_jedec_init(struct sysinfo *ctrl); enum raminit_status train_receive_enable(struct sysinfo *ctrl); enum raminit_status train_read_mpr(struct sysinfo *ctrl); @@ -86,10 +86,10 @@ index a7551ad63c..666b233c45 100644 void configure_refresh(struct sysinfo *ctrl); diff --git a/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c new file mode 100644 -index 0000000000..1ba28a3bd4 +index 0000000000..ef6483e2bd --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c -@@ -0,0 +1,580 @@ +@@ -0,0 +1,581 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <assert.h> @@ -106,7 +106,8 @@ index 0000000000..1ba28a3bd4 + +static void reset_dram_dll(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank) +{ -+ reut_issue_mrs(ctrl, channel, BIT(rank), 0, ctrl->mr0[channel][rank] | MR0_DLL_RESET); ++ const uint16_t mr0reg = ctrl->mr0[channel][rank / 2]; ++ reut_issue_mrs(ctrl, channel, BIT(rank), 0, mr0reg | MR0_DLL_RESET); +} + +static void program_wdb_pattern(struct sysinfo *ctrl, const bool invert) @@ -463,7 +464,7 @@ index 0000000000..1ba28a3bd4 + continue; + + /** TODO: Differs for LPDDR **/ -+ uint16_t mr1reg = ctrl->mr1[channel][rank]; ++ uint16_t mr1reg = ctrl->mr1[channel][rank / 2]; + mr1reg &= ~MR1_QOFF_ENABLE; + mr1reg |= MR1_WL_ENABLE; + if (is_hsw_ult()) { @@ -605,7 +606,7 @@ index 0000000000..1ba28a3bd4 + mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), 0); + + /** TODO: Differs for LPDDR **/ -+ const uint16_t mr1reg = ctrl->mr1[channel][rank] | MR1_QOFF_ENABLE; ++ const uint16_t mr1reg = ctrl->mr1[channel][rank / 2] | MR1_QOFF_ENABLE; + reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg); + + printk(BIOS_DEBUG, "\nC%u.R%u: LftEdge Width\n", channel, rank); diff --git a/config/coreboot/haswell/patches/0025-haswell-NRI-Add-final-raminit-steps.patch b/config/coreboot/haswell/patches/0015-haswell-NRI-Add-final-raminit-steps.patch index d15ea5d1..3626bf6d 100644 --- a/config/coreboot/haswell/patches/0025-haswell-NRI-Add-final-raminit-steps.patch +++ b/config/coreboot/haswell/patches/0015-haswell-NRI-Add-final-raminit-steps.patch @@ -1,7 +1,7 @@ -From d041b14f3af69db5f4598c84e3f53c9cd572ffb5 Mon Sep 17 00:00:00 2001 +From eba8680d618db95028e3f984f25881df0e67abf7 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 14:29:05 +0200 -Subject: [PATCH 25/26] haswell NRI: Add final raminit steps +Subject: [PATCH 15/20] haswell NRI: Add final raminit steps Implement the remaining raminit steps. Although many training steps are missing, this is enough to boot on the Asrock B85M Pro4. @@ -10,7 +10,7 @@ Change-Id: I94f3b65f0218d4da4fda4d84592dfd91f77f8f21 Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- src/northbridge/intel/haswell/Kconfig | 4 +- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/activate_mc.c | 388 ++++++++++++++++++ .../haswell/native_raminit/raminit_main.c | 5 +- .../haswell/native_raminit/raminit_native.c | 5 +- @@ -21,10 +21,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com> create mode 100644 src/northbridge/intel/haswell/native_raminit/activate_mc.c diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig -index b659bf6d98..61f2a3c64c 100644 +index 4b83a25bc1..c6ab27184e 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig -@@ -10,12 +10,12 @@ config NORTHBRIDGE_INTEL_HASWELL +@@ -11,12 +11,12 @@ config NORTHBRIDGE_INTEL_HASWELL if NORTHBRIDGE_INTEL_HASWELL config USE_NATIVE_RAMINIT @@ -39,10 +39,10 @@ index b659bf6d98..61f2a3c64c 100644 config HASWELL_VBOOT_IN_BOOTBLOCK depends on VBOOT -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 40c2f5e014..d97da72890 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -466,10 +466,10 @@ index 1ff23be615..3a65fb01fb 100644 - die("NATIVE RAMINIT: More Magic (tm) required.\n"); } diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index bd9bc8e692..1ea729b23d 100644 +index 2fed93de5b..5f7ceec222 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -200,8 +200,6 @@ void perform_raminit(const int s3resume) +@@ -199,8 +199,6 @@ void perform_raminit(const int s3resume) else me_status = ME_INIT_STATUS_SUCCESS; @@ -478,7 +478,7 @@ index bd9bc8e692..1ea729b23d 100644 intel_early_me_init_done(me_status); } -@@ -217,7 +215,8 @@ void perform_raminit(const int s3resume) +@@ -214,7 +212,8 @@ void perform_raminit(const int s3resume) } /* Save training data on non-S3 resumes */ @@ -489,10 +489,10 @@ index bd9bc8e692..1ea729b23d 100644 /** TODO: setup_sdram_meminfo **/ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 666b233c45..98e39cb76e 100644 +index 86d89f2120..9bab57b518 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -449,6 +449,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl); +@@ -447,6 +447,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl); enum raminit_status train_receive_enable(struct sysinfo *ctrl); enum raminit_status train_read_mpr(struct sysinfo *ctrl); enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0016-Haswell-NRI-Implement-fast-boot-path.patch b/config/coreboot/haswell/patches/0016-Haswell-NRI-Implement-fast-boot-path.patch new file mode 100644 index 00000000..c2fd8b60 --- /dev/null +++ b/config/coreboot/haswell/patches/0016-Haswell-NRI-Implement-fast-boot-path.patch @@ -0,0 +1,722 @@ +From c7d6a901edf648f0f02dd2053337bcf3a319e49b Mon Sep 17 00:00:00 2001 +From: Angel Pons <th3fanbus@gmail.com> +Date: Sat, 13 Apr 2024 01:16:30 +0200 +Subject: [PATCH 16/20] Haswell NRI: Implement fast boot path + +When the memory configuration hasn't changed, there is no need to do +full memory training. Instead, boot firmware can use saved training +data to reinitialise the memory controller and memory. + +Unlike native RAM init for other platforms, Haswell does not save the +main structure (the "mighty ctrl" struct) to flash. Instead, separate +structures define the data to be saved, which can be smaller than the +main structure. + +This makes S3 suspend and resume work: RAM contents MUST be preserved +for a S3 resume to succeed, but RAM training destroys RAM contents. + +Change-Id: I06f6cd39ceecdca104fae89159f28e85cf7ff4e6 +Signed-off-by: Angel Pons <th3fanbus@gmail.com> +--- + .../intel/haswell/native_raminit/Makefile.mk | 1 + + .../haswell/native_raminit/activate_mc.c | 17 + + .../intel/haswell/native_raminit/ddr3.c | 41 ++ + .../haswell/native_raminit/raminit_main.c | 34 +- + .../haswell/native_raminit/raminit_native.c | 30 +- + .../haswell/native_raminit/raminit_native.h | 18 + + .../haswell/native_raminit/save_restore.c | 387 ++++++++++++++++++ + 7 files changed, 504 insertions(+), 24 deletions(-) + create mode 100644 src/northbridge/intel/haswell/native_raminit/save_restore.c + +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk +index d97da72890..8fdd17c542 100644 +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk +@@ -13,6 +13,7 @@ romstage-y += raminit_main.c + romstage-y += raminit_native.c + romstage-y += ranges.c + romstage-y += reut.c ++romstage-y += save_restore.c + romstage-y += setup_wdb.c + romstage-y += spd_bitmunching.c + romstage-y += testing_io.c +diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c +index 78a7ad27ef..0b3eb917da 100644 +--- a/src/northbridge/intel/haswell/native_raminit/activate_mc.c ++++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c +@@ -333,6 +333,23 @@ enum raminit_status activate_mc(struct sysinfo *ctrl) + return RAMINIT_STATUS_SUCCESS; + } + ++enum raminit_status normal_state(struct sysinfo *ctrl) ++{ ++ /* Enable periodic COMP */ ++ mchbar_write32(M_COMP, (union pcu_comp_reg) { ++ .comp_interval = COMP_INT, ++ }.raw); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ /* Set MC to normal mode and clean the ODT and CKE */ ++ mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12); ++ } ++ power_down_config(ctrl); ++ return RAMINIT_STATUS_SUCCESS; ++} ++ + static void mc_lockdown(void) + { + /* Lock memory controller registers */ +diff --git a/src/northbridge/intel/haswell/native_raminit/ddr3.c b/src/northbridge/intel/haswell/native_raminit/ddr3.c +index 6ddb11488b..9b6368edb1 100644 +--- a/src/northbridge/intel/haswell/native_raminit/ddr3.c ++++ b/src/northbridge/intel/haswell/native_raminit/ddr3.c +@@ -2,6 +2,7 @@ + + #include <assert.h> + #include <console/console.h> ++#include <delay.h> + #include <northbridge/intel/haswell/haswell.h> + #include <types.h> + +@@ -215,3 +216,43 @@ enum raminit_status ddr3_jedec_init(struct sysinfo *ctrl) + ddr3_program_mr0(ctrl, 1); + return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT); + } ++ ++enum raminit_status exit_selfrefresh(struct sysinfo *ctrl) ++{ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ /* Fields in ctrl aren't populated on a warm boot */ ++ union ddr_data_control_0_reg data_control_0 = { ++ .raw = mchbar_read32(DQ_CONTROL_0(channel, 0)), ++ }; ++ data_control_0.read_rf_rd = 1; ++ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) { ++ if (!rank_in_ch(ctrl, rank, channel)) ++ continue; ++ ++ data_control_0.read_rf_rank = rank; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ } ++ } ++ ++ /* Time needed to stabilize the DCLK (~6 us) */ ++ udelay(6); ++ ++ /* Pull the DIMMs out of self refresh by asserting CKE high */ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ const union reut_misc_cke_ctrl_reg reut_misc_cke_ctrl = { ++ .cke_on = ctrl->rankmap[channel], ++ }; ++ mchbar_write32(REUT_ch_MISC_CKE_CTRL(channel), reut_misc_cke_ctrl.raw); ++ } ++ mchbar_write32(REUT_MISC_ODT_CTRL, 0); ++ ++ const enum raminit_status status = reut_issue_zq(ctrl, ctrl->chanmap, ZQ_LONG); ++ if (status) { ++ /* ZQCL errors don't seem to be a fatal problem here */ ++ printk(BIOS_ERR, "ZQ Long failed during S3 resume or warm reset flow\n"); ++ } ++ return RAMINIT_STATUS_SUCCESS; ++} +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c +index 3a65fb01fb..056dde1adc 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c +@@ -64,6 +64,22 @@ static const struct task_entry cold_boot[] = { + { train_read_mpr, true, "RDMPRT", }, + { train_jedec_write_leveling, true, "JWRL", }, + { activate_mc, true, "ACTIVATE", }, ++ { save_training_values, true, "SAVE_TRAIN", }, ++ { save_non_training, true, "SAVE_NONT", }, ++ { raminit_done, true, "RAMINITEND", }, ++}; ++ ++static const struct task_entry fast_boot[] = { ++ { collect_spd_info, true, "PROCSPD", }, ++ { restore_non_training, true, "RST_NONT", }, ++ { initialise_mpll, true, "INITMPLL", }, ++ { configure_mc, true, "CONFMC", }, ++ { configure_memory_map, true, "MEMMAP", }, ++ { do_jedec_init, true, "JEDECINIT", }, ++ { pre_training, true, "PRETRAIN", }, ++ { restore_training_values, true, "RST_TRAIN", }, ++ { exit_selfrefresh, true, "EXIT_SR", }, ++ { normal_state, true, "NORMALMODE", }, + { raminit_done, true, "RAMINITEND", }, + }; + +@@ -102,11 +118,11 @@ static void initialize_ctrl(struct sysinfo *ctrl) + ctrl->bootmode = bootmode; + } + +-static enum raminit_status try_raminit(struct sysinfo *ctrl) ++static enum raminit_status try_raminit( ++ struct sysinfo *ctrl, ++ const struct task_entry *const schedule, ++ const size_t length) + { +- const struct task_entry *const schedule = cold_boot; +- const size_t length = ARRAY_SIZE(cold_boot); +- + enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR; + + for (size_t i = 0; i < length; i++) { +@@ -140,8 +156,16 @@ void raminit_main(const enum raminit_boot_mode bootmode) + mighty_ctrl.bootmode = bootmode; + initialize_ctrl(&mighty_ctrl); + ++ enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR; ++ ++ if (bootmode != BOOTMODE_COLD) { ++ status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot)); ++ if (status == RAMINIT_STATUS_SUCCESS) ++ return; ++ } ++ + /** TODO: Try more than once **/ +- enum raminit_status status = try_raminit(&mighty_ctrl); ++ status = try_raminit(&mighty_ctrl, cold_boot, ARRAY_SIZE(cold_boot)); + + if (status != RAMINIT_STATUS_SUCCESS) + die("Memory initialization was met with utmost failure and misery\n"); +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c +index 5f7ceec222..3ad8ce29e7 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c +@@ -54,23 +54,17 @@ static bool early_init_native(enum raminit_boot_mode bootmode) + return cpu_replaced; + } + +-#define MRC_CACHE_VERSION 1 +- +-struct mrc_data { +- const void *buffer; +- size_t buffer_len; +-}; +- +-static void save_mrc_data(struct mrc_data *md) ++static void save_mrc_data(void) + { +- mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len); ++ mrc_cache_stash_data(MRC_TRAINING_DATA, reg_frame_rev(), ++ reg_frame_ptr(), reg_frame_size()); + } + + static struct mrc_data prepare_mrc_cache(void) + { + struct mrc_data md = {0}; + md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, +- MRC_CACHE_VERSION, ++ reg_frame_rev(), + &md.buffer_len); + return md; + } +@@ -94,14 +88,15 @@ static void raminit_reset(void) + } + + static enum raminit_boot_mode do_actual_raminit( +- struct mrc_data *md, + const bool s3resume, + const bool cpu_replaced, + const enum raminit_boot_mode orig_bootmode) + { ++ struct mrc_data md = prepare_mrc_cache(); ++ + enum raminit_boot_mode bootmode = orig_bootmode; + +- bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/ ++ bool save_data_valid = md.buffer && md.buffer_len == reg_frame_size(); + + if (s3resume) { + if (bootmode == BOOTMODE_COLD) { +@@ -154,7 +149,7 @@ static enum raminit_boot_mode do_actual_raminit( + assert(save_data_valid != (bootmode == BOOTMODE_COLD)); + if (save_data_valid) { + printk(BIOS_INFO, "Using cached memory parameters\n"); +- die("RAMINIT: Fast boot is not yet implemented\n"); ++ memcpy(reg_frame_ptr(), md.buffer, reg_frame_size()); + } + printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]); + printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]); +@@ -181,10 +176,8 @@ void perform_raminit(const int s3resume) + wait_txt_clear(); + wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); + +- struct mrc_data md = prepare_mrc_cache(); +- + const enum raminit_boot_mode bootmode = +- do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode); ++ do_actual_raminit(s3resume, cpu_replaced, orig_bootmode); + + /** TODO: report_memory_config **/ + +@@ -212,9 +205,8 @@ void perform_raminit(const int s3resume) + } + + /* Save training data on non-S3 resumes */ +- /** TODO: Enable this once training data is populated **/ +- if (0 && !s3resume) +- save_mrc_data(&md); ++ if (!s3resume) ++ save_mrc_data(); + + /** TODO: setup_sdram_meminfo **/ + } +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +index 9bab57b518..0750904aec 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +@@ -169,6 +169,8 @@ enum regfile_mode { + REG_FILE_USE_CURRENT, /* Used when changing parameters after the test */ + }; + ++struct register_save_frame; ++ + struct wdb_pat { + uint32_t start_ptr; /* Starting pointer in WDB */ + uint32_t stop_ptr; /* Stopping pointer in WDB */ +@@ -219,6 +221,7 @@ enum raminit_status { + RAMINIT_STATUS_RCVEN_FAILURE, + RAMINIT_STATUS_RMPR_FAILURE, + RAMINIT_STATUS_JWRL_FAILURE, ++ RAMINIT_STATUS_INVALID_CACHE, + RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ + }; + +@@ -228,6 +231,11 @@ enum generic_stepping { + STEPPING_C0 = 3, + }; + ++struct mrc_data { ++ const void *buffer; ++ size_t buffer_len; ++}; ++ + struct raminit_dimm_info { + spd_raw_data raw_spd; + struct dimm_attr_ddr3_st data; +@@ -447,12 +455,22 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl); + enum raminit_status train_receive_enable(struct sysinfo *ctrl); + enum raminit_status train_read_mpr(struct sysinfo *ctrl); + enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl); ++enum raminit_status save_training_values(struct sysinfo *ctrl); ++enum raminit_status restore_training_values(struct sysinfo *ctrl); ++enum raminit_status save_non_training(struct sysinfo *ctrl); ++enum raminit_status restore_non_training(struct sysinfo *ctrl); ++enum raminit_status exit_selfrefresh(struct sysinfo *ctrl); ++enum raminit_status normal_state(struct sysinfo *ctrl); + enum raminit_status activate_mc(struct sysinfo *ctrl); + enum raminit_status raminit_done(struct sysinfo *ctrl); + + void configure_timings(struct sysinfo *ctrl); + void configure_refresh(struct sysinfo *ctrl); + ++struct register_save_frame *reg_frame_ptr(void); ++size_t reg_frame_size(void); ++uint32_t reg_frame_rev(void); ++ + uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr); + uint32_t get_tXPDLL(uint32_t mem_clock_mhz); + uint32_t get_tAONPD(uint32_t mem_clock_mhz); +diff --git a/src/northbridge/intel/haswell/native_raminit/save_restore.c b/src/northbridge/intel/haswell/native_raminit/save_restore.c +new file mode 100644 +index 0000000000..f1f50e3ff8 +--- /dev/null ++++ b/src/northbridge/intel/haswell/native_raminit/save_restore.c +@@ -0,0 +1,387 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include <assert.h> ++#include <console/console.h> ++#include <northbridge/intel/haswell/haswell.h> ++#include <types.h> ++ ++#include "raminit_native.h" ++ ++uint32_t reg_frame_rev(void) ++{ ++ /* ++ * Equivalent to MRC_CACHE_REVISION, but hidden via abstraction. ++ * The structures that get saved to flash are contained within ++ * this translation unit, so changes outside this file shouldn't ++ * require invalidating the cache. ++ */ ++ return 1; ++} ++ ++struct register_save { ++ uint16_t lower; ++ uint16_t upper; ++}; ++ ++/** TODO: Haswell DDRIO aliases writes: 0x80 .. 0xff => 0x00 .. 0x7f **/ ++static const struct register_save ddrio_per_byte_list[] = { ++ {0x0000, 0x003c}, /* 16 registers */ ++// {0x0048, 0x0084}, /* 16 registers */ /** TODO: BDW support **/ ++ {0x0048, 0x004c}, /* 2 registers */ ++ {0x005c, 0x0078}, /* 8 registers */ ++}; ++#define DDRIO_PER_BYTE_REGISTER_COUNT (16 + 2 + 8) ++ ++static const struct register_save ddrio_per_ch_list[] = { ++ /* CKE */ ++ {0x1204, 0x1208}, /* 2 registers */ ++ {0x1214, 0x121c}, /* 3 registers */ ++ /* CMD North */ ++ {0x1404, 0x140c}, /* 3 registers */ ++ /* CLK */ ++ {0x1808, 0x1810}, /* 3 registers */ ++ /* CMD South */ ++ {0x1a04, 0x1a0c}, /* 3 registers */ ++ /* CTL */ ++ {0x1c14, 0x1c1c}, /* 3 registers */ ++}; ++#define DDRIO_PER_CH_REGISTER_COUNT (2 + 3 * 5) ++ ++static const struct register_save ddrio_common_list[] = { ++ {0x2000, 0x2008}, /* 3 registers */ ++ {0x3a14, 0x3a1c}, /* 3 registers */ ++ {0x3a24, 0x3a24}, /* 1 registers */ ++}; ++ ++#define DDRIO_COMMON_REGISTER_COUNT (3 + 3 + 1) ++ ++static const struct register_save mcmain_per_ch_list[] = { ++ {0x4000, 0x4014}, /* 6 registers */ ++ {0x4024, 0x4028}, /* 2 registers */ ++ {0x40d0, 0x40d0}, /* 1 registers */ ++ {0x4220, 0x4224}, /* 2 registers */ ++ {0x4294, 0x4294}, /* 1 registers */ ++ {0x429c, 0x42a0}, /* 2 registers */ ++ {0x42ec, 0x42fc}, /* 5 registers */ ++ {0x4328, 0x4328}, /* 1 registers */ ++ {0x438c, 0x4390}, /* 2 registers */ ++}; ++#define MCMAIN_PER_CH_REGISTER_COUNT (6 + 2 + 1 + 2 + 1 + 2 + 5 + 1 + 2) ++ ++static const struct register_save misc_common_list[] = { ++ {0x5884, 0x5888}, /* 2 registers */ ++ {0x5890, 0x589c}, /* 4 registers */ ++ {0x58a4, 0x58a4}, /* 1 registers */ ++ {0x58d0, 0x58e4}, /* 6 registers */ ++ {0x5880, 0x5880}, /* 1 registers */ ++ {0x5000, 0x50dc}, /* 56 registers */ ++ {0x59b8, 0x59b8} /* 1 registers */ ++}; ++#define MISC_COMMON_REGISTER_COUNT (2 + 4 + 1 + 6 + 1 + 56 + 1) ++ ++struct save_params { ++ bool is_initialised; ++ ++ /* Memory base frequency, either 100 or 133 MHz */ ++ uint8_t base_freq; ++ ++ /* Multiplier */ ++ uint32_t multiplier; ++ ++ /* Memory clock in MHz */ ++ uint32_t mem_clock_mhz; ++ ++ /* Memory clock in femtoseconds */ ++ uint32_t mem_clock_fs; ++ ++ /* Quadrature clock in picoseconds */ ++ uint16_t qclkps; ++ ++ /* Bitfield of supported CAS latencies */ ++ uint16_t cas_supported; ++ ++ /* CPUID value */ ++ uint32_t cpu; ++ ++ /* Cached CPU stepping value */ ++ uint8_t stepping; ++ ++ uint16_t vdd_mv; ++ ++ union dimm_flags_ddr3_st flags; ++ ++ /* Except for tCK, everything is stored in DCLKs */ ++ uint32_t tCK; ++ uint32_t tAA; ++ uint32_t tWR; ++ uint32_t tRCD; ++ uint32_t tRRD; ++ uint32_t tRP; ++ uint32_t tRAS; ++ uint32_t tRC; ++ uint32_t tRFC; ++ uint32_t tWTR; ++ uint32_t tRTP; ++ uint32_t tFAW; ++ uint32_t tCWL; ++ uint32_t tCMD; ++ ++ uint32_t tREFI; ++ uint32_t tXP; ++ ++ uint8_t lpddr_cke_rank_map[NUM_CHANNELS]; ++ ++ struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS]; ++ ++ uint8_t chanmap; ++ ++ uint32_t channel_size_mb[NUM_CHANNELS]; ++ ++ /* DIMMs per channel */ ++ uint8_t dpc[NUM_CHANNELS]; ++ ++ uint8_t rankmap[NUM_CHANNELS]; ++ ++ /* Whether a rank is mirrored or not (only rank 1 of each DIMM can be) */ ++ uint8_t rank_mirrored[NUM_CHANNELS]; ++ ++ /* ++ * FIXME: LPDDR support is incomplete. The largest chunks are missing, ++ * but some LPDDR-specific variations in algorithms have been handled. ++ * LPDDR-specific functions have stubs which will halt upon execution. ++ */ ++ bool lpddr; ++ ++ uint8_t lanes; ++ ++ /* FIXME: ECC support missing */ ++ bool is_ecc; ++}; ++ ++struct register_save_frame { ++ uint32_t ddrio_per_byte[NUM_CHANNELS][NUM_LANES][DDRIO_PER_BYTE_REGISTER_COUNT]; ++ uint32_t ddrio_per_ch[NUM_CHANNELS][DDRIO_PER_CH_REGISTER_COUNT]; ++ uint32_t ddrio_common[DDRIO_COMMON_REGISTER_COUNT]; ++ uint32_t mcmain_per_ch[NUM_CHANNELS][MCMAIN_PER_CH_REGISTER_COUNT]; ++ uint32_t misc_common[MISC_COMMON_REGISTER_COUNT]; ++ struct save_params params; ++}; ++ ++struct register_save_frame *reg_frame_ptr(void) ++{ ++ /* The chonky register save frame struct, used for fast boot and S3 resume */ ++ static struct register_save_frame register_frame = { 0 }; ++ return ®ister_frame; ++} ++ ++size_t reg_frame_size(void) ++{ ++ return sizeof(struct register_save_frame); ++} ++ ++typedef void (*reg_func_t)(const uint16_t offset, uint32_t *const value); ++ ++static void save_value(const uint16_t offset, uint32_t *const value) ++{ ++ *value = mchbar_read32(offset); ++} ++ ++static void restore_value(const uint16_t offset, uint32_t *const value) ++{ ++ mchbar_write32(offset, *value); ++} ++ ++static void save_restore( ++ uint32_t *reg_frame, ++ const uint16_t g_offset, ++ const struct register_save *reg_save_list, ++ const size_t reg_save_length, ++ reg_func_t handle_reg) ++{ ++ for (size_t i = 0; i < reg_save_length; i++) { ++ const struct register_save *entry = ®_save_list[i]; ++ for (uint16_t offset = entry->lower; offset <= entry->upper; offset += 4) { ++ handle_reg(offset + g_offset, reg_frame++); ++ } ++ } ++} ++ ++static void save_restore_all(struct register_save_frame *reg_frame, reg_func_t handle_reg) ++{ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ for (uint8_t byte = 0; byte < NUM_LANES; byte++) { ++ const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, byte); ++ save_restore( ++ reg_frame->ddrio_per_byte[channel][byte], ++ g_offset, ++ ddrio_per_byte_list, ++ ARRAY_SIZE(ddrio_per_byte_list), ++ handle_reg); ++ } ++ } ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, 0); ++ save_restore( ++ reg_frame->ddrio_per_ch[channel], ++ g_offset, ++ ddrio_per_ch_list, ++ ARRAY_SIZE(ddrio_per_ch_list), ++ handle_reg); ++ } ++ save_restore( ++ reg_frame->ddrio_common, ++ 0, ++ ddrio_common_list, ++ ARRAY_SIZE(ddrio_common_list), ++ handle_reg); ++ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ const uint16_t g_offset = _MCMAIN_C(0, channel); ++ save_restore( ++ reg_frame->mcmain_per_ch[channel], ++ g_offset, ++ mcmain_per_ch_list, ++ ARRAY_SIZE(mcmain_per_ch_list), ++ handle_reg); ++ } ++ save_restore( ++ reg_frame->misc_common, ++ 0, ++ misc_common_list, ++ ARRAY_SIZE(misc_common_list), ++ handle_reg); ++} ++ ++enum raminit_status save_training_values(struct sysinfo *ctrl) ++{ ++ save_restore_all(reg_frame_ptr(), save_value); ++ return RAMINIT_STATUS_SUCCESS; ++} ++ ++enum raminit_status restore_training_values(struct sysinfo *ctrl) ++{ ++ save_restore_all(reg_frame_ptr(), restore_value); ++ return RAMINIT_STATUS_SUCCESS; ++} ++ ++enum raminit_status save_non_training(struct sysinfo *ctrl) ++{ ++ struct register_save_frame *reg_frame = reg_frame_ptr(); ++ struct save_params *params = ®_frame->params; ++ ++ params->is_initialised = true; ++ ++ params->base_freq = ctrl->base_freq; ++ params->multiplier = ctrl->multiplier; ++ params->mem_clock_mhz = ctrl->mem_clock_mhz; ++ params->mem_clock_fs = ctrl->mem_clock_fs; ++ params->qclkps = ctrl->qclkps; ++ params->cas_supported = ctrl->cas_supported; ++ params->cpu = ctrl->cpu; ++ params->stepping = ctrl->stepping; ++ params->vdd_mv = ctrl->vdd_mv; ++ params->flags = ctrl->flags; ++ ++ params->tCK = ctrl->tCK; ++ params->tAA = ctrl->tAA; ++ params->tWR = ctrl->tWR; ++ params->tRCD = ctrl->tRCD; ++ params->tRRD = ctrl->tRRD; ++ params->tRP = ctrl->tRP; ++ params->tRAS = ctrl->tRAS; ++ params->tRC = ctrl->tRC; ++ params->tRFC = ctrl->tRFC; ++ params->tWTR = ctrl->tWTR; ++ params->tRTP = ctrl->tRTP; ++ params->tFAW = ctrl->tFAW; ++ params->tCWL = ctrl->tCWL; ++ params->tCMD = ctrl->tCMD; ++ params->tREFI = ctrl->tREFI; ++ params->tXP = ctrl->tXP; ++ ++ params->chanmap = ctrl->chanmap; ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ params->lpddr_cke_rank_map[channel] = ctrl->lpddr_cke_rank_map[channel]; ++ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) ++ params->dimms[channel][slot] = ctrl->dimms[channel][slot]; ++ } ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ params->dpc[channel] = ctrl->dpc[channel]; ++ params->rankmap[channel] = ctrl->rankmap[channel]; ++ params->rank_mirrored[channel] = ctrl->rank_mirrored[channel]; ++ params->channel_size_mb[channel] = ctrl->channel_size_mb[channel]; ++ } ++ params->lpddr = ctrl->lpddr; ++ params->lanes = ctrl->lanes; ++ params->is_ecc = ctrl->is_ecc; ++ return RAMINIT_STATUS_SUCCESS; ++} ++ ++#define RAMINIT_COMPARE(_s1, _s2) \ ++ ((sizeof(_s1) == sizeof(_s2)) && !memcmp(_s1, _s2, sizeof(_s1))) ++ ++enum raminit_status restore_non_training(struct sysinfo *ctrl) ++{ ++ struct register_save_frame *reg_frame = reg_frame_ptr(); ++ struct save_params *params = ®_frame->params; ++ ++ if (!params->is_initialised) { ++ printk(BIOS_WARNING, "Cannot fast boot: saved data is invalid\n"); ++ return RAMINIT_STATUS_INVALID_CACHE; ++ } ++ ++ if (!RAMINIT_COMPARE(ctrl->dimms, params->dimms)) { ++ printk(BIOS_WARNING, "Cannot fast boot: DIMMs have changed\n"); ++ return RAMINIT_STATUS_INVALID_CACHE; ++ } ++ ++ if (ctrl->cpu != params->cpu) { ++ printk(BIOS_WARNING, "Cannot fast boot: CPU has changed\n"); ++ return RAMINIT_STATUS_INVALID_CACHE; ++ } ++ ++ ctrl->base_freq = params->base_freq; ++ ctrl->multiplier = params->multiplier; ++ ctrl->mem_clock_mhz = params->mem_clock_mhz; ++ ctrl->mem_clock_fs = params->mem_clock_fs; ++ ctrl->qclkps = params->qclkps; ++ ctrl->cas_supported = params->cas_supported; ++ ctrl->cpu = params->cpu; ++ ctrl->stepping = params->stepping; ++ ctrl->vdd_mv = params->vdd_mv; ++ ctrl->flags = params->flags; ++ ++ ctrl->tCK = params->tCK; ++ ctrl->tAA = params->tAA; ++ ctrl->tWR = params->tWR; ++ ctrl->tRCD = params->tRCD; ++ ctrl->tRRD = params->tRRD; ++ ctrl->tRP = params->tRP; ++ ctrl->tRAS = params->tRAS; ++ ctrl->tRC = params->tRC; ++ ctrl->tRFC = params->tRFC; ++ ctrl->tWTR = params->tWTR; ++ ctrl->tRTP = params->tRTP; ++ ctrl->tFAW = params->tFAW; ++ ctrl->tCWL = params->tCWL; ++ ctrl->tCMD = params->tCMD; ++ ctrl->tREFI = params->tREFI; ++ ctrl->tXP = params->tXP; ++ ++ ctrl->chanmap = params->chanmap; ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ ctrl->lpddr_cke_rank_map[channel] = params->lpddr_cke_rank_map[channel]; ++ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) ++ ctrl->dimms[channel][slot] = params->dimms[channel][slot]; ++ } ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ ctrl->dpc[channel] = params->dpc[channel]; ++ ctrl->rankmap[channel] = params->rankmap[channel]; ++ ctrl->rank_mirrored[channel] = params->rank_mirrored[channel]; ++ ctrl->channel_size_mb[channel] = params->channel_size_mb[channel]; ++ } ++ ctrl->lpddr = params->lpddr; ++ ctrl->lanes = params->lanes; ++ ctrl->is_ecc = params->is_ecc; ++ return RAMINIT_STATUS_SUCCESS; ++} +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0017-haswell-NRI-Do-sense-amplifier-offset-training.patch b/config/coreboot/haswell/patches/0017-haswell-NRI-Do-sense-amplifier-offset-training.patch new file mode 100644 index 00000000..846fe9a3 --- /dev/null +++ b/config/coreboot/haswell/patches/0017-haswell-NRI-Do-sense-amplifier-offset-training.patch @@ -0,0 +1,476 @@ +From be58501141aa97aa544b670e566cd6cf6797c18e Mon Sep 17 00:00:00 2001 +From: Angel Pons <th3fanbus@gmail.com> +Date: Wed, 17 Apr 2024 13:20:32 +0200 +Subject: [PATCH 17/20] haswell NRI: Do sense amplifier offset training + +Quoting Wikipedia: + + A sense amplifier is a circuit that is used to amplify and detect + small signals in electronic systems. It is commonly used in memory + circuits, such as dynamic random access memory (DRAM), to read and + amplify the weak signals stored in memory cells. + +In this case, we're calibrating the sense amplifiers in the memory +controller. This training procedure uses a magic "sense amp offset +cancel" mode of the DDRIO to observe the sampled logic levels, and +sweeps Vref to find the low-high transition for each bit lane. The +procedure consists of two stages: the first stage centers per-byte +Vref (to ensure per-bit Vref offsets are as small as possible) and +the second stage centers per-bit Vref. + +Because this procedure uses the "sense amp offset cancel" mode, it +does not rely on DRAM being trained. It is assumed that the memory +controller simply makes sense amp output levels observable via the +`DDR_DATA_TRAIN_FEEDBACK` register and that the memory bus is idle +during this training step (so the lane voltage is Vdd / 2). + +Note: This procedure will need to be adapted for Broadwell because +it has per-rank per-bit RxVref registers, whereas Haswell only has +a single per-bit RxVref register for all ranks. + +Change-Id: Ia07db68763f90e9701c8a376e01279ada8dbbe07 +Signed-off-by: Angel Pons <th3fanbus@gmail.com> +--- + .../intel/haswell/native_raminit/Makefile.mk | 1 + + .../haswell/native_raminit/raminit_main.c | 1 + + .../haswell/native_raminit/raminit_native.h | 12 + + .../native_raminit/train_sense_amp_offset.c | 341 ++++++++++++++++++ + .../intel/haswell/registers/mchbar.h | 2 + + 5 files changed, 357 insertions(+) + create mode 100644 src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c + +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk +index 8fdd17c542..4bd668a2d6 100644 +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk +@@ -21,3 +21,4 @@ romstage-y += timings_refresh.c + romstage-y += train_jedec_write_leveling.c + romstage-y += train_read_mpr.c + romstage-y += train_receive_enable.c ++romstage-y += train_sense_amp_offset.c +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c +index 056dde1adc..ce637e2d03 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c +@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = { + { configure_memory_map, true, "MEMMAP", }, + { do_jedec_init, true, "JEDECINIT", }, + { pre_training, true, "PRETRAIN", }, ++ { train_sense_amp_offset, true, "SOT", }, + { train_receive_enable, true, "RCVET", }, + { train_read_mpr, true, "RDMPRT", }, + { train_jedec_write_leveling, true, "JWRL", }, +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +index 0750904aec..95ccd0a8b3 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +@@ -22,6 +22,8 @@ + #define NUM_LANES 9 + #define NUM_LANES_NO_ECC 8 + ++#define NUM_BITS 8 ++ + #define COMP_INT 10 + + /* Always use 12 legs for emphasis (not trained) */ +@@ -218,6 +220,7 @@ enum raminit_status { + RAMINIT_STATUS_MPLL_INIT_FAILURE, + RAMINIT_STATUS_POLL_TIMEOUT, + RAMINIT_STATUS_REUT_ERROR, ++ RAMINIT_STATUS_SAMP_OFFSET_FAILURE, + RAMINIT_STATUS_RCVEN_FAILURE, + RAMINIT_STATUS_RMPR_FAILURE, + RAMINIT_STATUS_JWRL_FAILURE, +@@ -243,6 +246,12 @@ struct raminit_dimm_info { + bool valid; + }; + ++struct vref_margin { ++ uint8_t low; ++ uint8_t center; ++ uint8_t high; ++}; ++ + struct sysinfo { + enum raminit_boot_mode bootmode; + enum generic_stepping stepping; +@@ -330,6 +339,8 @@ struct sysinfo { + uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; + int8_t rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; + ++ struct vref_margin rxdqvrefpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS]; ++ + uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS]; + uint8_t ctl_pi_code[NUM_CHANNELS][NUM_SLOTRANKS]; + uint8_t cke_pi_code[NUM_CHANNELS][NUM_SLOTRANKS]; +@@ -452,6 +463,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl); + enum raminit_status configure_mc(struct sysinfo *ctrl); + enum raminit_status configure_memory_map(struct sysinfo *ctrl); + enum raminit_status do_jedec_init(struct sysinfo *ctrl); ++enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl); + enum raminit_status train_receive_enable(struct sysinfo *ctrl); + enum raminit_status train_read_mpr(struct sysinfo *ctrl); + enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl); +diff --git a/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c +new file mode 100644 +index 0000000000..d4f199fefb +--- /dev/null ++++ b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c +@@ -0,0 +1,341 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include <assert.h> ++#include <commonlib/bsd/clamp.h> ++#include <console/console.h> ++#include <delay.h> ++#include <lib.h> ++#include <types.h> ++ ++#include "raminit_native.h" ++ ++#define VREF_OFFSET_PLOT RAM_DEBUG ++#define SAMP_OFFSET_PLOT RAM_DEBUG ++ ++struct vref_train_data { ++ int8_t best_sum; ++ int8_t best_vref; ++ int8_t sum_bits; ++ uint8_t high_mask; ++ uint8_t low_mask; ++}; ++ ++static enum raminit_status train_vref_offset(struct sysinfo *ctrl) ++{ ++ const int8_t vref_start = -15; ++ const int8_t vref_stop = 15; ++ const struct vref_train_data initial_vref_values = { ++ .best_sum = -NUM_LANES, ++ .best_vref = 0, ++ .high_mask = 0, ++ .low_mask = 0xff, ++ }; ++ struct vref_train_data vref_data[NUM_CHANNELS][NUM_LANES]; ++ ++ printk(VREF_OFFSET_PLOT, "Plot of sum_bits across Vref settings\nChannel"); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ printk(VREF_OFFSET_PLOT, "\t%u\t\t", channel); ++ } ++ ++ printk(VREF_OFFSET_PLOT, "\nByte"); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ printk(VREF_OFFSET_PLOT, "\t"); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ printk(VREF_OFFSET_PLOT, "%u ", byte); ++ vref_data[channel][byte] = initial_vref_values; ++ union ddr_data_control_2_reg data_control_2 = { ++ .raw = ctrl->dq_control_2[channel][byte], ++ }; ++ data_control_2.force_bias_on = 1; ++ data_control_2.force_rx_on = 1; ++ mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw); ++ } ++ } ++ ++ /* Sweep through Vref settings and find point SampOffset of +/- 7 passes */ ++ printk(VREF_OFFSET_PLOT, "\n1/2 Vref"); ++ for (int8_t vref = vref_start; vref <= vref_stop; vref++) { ++ printk(VREF_OFFSET_PLOT, "\n% 3d", vref); ++ ++ /* ++ * To perform this test, enable offset cancel mode and enable ODT. ++ * Check results and update variables. Ideal result is all zeroes. ++ * Clear offset cancel mode at end of test to write RX_OFFSET_VDQ. ++ */ ++ change_1d_margin_multicast(ctrl, RdV, vref, 0, false, REG_FILE_USE_RANK); ++ ++ /* Program settings for Vref and SampOffset = 7 (8 + 7) */ ++ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0xffffffff); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ /* Propagate delay values (without a read command) */ ++ union ddr_data_control_0_reg data_control_0 = { ++ .raw = ctrl->dq_control_0[channel], ++ }; ++ data_control_0.read_rf_rd = 1; ++ data_control_0.read_rf_wr = 0; ++ data_control_0.read_rf_rank = 0; ++ data_control_0.force_odt_on = 1; ++ data_control_0.samp_train_mode = 1; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ udelay(1); ++ data_control_0.samp_train_mode = 0; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ const uint8_t feedback = get_data_train_feedback(channel, byte); ++ struct vref_train_data *curr_data = &vref_data[channel][byte]; ++ curr_data->low_mask &= feedback; ++ curr_data->sum_bits = -popcnt(feedback); ++ } ++ } ++ ++ /* Program settings for Vref and SampOffset = -7 (8 - 7) */ ++ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0x11111111); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ /* Propagate delay values (without a read command) */ ++ union ddr_data_control_0_reg data_control_0 = { ++ .raw = ctrl->dq_control_0[channel], ++ }; ++ data_control_0.read_rf_rd = 1; ++ data_control_0.read_rf_wr = 0; ++ data_control_0.read_rf_rank = 0; ++ data_control_0.force_odt_on = 1; ++ data_control_0.samp_train_mode = 1; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ udelay(1); ++ data_control_0.samp_train_mode = 0; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ printk(VREF_OFFSET_PLOT, "\t"); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ const uint8_t feedback = get_data_train_feedback(channel, byte); ++ struct vref_train_data *curr_data = &vref_data[channel][byte]; ++ curr_data->high_mask |= feedback; ++ curr_data->sum_bits += popcnt(feedback); ++ printk(VREF_OFFSET_PLOT, "%d ", curr_data->sum_bits); ++ if (curr_data->sum_bits > curr_data->best_sum) { ++ curr_data->best_sum = curr_data->sum_bits; ++ curr_data->best_vref = vref; ++ ctrl->rxvref[channel][0][byte] = vref; ++ } else if (curr_data->sum_bits == curr_data->best_sum) { ++ curr_data->best_vref = vref; ++ } ++ } ++ } ++ } ++ printk(BIOS_DEBUG, "\n\nHi-Lo (XOR):"); ++ enum raminit_status status = RAMINIT_STATUS_SUCCESS; ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ printk(BIOS_DEBUG, "\n C%u:", channel); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ struct vref_train_data *const curr_data = &vref_data[channel][byte]; ++ const uint8_t bit_xor = curr_data->high_mask ^ curr_data->low_mask; ++ printk(BIOS_DEBUG, "\t0x%02x", bit_xor); ++ if (bit_xor == 0xff) ++ continue; ++ ++ /* Report an error if any bit did not change */ ++ status = RAMINIT_STATUS_SAMP_OFFSET_FAILURE; ++ } ++ } ++ if (status) ++ printk(BIOS_ERR, "\nUnexpected bit error in Vref offset training\n"); ++ ++ printk(BIOS_DEBUG, "\n\nRdVref:"); ++ change_1d_margin_multicast(ctrl, RdV, 0, 0, false, REG_FILE_USE_RANK); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ printk(BIOS_DEBUG, "\n C%u:", channel); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ struct vref_train_data *const curr_data = &vref_data[channel][byte]; ++ const int8_t vref_width = ++ curr_data->best_vref - ctrl->rxvref[channel][0][byte]; ++ ++ /* ++ * Step size for Rx Vref in DATA_OFFSET_TRAIN is about 3.9 mV ++ * whereas Rx Vref step size in RX_TRAIN_RANK is about 7.8 mV ++ */ ++ int8_t vref = ctrl->rxvref[channel][0][byte] + vref_width / 2; ++ if (vref < 0) ++ vref--; ++ else ++ vref++; ++ ++ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) { ++ if (!rank_in_ch(ctrl, rank, channel)) ++ continue; ++ ++ ctrl->rxvref[channel][rank][byte] = vref / 2; ++ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0); ++ } ++ printk(BIOS_DEBUG, "\t% 4d", ctrl->rxvref[channel][0][byte]); ++ } ++ } ++ printk(BIOS_DEBUG, "\n\n"); ++ return status; ++} ++ ++/** ++ * LPDDR has an additional bit for DQS per each byte. ++ * ++ * TODO: The DQS value must be written into Data Control 2. ++ */ ++#define NUM_OFFSET_TRAIN_BITS (NUM_BITS + 1) ++ ++#define PLOT_CH_SPACE " " ++ ++struct samp_train_data { ++ uint8_t first_zero; ++ uint8_t last_one; ++}; ++ ++static void train_samp_offset(struct sysinfo *ctrl) ++{ ++ const uint8_t max_train_bits = ctrl->lpddr ? NUM_OFFSET_TRAIN_BITS : NUM_BITS; ++ ++ struct samp_train_data samp_data[NUM_CHANNELS][NUM_LANES][NUM_OFFSET_TRAIN_BITS] = {0}; ++ ++ printk(BIOS_DEBUG, "Channel "); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ printk(BIOS_DEBUG, "%u ", channel); /* Same length as PLOT_CH_SPACE */ ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) ++ printk(BIOS_DEBUG, " %s ", ctrl->lpddr ? " " : ""); ++ } ++ printk(BIOS_DEBUG, "\nByte "); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) ++ printk(BIOS_DEBUG, "%u %s ", byte, ctrl->lpddr ? " " : ""); ++ ++ printk(BIOS_DEBUG, PLOT_CH_SPACE); ++ } ++ printk(SAMP_OFFSET_PLOT, "\nBits "); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) ++ printk(SAMP_OFFSET_PLOT, "01234567%s ", ctrl->lpddr ? "S" : ""); ++ ++ printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE); ++ } ++ printk(SAMP_OFFSET_PLOT, "\n SAmp\n"); ++ for (uint8_t samp_offset = 1; samp_offset <= 15; samp_offset++) { ++ printk(SAMP_OFFSET_PLOT, "% 5d\t", samp_offset); ++ ++ uint32_t rx_offset_vdq = 0; ++ for (uint8_t bit = 0; bit < NUM_BITS; bit++) { ++ rx_offset_vdq += samp_offset << (4 * bit); ++ } ++ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, rx_offset_vdq); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ /* Propagate delay values (without a read command) */ ++ union ddr_data_control_0_reg data_control_0 = { ++ .raw = ctrl->dq_control_0[channel], ++ }; ++ data_control_0.read_rf_rd = 1; ++ data_control_0.read_rf_wr = 0; ++ data_control_0.read_rf_rank = 0; ++ data_control_0.force_odt_on = 1; ++ data_control_0.samp_train_mode = 1; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ udelay(1); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ const uint32_t feedback = ++ get_data_train_feedback(channel, byte); ++ ++ for (uint8_t bit = 0; bit < max_train_bits; bit++) { ++ struct samp_train_data *const curr_data = ++ &samp_data[channel][byte][bit]; ++ const bool result = feedback & BIT(bit); ++ if (result) { ++ curr_data->last_one = samp_offset; ++ } else if (curr_data->first_zero == 0) { ++ curr_data->first_zero = samp_offset; ++ } ++ printk(SAMP_OFFSET_PLOT, result ? "." : "#"); ++ } ++ printk(SAMP_OFFSET_PLOT, " "); ++ } ++ printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE); ++ data_control_0.samp_train_mode = 0; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ } ++ printk(SAMP_OFFSET_PLOT, "\n"); ++ } ++ printk(BIOS_DEBUG, "\nBitSAmp "); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ uint32_t rx_offset_vdq = 0; ++ for (uint8_t bit = 0; bit < max_train_bits; bit++) { ++ struct samp_train_data *const curr_data = ++ &samp_data[channel][byte][bit]; ++ ++ uint8_t vref = curr_data->first_zero + curr_data->last_one; ++ vref = clamp_u8(0, vref / 2, 15); ++ /* ++ * Check for saturation conditions to make sure ++ * we are as close as possible to Vdd/2 (750 mV). ++ */ ++ if (curr_data->first_zero == 0) ++ vref = 15; ++ if (curr_data->last_one == 0) ++ vref = 0; ++ ++ ctrl->rxdqvrefpb[channel][0][byte][bit].center = vref; ++ rx_offset_vdq += vref & 0xf << (4 * bit); ++ printk(BIOS_DEBUG, "%x", vref); ++ } ++ mchbar_write32(RX_OFFSET_VDQ(channel, byte), rx_offset_vdq); ++ printk(BIOS_DEBUG, " "); ++ download_regfile(ctrl, channel, 1, 0, REG_FILE_USE_RANK, 0, 1, 0); ++ } ++ printk(BIOS_DEBUG, PLOT_CH_SPACE); ++ } ++ printk(BIOS_DEBUG, "\n"); ++} ++ ++enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl) ++{ ++ printk(BIOS_DEBUG, "Stage 1: Vref offset training\n"); ++ const enum raminit_status status = train_vref_offset(ctrl); ++ ++ printk(BIOS_DEBUG, "Stage 2: Samp offset training\n"); ++ train_samp_offset(ctrl); ++ ++ /* Clean up after test */ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) ++ mchbar_write32(DQ_CONTROL_2(channel, byte), ++ ctrl->dq_control_2[channel][byte]); ++ } ++ io_reset(); ++ return status; ++} +diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h +index 49a215aa71..1a168a3fc8 100644 +--- a/src/northbridge/intel/haswell/registers/mchbar.h ++++ b/src/northbridge/intel/haswell/registers/mchbar.h +@@ -18,6 +18,8 @@ + #define RX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0000, ch, rank, byte) + #define TX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0020, ch, rank, byte) + ++#define RX_OFFSET_VDQ(ch, byte) _DDRIO_C_R_B(0x004c, ch, 0, byte) ++ + #define DDR_DATA_TRAIN_FEEDBACK(ch, byte) _DDRIO_C_R_B(0x0054, ch, 0, byte) + + #define DQ_CONTROL_1(ch, byte) _DDRIO_C_R_B(0x0060, ch, 0, byte) +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0018-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/haswell/patches/0018-Remove-warning-for-coreboot-images-built-without-a-p.patch new file mode 100644 index 00000000..34309242 --- /dev/null +++ b/config/coreboot/haswell/patches/0018-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -0,0 +1,39 @@ +From c25dcd8ac80598939edffd011df0fd9ba3d8a1a8 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin <nic.c3.14@gmail.com> +Date: Fri, 12 May 2023 19:55:15 -0600 +Subject: [PATCH 18/20] Remove warning for coreboot images built without a + payload + +I added this in upstream to prevent people from accidentally flashing +roms without a payload resulting in a no boot situation, but in +libreboot lbmk handles the payload and thus this warning always comes +up. This has caused confusion and concern so just patch it out. +--- + payloads/Makefile.mk | 13 +------------ + 1 file changed, 1 insertion(+), 12 deletions(-) + +diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk +index a2336aa876..4f1692a873 100644 +--- a/payloads/Makefile.mk ++++ b/payloads/Makefile.mk +@@ -49,16 +49,5 @@ distclean-payloads: + print-repo-info-payloads: + -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) + +-ifeq ($(CONFIG_PAYLOAD_NONE),y) +-show_notices:: warn_no_payload +-endif +- +-warn_no_payload: +- printf "\n\t** WARNING **\n" +- printf "coreboot has been built without a payload. Writing\n" +- printf "a coreboot image without a payload to your board's\n" +- printf "flash chip will result in a non-booting system. You\n" +- printf "can use cbfstool to add a payload to the image.\n\n" +- + .PHONY: force-payload coreinfo nvramcui +-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload ++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch new file mode 100644 index 00000000..e197b3f3 --- /dev/null +++ b/config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch @@ -0,0 +1,36 @@ +From 081890bab8d454247b6f7e9cb209f46159c45c8b Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Sun, 5 Nov 2023 23:19:42 +0000 +Subject: [PATCH 19/20] use mirrorservice.org for gcc downloads + +the gnu.org 302 redirect often fails + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + util/crossgcc/buildgcc | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc +index 0a0462e2f6..6ae201239d 100755 +--- a/util/crossgcc/buildgcc ++++ b/util/crossgcc/buildgcc +@@ -69,11 +69,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" + # to the jenkins build as well, or the builder won't download it. + + # GCC toolchain archive locations +-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" +-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" +-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" +-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" +-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" ++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp" ++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" ++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" ++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" ++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" + IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" + # CLANG toolchain archive locations + LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch new file mode 100644 index 00000000..60490608 --- /dev/null +++ b/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -0,0 +1,204 @@ +From 1a4f454e05b613cb080cdd063dd3efb1fdbb748b Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@libreboot.org> +Date: Sun, 19 Feb 2023 18:21:43 +0000 +Subject: [PATCH 20/20] util/ifdtool: add --nuke flag (all 0xFF on region) + +When this option is used, the region's contents are overwritten +with all ones (0xFF). + +Example: + +./ifdtool --nuke gbe coreboot.rom +./ifdtool --nuke bios coreboot.com +./ifdtool --nuke me coreboot.com + +Rebased since the last revision update in lbmk. + +Signed-off-by: Leah Rowe <leah@libreboot.org> +--- + util/ifdtool/ifdtool.c | 113 ++++++++++++++++++++++++++++++----------- + 1 file changed, 82 insertions(+), 31 deletions(-) + +diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c +index 516570e0a3..1638e1710e 100644 +--- a/util/ifdtool/ifdtool.c ++++ b/util/ifdtool/ifdtool.c +@@ -2143,6 +2143,7 @@ static void print_usage(const char *name) + " tgl - Tiger Lake\n" + " wbg - Wellsburg\n" + " -S | --setpchstrap Write a PCH strap\n" ++ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n" + " -V | --newvalue The new value to write into PCH strap specified by -S\n" + " -v | --version: print the version\n" + " -h | --help: print this help\n\n" +@@ -2151,6 +2152,60 @@ static void print_usage(const char *name) + "\n"); + } + ++static int ++get_region_type_string(const char *region_type_string) ++{ ++ if (!strcasecmp("Descriptor", region_type_string)) ++ return 0; ++ else if (!strcasecmp("BIOS", region_type_string)) ++ return 1; ++ else if (!strcasecmp("ME", region_type_string)) ++ return 2; ++ else if (!strcasecmp("GbE", region_type_string)) ++ return 3; ++ else if (!strcasecmp("Platform Data", region_type_string)) ++ return 4; ++ else if (!strcasecmp("Device Exp1", region_type_string)) ++ return 5; ++ else if (!strcasecmp("Secondary BIOS", region_type_string)) ++ return 6; ++ else if (!strcasecmp("Reserved", region_type_string)) ++ return 7; ++ else if (!strcasecmp("EC", region_type_string)) ++ return 8; ++ else if (!strcasecmp("Device Exp2", region_type_string)) ++ return 9; ++ else if (!strcasecmp("IE", region_type_string)) ++ return 10; ++ else if (!strcasecmp("10GbE_0", region_type_string)) ++ return 11; ++ else if (!strcasecmp("10GbE_1", region_type_string)) ++ return 12; ++ else if (!strcasecmp("PTT", region_type_string)) ++ return 15; ++ return -1; ++} ++ ++static void ++nuke(const char *filename, char *image, int size, int region_type) ++{ ++ int i; ++ struct region region; ++ const struct frba *frba = find_frba(image, size); ++ if (!frba) ++ exit(EXIT_FAILURE); ++ ++ region = get_region(frba, region_type); ++ if (region.size > 0) { ++ for (i = region.base; i <= region.limit; i++) { ++ if ((i + 1) > (size)) ++ break; ++ image[i] = 0xFF; ++ } ++ write_image(filename, image, size); ++ } ++} ++ + int main(int argc, char *argv[]) + { + int opt, option_index = 0; +@@ -2158,6 +2213,7 @@ int main(int argc, char *argv[]) + int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; + int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; + int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; ++ int mode_nuke = 0; + int mode_gpr0_disable = 0, mode_gpr0_enable = 0; + char *region_type_string = NULL, *region_fname = NULL; + const char *layout_fname = NULL; +@@ -2192,6 +2248,7 @@ int main(int argc, char *argv[]) + {"validate", 0, NULL, 't'}, + {"setpchstrap", 1, NULL, 'S'}, + {"newvalue", 1, NULL, 'V'}, ++ {"nuke", 1, NULL, 'N'}, + {0, 0, 0, 0} + }; + +@@ -2241,35 +2298,8 @@ int main(int argc, char *argv[]) + region_fname++; + // Descriptor, BIOS, ME, GbE, Platform + // valid type? +- if (!strcasecmp("Descriptor", region_type_string)) +- region_type = 0; +- else if (!strcasecmp("BIOS", region_type_string)) +- region_type = 1; +- else if (!strcasecmp("ME", region_type_string)) +- region_type = 2; +- else if (!strcasecmp("GbE", region_type_string)) +- region_type = 3; +- else if (!strcasecmp("Platform Data", region_type_string)) +- region_type = 4; +- else if (!strcasecmp("Device Exp1", region_type_string)) +- region_type = 5; +- else if (!strcasecmp("Secondary BIOS", region_type_string)) +- region_type = 6; +- else if (!strcasecmp("Reserved", region_type_string)) +- region_type = 7; +- else if (!strcasecmp("EC", region_type_string)) +- region_type = 8; +- else if (!strcasecmp("Device Exp2", region_type_string)) +- region_type = 9; +- else if (!strcasecmp("IE", region_type_string)) +- region_type = 10; +- else if (!strcasecmp("10GbE_0", region_type_string)) +- region_type = 11; +- else if (!strcasecmp("10GbE_1", region_type_string)) +- region_type = 12; +- else if (!strcasecmp("PTT", region_type_string)) +- region_type = 15; +- if (region_type == -1) { ++ if ((region_type = ++ get_region_type_string(region_type_string)) == -1) { + fprintf(stderr, "No such region type: '%s'\n\n", + region_type_string); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); +@@ -2441,6 +2471,22 @@ int main(int argc, char *argv[]) + case 't': + mode_validate = 1; + break; ++ case 'N': ++ region_type_string = strdup(optarg); ++ if (!region_type_string) { ++ fprintf(stderr, "No region specified\n"); ++ print_usage(argv[0]); ++ exit(EXIT_FAILURE); ++ } ++ if ((region_type = ++ get_region_type_string(region_type_string)) == -1) { ++ fprintf(stderr, "No such region type: '%s'\n\n", ++ region_type_string); ++ print_usage(argv[0]); ++ exit(EXIT_FAILURE); ++ } ++ mode_nuke = 1; ++ break; + case 'v': + print_version(); + exit(EXIT_SUCCESS); +@@ -2457,7 +2503,7 @@ int main(int argc, char *argv[]) + if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + + mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | + mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + +- (mode_gpr0_disable | mode_gpr0_enable)) > 1) { ++ (mode_gpr0_disable | mode_gpr0_enable) + mode_nuke) > 1) { + fprintf(stderr, "You may not specify more than one mode.\n\n"); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); + exit(EXIT_FAILURE); +@@ -2466,7 +2512,8 @@ int main(int argc, char *argv[]) + if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + + mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + + mode_locked + mode_unlocked + mode_density + mode_altmedisable + +- mode_validate + (mode_gpr0_disable | mode_gpr0_enable)) == 0) { ++ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + ++ mode_nuke) == 0) { + fprintf(stderr, "You need to specify a mode.\n\n"); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); + exit(EXIT_FAILURE); +@@ -2576,6 +2623,10 @@ int main(int argc, char *argv[]) + write_image(new_filename, image, size); + } + ++ if (mode_nuke) { ++ nuke(new_filename, image, size, region_type); ++ } ++ + if (mode_altmedisable) { + struct fpsba *fpsba = find_fpsba(image, size); + struct fmsba *fmsba = find_fmsba(image, size); +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch new file mode 100644 index 00000000..81b8e839 --- /dev/null +++ b/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -0,0 +1,292 @@ +From d97b865a2210e70583e8bf5ee3a73d3c131b29c1 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Sat, 2 Mar 2024 22:51:09 +0000 +Subject: [PATCH 1/4] nb/intel/haswell: make IOMMU a runtime option + +When I tested graphics cards on a coreboot port for Dell +OptiPlex 9020 SFF, I could not use a graphics card unless +I set iommu=off on the Linux cmdline. + +Coreboot's current behaviour is to check whether the CPU +has vt-d support and, if it does, initialise the IOMMU. + +This patch maintains the current behaviour by default, but +allows the user to turn *off* the IOMMU, even if vt-d is +supported by the host CPU. + +If iommu=Disable is specified, the check will not be +performed, and the IOMMU will be left disabled. This option +has been added to all current Haswell boards, though it is +recommended to leave the IOMMU turned on in most setups. + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/mainboard/asrock/b85m_pro4/cmos.default | 1 + + src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++ + src/mainboard/asrock/h81m-hds/cmos.default | 1 + + src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++ + src/mainboard/dell/optiplex_9020/cmos.default | 1 + + src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++ + src/mainboard/google/beltino/cmos.layout | 5 +++++ + src/mainboard/google/slippy/cmos.layout | 5 +++++ + src/mainboard/intel/baskingridge/cmos.layout | 4 ++++ + src/mainboard/lenovo/haswell/cmos.default | 1 + + src/mainboard/lenovo/haswell/cmos.layout | 3 +++ + src/mainboard/supermicro/x10slm-f/cmos.default | 1 + + src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++ + src/northbridge/intel/haswell/early_init.c | 5 +++++ + 14 files changed, 48 insertions(+) + +diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default +index 01bf20ad16..dfc8b80fb0 100644 +--- a/src/mainboard/asrock/b85m_pro4/cmos.default ++++ b/src/mainboard/asrock/b85m_pro4/cmos.default +@@ -4,3 +4,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Enable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout +index efdc333fc2..c9883ea71d 100644 +--- a/src/mainboard/asrock/b85m_pro4/cmos.layout ++++ b/src/mainboard/asrock/b85m_pro4/cmos.layout +@@ -11,6 +11,7 @@ + 395 4 e 4 debug_level + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail ++ 412 1 e 6 iommu + 984 16 h 0 check_sum + # ----------------------------------------------------------------- + +@@ -38,6 +39,8 @@ + 5 0 Disable + 5 1 Enable + 5 2 Keep ++ 6 0 Disable ++ 6 1 Enable + # ----------------------------------------------------------------- + + # ----------------------------------------------------------------- +diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default +index 01bf20ad16..dfc8b80fb0 100644 +--- a/src/mainboard/asrock/h81m-hds/cmos.default ++++ b/src/mainboard/asrock/h81m-hds/cmos.default +@@ -4,3 +4,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Enable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout +index c9ba76c78f..95ee3d36fb 100644 +--- a/src/mainboard/asrock/h81m-hds/cmos.layout ++++ b/src/mainboard/asrock/h81m-hds/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# enable or disable iommu ++412 1 e 6 iommu ++ + # coreboot config options: check sums + 984 16 h 0 check_sum + +@@ -52,6 +55,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index cd4046f1ab..c974022472 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -3,3 +3,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Disable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout +index c9ba76c78f..72ff9c4bee 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.layout ++++ b/src/mainboard/dell/optiplex_9020/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# turn iommu on or off ++412 1 e 6 iommu ++ + # coreboot config options: check sums + 984 16 h 0 check_sum + +@@ -52,6 +55,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout +index 78d44c1415..c143979ae1 100644 +--- a/src/mainboard/google/beltino/cmos.layout ++++ b/src/mainboard/google/beltino/cmos.layout +@@ -19,6 +19,9 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++# enable or disable iommu ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +50,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout +index 78d44c1415..c143979ae1 100644 +--- a/src/mainboard/google/slippy/cmos.layout ++++ b/src/mainboard/google/slippy/cmos.layout +@@ -19,6 +19,9 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++# enable or disable iommu ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +50,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout +index 78d44c1415..f2c602f541 100644 +--- a/src/mainboard/intel/baskingridge/cmos.layout ++++ b/src/mainboard/intel/baskingridge/cmos.layout +@@ -19,6 +19,8 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +49,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default +index 08db97c5a9..cc6b363cd9 100644 +--- a/src/mainboard/lenovo/haswell/cmos.default ++++ b/src/mainboard/lenovo/haswell/cmos.default +@@ -14,3 +14,4 @@ trackpoint=Enable + backlight=Keyboard + enable_dual_graphics=Disable + usb_always_on=Disable ++iommu=Enable +diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout +index 27915d3ab7..59df76b64c 100644 +--- a/src/mainboard/lenovo/haswell/cmos.layout ++++ b/src/mainboard/lenovo/haswell/cmos.layout +@@ -23,6 +23,7 @@ entries + + # coreboot config options: EC + 411 1 e 8 first_battery ++413 1 e 14 iommu + 415 1 e 1 wlan + 416 1 e 1 trackpoint + 417 1 e 1 fn_ctrl_swap +@@ -72,6 +73,8 @@ enumerations + 13 0 Disable + 13 1 AC and battery + 13 2 AC only ++14 0 Disable ++14 1 Enable + + # ----------------------------------------------------------------- + checksums +diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default +index 7ce38fb5d7..6049e7938a 100644 +--- a/src/mainboard/supermicro/x10slm-f/cmos.default ++++ b/src/mainboard/supermicro/x10slm-f/cmos.default +@@ -5,3 +5,4 @@ debug_level=Debug + nmi=Enable + power_on_after_fail=Keep + hide_ast2400=Disable ++iommu=Enable +diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout +index 38ba87aa45..24d39e97ee 100644 +--- a/src/mainboard/supermicro/x10slm-f/cmos.layout ++++ b/src/mainboard/supermicro/x10slm-f/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# enable or disable iommu ++412 1 e 6 iommu ++ + # coreboot config options: mainboard + 416 1 e 1 hide_ast2400 + +@@ -55,6 +58,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c +index e47deb5da6..1a7e0b1076 100644 +--- a/src/northbridge/intel/haswell/early_init.c ++++ b/src/northbridge/intel/haswell/early_init.c +@@ -5,6 +5,7 @@ + #include <device/mmio.h> + #include <device/pci_def.h> + #include <device/pci_ops.h> ++#include <option.h> + + #include "haswell.h" + +@@ -157,6 +158,10 @@ static void haswell_setup_misc(void) + static void haswell_setup_iommu(void) + { + const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); ++ u8 enable_iommu = get_uint_option("iommu", 1); ++ ++ if (!enable_iommu) ++ return; + + if (capid0_a & VTD_DISABLE) + return; +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch new file mode 100644 index 00000000..fbb40293 --- /dev/null +++ b/config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -0,0 +1,29 @@ +From 153ca1a43c2c978fa2b2b82d988b0f838953cfb9 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Sat, 2 Mar 2024 23:00:09 +0000 +Subject: [PATCH 2/4] dell/optiplex_9020: Disable IOMMU by default + +Needed to make graphics cards work. Turning it on is +recommended if only using iGPU, otherwise leave it off +by default. The IOMMU is extremely buggy when a graphics +card is used. Leaving it off by default will ensure that +the default ROM images in Libreboot will work on any setup. + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/mainboard/dell/optiplex_9020/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index c974022472..a0acd7b6bb 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -3,4 +3,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Disable + power_on_after_fail=Disable +-iommu=Enable ++iommu=Disable +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch b/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch new file mode 100644 index 00000000..e2db6a17 --- /dev/null +++ b/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch @@ -0,0 +1,602 @@ +From 05cc767d1398f91533e87db5ceaa0aabb7918425 Mon Sep 17 00:00:00 2001 +From: Mate Kukri <kukri.mate@gmail.com> +Date: Thu, 18 Apr 2024 20:28:45 +0100 +Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization + +There are 4 different chassis types specified by vendor firmware, each +with a slightly different HWM configuration. + +The chassis type to use is determined at runtime by reading a set of +4 PCH GPIOs: 70, 38, 17, and 1. + +Additionally vendor firmware also provides an option to run the fans at +full speed. This is substituted with a coreboot nvram option in this +implementation. + +This was tested to make fan control work on my OptiPlex 7020 SFF. + +NOTE: This is superficially similar to the OptiPlex 9010's SCH5545 +however the OptiPlex 9020's SCH5555 does not use externally +programmed EC firmware. + +Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 +Signed-off-by: Mate Kukri <kukri.mate@gmail.com> +--- + src/mainboard/dell/optiplex_9020/Makefile.mk | 3 +- + src/mainboard/dell/optiplex_9020/bootblock.c | 25 +- + src/mainboard/dell/optiplex_9020/cmos.default | 1 + + src/mainboard/dell/optiplex_9020/cmos.layout | 5 +- + src/mainboard/dell/optiplex_9020/mainboard.c | 387 ++++++++++++++++++ + src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++ + src/mainboard/dell/optiplex_9020/sch5555_ec.h | 10 + + 7 files changed, 463 insertions(+), 22 deletions(-) + create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c + create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h + +diff --git a/src/mainboard/dell/optiplex_9020/Makefile.mk b/src/mainboard/dell/optiplex_9020/Makefile.mk +index 6ca2f2afaa..08e2e53577 100644 +--- a/src/mainboard/dell/optiplex_9020/Makefile.mk ++++ b/src/mainboard/dell/optiplex_9020/Makefile.mk +@@ -2,4 +2,5 @@ + + romstage-y += gpio.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +-bootblock-y += bootblock.c ++ramstage-y += sch5555_ec.c ++bootblock-y += bootblock.c sch5555_ec.c +diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c +index 2837cf9cf1..e5e759273e 100644 +--- a/src/mainboard/dell/optiplex_9020/bootblock.c ++++ b/src/mainboard/dell/optiplex_9020/bootblock.c +@@ -4,29 +4,14 @@ + #include <device/pnp_ops.h> + #include <superio/smsc/sch555x/sch555x.h> + #include <southbridge/intel/lynxpoint/pch.h> +- +-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) +-{ +- // Clear EC-to-Host mailbox +- uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); +- outb(tmp, SCH555x_EMI_IOBASE + 1); +- +- // Send address and value to the EC +- sch555x_emi_write16(0, (addr1 * 2) | 0x101); +- sch555x_emi_write32(4, val | (addr2 << 16)); +- +- // Wait for acknowledgement message from EC +- outb(1, SCH555x_EMI_IOBASE); +- size_t timeout = 0; +- do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0); +-} ++#include "sch5555_ec.h" + + struct ec_init_entry { + uint16_t addr; + uint8_t val; + }; + +-static void ec_init(void) ++static void bootblock_ec_init(void) + { + /* + * Tables from CORE_PEI +@@ -108,9 +93,9 @@ void mainboard_config_superio(void) + outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); + outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); + +- // Magic EC init +- ec_init(); ++ // Perform bootblock EC initialization ++ bootblock_ec_init(); + +- // Magic EC init is needed for UART1 initialization to work ++ // Bootblock EC initialization is required for UART1 to work + sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + } +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index a0acd7b6bb..9e02534c16 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -4,3 +4,4 @@ debug_level=Debug + nmi=Disable + power_on_after_fail=Disable + iommu=Disable ++fan_full_speed=Disable +diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout +index 72ff9c4bee..4a1496a878 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.layout ++++ b/src/mainboard/dell/optiplex_9020/cmos.layout +@@ -22,7 +22,10 @@ entries + 409 2 e 5 power_on_after_fail + + # turn iommu on or off +-412 1 e 6 iommu ++411 1 e 6 iommu ++ ++# coreboot config options: EC ++412 1 e 1 fan_full_speed + + # coreboot config options: check sums + 984 16 h 0 check_sum +diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c +index c834fea5d3..0b7829c736 100644 +--- a/src/mainboard/dell/optiplex_9020/mainboard.c ++++ b/src/mainboard/dell/optiplex_9020/mainboard.c +@@ -1,7 +1,12 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + ++#include <bootstate.h> ++#include <cpu/x86/msr.h> + #include <device/device.h> + #include <drivers/intel/gma/int15.h> ++#include <option.h> ++#include <southbridge/intel/common/gpio.h> ++#include "sch5555_ec.h" + + static void mainboard_enable(struct device *dev) + { +@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev) + struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + }; ++ ++#define HWM_TAB_ADD_TEMP_TARGET 1 ++#define HWM_TAB_PKG_POWER_ANY 0xffff ++#define CHASSIS_TYPE_UNKNOWN 0xff ++ ++struct hwm_tab_entry { ++ uint16_t addr; ++ uint8_t val; ++ uint8_t flags; ++ uint16_t pkg_power; ++}; ++ ++struct hwm_tab_entry HWM_TAB3[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x8a, 0, 0x0010 }, ++ { 0x086, 0x4c, 0, 0x0010 }, ++ { 0x08a, 0x66, 0, 0x0010 }, ++ { 0x08b, 0x5b, 0, 0x0010 }, ++ { 0x090, 0x65, 0, 0xffff }, ++ { 0x091, 0x70, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0e, 0, 0xffff }, ++ { 0x0a1, 0x0e, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x86, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x9a, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x99, 0, 0xffff }, ++ { 0x280, 0xa0, 0, 0x0010 }, ++ { 0x281, 0x0f, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x68, 0, 0x0010 }, ++ { 0x289, 0x10, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB4[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x99, 0, 0x0020 }, ++ { 0x085, 0xad, 0, 0x0010 }, ++ { 0x086, 0x1c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x41, 0, 0x0010 }, ++ { 0x08b, 0x76, 0, 0x0020 }, ++ { 0x08b, 0x8b, 0, 0x0010 }, ++ { 0x090, 0x5e, 0, 0xffff }, ++ { 0x091, 0x5e, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0a, 0, 0xffff }, ++ { 0x0a1, 0x0a, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x90, 0, 0xffff }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x28, 0, 0x0020 }, ++ { 0x289, 0x0a, 0, 0x0020 }, ++ { 0x288, 0x28, 0, 0x0010 }, ++ { 0x289, 0x0a, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB5[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x66, 0, 0x0020 }, ++ { 0x085, 0x5d, 0, 0x0010 }, ++ { 0x086, 0x1c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x41, 0, 0x0010 }, ++ { 0x08b, 0x76, 0, 0x0020 }, ++ { 0x08b, 0x80, 0, 0x0010 }, ++ { 0x090, 0x5d, 0, 0x0020 }, ++ { 0x090, 0x5e, 0, 0x0010 }, ++ { 0x091, 0x5e, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa3, 0, 0x0020 }, ++ { 0x098, 0xa4, 0, 0x0010 }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x08, 0, 0xffff }, ++ { 0x0a1, 0x0a, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x98, 0, 0x0020 }, ++ { 0x1be, 0x90, 0, 0x0010 }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x28, 0, 0x0020 }, ++ { 0x289, 0x0a, 0, 0x0020 }, ++ { 0x288, 0x28, 0, 0x0010 }, ++ { 0x289, 0x0a, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB6[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x98, 0, 0xffff }, ++ { 0x086, 0x3c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x3d, 0, 0x0010 }, ++ { 0x08b, 0x44, 0, 0x0020 }, ++ { 0x08b, 0x51, 0, 0x0010 }, ++ { 0x090, 0x61, 0, 0xffff }, ++ { 0x091, 0x6d, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0x9f, 0, 0x0020 }, ++ { 0x098, 0xa4, 0, 0x0010 }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0e, 0, 0xffff }, ++ { 0x0a1, 0x0e, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9b, 0, 0x0020 }, ++ { 0x0b0, 0x98, 0, 0x0010 }, ++ { 0x0b3, 0x9a, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x9a, 0, 0x0020 }, ++ { 0x1be, 0x96, 0, 0x0010 }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x94, 0, 0x0020 }, ++ { 0x289, 0x11, 0, 0x0020 }, ++ { 0x288, 0x94, 0, 0x0010 }, ++ { 0x289, 0x11, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++static uint8_t get_chassis_type(void) ++{ ++ uint8_t gpio_chassis_type; ++ ++ // Read chassis type from GPIO ++ gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 | ++ get_gpio(17) << 1 | get_gpio(1); ++ ++ printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type); ++ ++ // Turn it into internal chassis index ++ switch (gpio_chassis_type) { ++ case 0x08: ++ case 0x0a: ++ return 4; ++ case 0x0b: ++ return 3; ++ case 0x0c: ++ return 5; ++ case 0x0d: // SFF ++ case 0x0e: ++ case 0x0f: ++ return 6; ++ default: ++ return CHASSIS_TYPE_UNKNOWN; ++ } ++ ++} ++ ++static uint8_t get_temp_target(void) ++{ ++ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; ++ if (!val) ++ val = 20; ++ return 0x95 - val; ++} ++ ++static uint16_t get_pkg_power(void) ++{ ++ uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf; ++ if (rapl_power_unit) ++ rapl_power_unit = 2 << (rapl_power_unit - 1); ++ uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff; ++ if (pkg_power_info / rapl_power_unit > 0x41) ++ return 32; ++ else ++ return 16; ++} ++ ++static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size) ++{ ++ uint8_t temp_target = get_temp_target(); ++ uint16_t pkg_power = get_pkg_power(); ++ ++ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); ++ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); ++ ++ for (size_t i = 0; i < size; ++i) { ++ // Skip entry if it doesn't apply for this package power ++ if (arr[i].pkg_power != pkg_power && ++ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) ++ continue; ++ ++ uint8_t val = arr[i].val; ++ ++ // Add temp target to value if requested (current tables never do) ++ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) ++ val += temp_target; ++ ++ // Perform write ++ ec_write(1, arr[i].addr, val); ++ ++ } ++} ++ ++static void sch5555_ec_hwm_init(void *arg) ++{ ++ uint8_t chassis_type, saved_2fc; ++ ++ printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n"); ++ ++ saved_2fc = ec_read(1, 0x2fc); ++ ec_write(1, 0x2fc, 0xa0); ++ ec_write(1, 0x2fd, 0x32); ++ ++ chassis_type = get_chassis_type(); ++ ++ if (chassis_type != CHASSIS_TYPE_UNKNOWN) { ++ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); ++ } else { ++ printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n"); ++ } ++ ++ // Apply HWM table based on chassis type ++ switch (chassis_type) { ++ case 3: ++ apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3)); ++ break; ++ case 4: ++ apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4)); ++ break; ++ case 5: ++ apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5)); ++ break; ++ case 6: ++ apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6)); ++ break; ++ } ++ ++ // NOTE: vendor firmware applies these when "max core address" > 2 ++ // i think this is always the case ++ ec_write(1, 0x9e, 0x30); ++ ec_write(1, 0xeb, ec_read(1, 0xea)); ++ ++ ec_write(1, 0x2fc, saved_2fc); ++ ++ // Apply full speed fan config if requested or if the chassis type is unknown ++ if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) { ++ printk(BIOS_DEBUG, "Setting full fan speed\n"); ++ ec_write(1, 0x80, 0x60 | ec_read(1, 0x80)); ++ ec_write(1, 0x81, 0x60 | ec_read(1, 0x81)); ++ } ++ ++ ec_read(1, 0xb8); ++ ++ if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) { ++ ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb); ++ ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb); ++ ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb); ++ ec_write(1, 0x8a, 0x99); ++ ec_write(1, 0x8b, 0x47); ++ ec_write(1, 0x8c, 0x91); ++ } ++} ++ ++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); +diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c +new file mode 100644 +index 0000000000..a1067ac063 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c +@@ -0,0 +1,54 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <arch/io.h> ++#include <device/pnp_ops.h> ++#include <superio/smsc/sch555x/sch555x.h> ++#include "sch5555_ec.h" ++ ++uint8_t ec_read(uint8_t addr1, uint16_t addr2) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++ ++ // read result ++ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); ++ return inb(SCH555x_EMI_IOBASE + 4); ++} ++ ++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address and value ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t retry = 0; retry < 0xfff; ++retry) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++} +diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h +new file mode 100644 +index 0000000000..7e399e8e74 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h +@@ -0,0 +1,10 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __SCH5555_EC_H__ ++#define __SCH5555_EC_H__ ++ ++uint8_t ec_read(uint8_t addr1, uint16_t addr2); ++ ++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val); ++ ++#endif +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch new file mode 100644 index 00000000..fb112f8c --- /dev/null +++ b/config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -0,0 +1,51 @@ +From ae494dc1b1dde92ec42390b85ced0ffe816f5110 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Sat, 6 Apr 2024 01:22:47 +0100 +Subject: [PATCH 4/4] nb/haswell: Fully disable iGPU when dGPU is used + +My earlier patch disabled decode *and* disabled the iGPU itself, but +a subsequent revision disabled only VGA decode. Upon revisiting, I +found that, actually, yes, you also need to disable the iGPU entirely. + +Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU. +With this patch, the iGPU is completely disabled when you install a +graphics card, but the iGPU is available to use when no graphics card +is present. + +For more context, see: + +Author: Leah Rowe <info@minifree.org> +Date: Fri Feb 23 13:33:31 2024 +0000 + + nb/haswell: Disable iGPU when dGPU is used + +And look at the Gerrit comments: + +https://review.coreboot.org/c/coreboot/+/80717/ + +So, my original submission on change 80717 was actually correct. +This patch fixes the issue. I tested on iGPU and dGPU, with both +broadwell and haswell mrc.bin. + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/northbridge/intel/haswell/gma.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c +index 9e9f9804f5..526a51aff0 100644 +--- a/src/northbridge/intel/haswell/gma.c ++++ b/src/northbridge/intel/haswell/gma.c +@@ -464,6 +464,9 @@ static void gma_func0_disable(struct device *dev) + { + /* Disable VGA decode */ + pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); ++ ++ /* Required or else the graphics card doesn't work */ ++ dev->enabled = 0; + } + + static struct device_operations gma_func0_ops = { +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch b/config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch new file mode 100644 index 00000000..52147426 --- /dev/null +++ b/config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch @@ -0,0 +1,49 @@ +From 355536155898e649fa50277136ccd2df53a52bb1 Mon Sep 17 00:00:00 2001 +From: Mate Kukri <kukri.mate@gmail.com> +Date: Wed, 10 Apr 2024 20:31:35 +0100 +Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device + +These machines come with a TPM1.2 device by default. It is somewhat +obsolete these days, but there is no harm in enabling it. + +Change-Id: Iec05321862aed58695c256b00494e5953219786d +Signed-off-by: Mate Kukri <kukri.mate@gmail.com> +Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827 +Reviewed-by: Angel Pons <th3fanbus@gmail.com> +Tested-by: build bot (Jenkins) <no-reply@coreboot.org> +--- + src/mainboard/dell/optiplex_9020/Kconfig | 2 ++ + src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++ + 2 files changed, 5 insertions(+) + +diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig +index 2de4a9abd6..38c3281e70 100644 +--- a/src/mainboard/dell/optiplex_9020/Kconfig ++++ b/src/mainboard/dell/optiplex_9020/Kconfig +@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION ++ select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT +diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb +index dce5869478..841285bb9c 100644 +--- a/src/mainboard/dell/optiplex_9020/devicetree.cb ++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb +@@ -70,6 +70,9 @@ chip northbridge/intel/haswell + device pnp 2e.b off end # Floppy Controller + device pnp 2e.11 off end # Parallel Port + end ++ chip drivers/pc80/tpm ++ device pnp 0c31.0 on end ++ end + end + device pci 1f.2 on end # SATA controller 1 + device pci 1f.3 on end # SMBus +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch b/config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch deleted file mode 100644 index 9f22c06d..00000000 --- a/config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 29c1116ebd5879568010a8386e4838294a78b408 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 16 Jul 2023 03:48:23 +0100 -Subject: [PATCH 1/1] coreboot/haswell: fix acpica downloads - -the upstream link died. i now host the relevant acpica -tarball myself, on libreboot rsync. this patch makes -coreboot crossgcc use that - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/crossgcc/buildgcc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 3c4b10cc92..0c4262b7b1 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -52,7 +52,7 @@ MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz" - MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" - GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz" - BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz" --IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz" -+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz" - # CLANG toolchain archive locations - LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" - CLANG_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/clang-${CLANG_VERSION}.src.tar.xz" --- -2.40.1 - diff --git a/config/coreboot/haswell/patches/0028-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/haswell/patches/0028-use-mirrorservice.org-for-gcc-downloads.patch deleted file mode 100644 index 0d0a66a1..00000000 --- a/config/coreboot/haswell/patches/0028-use-mirrorservice.org-for-gcc-downloads.patch +++ /dev/null @@ -1,36 +0,0 @@ -From ca1bd48a87ab46ebfb444b0e092442bf6270ec7a Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 5 Nov 2023 23:19:42 +0000 -Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads - -the gnu.org 302 redirect often fails - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/crossgcc/buildgcc | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index d4cc8b2a24..526940acfa 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -47,11 +47,11 @@ NASM_VERSION=2.15.05 - # These are sanitized by the jenkins toolchain test builder, so if - # a completely new URL is added here, it probably needs to be added - # to the jenkins build as well, or the builder won't download it. --GMP_ARCHIVE="https://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz" --MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz" --MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" --GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz" --BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz" -+GMP_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp/gmp-${GMP_VERSION}.tar.xz" -+MPFR_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr/mpfr-${MPFR_VERSION}.tar.xz" -+MPC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc/mpc-${MPC_VERSION}.tar.gz" -+GCC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz" -+BINUTILS_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.xz" - IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz" - # CLANG toolchain archive locations - LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0029-ifdtool-nuke-option.patch b/config/coreboot/haswell/patches/0029-ifdtool-nuke-option.patch deleted file mode 100644 index 18d6a21e..00000000 --- a/config/coreboot/haswell/patches/0029-ifdtool-nuke-option.patch +++ /dev/null @@ -1,194 +0,0 @@ -From 6f94e9aa38a5d6589b1a64642dfcb5ccbf90b8d3 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Tue, 9 Jan 2024 01:53:54 +0000 -Subject: [PATCH 1/1] ifdtool nuke option - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++----------- - 1 file changed, 83 insertions(+), 31 deletions(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index e97efcc206..ee27e7f2e6 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -1711,6 +1711,7 @@ static void print_usage(const char *name) - " tgl - Tiger Lake\n" - " -S | --setpchstrap Write a PCH strap\n" - " -V | --newvalue The new value to write into PCH strap specified by -S\n" -+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" - "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, " -@@ -1718,6 +1719,60 @@ static void print_usage(const char *name) - "\n"); - } - -+static int -+get_region_type_string(const char *region_type_string) -+{ -+ if (!strcasecmp("Descriptor", region_type_string)) -+ return 0; -+ else if (!strcasecmp("BIOS", region_type_string)) -+ return 1; -+ else if (!strcasecmp("ME", region_type_string)) -+ return 2; -+ else if (!strcasecmp("GbE", region_type_string)) -+ return 3; -+ else if (!strcasecmp("Platform Data", region_type_string)) -+ return 4; -+ else if (!strcasecmp("Device Exp1", region_type_string)) -+ return 5; -+ else if (!strcasecmp("Secondary BIOS", region_type_string)) -+ return 6; -+ else if (!strcasecmp("Reserved", region_type_string)) -+ return 7; -+ else if (!strcasecmp("EC", region_type_string)) -+ return 8; -+ else if (!strcasecmp("Device Exp2", region_type_string)) -+ return 9; -+ else if (!strcasecmp("IE", region_type_string)) -+ return 10; -+ else if (!strcasecmp("10GbE_0", region_type_string)) -+ return 11; -+ else if (!strcasecmp("10GbE_1", region_type_string)) -+ return 12; -+ else if (!strcasecmp("PTT", region_type_string)) -+ return 15; -+ return -1; -+} -+ -+static void -+nuke(const char *filename, char *image, int size, int region_type) -+{ -+ int i; -+ region_t region; -+ const frba_t *frba = find_frba(image, size); -+ if (!frba) -+ exit(EXIT_FAILURE); -+ -+ region = get_region(frba, region_type); -+ if (region.size > 0) { -+ for (i = region.base; i <= region.limit; i++) { -+ if ((i + 1) > (size)) -+ break; -+ image[i] = 0xFF; -+ } -+ write_image(filename, image, size); -+ } -+} -+ - int main(int argc, char *argv[]) - { - int opt, option_index = 0; -@@ -1725,6 +1780,7 @@ int main(int argc, char *argv[]) - int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; - int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; - int mode_read = 0, mode_altmedisable = 0, altmedisable = 0; -+ int mode_nuke = 0; - char *region_type_string = NULL, *region_fname = NULL; - const char *layout_fname = NULL; - char *new_filename = NULL; -@@ -1755,6 +1811,7 @@ int main(int argc, char *argv[]) - {"validate", 0, NULL, 't'}, - {"setpchstrap", 1, NULL, 'S'}, - {"newvalue", 1, NULL, 'V'}, -+ {"nuke", 1, NULL, 'N'}, - {0, 0, 0, 0} - }; - -@@ -1795,35 +1852,8 @@ int main(int argc, char *argv[]) - region_fname++; - // Descriptor, BIOS, ME, GbE, Platform - // valid type? -- if (!strcasecmp("Descriptor", region_type_string)) -- region_type = 0; -- else if (!strcasecmp("BIOS", region_type_string)) -- region_type = 1; -- else if (!strcasecmp("ME", region_type_string)) -- region_type = 2; -- else if (!strcasecmp("GbE", region_type_string)) -- region_type = 3; -- else if (!strcasecmp("Platform Data", region_type_string)) -- region_type = 4; -- else if (!strcasecmp("Device Exp1", region_type_string)) -- region_type = 5; -- else if (!strcasecmp("Secondary BIOS", region_type_string)) -- region_type = 6; -- else if (!strcasecmp("Reserved", region_type_string)) -- region_type = 7; -- else if (!strcasecmp("EC", region_type_string)) -- region_type = 8; -- else if (!strcasecmp("Device Exp2", region_type_string)) -- region_type = 9; -- else if (!strcasecmp("IE", region_type_string)) -- region_type = 10; -- else if (!strcasecmp("10GbE_0", region_type_string)) -- region_type = 11; -- else if (!strcasecmp("10GbE_1", region_type_string)) -- region_type = 12; -- else if (!strcasecmp("PTT", region_type_string)) -- region_type = 15; -- if (region_type == -1) { -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { - fprintf(stderr, "No such region type: '%s'\n\n", - region_type_string); - print_usage(argv[0]); -@@ -1988,6 +2018,22 @@ int main(int argc, char *argv[]) - case 't': - mode_validate = 1; - break; -+ case 'N': -+ region_type_string = strdup(optarg); -+ if (!region_type_string) { -+ fprintf(stderr, "No region specified\n"); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { -+ fprintf(stderr, "No such region type: '%s'\n\n", -+ region_type_string); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ mode_nuke = 1; -+ break; - case 'v': - print_version(); - exit(EXIT_SUCCESS); -@@ -2003,7 +2049,8 @@ int main(int argc, char *argv[]) - - if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_setstrap + - mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked | -- mode_locked) + mode_altmedisable + mode_validate) > 1) { -+ mode_locked) + mode_altmedisable + mode_validate + -+ mode_nuke) > 1) { - fprintf(stderr, "You may not specify more than one mode.\n\n"); - print_usage(argv[0]); - exit(EXIT_FAILURE); -@@ -2011,7 +2058,8 @@ int main(int argc, char *argv[]) - - if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_setstrap + - mode_newlayout + mode_spifreq + mode_em100 + mode_locked + -- mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) { -+ mode_unlocked + mode_density + mode_altmedisable + -+ mode_validate + mode_nuke) == 0) { - fprintf(stderr, "You need to specify a mode.\n\n"); - print_usage(argv[0]); - exit(EXIT_FAILURE); -@@ -2109,6 +2157,10 @@ int main(int argc, char *argv[]) - write_image(new_filename, image, size); - } - -+ if (mode_nuke) { -+ nuke(new_filename, image, size, region_type); -+ } -+ - if (mode_altmedisable) { - fpsba_t *fpsba = find_fpsba(image, size); - fmsba_t *fmsba = find_fmsba(image, size); --- -2.39.2 - diff --git a/config/coreboot/haswell/target.cfg b/config/coreboot/haswell/target.cfg index b3196341..a38399e4 100644 --- a/config/coreboot/haswell/target.cfg +++ b/config/coreboot/haswell/target.cfg @@ -1,3 +1,3 @@ tree="haswell" -rev="1411ecf6f0b2c7395bcb96b856dcfdddb1b0c81b" +rev="b7341da19133991efd29880849bdaab29a6e243d" xarch="i386-elf" diff --git a/config/coreboot/hp2170p_16mb/target.cfg b/config/coreboot/hp2170p_16mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp2170p_16mb/target.cfg +++ b/config/coreboot/hp2170p_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp2560p_8mb/target.cfg b/config/coreboot/hp2560p_8mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp2560p_8mb/target.cfg +++ b/config/coreboot/hp2560p_8mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp2570p_16mb/target.cfg b/config/coreboot/hp2570p_16mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp2570p_16mb/target.cfg +++ b/config/coreboot/hp2570p_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8200sff_4mb/target.cfg b/config/coreboot/hp8200sff_4mb/target.cfg index 0badb4fb..12afcd76 100644 --- a/config/coreboot/hp8200sff_4mb/target.cfg +++ b/config/coreboot/hp8200sff_4mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8200sff_8mb/target.cfg b/config/coreboot/hp8200sff_8mb/target.cfg index 0badb4fb..12afcd76 100644 --- a/config/coreboot/hp8200sff_8mb/target.cfg +++ b/config/coreboot/hp8200sff_8mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp820g2_12mb/target.cfg b/config/coreboot/hp820g2_12mb/target.cfg index 8688df3f..e19a0d14 100644 --- a/config/coreboot/hp820g2_12mb/target.cfg +++ b/config/coreboot/hp820g2_12mb/target.cfg @@ -5,3 +5,5 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" +status="stable" diff --git a/config/coreboot/hp8300cmt_16mb/target.cfg b/config/coreboot/hp8300cmt_16mb/target.cfg index 0badb4fb..12afcd76 100644 --- a/config/coreboot/hp8300cmt_16mb/target.cfg +++ b/config/coreboot/hp8300cmt_16mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8300usdt_16mb/target.cfg b/config/coreboot/hp8300usdt_16mb/target.cfg index 0badb4fb..12afcd76 100644 --- a/config/coreboot/hp8300usdt_16mb/target.cfg +++ b/config/coreboot/hp8300usdt_16mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8460pintel_8mb/target.cfg b/config/coreboot/hp8460pintel_8mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp8460pintel_8mb/target.cfg +++ b/config/coreboot/hp8460pintel_8mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8470pintel_16mb/target.cfg b/config/coreboot/hp8470pintel_16mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp8470pintel_16mb/target.cfg +++ b/config/coreboot/hp8470pintel_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8560w_8mb/target.cfg b/config/coreboot/hp8560w_8mb/target.cfg index ae56c735..a352b46d 100644 --- a/config/coreboot/hp8560w_8mb/target.cfg +++ b/config/coreboot/hp8560w_8mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="unstable" diff --git a/config/coreboot/hp9470m_16mb/target.cfg b/config/coreboot/hp9470m_16mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp9470m_16mb/target.cfg +++ b/config/coreboot/hp9470m_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch new file mode 100644 index 00000000..a06a5058 --- /dev/null +++ b/config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch @@ -0,0 +1,23 @@ +From 4c5971a6fcf7e948f7df4d0ce2ab0751060cb2ca Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@retroboot.org> +Date: Fri, 19 Mar 2021 05:54:58 +0000 +Subject: [PATCH 01/18] apple/macbook21: Set default VRAM to 64MiB instead of + 8MiB + +--- + src/mainboard/apple/macbook21/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default +index cf1bc4566e..dc0df3b6d6 100644 +--- a/src/mainboard/apple/macbook21/cmos.default ++++ b/src/mainboard/apple/macbook21/cmos.default +@@ -5,4 +5,4 @@ boot_devices='' + boot_default=0x40 + cmos_defaults_loaded=Yes + lpt=Enable +-gfx_uma_size=8M ++gfx_uma_size=64M +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch new file mode 100644 index 00000000..57c32ec7 --- /dev/null +++ b/config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch @@ -0,0 +1,68 @@ +From ff523fd40649b72512b0f1253701509d83ca4a8d Mon Sep 17 00:00:00 2001 +From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> +Date: Wed, 27 Oct 2021 13:36:01 +0200 +Subject: [PATCH 02/18] add c3 and clockgen to apple/macbook21 + +--- + src/mainboard/apple/macbook21/Kconfig | 1 + + src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++ + src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++ + 3 files changed, 20 insertions(+) + +diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig +index 5f5ffde588..27377b737c 100644 +--- a/src/mainboard/apple/macbook21/Kconfig ++++ b/src/mainboard/apple/macbook21/Kconfig +@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select I945_LVDS ++ select DRIVERS_I2C_CK505 + + config MAINBOARD_DIR + default "apple/macbook21" +diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c +index 13d06f0839..88b8669c61 100644 +--- a/src/mainboard/apple/macbook21/cstates.c ++++ b/src/mainboard/apple/macbook21/cstates.c +@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = { + .addrh = 0, + } + }, ++ { ++ .ctype = 3, ++ .latency = 17, ++ .power = 250, ++ .resource = { ++ .space_id = ACPI_ADDRESS_SPACE_FIXED, ++ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, ++ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, ++ .access_size = ACPI_ACCESS_SIZE_UNDEFINED, ++ .addrl = 0x20, ++ .addrh = 0, ++ } ++ }, + }; + + int get_cst_entries(const acpi_cstate_t **entries) +diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb +index dd701da7ed..5587c48d1f 100644 +--- a/src/mainboard/apple/macbook21/devicetree.cb ++++ b/src/mainboard/apple/macbook21/devicetree.cb +@@ -100,7 +100,13 @@ chip northbridge/intel/i945 + end + device pci 1f.3 on # SMBUS + subsystemid 0x8086 0x7270 ++ chip drivers/i2c/ck505 ++ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }" ++ register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }" ++ device i2c 69 on end ++ end + end ++ + end + end + end +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch new file mode 100644 index 00000000..d8ca5b1f --- /dev/null +++ b/config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch @@ -0,0 +1,23 @@ +From fe79712702002bf2044227d6c3cef7ae022e3539 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@osboot.org> +Date: Sun, 3 Jan 2021 03:34:01 +0000 +Subject: [PATCH 03/18] lenovo/x60: 64MiB Video RAM changed to default + (previously it was 8MiB) + +--- + src/mainboard/lenovo/x60/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default +index 5c3576d1f3..88170a1aab 100644 +--- a/src/mainboard/lenovo/x60/cmos.default ++++ b/src/mainboard/lenovo/x60/cmos.default +@@ -15,4 +15,4 @@ trackpoint=Enable + sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable +-gfx_uma_size=8M ++gfx_uma_size=64M +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch new file mode 100644 index 00000000..630e68a6 --- /dev/null +++ b/config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch @@ -0,0 +1,22 @@ +From 79440902866bdafeec651476a5a0e51d42b43b21 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <leah@osboot.org> +Date: Mon, 22 Feb 2021 22:16:59 +0000 +Subject: [PATCH 04/18] lenovo/t60: make 64MiB VRAM the default in cmos.default + +--- + src/mainboard/lenovo/t60/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default +index af865f16da..7f03157df7 100644 +--- a/src/mainboard/lenovo/t60/cmos.default ++++ b/src/mainboard/lenovo/t60/cmos.default +@@ -15,4 +15,4 @@ trackpoint=Enable + sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable +-gfx_uma_size=8M ++gfx_uma_size=64M +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch b/config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch new file mode 100644 index 00000000..dcb28780 --- /dev/null +++ b/config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch @@ -0,0 +1,34 @@ +From 5d8fc92948782e9837b26ee8cdfaa88f41fce174 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Fri, 26 Apr 2024 09:16:57 +0100 +Subject: [PATCH 1/1] buildgcc: use mirrorservice for gnu toolchains + +Signed-off-by: Leah Rowe <info@minifree.org> +--- + util/crossgcc/buildgcc | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc +index 0de27ed6e8..0faea86894 100755 +--- a/util/crossgcc/buildgcc ++++ b/util/crossgcc/buildgcc +@@ -66,11 +66,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" + # to the jenkins build as well, or the builder won't download it. + + # GCC toolchain archive locations +-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" +-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" +-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" +-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" +-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" ++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp" ++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" ++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" ++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" ++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" + IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" + # CLANG toolchain archive locations + LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch b/config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch new file mode 100644 index 00000000..e11e33da --- /dev/null +++ b/config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch @@ -0,0 +1,56 @@ +From 412f1d68c610f69384b156f09f0b326af984b7cc Mon Sep 17 00:00:00 2001 +From: Bill XIE <persmule@hardenedlinux.org> +Date: Sat, 7 Oct 2023 01:32:51 +0800 +Subject: [PATCH 1/2] drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 + resume + +After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS +defaults to extend to bank 1"), Thinkpad X200 with +CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via +bisect). + +Further inspection shows that DRAM training result of GM45 is stored +in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume +to restore, but it will be erased by sanitize_cmos(), which now clears +both bank 0 and bank 1, leaving only "untrained" result restored, so s3 +resume will fail. + +However, resetting CMOS seems unnecessary during s3 resume. Now, +cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true. + +Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from + s3 again with these changes. + +Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b +Signed-off-by: Bill XIE <persmule@hardenedlinux.org> +Reviewed-on: https://review.coreboot.org/c/coreboot/+/78288 +Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> +Tested-by: build bot (Jenkins) <no-reply@coreboot.org> +--- + src/drivers/pc80/rtc/option.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c +index e8e2345133..e6cfa175ad 100644 +--- a/src/drivers/pc80/rtc/option.c ++++ b/src/drivers/pc80/rtc/option.c +@@ -1,5 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + ++#include <acpi/acpi.h> + #include <console/console.h> + #include <string.h> + #include <cbfs.h> +@@ -200,7 +201,8 @@ void sanitize_cmos(void) + { + const unsigned char *cmos_default; + const bool cmos_need_reset = +- CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid(); ++ (CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid()) ++ && !acpi_is_wakeup_s3(); + size_t length = 128; + size_t i; + +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch b/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch new file mode 100644 index 00000000..1a614db7 --- /dev/null +++ b/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch @@ -0,0 +1,51 @@ +From 0bc5a67f926e193a429cce4028fb382c49fa08f8 Mon Sep 17 00:00:00 2001 +From: Bill XIE <persmule@hardenedlinux.org> +Date: Fri, 3 Nov 2023 12:34:01 +0800 +Subject: [PATCH 2/2] drivers/pc80/rtc/option.c: Reset only CMOS range covered + by checksum + +Proposed in the comment of commit 29030d0f3dad +("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), +during sanitize_cmos(), only reset CMOS range covered by checksum and +the checksum itself from the file cmos.default in CBFS, in order to +prevent other runtime data in CMOS (e.g. the DRAM training data on +GM45 platforms for s3 resume) being erased. + +Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: + Bring HEAP_SIZE to a common, large value"), which is already + before my commit 29030d0f3dad , Thinkpad X200 with + CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, + indicating that DRAM training data are no longer erased. + +Signed-off-by: Bill XIE <persmule@hardenedlinux.org> +Co-authored-by: Jonathon Hall <jonathon.hall@puri.sm> +Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a +Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906 +Tested-by: build bot (Jenkins) <no-reply@coreboot.org> +Reviewed-by: Nico Huber <nico.h@gmx.de> +Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> +--- + src/drivers/pc80/rtc/option.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c +index e6cfa175ad..cb18e14ae9 100644 +--- a/src/drivers/pc80/rtc/option.c ++++ b/src/drivers/pc80/rtc/option.c +@@ -213,8 +213,12 @@ void sanitize_cmos(void) + return; + + u8 control_state = cmos_disable_rtc(); +- for (i = 14; i < MIN(128, length); i++) ++ /* Copy checked range and the checksum from the default */ ++ for (i = LB_CKS_RANGE_START; i < MIN(LB_CKS_RANGE_END + 1, length); i++) + cmos_write_inner(cmos_default[i], i); ++ /* CMOS checksum takes 2 bytes */ ++ cmos_write_inner(cmos_default[LB_CKS_LOC], LB_CKS_LOC); ++ cmos_write_inner(cmos_default[LB_CKS_LOC + 1], LB_CKS_LOC + 1); + cmos_restore_rtc(control_state); + } + } +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0026-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/i945/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch index 547c6392..547c6392 100644 --- a/config/coreboot/haswell/patches/0026-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/i945/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch diff --git a/config/coreboot/i945/target.cfg b/config/coreboot/i945/target.cfg new file mode 100644 index 00000000..16a4de7d --- /dev/null +++ b/config/coreboot/i945/target.cfg @@ -0,0 +1,2 @@ +tree="i945" +rev="e70bc423f9a2e1d13827f2703efe1f9c72549f20" diff --git a/config/coreboot/kcma-d8-rdimm_16mb/target.cfg b/config/coreboot/kcma-d8-rdimm_16mb/target.cfg index d5d37291..c618cc13 100644 --- a/config/coreboot/kcma-d8-rdimm_16mb/target.cfg +++ b/config/coreboot/kcma-d8-rdimm_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" +status="untested" diff --git a/config/coreboot/kcma-d8-rdimm_2mb/target.cfg b/config/coreboot/kcma-d8-rdimm_2mb/target.cfg index d5d37291..c618cc13 100644 --- a/config/coreboot/kcma-d8-rdimm_2mb/target.cfg +++ b/config/coreboot/kcma-d8-rdimm_2mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" +status="untested" diff --git a/config/coreboot/kcma-d8-udimm_16mb/target.cfg b/config/coreboot/kcma-d8-udimm_16mb/target.cfg index 35354c26..37d16a2a 100644 --- a/config/coreboot/kcma-d8-udimm_16mb/target.cfg +++ b/config/coreboot/kcma-d8-udimm_16mb/target.cfg @@ -6,3 +6,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" +status="untested" diff --git a/config/coreboot/kcma-d8-udimm_2mb/target.cfg b/config/coreboot/kcma-d8-udimm_2mb/target.cfg index 35354c26..37d16a2a 100644 --- a/config/coreboot/kcma-d8-udimm_2mb/target.cfg +++ b/config/coreboot/kcma-d8-udimm_2mb/target.cfg @@ -6,3 +6,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" +status="untested" diff --git a/config/coreboot/kfsn4-dre_1mb/target.cfg b/config/coreboot/kfsn4-dre_1mb/target.cfg index 19c57b8d..15f35ccd 100644 --- a/config/coreboot/kfsn4-dre_1mb/target.cfg +++ b/config/coreboot/kfsn4-dre_1mb/target.cfg @@ -4,3 +4,4 @@ payload_seabios="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kfsn4-dre_2mb/target.cfg b/config/coreboot/kfsn4-dre_2mb/target.cfg index 9bd20d45..e65a5e9c 100644 --- a/config/coreboot/kfsn4-dre_2mb/target.cfg +++ b/config/coreboot/kfsn4-dre_2mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg b/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg index 2867a730..e074689c 100644 --- a/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg +++ b/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg b/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg index 2867a730..e074689c 100644 --- a/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg +++ b/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kgpe-d16-udimm_16mb/target.cfg b/config/coreboot/kgpe-d16-udimm_16mb/target.cfg index 5b4010d8..1e128ae9 100644 --- a/config/coreboot/kgpe-d16-udimm_16mb/target.cfg +++ b/config/coreboot/kgpe-d16-udimm_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kgpe-d16-udimm_2mb/target.cfg b/config/coreboot/kgpe-d16-udimm_2mb/target.cfg index 5b4010d8..1e128ae9 100644 --- a/config/coreboot/kgpe-d16-udimm_2mb/target.cfg +++ b/config/coreboot/kgpe-d16-udimm_2mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/macbook11/config/libgfxinit_corebootfb b/config/coreboot/macbook11/config/libgfxinit_corebootfb index 17efec62..1fe47062 100644 --- a/config/coreboot/macbook11/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook11/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +111,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +129,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Macbook1,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +166,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -203,23 +193,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +219,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +237,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +263,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +301,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +312,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -350,7 +337,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -358,13 +346,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -382,11 +379,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -402,14 +399,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -431,11 +427,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -455,14 +446,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -470,39 +457,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -510,7 +480,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -526,7 +496,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -546,29 +515,22 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook11/config/libgfxinit_txtmode b/config/coreboot/macbook11/config/libgfxinit_txtmode index da70f85a..5779bb7f 100644 --- a/config/coreboot/macbook11/config/libgfxinit_txtmode +++ b/config/coreboot/macbook11/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +111,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +129,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Macbook1,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +166,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -203,23 +193,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +219,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +237,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +263,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +301,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +312,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -348,7 +335,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -356,13 +344,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -380,11 +377,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -400,14 +397,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -429,11 +425,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -453,14 +444,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -468,39 +455,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -508,7 +478,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -524,7 +494,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -544,29 +513,22 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook11/target.cfg b/config/coreboot/macbook11/target.cfg index cc83f2c3..404e0129 100644 --- a/config/coreboot/macbook11/target.cfg +++ b/config/coreboot/macbook11/target.cfg @@ -1,6 +1,7 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb b/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb index 8dc8524d..634f287c 100644 --- a/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb @@ -17,12 +17,10 @@ CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +61,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +74,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +110,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +128,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Macbook1,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +165,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -203,23 +192,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +218,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +236,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +262,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +300,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +311,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -350,7 +336,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -358,13 +345,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -382,11 +378,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -402,14 +398,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_USE_PC_CMOS_ALTCENTURY=y CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -431,11 +426,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -455,14 +445,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -470,27 +456,10 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set @@ -526,7 +495,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -546,17 +514,12 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -568,7 +531,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode b/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode index 2dee7106..6549df1b 100644 --- a/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode @@ -17,12 +17,10 @@ CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +61,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +74,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +110,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +128,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Macbook1,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +165,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -203,23 +192,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +218,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +236,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +262,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +300,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +311,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -348,7 +334,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -356,13 +343,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -380,11 +376,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -400,14 +396,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_USE_PC_CMOS_ALTCENTURY=y CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -429,11 +424,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -453,14 +443,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -468,27 +454,10 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set @@ -524,7 +493,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -544,17 +512,12 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -566,7 +529,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook11_16mb/target.cfg b/config/coreboot/macbook11_16mb/target.cfg index cc83f2c3..404e0129 100644 --- a/config/coreboot/macbook11_16mb/target.cfg +++ b/config/coreboot/macbook11_16mb/target.cfg @@ -1,6 +1,7 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/macbook21/config/libgfxinit_corebootfb b/config/coreboot/macbook21/config/libgfxinit_corebootfb index ca8b079b..900e1b32 100644 --- a/config/coreboot/macbook21/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook21/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +111,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +129,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +166,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -203,23 +193,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +219,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +237,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +263,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +301,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +312,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -350,7 +337,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -358,13 +346,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -382,11 +379,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -402,14 +399,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -431,11 +427,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -455,14 +446,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -470,39 +457,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -510,7 +480,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -526,7 +496,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -546,29 +515,22 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook21/config/libgfxinit_txtmode b/config/coreboot/macbook21/config/libgfxinit_txtmode index db019922..49cde773 100644 --- a/config/coreboot/macbook21/config/libgfxinit_txtmode +++ b/config/coreboot/macbook21/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +111,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +129,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +166,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -203,23 +193,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +219,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +237,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +263,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +301,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +312,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -348,7 +335,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -356,13 +344,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -380,11 +377,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -400,14 +397,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -429,11 +425,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -453,14 +444,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -468,39 +455,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -508,7 +478,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -524,7 +494,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -544,29 +513,22 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook21/target.cfg b/config/coreboot/macbook21/target.cfg index 8688df3f..e9eab4e9 100644 --- a/config/coreboot/macbook21/target.cfg +++ b/config/coreboot/macbook21/target.cfg @@ -1,7 +1,8 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb b/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb index 06889a94..70287afc 100644 --- a/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb @@ -17,12 +17,10 @@ CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +61,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +74,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +110,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +128,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +165,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -203,23 +192,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +218,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +236,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +262,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +300,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +311,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -350,7 +336,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -358,13 +345,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -382,11 +378,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -402,14 +398,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_USE_PC_CMOS_ALTCENTURY=y CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -431,11 +426,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -455,14 +445,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -470,27 +456,10 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set @@ -526,7 +495,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -546,17 +514,12 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -568,7 +531,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode b/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode index 9e9ec4f9..e9712d24 100644 --- a/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode @@ -17,12 +17,10 @@ CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +61,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +74,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +110,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +128,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +165,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -203,23 +192,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +218,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +236,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +262,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +300,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +311,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -348,7 +334,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -356,13 +343,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -380,11 +376,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -400,14 +396,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_USE_PC_CMOS_ALTCENTURY=y CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -429,11 +424,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -453,14 +443,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -468,27 +454,10 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set @@ -524,7 +493,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -544,17 +512,12 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -566,7 +529,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook21_16mb/target.cfg b/config/coreboot/macbook21_16mb/target.cfg index 8688df3f..e9eab4e9 100644 --- a/config/coreboot/macbook21_16mb/target.cfg +++ b/config/coreboot/macbook21_16mb/target.cfg @@ -1,7 +1,8 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/qemu_arm64_12mb/target.cfg b/config/coreboot/qemu_arm64_12mb/target.cfg index a7c36159..3ff37611 100644 --- a/config/coreboot/qemu_arm64_12mb/target.cfg +++ b/config/coreboot/qemu_arm64_12mb/target.cfg @@ -1,3 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" +status="untested" diff --git a/config/coreboot/qemu_x86_12mb/target.cfg b/config/coreboot/qemu_x86_12mb/target.cfg index 4d03eb4a..d92fda66 100644 --- a/config/coreboot/qemu_x86_12mb/target.cfg +++ b/config/coreboot/qemu_x86_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="both" +status="untested" diff --git a/config/coreboot/r400_16mb/target.cfg b/config/coreboot/r400_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/r400_16mb/target.cfg +++ b/config/coreboot/r400_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/r400_4mb/target.cfg b/config/coreboot/r400_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/r400_4mb/target.cfg +++ b/config/coreboot/r400_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/r400_8mb/target.cfg b/config/coreboot/r400_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/r400_8mb/target.cfg +++ b/config/coreboot/r400_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/r500_4mb/target.cfg b/config/coreboot/r500_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/r500_4mb/target.cfg +++ b/config/coreboot/r500_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t1650_12mb/config/libgfxinit_txtmode b/config/coreboot/t1650_12mb/config/libgfxinit_txtmode index b88ef084..3128736d 100644 --- a/config/coreboot/t1650_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t1650_12mb/config/libgfxinit_txtmode @@ -135,6 +135,7 @@ CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/t1650_12mb/target.cfg b/config/coreboot/t1650_12mb/target.cfg index e6d3bec6..6333672b 100644 --- a/config/coreboot/t1650_12mb/target.cfg +++ b/config/coreboot/t1650_12mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t400_16mb/target.cfg b/config/coreboot/t400_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t400_16mb/target.cfg +++ b/config/coreboot/t400_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t400_4mb/target.cfg b/config/coreboot/t400_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t400_4mb/target.cfg +++ b/config/coreboot/t400_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t400_8mb/target.cfg b/config/coreboot/t400_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t400_8mb/target.cfg +++ b/config/coreboot/t400_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t420_8mb/target.cfg b/config/coreboot/t420_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t420_8mb/target.cfg +++ b/config/coreboot/t420_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t420s_8mb/target.cfg b/config/coreboot/t420s_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t420s_8mb/target.cfg +++ b/config/coreboot/t420s_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t430_12mb/target.cfg b/config/coreboot/t430_12mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t430_12mb/target.cfg +++ b/config/coreboot/t430_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..5026c68e --- /dev/null +++ b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,659 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad T440p" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T440p" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0416" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0x800000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="t440p" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN0036" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T440p" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_LENOVO_THINKPAD_T440P=y +# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X220_EDP is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +CONFIG_HWBASE_DEBUG_NULL=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..a6b1bf70 --- /dev/null +++ b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode @@ -0,0 +1,656 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad T440p" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T440p" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0416" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0x800000 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="t440p" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN0036" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T440p" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_LENOVO_THINKPAD_T440P=y +# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X220_EDP is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +CONFIG_HWBASE_DEBUG_NULL=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/t440pbmrc_12mb/target.cfg b/config/coreboot/t440pbmrc_12mb/target.cfg new file mode 100644 index 00000000..e19a0d14 --- /dev/null +++ b/config/coreboot/t440pbmrc_12mb/target.cfg @@ -0,0 +1,9 @@ +tree="default" +xarch="i386-elf" +payload_grub="y" +payload_grub_withseabios="y" +payload_seabios="y" +payload_memtest="y" +grub_scan_disk="ahci" +release="n" +status="stable" diff --git a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..dd614202 --- /dev/null +++ b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,668 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad T440p" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T440p" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0416" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0x800000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="t440p" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T440p" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_LENOVO_THINKPAD_T440P=y +# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN0036" +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_H8_HAS_LEDLOGO=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode index 967b3b2e..a0dce901 100644 --- a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode @@ -6,7 +6,6 @@ # # General setup # -CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y @@ -14,12 +13,15 @@ CONFIG_COMPILER_GCC=y CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set +# CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set # CONFIG_OPTION_BACKEND_NONE is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -36,6 +38,12 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) # end of General setup # @@ -53,30 +61,28 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set -# CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_DELL is not set -# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set -# CONFIG_VENDOR_GIZMOSPHERE is not set # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set -# CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_OCP is not set # CONFIG_VENDOR_OPENCELLULAR is not set @@ -91,7 +97,6 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set # CONFIG_VENDOR_SAPPHIRE is not set -# CONFIG_VENDOR_SCALEWAY is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SIFIVE is not set # CONFIG_VENDOR_STARLABS is not set @@ -109,33 +114,32 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE0000 +CONFIG_CBFS_SIZE=0x800000 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_POST_DEVICE=y CONFIG_POST_IO=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" # CONFIG_VBOOT is not set -CONFIG_VBOOT_VBNV_OFFSET=0x2a CONFIG_VARIANT_DIR="t440p" -CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" -CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 -CONFIG_OVERRIDE_DEVICETREE="" CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xff7c0000 CONFIG_DCACHE_RAM_SIZE=0x40000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_HAVE_INTEL_FIRMWARE=y CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 @@ -148,15 +152,16 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T440p" CONFIG_HAVE_IFD_BIN=y -CONFIG_PCIEXP_HOTPLUG_BUSES=8 -CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 -# CONFIG_BOARD_LENOVO_G505S is not set CONFIG_BOARD_LENOVO_THINKPAD_T440P=y # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set # CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T500 is not set @@ -177,6 +182,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y # CONFIG_BOARD_LENOVO_Z61T is not set # CONFIG_BOARD_LENOVO_R60 is not set # CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set # CONFIG_BOARD_LENOVO_X131E is not set # CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set @@ -188,6 +194,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y @@ -195,11 +202,16 @@ CONFIG_PS2K_EISAID="LEN0071" CONFIG_PS2M_EISAID="LEN0036" CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" -# CONFIG_PCIEXP_L1_SUB_STATE is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_HEAP_SIZE=0x4000 +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -212,6 +224,7 @@ CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set CONFIG_COREBOOT_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=12288 @@ -233,7 +246,6 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # -CONFIG_ARCH_ALL_STAGES_X86=y CONFIG_CHIPSET_DEVICETREE="" CONFIG_CBFS_MCACHE_SIZE=0x4000 CONFIG_ROMSTAGE_ADDR=0x2000000 @@ -241,34 +253,34 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_TSEG_SIZE=0x800000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_CPU_SPECIFIC_OPTIONS=y CONFIG_SERIRQ_CONTINUOUS_MODE=y -CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d" +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 CONFIG_IED_REGION_SIZE=0x400000 -CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 -CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4 -CONFIG_UART_PCI_ADDR=0x0 -CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 # # CPU # CONFIG_CPU_INTEL_HASWELL=y -CONFIG_SSE2=y CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -277,7 +289,6 @@ CONFIG_SET_MSR_AESNI_LOCK_BIT=y CONFIG_CPU_INTEL_COMMON_TIMEBASE=y CONFIG_CPU_INTEL_COMMON_VOLTAGE=y CONFIG_CPU_INTEL_COMMON_SMM=y -CONFIG_MICROCODE_UPDATE_PRE_RAM=y CONFIG_PARALLEL_MP=y CONFIG_XAPIC_ONLY=y # CONFIG_X2APIC_ONLY is not set @@ -286,14 +297,13 @@ CONFIG_XAPIC_ONLY=y CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y -CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y -CONFIG_SMM_STUB_STACK_SIZE=0x400 -CONFIG_CPU_INFO_V2=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y -CONFIG_MMX=y CONFIG_SSE=y +CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y @@ -310,9 +320,7 @@ CONFIG_USE_NATIVE_RAMINIT=y # # Southbridge # -CONFIG_SOUTH_BRIDGE_OPTIONS=y -CONFIG_HPET_MIN_TICKS=0x80 -CONFIG_PCIEXP_HOTPLUG=y +# CONFIG_PCIEXP_HOTPLUG is not set CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y CONFIG_FINALIZE_USB_ROUTE_XHCI=y @@ -328,12 +336,12 @@ CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y # CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 CONFIG_RCBA_LENGTH=0x4000 @@ -347,11 +355,13 @@ CONFIG_RCBA_LENGTH=0x4000 # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -# CONFIG_H8_BEEP_ON_DEATH is not set -# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_H8_HAS_LEDLOGO=y CONFIG_EC_LENOVO_PMH7=y # @@ -374,8 +384,10 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_NUM_IPI_STARTS=2 +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -385,6 +397,7 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -396,6 +409,7 @@ CONFIG_MAINBOARD_HAS_LIBGFXINIT=y CONFIG_MAINBOARD_USE_LIBGFXINIT=y # CONFIG_VGA_ROM_RUN is not set # CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y # # Display @@ -407,17 +421,14 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_AZALIA_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y -# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set -CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -425,7 +436,8 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATOR_V4=y +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y # end of Devices # @@ -435,21 +447,19 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 # CONFIG_ELOG is not set CONFIG_CACHE_MRC_SETTINGS=y # CONFIG_MRC_SETTINGS_PROTECT is not set -CONFIG_MRC_STASH_TO_CBMEM=y # CONFIG_SMMSTORE is not set CONFIG_SPI_FLASH=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y -CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y # CONFIG_SPI_FLASH_NO_FAST_READ is not set CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y CONFIG_TPM_INIT_RAMSTAGE=y # CONFIG_TPM_PPI is not set @@ -460,28 +470,35 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y # CONFIG_USBDEBUG is not set # CONFIG_VPD is not set # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set CONFIG_INTEL_DDI=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" CONFIG_GFX_GMA=y -CONFIG_GFX_GMA_PANEL_1_ON_EDP=y -CONFIG_INTEL_GMA_OPREGION_2_0=y CONFIG_GFX_GMA_DYN_CPU=y CONFIG_GFX_GMA_GENERATION="Haswell" CONFIG_GFX_GMA_PCH="Lynx_Point" CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_MEMORY_MAPPED_TPM=y CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y # end of Generic Drivers # @@ -509,7 +526,11 @@ CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set # CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set -# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -531,6 +552,9 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y @@ -548,17 +572,18 @@ CONFIG_SQUELCH_EARLY_SMP=y CONFIG_CONSOLE_CBMEM=y # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_EM100PRO_SPI_CONSOLE is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -566,7 +591,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -580,6 +605,7 @@ CONFIG_USE_WATCHDOG_ON_BOOT=y # System tables # CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -587,32 +613,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # Payload # CONFIG_PAYLOAD_NONE=y -# CONFIG_PAYLOAD_ELF is not set -# CONFIG_PAYLOAD_BOOTBOOT is not set -# CONFIG_PAYLOAD_FILO is not set -# CONFIG_PAYLOAD_GRUB2 is not set -# CONFIG_PAYLOAD_SEAGRUB is not set -# CONFIG_PAYLOAD_LINUXBOOT is not set -# CONFIG_PAYLOAD_SEABIOS is not set -# CONFIG_PAYLOAD_UBOOT is not set -# CONFIG_PAYLOAD_YABITS is not set -# CONFIG_PAYLOAD_LINUX is not set -# CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_OPTIONS="" -# CONFIG_PXE is not set -CONFIG_COMPRESS_SECONDARY_PAYLOAD=y - -# -# Secondary Payloads -# -# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set -# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set -# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set -# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set -# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set -# CONFIG_TINT_SECONDARY_PAYLOAD is not set -# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set -# end of Secondary Payloads # end of Payload # @@ -625,6 +625,10 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y # CONFIG_DISPLAY_MTRRS is not set # +# Vendorcode Debug Settings +# + +# # BLOB Debug Settings # @@ -637,13 +641,14 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set CONFIG_HAVE_EM100_SUPPORT=y # CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_RAMSTAGE_ADA=y @@ -651,6 +656,7 @@ CONFIG_RAMSTAGE_LIBHWBASE=y CONFIG_HWBASE_DYNAMIC_MMIO=y CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y CONFIG_WARNINGS_ARE_ERRORS=y CONFIG_MAX_REBOOT_CNT=3 CONFIG_RELOCATABLE_MODULES=y diff --git a/config/coreboot/t440plibremrc_12mb/target.cfg b/config/coreboot/t440plibremrc_12mb/target.cfg index d36486ab..0efb19ed 100644 --- a/config/coreboot/t440plibremrc_12mb/target.cfg +++ b/config/coreboot/t440plibremrc_12mb/target.cfg @@ -1,6 +1,8 @@ tree="haswell" xarch="i386-elf" -payload_grub="n" -payload_grub_withseabios="n" +payload_grub="y" +payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" +grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb index f2067194..d7124b0f 100644 --- a/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb @@ -119,7 +119,7 @@ CONFIG_CBFS_SIZE=0x800000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t440p" diff --git a/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode index 9fa0abac..fc7db117 100644 --- a/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode @@ -117,7 +117,7 @@ CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x800000 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t440p" diff --git a/config/coreboot/t440pmrc_12mb/target.cfg b/config/coreboot/t440pmrc_12mb/target.cfg index 8688df3f..e19a0d14 100644 --- a/config/coreboot/t440pmrc_12mb/target.cfg +++ b/config/coreboot/t440pmrc_12mb/target.cfg @@ -5,3 +5,5 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" +status="stable" diff --git a/config/coreboot/t500_16mb/target.cfg b/config/coreboot/t500_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t500_16mb/target.cfg +++ b/config/coreboot/t500_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t500_4mb/target.cfg b/config/coreboot/t500_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t500_4mb/target.cfg +++ b/config/coreboot/t500_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t500_8mb/target.cfg b/config/coreboot/t500_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t500_8mb/target.cfg +++ b/config/coreboot/t500_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t520_8mb/target.cfg b/config/coreboot/t520_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t520_8mb/target.cfg +++ b/config/coreboot/t520_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t530_12mb/target.cfg b/config/coreboot/t530_12mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t530_12mb/target.cfg +++ b/config/coreboot/t530_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb index 64ef081d..7867f6dd 100644 --- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb +++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,12 +112,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t60" @@ -134,25 +128,22 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM0057" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -184,22 +175,20 @@ CONFIG_BOARD_LENOVO_T60=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM0057" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -213,7 +202,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -241,26 +229,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -268,6 +255,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -285,12 +273,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -310,7 +299,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -345,8 +334,8 @@ CONFIG_SUPERIO_NSC_PC87384=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -357,11 +346,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -371,7 +357,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -397,7 +382,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -405,6 +391,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -412,7 +403,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -430,11 +425,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -450,18 +445,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -483,11 +473,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -507,14 +492,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -522,39 +503,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -562,7 +526,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -579,7 +543,6 @@ CONFIG_HAVE_MP_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -599,29 +562,22 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode index a04bafeb..aee059ba 100644 --- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode +++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,12 +112,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t60" @@ -134,25 +128,22 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM0057" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -184,22 +175,20 @@ CONFIG_BOARD_LENOVO_T60=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM0057" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -213,7 +202,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -241,26 +229,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -268,6 +255,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -285,12 +273,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -310,7 +299,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -345,8 +334,8 @@ CONFIG_SUPERIO_NSC_PC87384=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -357,11 +346,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -371,7 +357,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -395,7 +380,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -403,6 +389,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -410,7 +401,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -428,11 +423,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -448,18 +443,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -481,11 +471,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -505,14 +490,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -520,39 +501,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -560,7 +524,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -577,7 +541,6 @@ CONFIG_HAVE_MP_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -597,29 +560,22 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/t60_16mb_intelgpu/target.cfg b/config/coreboot/t60_16mb_intelgpu/target.cfg index 5316aa6f..6a6d833a 100644 --- a/config/coreboot/t60_16mb_intelgpu/target.cfg +++ b/config/coreboot/t60_16mb_intelgpu/target.cfg @@ -1,7 +1,8 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" +status="untested" diff --git a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb index 0916331f..b42d92e7 100644 --- a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb +++ b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,12 +112,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t60" @@ -134,25 +128,22 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM0057" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -184,22 +175,20 @@ CONFIG_BOARD_LENOVO_T60=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM0057" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -213,7 +202,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -241,26 +229,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -268,6 +255,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -285,12 +273,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -310,7 +299,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -345,8 +334,8 @@ CONFIG_SUPERIO_NSC_PC87384=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -357,11 +346,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -371,7 +357,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -397,7 +382,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -405,6 +391,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -412,7 +403,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -430,11 +425,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -450,18 +445,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -483,11 +473,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -507,14 +492,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -522,39 +503,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -562,7 +526,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -579,7 +543,6 @@ CONFIG_HAVE_MP_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -599,29 +562,22 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode index b41b4286..1fc2ab3c 100644 --- a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode +++ b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,12 +112,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t60" @@ -134,25 +128,22 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM0057" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -184,22 +175,20 @@ CONFIG_BOARD_LENOVO_T60=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM0057" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -213,7 +202,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -241,26 +229,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -268,6 +255,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -285,12 +273,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -310,7 +299,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -345,8 +334,8 @@ CONFIG_SUPERIO_NSC_PC87384=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -357,11 +346,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -371,7 +357,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -395,7 +380,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -403,6 +389,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -410,7 +401,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -428,11 +423,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -448,18 +443,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -481,11 +471,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -505,14 +490,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -520,39 +501,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -560,7 +524,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -577,7 +541,6 @@ CONFIG_HAVE_MP_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -597,29 +560,22 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/t60_intelgpu/target.cfg b/config/coreboot/t60_intelgpu/target.cfg index 5316aa6f..6a6d833a 100644 --- a/config/coreboot/t60_intelgpu/target.cfg +++ b/config/coreboot/t60_intelgpu/target.cfg @@ -1,7 +1,8 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" +status="untested" diff --git a/config/coreboot/w500_16mb/target.cfg b/config/coreboot/w500_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/w500_16mb/target.cfg +++ b/config/coreboot/w500_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/w500_4mb/target.cfg b/config/coreboot/w500_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/w500_4mb/target.cfg +++ b/config/coreboot/w500_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/w500_8mb/target.cfg b/config/coreboot/w500_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/w500_8mb/target.cfg +++ b/config/coreboot/w500_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/w530_12mb/target.cfg b/config/coreboot/w530_12mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/w530_12mb/target.cfg +++ b/config/coreboot/w530_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/w541_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..ae155585 --- /dev/null +++ b/config/coreboot/w541_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,667 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad W541" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W541" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0x800000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="w541" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad W541" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set +CONFIG_BOARD_LENOVO_THINKPAD_W541=y +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN004A" +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="DP3" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_H8_HAS_LEDLOGO=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/w541_12mb/config/libgfxinit_txtmode b/config/coreboot/w541_12mb/config/libgfxinit_txtmode index b3e169d4..9a891434 100644 --- a/config/coreboot/w541_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w541_12mb/config/libgfxinit_txtmode @@ -6,7 +6,6 @@ # # General setup # -CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y @@ -14,12 +13,15 @@ CONFIG_COMPILER_GCC=y CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set +# CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set # CONFIG_OPTION_BACKEND_NONE is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -36,6 +38,12 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) # end of General setup # @@ -53,30 +61,28 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set -# CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_DELL is not set -# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set -# CONFIG_VENDOR_GIZMOSPHERE is not set # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set -# CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_OCP is not set # CONFIG_VENDOR_OPENCELLULAR is not set @@ -91,7 +97,6 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set # CONFIG_VENDOR_SAPPHIRE is not set -# CONFIG_VENDOR_SCALEWAY is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SIFIVE is not set # CONFIG_VENDOR_STARLABS is not set @@ -109,33 +114,32 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE0000 +CONFIG_CBFS_SIZE=0x800000 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_POST_DEVICE=y CONFIG_POST_IO=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" # CONFIG_VBOOT is not set -CONFIG_VBOOT_VBNV_OFFSET=0x2a CONFIG_VARIANT_DIR="w541" -CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" -CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 -CONFIG_OVERRIDE_DEVICETREE="" CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xff7c0000 CONFIG_DCACHE_RAM_SIZE=0x40000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_HAVE_INTEL_FIRMWARE=y CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 @@ -148,12 +152,16 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad W541" CONFIG_HAVE_IFD_BIN=y -# CONFIG_BOARD_LENOVO_G505S is not set # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set CONFIG_BOARD_LENOVO_THINKPAD_W541=y # CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set # CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T500 is not set @@ -174,6 +182,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y # CONFIG_BOARD_LENOVO_Z61T is not set # CONFIG_BOARD_LENOVO_R60 is not set # CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set # CONFIG_BOARD_LENOVO_X131E is not set # CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set @@ -185,6 +194,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y @@ -192,11 +202,16 @@ CONFIG_PS2K_EISAID="LEN0071" CONFIG_PS2M_EISAID="LEN004A" CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" CONFIG_GFX_GMA_PANEL_1_PORT="DP3" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_HEAP_SIZE=0x4000 +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -209,6 +224,7 @@ CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set CONFIG_COREBOOT_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=12288 @@ -230,7 +246,6 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # -CONFIG_ARCH_ALL_STAGES_X86=y CONFIG_CHIPSET_DEVICETREE="" CONFIG_CBFS_MCACHE_SIZE=0x4000 CONFIG_ROMSTAGE_ADDR=0x2000000 @@ -238,34 +253,34 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_TSEG_SIZE=0x800000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_CPU_SPECIFIC_OPTIONS=y CONFIG_SERIRQ_CONTINUOUS_MODE=y -CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d" +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 CONFIG_IED_REGION_SIZE=0x400000 -CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 -CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4 -CONFIG_UART_PCI_ADDR=0x0 -CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 # # CPU # CONFIG_CPU_INTEL_HASWELL=y -CONFIG_SSE2=y CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -274,7 +289,6 @@ CONFIG_SET_MSR_AESNI_LOCK_BIT=y CONFIG_CPU_INTEL_COMMON_TIMEBASE=y CONFIG_CPU_INTEL_COMMON_VOLTAGE=y CONFIG_CPU_INTEL_COMMON_SMM=y -CONFIG_MICROCODE_UPDATE_PRE_RAM=y CONFIG_PARALLEL_MP=y CONFIG_XAPIC_ONLY=y # CONFIG_X2APIC_ONLY is not set @@ -283,14 +297,13 @@ CONFIG_XAPIC_ONLY=y CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y -CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y -CONFIG_SMM_STUB_STACK_SIZE=0x400 -CONFIG_CPU_INFO_V2=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y -CONFIG_MMX=y CONFIG_SSE=y +CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y @@ -307,8 +320,6 @@ CONFIG_USE_NATIVE_RAMINIT=y # # Southbridge # -CONFIG_SOUTH_BRIDGE_OPTIONS=y -CONFIG_HPET_MIN_TICKS=0x80 # CONFIG_PCIEXP_HOTPLUG is not set CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y @@ -325,12 +336,12 @@ CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y # CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 CONFIG_RCBA_LENGTH=0x4000 @@ -347,8 +358,10 @@ CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_H8_HAS_LEDLOGO=y CONFIG_EC_LENOVO_PMH7=y # @@ -371,8 +384,10 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_NUM_IPI_STARTS=2 +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -382,6 +397,7 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -393,6 +409,7 @@ CONFIG_MAINBOARD_HAS_LIBGFXINIT=y CONFIG_MAINBOARD_USE_LIBGFXINIT=y # CONFIG_VGA_ROM_RUN is not set # CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y # # Display @@ -404,14 +421,14 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_AZALIA_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -419,7 +436,8 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATOR_V4=y +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y # end of Devices # @@ -429,21 +447,19 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 # CONFIG_ELOG is not set CONFIG_CACHE_MRC_SETTINGS=y # CONFIG_MRC_SETTINGS_PROTECT is not set -CONFIG_MRC_STASH_TO_CBMEM=y # CONFIG_SMMSTORE is not set CONFIG_SPI_FLASH=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y -CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y # CONFIG_SPI_FLASH_NO_FAST_READ is not set CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y CONFIG_TPM_INIT_RAMSTAGE=y # CONFIG_TPM_PPI is not set @@ -454,27 +470,34 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y # CONFIG_USBDEBUG is not set # CONFIG_VPD is not set # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set CONFIG_INTEL_DDI=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" CONFIG_GFX_GMA=y -CONFIG_GFX_GMA_PANEL_1_ON_EDP=y -CONFIG_INTEL_GMA_OPREGION_2_0=y CONFIG_GFX_GMA_DYN_CPU=y CONFIG_GFX_GMA_GENERATION="Haswell" CONFIG_GFX_GMA_PCH="Lynx_Point" CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_MEMORY_MAPPED_TPM=y CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y # end of Generic Drivers # @@ -502,7 +525,11 @@ CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set # CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set -# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -524,6 +551,9 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y @@ -541,6 +571,7 @@ CONFIG_SQUELCH_EARLY_SMP=y CONFIG_CONSOLE_CBMEM=y # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_EM100PRO_SPI_CONSOLE is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y @@ -573,6 +604,7 @@ CONFIG_USE_WATCHDOG_ON_BOOT=y # System tables # CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -580,32 +612,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # Payload # CONFIG_PAYLOAD_NONE=y -# CONFIG_PAYLOAD_ELF is not set -# CONFIG_PAYLOAD_BOOTBOOT is not set -# CONFIG_PAYLOAD_FILO is not set -# CONFIG_PAYLOAD_GRUB2 is not set -# CONFIG_PAYLOAD_SEAGRUB is not set -# CONFIG_PAYLOAD_LINUXBOOT is not set -# CONFIG_PAYLOAD_SEABIOS is not set -# CONFIG_PAYLOAD_UBOOT is not set -# CONFIG_PAYLOAD_YABITS is not set -# CONFIG_PAYLOAD_LINUX is not set -# CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_OPTIONS="" -# CONFIG_PXE is not set -CONFIG_COMPRESS_SECONDARY_PAYLOAD=y - -# -# Secondary Payloads -# -# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set -# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set -# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set -# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set -# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set -# CONFIG_TINT_SECONDARY_PAYLOAD is not set -# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set -# end of Secondary Payloads # end of Payload # @@ -618,6 +624,10 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y # CONFIG_DISPLAY_MTRRS is not set # +# Vendorcode Debug Settings +# + +# # BLOB Debug Settings # @@ -630,7 +640,6 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set @@ -638,6 +647,7 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_ADA_CODE is not set CONFIG_HAVE_EM100_SUPPORT=y # CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_RAMSTAGE_ADA=y @@ -645,6 +655,7 @@ CONFIG_RAMSTAGE_LIBHWBASE=y CONFIG_HWBASE_DYNAMIC_MMIO=y CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y CONFIG_WARNINGS_ARE_ERRORS=y CONFIG_MAX_REBOOT_CNT=3 CONFIG_RELOCATABLE_MODULES=y diff --git a/config/coreboot/w541_12mb/target.cfg b/config/coreboot/w541_12mb/target.cfg index d36486ab..0efb19ed 100644 --- a/config/coreboot/w541_12mb/target.cfg +++ b/config/coreboot/w541_12mb/target.cfg @@ -1,6 +1,8 @@ tree="haswell" xarch="i386-elf" -payload_grub="n" -payload_grub_withseabios="n" +payload_grub="y" +payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" +grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..a5342fbb --- /dev/null +++ b/config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,659 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad W541" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W541" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0x800000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="w541" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN004A" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad W541" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set +CONFIG_BOARD_LENOVO_THINKPAD_W541=y +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X220_EDP is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="DP3" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..60686a0f --- /dev/null +++ b/config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode @@ -0,0 +1,656 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad W541" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W541" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0x800000 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="w541" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN004A" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad W541" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set +CONFIG_BOARD_LENOVO_THINKPAD_W541=y +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X220_EDP is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="DP3" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/w541bmrc_12mb/target.cfg b/config/coreboot/w541bmrc_12mb/target.cfg new file mode 100644 index 00000000..e19a0d14 --- /dev/null +++ b/config/coreboot/w541bmrc_12mb/target.cfg @@ -0,0 +1,9 @@ +tree="default" +xarch="i386-elf" +payload_grub="y" +payload_grub_withseabios="y" +payload_seabios="y" +payload_memtest="y" +grub_scan_disk="ahci" +release="n" +status="stable" diff --git a/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb index 314dbbc9..3f0cf31a 100644 --- a/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb @@ -119,7 +119,7 @@ CONFIG_CBFS_SIZE=0x800000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="w541" diff --git a/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode b/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode index 8f09ec77..e0d0c538 100644 --- a/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode @@ -117,7 +117,7 @@ CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x800000 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="w541" diff --git a/config/coreboot/w541mrc_12mb/target.cfg b/config/coreboot/w541mrc_12mb/target.cfg index 8688df3f..e19a0d14 100644 --- a/config/coreboot/w541mrc_12mb/target.cfg +++ b/config/coreboot/w541mrc_12mb/target.cfg @@ -5,3 +5,5 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" +status="stable" diff --git a/config/coreboot/x200_16mb/target.cfg b/config/coreboot/x200_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x200_16mb/target.cfg +++ b/config/coreboot/x200_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x200_4mb/target.cfg b/config/coreboot/x200_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x200_4mb/target.cfg +++ b/config/coreboot/x200_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x200_8mb/target.cfg b/config/coreboot/x200_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x200_8mb/target.cfg +++ b/config/coreboot/x200_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x220_8mb/target.cfg b/config/coreboot/x220_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x220_8mb/target.cfg +++ b/config/coreboot/x220_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x220edp_8mb/target.cfg b/config/coreboot/x220edp_8mb/target.cfg index 8688df3f..529581bd 100644 --- a/config/coreboot/x220edp_8mb/target.cfg +++ b/config/coreboot/x220edp_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="broken" # TODO: VCC3P patch diff --git a/config/coreboot/x220edp_8mb/warn.txt b/config/coreboot/x220edp_8mb/warn.txt new file mode 100644 index 00000000..a153edeb --- /dev/null +++ b/config/coreboot/x220edp_8mb/warn.txt @@ -0,0 +1 @@ +TODO: VCC3P patch diff --git a/config/coreboot/x230_12mb/target.cfg b/config/coreboot/x230_12mb/target.cfg index 8688df3f..f16a94a4 100644 --- a/config/coreboot/x230_12mb/target.cfg +++ b/config/coreboot/x230_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/x230_12mb/warn.txt b/config/coreboot/x230_12mb/warn.txt new file mode 100644 index 00000000..a153edeb --- /dev/null +++ b/config/coreboot/x230_12mb/warn.txt @@ -0,0 +1 @@ +TODO: VCC3P patch diff --git a/config/coreboot/x230_16mb/target.cfg b/config/coreboot/x230_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x230_16mb/target.cfg +++ b/config/coreboot/x230_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x230edp_12mb/target.cfg b/config/coreboot/x230edp_12mb/target.cfg index 8688df3f..529581bd 100644 --- a/config/coreboot/x230edp_12mb/target.cfg +++ b/config/coreboot/x230edp_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="broken" # TODO: VCC3P patch diff --git a/config/coreboot/x230t_12mb/target.cfg b/config/coreboot/x230t_12mb/target.cfg index 8688df3f..f16a94a4 100644 --- a/config/coreboot/x230t_12mb/target.cfg +++ b/config/coreboot/x230t_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/x230t_16mb/target.cfg b/config/coreboot/x230t_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x230t_16mb/target.cfg +++ b/config/coreboot/x230t_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x301_16mb/target.cfg b/config/coreboot/x301_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x301_16mb/target.cfg +++ b/config/coreboot/x301_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x301_4mb/target.cfg b/config/coreboot/x301_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x301_4mb/target.cfg +++ b/config/coreboot/x301_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x301_8mb/target.cfg b/config/coreboot/x301_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x301_8mb/target.cfg +++ b/config/coreboot/x301_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x60/config/libgfxinit_corebootfb b/config/coreboot/x60/config/libgfxinit_corebootfb index da9884e7..8197735b 100644 --- a/config/coreboot/x60/config/libgfxinit_corebootfb +++ b/config/coreboot/x60/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,14 +112,13 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set +CONFIG_VBOOT_VBNV_OFFSET=0x76 CONFIG_IRQ_SLOT_COUNT=18 CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set @@ -134,26 +129,23 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM3780" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_VBOOT_SLOTS_RW_A=y CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -185,22 +177,20 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set CONFIG_BOARD_LENOVO_X60=y CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM3780" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -214,7 +204,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -242,26 +231,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -269,6 +257,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -286,12 +275,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -311,7 +301,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -347,8 +337,8 @@ CONFIG_SUPERIO_NSC_PC87392=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -359,11 +349,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -373,7 +360,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -399,7 +385,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -407,6 +394,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -414,7 +406,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -436,11 +432,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -456,18 +452,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -489,11 +480,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -513,14 +499,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -528,39 +510,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -568,7 +533,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -587,7 +552,6 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -607,17 +571,12 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -625,12 +584,10 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_PIRQ is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/x60/config/libgfxinit_txtmode b/config/coreboot/x60/config/libgfxinit_txtmode index 218e23f4..9ac40a02 100644 --- a/config/coreboot/x60/config/libgfxinit_txtmode +++ b/config/coreboot/x60/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,14 +112,13 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set +CONFIG_VBOOT_VBNV_OFFSET=0x76 CONFIG_IRQ_SLOT_COUNT=18 CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set @@ -134,26 +129,23 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM3780" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_VBOOT_SLOTS_RW_A=y CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -185,22 +177,20 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set CONFIG_BOARD_LENOVO_X60=y CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM3780" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -214,7 +204,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -242,26 +231,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -269,6 +257,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -286,12 +275,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -311,7 +301,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -347,8 +337,8 @@ CONFIG_SUPERIO_NSC_PC87392=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -359,11 +349,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -373,7 +360,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -397,7 +383,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -405,6 +392,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -412,7 +404,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -434,11 +430,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -454,18 +450,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -487,11 +478,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -511,14 +497,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -526,39 +508,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -566,7 +531,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -585,7 +550,6 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -605,17 +569,12 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -623,12 +582,10 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_PIRQ is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/x60/target.cfg b/config/coreboot/x60/target.cfg index 5316aa6f..6a6d833a 100644 --- a/config/coreboot/x60/target.cfg +++ b/config/coreboot/x60/target.cfg @@ -1,7 +1,8 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" +status="untested" diff --git a/config/coreboot/x60_16mb/config/libgfxinit_corebootfb b/config/coreboot/x60_16mb/config/libgfxinit_corebootfb index 68b98d98..fc3a4402 100644 --- a/config/coreboot/x60_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x60_16mb/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,14 +112,13 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set +CONFIG_VBOOT_VBNV_OFFSET=0x76 CONFIG_IRQ_SLOT_COUNT=18 CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set @@ -134,26 +129,23 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM3780" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_VBOOT_SLOTS_RW_A=y CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -185,22 +177,20 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set CONFIG_BOARD_LENOVO_X60=y CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM3780" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -214,7 +204,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -242,26 +231,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -269,6 +257,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -286,12 +275,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -311,7 +301,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -347,8 +337,8 @@ CONFIG_SUPERIO_NSC_PC87392=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -359,11 +349,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -373,7 +360,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -399,7 +385,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -407,6 +394,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -414,7 +406,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -436,11 +432,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -456,18 +452,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -489,11 +480,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -513,14 +499,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -528,39 +510,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -568,7 +533,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -587,7 +552,6 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -607,17 +571,12 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -625,12 +584,10 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_PIRQ is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/x60_16mb/config/libgfxinit_txtmode b/config/coreboot/x60_16mb/config/libgfxinit_txtmode index f6883deb..c4049565 100644 --- a/config/coreboot/x60_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x60_16mb/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,14 +112,13 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set +CONFIG_VBOOT_VBNV_OFFSET=0x76 CONFIG_IRQ_SLOT_COUNT=18 CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set @@ -134,26 +129,23 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM3780" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_VBOOT_SLOTS_RW_A=y CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -185,22 +177,20 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set CONFIG_BOARD_LENOVO_X60=y CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM3780" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -214,7 +204,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -242,26 +231,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -269,6 +257,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -286,12 +275,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -311,7 +301,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -347,8 +337,8 @@ CONFIG_SUPERIO_NSC_PC87392=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -359,11 +349,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -373,7 +360,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -397,7 +383,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -405,6 +392,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -412,7 +404,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -434,11 +430,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -454,18 +450,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -487,11 +478,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -511,14 +497,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -526,39 +508,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -566,7 +531,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -585,7 +550,6 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -605,17 +569,12 @@ CONFIG_PAYLOAD_NONE=y # CONFIG_DISPLAY_MTRRS is not set # -# Vendorcode Debug Settings -# - -# # BLOB Debug Settings # # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -623,12 +582,10 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_PIRQ is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/x60_16mb/target.cfg b/config/coreboot/x60_16mb/target.cfg index 5316aa6f..6a6d833a 100644 --- a/config/coreboot/x60_16mb/target.cfg +++ b/config/coreboot/x60_16mb/target.cfg @@ -1,7 +1,8 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" +status="untested" diff --git a/config/git/grub b/config/git/grub index 3abec3e4..b52fa0fb 100644 --- a/config/git/grub +++ b/config/git/grub @@ -1,5 +1,5 @@ {grub}{ - rev: b835601c7639ed1890f2d3db91900a8506011a8e + rev: 8719cc2040368d43ab2de0b6e1b850b2c9cfc5b7 loc: grub url: git://git.savannah.gnu.org/grub.git bkup_url: https://codeberg.org/libreboot/grub diff --git a/config/grub/modules.list b/config/grub/modules.list index 40bfd339..f3768adb 100644 --- a/config/grub/modules.list +++ b/config/grub/modules.list @@ -36,6 +36,7 @@ crypto \ cryptodisk \ diskfilter \ echo \ +xhci \ ehci \ eval \ exfat \ diff --git a/config/grub/patches/0005-xhci/0001-grub-core-bus-usb-Parse-SuperSpeed-companion-descrip.patch b/config/grub/patches/0005-xhci/0001-grub-core-bus-usb-Parse-SuperSpeed-companion-descrip.patch new file mode 100644 index 00000000..f533269f --- /dev/null +++ b/config/grub/patches/0005-xhci/0001-grub-core-bus-usb-Parse-SuperSpeed-companion-descrip.patch @@ -0,0 +1,245 @@ +From 90c9011f2e0350a97e3df44b0fc6dd022e04c276 Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph <patrick.rudolph@9elements.com> +Date: Sun, 15 Nov 2020 19:00:27 +0100 +Subject: [PATCH 1/8] grub-core/bus/usb: Parse SuperSpeed companion descriptors + +Parse the SS_ENDPOINT_COMPANION descriptor, which is only present on USB 3.0 +capable devices and xHCI controllers. Make the descendp an array of pointers +to the endpoint descriptor as it's no longer an continous array. + +Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> +--- + grub-core/bus/usb/serial/common.c | 2 +- + grub-core/bus/usb/usb.c | 44 +++++++++++++++++++------------ + grub-core/bus/usb/usbhub.c | 22 ++++++++++++---- + grub-core/commands/usbtest.c | 2 +- + grub-core/disk/usbms.c | 2 +- + grub-core/term/usb_keyboard.c | 2 +- + include/grub/usb.h | 2 +- + include/grub/usbdesc.h | 11 +++++++- + 8 files changed, 59 insertions(+), 28 deletions(-) + +diff --git a/grub-core/bus/usb/serial/common.c b/grub-core/bus/usb/serial/common.c +index e9c995a0a..fc847d66d 100644 +--- a/grub-core/bus/usb/serial/common.c ++++ b/grub-core/bus/usb/serial/common.c +@@ -72,7 +72,7 @@ grub_usbserial_attach (grub_usb_device_t usbdev, int configno, int interfno, + for (j = 0; j < interf->endpointcnt; j++) + { + struct grub_usb_desc_endp *endp; +- endp = &usbdev->config[0].interf[interfno].descendp[j]; ++ endp = usbdev->config[0].interf[interfno].descendp[j]; + + if ((endp->endp_addr & 128) && (endp->attrib & 3) == 2 + && (in_endp == GRUB_USB_SERIAL_ENDPOINT_LAST_MATCHING +diff --git a/grub-core/bus/usb/usb.c b/grub-core/bus/usb/usb.c +index 7bd49d201..e578af793 100644 +--- a/grub-core/bus/usb/usb.c ++++ b/grub-core/bus/usb/usb.c +@@ -118,7 +118,7 @@ grub_usb_device_initialize (grub_usb_device_t dev) + struct grub_usb_desc_device *descdev; + struct grub_usb_desc_config config; + grub_usb_err_t err; +- int i; ++ int i, j; + + /* First we have to read first 8 bytes only and determine + * max. size of packet */ +@@ -152,6 +152,7 @@ grub_usb_device_initialize (grub_usb_device_t dev) + int currif; + char *data; + struct grub_usb_desc *desc; ++ struct grub_usb_desc_endp *endp; + + /* First just read the first 4 bytes of the configuration + descriptor, after that it is known how many bytes really have +@@ -201,24 +202,27 @@ grub_usb_device_initialize (grub_usb_device_t dev) + = (struct grub_usb_desc_if *) &data[pos]; + pos += dev->config[i].interf[currif].descif->length; + ++ dev->config[i].interf[currif].descendp = grub_malloc ( ++ dev->config[i].interf[currif].descif->endpointcnt * ++ sizeof(struct grub_usb_desc_endp)); ++ ++ j = 0; + while (pos < config.totallen) + { + desc = (struct grub_usb_desc *)&data[pos]; +- if (desc->type == GRUB_USB_DESCRIPTOR_ENDPOINT) +- break; +- if (!desc->length) +- { +- err = GRUB_USB_ERR_BADDEVICE; +- goto fail; +- } +- pos += desc->length; +- } +- +- /* Point to the first endpoint. */ +- dev->config[i].interf[currif].descendp +- = (struct grub_usb_desc_endp *) &data[pos]; +- pos += (sizeof (struct grub_usb_desc_endp) +- * dev->config[i].interf[currif].descif->endpointcnt); ++ if (desc->type == GRUB_USB_DESCRIPTOR_ENDPOINT) { ++ endp = (struct grub_usb_desc_endp *) &data[pos]; ++ dev->config[i].interf[currif].descendp[j++] = endp; ++ pos += desc->length; ++ } else { ++ if (!desc->length) ++ { ++ err = GRUB_USB_ERR_BADDEVICE; ++ goto fail; ++ } ++ pos += desc->length; ++ } ++ } + } + } + +@@ -226,8 +230,14 @@ grub_usb_device_initialize (grub_usb_device_t dev) + + fail: + +- for (i = 0; i < GRUB_USB_MAX_CONF; i++) ++ for (i = 0; i < GRUB_USB_MAX_CONF; i++) { ++ int currif; ++ ++ for (currif = 0; currif < dev->config[i].descconf->numif; currif++) ++ grub_free (dev->config[i].interf[currif].descendp); ++ + grub_free (dev->config[i].descconf); ++ } + + return err; + } +diff --git a/grub-core/bus/usb/usbhub.c b/grub-core/bus/usb/usbhub.c +index f5608e330..2ae29cba1 100644 +--- a/grub-core/bus/usb/usbhub.c ++++ b/grub-core/bus/usb/usbhub.c +@@ -82,8 +82,14 @@ grub_usb_hub_add_dev (grub_usb_controller_t controller, + if (i == GRUB_USBHUB_MAX_DEVICES) + { + grub_error (GRUB_ERR_IO, "can't assign address to USB device"); +- for (i = 0; i < GRUB_USB_MAX_CONF; i++) +- grub_free (dev->config[i].descconf); ++ for (i = 0; i < GRUB_USB_MAX_CONF; i++) { ++ int currif; ++ ++ for (currif = 0; currif < dev->config[i].descconf->numif; currif++) ++ grub_free (dev->config[i].interf[currif].descendp); ++ ++ grub_free (dev->config[i].descconf); ++ } + grub_free (dev); + return NULL; + } +@@ -96,8 +102,14 @@ grub_usb_hub_add_dev (grub_usb_controller_t controller, + i, 0, 0, NULL); + if (err) + { +- for (i = 0; i < GRUB_USB_MAX_CONF; i++) +- grub_free (dev->config[i].descconf); ++ for (i = 0; i < GRUB_USB_MAX_CONF; i++) { ++ int currif; ++ ++ for (currif = 0; currif < dev->config[i].descconf->numif; currif++) ++ grub_free (dev->config[i].interf[currif].descendp); ++ ++ grub_free (dev->config[i].descconf); ++ } + grub_free (dev); + return NULL; + } +@@ -176,7 +188,7 @@ grub_usb_add_hub (grub_usb_device_t dev) + i++) + { + struct grub_usb_desc_endp *endp = NULL; +- endp = &dev->config[0].interf[0].descendp[i]; ++ endp = dev->config[0].interf[0].descendp[i]; + + if ((endp->endp_addr & 128) && grub_usb_get_ep_type(endp) + == GRUB_USB_EP_INTERRUPT) +diff --git a/grub-core/commands/usbtest.c b/grub-core/commands/usbtest.c +index 2c6d93fe6..55a657635 100644 +--- a/grub-core/commands/usbtest.c ++++ b/grub-core/commands/usbtest.c +@@ -185,7 +185,7 @@ usb_iterate (grub_usb_device_t dev, void *data __attribute__ ((unused))) + for (j = 0; j < interf->endpointcnt; j++) + { + struct grub_usb_desc_endp *endp; +- endp = &dev->config[0].interf[i].descendp[j]; ++ endp = dev->config[0].interf[i].descendp[j]; + + grub_printf ("Endpoint #%d: %s, max packed size: %d, transfer type: %s, latency: %d\n", + endp->endp_addr & 15, +diff --git a/grub-core/disk/usbms.c b/grub-core/disk/usbms.c +index b81e3ad9d..b1512dc12 100644 +--- a/grub-core/disk/usbms.c ++++ b/grub-core/disk/usbms.c +@@ -184,7 +184,7 @@ grub_usbms_attach (grub_usb_device_t usbdev, int configno, int interfno) + for (j = 0; j < interf->endpointcnt; j++) + { + struct grub_usb_desc_endp *endp; +- endp = &usbdev->config[0].interf[interfno].descendp[j]; ++ endp = usbdev->config[0].interf[interfno].descendp[j]; + + if ((endp->endp_addr & 128) && (endp->attrib & 3) == 2) + /* Bulk IN endpoint. */ +diff --git a/grub-core/term/usb_keyboard.c b/grub-core/term/usb_keyboard.c +index 7322d8dff..d590979f5 100644 +--- a/grub-core/term/usb_keyboard.c ++++ b/grub-core/term/usb_keyboard.c +@@ -175,7 +175,7 @@ grub_usb_keyboard_attach (grub_usb_device_t usbdev, int configno, int interfno) + for (j = 0; j < usbdev->config[configno].interf[interfno].descif->endpointcnt; + j++) + { +- endp = &usbdev->config[configno].interf[interfno].descendp[j]; ++ endp = usbdev->config[configno].interf[interfno].descendp[j]; + + if ((endp->endp_addr & 128) && grub_usb_get_ep_type(endp) + == GRUB_USB_EP_INTERRUPT) +diff --git a/include/grub/usb.h b/include/grub/usb.h +index 0f346af12..688c11f6d 100644 +--- a/include/grub/usb.h ++++ b/include/grub/usb.h +@@ -153,7 +153,7 @@ struct grub_usb_interface + { + struct grub_usb_desc_if *descif; + +- struct grub_usb_desc_endp *descendp; ++ struct grub_usb_desc_endp **descendp; + + /* A driver is handling this interface. Do we need to support multiple drivers + for single interface? +diff --git a/include/grub/usbdesc.h b/include/grub/usbdesc.h +index aac5ab05a..bb2ab2e27 100644 +--- a/include/grub/usbdesc.h ++++ b/include/grub/usbdesc.h +@@ -29,7 +29,8 @@ typedef enum { + GRUB_USB_DESCRIPTOR_INTERFACE, + GRUB_USB_DESCRIPTOR_ENDPOINT, + GRUB_USB_DESCRIPTOR_DEBUG = 10, +- GRUB_USB_DESCRIPTOR_HUB = 0x29 ++ GRUB_USB_DESCRIPTOR_HUB = 0x29, ++ GRUB_USB_DESCRIPTOR_SS_ENDPOINT_COMPANION = 0x30 + } grub_usb_descriptor_t; + + struct grub_usb_desc +@@ -105,6 +106,14 @@ struct grub_usb_desc_endp + grub_uint8_t interval; + } GRUB_PACKED; + ++struct grub_usb_desc_ssep { ++ grub_uint8_t length; ++ grub_uint8_t type; ++ grub_uint8_t maxburst; ++ grub_uint8_t attrib; ++ grub_uint16_t interval; ++} GRUB_PACKED; ++ + struct grub_usb_desc_str + { + grub_uint8_t length; +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0002-usb-Add-enum-for-xHCI.patch b/config/grub/patches/0005-xhci/0002-usb-Add-enum-for-xHCI.patch new file mode 100644 index 00000000..d61da615 --- /dev/null +++ b/config/grub/patches/0005-xhci/0002-usb-Add-enum-for-xHCI.patch @@ -0,0 +1,29 @@ +From e111983ca5e2a52bfe2bdc5cd639b06bb2f7902d Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph <patrick.rudolph@9elements.com> +Date: Sun, 15 Nov 2020 19:47:06 +0100 +Subject: [PATCH 2/8] usb: Add enum for xHCI + +Will be used in future patches. + +Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> +--- + include/grub/usb.h | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/include/grub/usb.h b/include/grub/usb.h +index 688c11f6d..ea6ee8c2c 100644 +--- a/include/grub/usb.h ++++ b/include/grub/usb.h +@@ -51,7 +51,8 @@ typedef enum + GRUB_USB_SPEED_NONE, + GRUB_USB_SPEED_LOW, + GRUB_USB_SPEED_FULL, +- GRUB_USB_SPEED_HIGH ++ GRUB_USB_SPEED_HIGH, ++ GRUB_USB_SPEED_SUPER + } grub_usb_speed_t; + + typedef int (*grub_usb_iterate_hook_t) (grub_usb_device_t dev, void *data); +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0003-usbtrans-Set-default-maximum-packet-size.patch b/config/grub/patches/0005-xhci/0003-usbtrans-Set-default-maximum-packet-size.patch new file mode 100644 index 00000000..70e73ca2 --- /dev/null +++ b/config/grub/patches/0005-xhci/0003-usbtrans-Set-default-maximum-packet-size.patch @@ -0,0 +1,33 @@ +From 3e25c83a1d1c6e149c7e9f0660ddadb2beca2476 Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph <patrick.rudolph@9elements.com> +Date: Sun, 15 Nov 2020 19:48:03 +0100 +Subject: [PATCH 3/8] usbtrans: Set default maximum packet size + +Set the maximum packet size to 512 for SuperSpeed devices. + +Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> +--- + grub-core/bus/usb/usbtrans.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/grub-core/bus/usb/usbtrans.c b/grub-core/bus/usb/usbtrans.c +index c5680b33a..c1080bb33 100644 +--- a/grub-core/bus/usb/usbtrans.c ++++ b/grub-core/bus/usb/usbtrans.c +@@ -128,8 +128,12 @@ grub_usb_control_msg (grub_usb_device_t dev, + setupdata_addr = grub_dma_get_phys (setupdata_chunk); + + /* Determine the maximum packet size. */ +- if (dev->descdev.maxsize0) ++ if (dev->descdev.maxsize0 && dev->speed != GRUB_USB_SPEED_SUPER) + max = dev->descdev.maxsize0; ++ else if (dev->descdev.maxsize0 && dev->speed == GRUB_USB_SPEED_SUPER) ++ max = 1UL << dev->descdev.maxsize0; ++ else if (dev->speed == GRUB_USB_SPEED_SUPER) ++ max = 512; + else + max = 64; + +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0004-grub-core-bus-usb-Add-function-pointer-for-attach-de.patch b/config/grub/patches/0005-xhci/0004-grub-core-bus-usb-Add-function-pointer-for-attach-de.patch new file mode 100644 index 00000000..a090e0ea --- /dev/null +++ b/config/grub/patches/0005-xhci/0004-grub-core-bus-usb-Add-function-pointer-for-attach-de.patch @@ -0,0 +1,121 @@ +From 89701aba00caa81bb566ab10da0c89264393be30 Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph <patrick.rudolph@9elements.com> +Date: Sun, 15 Nov 2020 19:51:42 +0100 +Subject: [PATCH 4/8] grub-core/bus/usb: Add function pointer for attach/detach + events + +The xHCI code needs to be called for attaching or detaching a device. +Introduce two functions pointers and call it from the USB hub code. + +Will be used in future commits, currently this doesn't change any functionality. + +Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> +--- + grub-core/bus/usb/ehci.c | 2 ++ + grub-core/bus/usb/ohci.c | 2 ++ + grub-core/bus/usb/uhci.c | 2 ++ + grub-core/bus/usb/usbhub.c | 19 +++++++++++++++++++ + include/grub/usb.h | 4 ++++ + 5 files changed, 29 insertions(+) + +diff --git a/grub-core/bus/usb/ehci.c b/grub-core/bus/usb/ehci.c +index 9abebc6bd..953b851c0 100644 +--- a/grub-core/bus/usb/ehci.c ++++ b/grub-core/bus/usb/ehci.c +@@ -1812,6 +1812,8 @@ static struct grub_usb_controller_dev usb_controller = { + .hubports = grub_ehci_hubports, + .portstatus = grub_ehci_portstatus, + .detect_dev = grub_ehci_detect_dev, ++ .attach_dev = NULL, ++ .detach_dev = NULL, + /* estimated max. count of TDs for one bulk transfer */ + .max_bulk_tds = GRUB_EHCI_N_TD * 3 / 4 + }; +diff --git a/grub-core/bus/usb/ohci.c b/grub-core/bus/usb/ohci.c +index 5363a61f6..7a3f3e154 100644 +--- a/grub-core/bus/usb/ohci.c ++++ b/grub-core/bus/usb/ohci.c +@@ -1440,6 +1440,8 @@ static struct grub_usb_controller_dev usb_controller = + .hubports = grub_ohci_hubports, + .portstatus = grub_ohci_portstatus, + .detect_dev = grub_ohci_detect_dev, ++ .attach_dev = NULL, ++ .detach_dev = NULL, + /* estimated max. count of TDs for one bulk transfer */ + .max_bulk_tds = GRUB_OHCI_TDS * 3 / 4 + }; +diff --git a/grub-core/bus/usb/uhci.c b/grub-core/bus/usb/uhci.c +index 0fdea4c1e..03c4605b2 100644 +--- a/grub-core/bus/usb/uhci.c ++++ b/grub-core/bus/usb/uhci.c +@@ -845,6 +845,8 @@ static struct grub_usb_controller_dev usb_controller = + .hubports = grub_uhci_hubports, + .portstatus = grub_uhci_portstatus, + .detect_dev = grub_uhci_detect_dev, ++ .attach_dev = NULL, ++ .detach_dev = NULL, + /* estimated max. count of TDs for one bulk transfer */ + .max_bulk_tds = N_TD * 3 / 4 + }; +diff --git a/grub-core/bus/usb/usbhub.c b/grub-core/bus/usb/usbhub.c +index 2ae29cba1..8e963e84b 100644 +--- a/grub-core/bus/usb/usbhub.c ++++ b/grub-core/bus/usb/usbhub.c +@@ -66,6 +66,15 @@ grub_usb_hub_add_dev (grub_usb_controller_t controller, + dev->split_hubport = split_hubport; + dev->split_hubaddr = split_hubaddr; + ++ if (controller->dev->attach_dev) { ++ err = controller->dev->attach_dev (controller, dev); ++ if (err) ++ { ++ grub_free (dev); ++ return NULL; ++ } ++ } ++ + err = grub_usb_device_initialize (dev); + if (err) + { +@@ -405,6 +414,8 @@ static void + detach_device (grub_usb_device_t dev) + { + unsigned i; ++ grub_usb_err_t err; ++ + int k; + if (!dev) + return; +@@ -425,6 +436,14 @@ detach_device (grub_usb_device_t dev) + if (inter && inter->detach_hook) + inter->detach_hook (dev, i, k); + } ++ if (dev->controller.dev->detach_dev) { ++ err = dev->controller.dev->detach_dev (&dev->controller, dev); ++ if (err) ++ { ++ // XXX ++ } ++ } ++ + grub_usb_devs[dev->addr] = 0; + } + +diff --git a/include/grub/usb.h b/include/grub/usb.h +index ea6ee8c2c..4dd179db2 100644 +--- a/include/grub/usb.h ++++ b/include/grub/usb.h +@@ -126,6 +126,10 @@ struct grub_usb_controller_dev + + grub_usb_speed_t (*detect_dev) (grub_usb_controller_t dev, int port, int *changed); + ++ grub_usb_err_t (*attach_dev) (grub_usb_controller_t ctrl, grub_usb_device_t dev); ++ ++ grub_usb_err_t (*detach_dev) (grub_usb_controller_t ctrl, grub_usb_device_t dev); ++ + /* Per controller flag - port reset pending, don't do another reset */ + grub_uint64_t pending_reset; + +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0005-grub-core-bus-usb-usbhub-Add-new-private-fields-for-.patch b/config/grub/patches/0005-xhci/0005-grub-core-bus-usb-usbhub-Add-new-private-fields-for-.patch new file mode 100644 index 00000000..7d69c3a6 --- /dev/null +++ b/config/grub/patches/0005-xhci/0005-grub-core-bus-usb-usbhub-Add-new-private-fields-for-.patch @@ -0,0 +1,77 @@ +From 5e5d74a4531770258e21dedd45c33f1a9d3afa6b Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph <patrick.rudolph@9elements.com> +Date: Sun, 15 Nov 2020 19:54:40 +0100 +Subject: [PATCH 5/8] grub-core/bus/usb/usbhub: Add new private fields for xHCI + controller + +Store the root port number, the route, consisting out of the port ID +in each nibble, and a pointer to driver private data. + +Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> +--- + grub-core/bus/usb/usbhub.c | 11 ++++++++--- + include/grub/usb.h | 5 +++++ + 2 files changed, 13 insertions(+), 3 deletions(-) + +diff --git a/grub-core/bus/usb/usbhub.c b/grub-core/bus/usb/usbhub.c +index 8e963e84b..b4b3a1a61 100644 +--- a/grub-core/bus/usb/usbhub.c ++++ b/grub-core/bus/usb/usbhub.c +@@ -49,7 +49,9 @@ static grub_usb_controller_dev_t grub_usb_list; + static grub_usb_device_t + grub_usb_hub_add_dev (grub_usb_controller_t controller, + grub_usb_speed_t speed, +- int split_hubport, int split_hubaddr) ++ int split_hubport, int split_hubaddr, ++ int root_portno, ++ grub_uint32_t route) + { + grub_usb_device_t dev; + int i; +@@ -65,6 +67,8 @@ grub_usb_hub_add_dev (grub_usb_controller_t controller, + dev->speed = speed; + dev->split_hubport = split_hubport; + dev->split_hubaddr = split_hubaddr; ++ dev->root_port = root_portno; ++ dev->route = route; + + if (controller->dev->attach_dev) { + err = controller->dev->attach_dev (controller, dev); +@@ -245,7 +249,7 @@ attach_root_port (struct grub_usb_hub *hub, int portno, + and full/low speed device connected to OHCI/UHCI needs not + transaction translation - e.g. hubport and hubaddr should be + always none (zero) for any device connected to any root hub. */ +- dev = grub_usb_hub_add_dev (hub->controller, speed, 0, 0); ++ dev = grub_usb_hub_add_dev (hub->controller, speed, 0, 0, portno, 0); + hub->controller->dev->pending_reset = 0; + npending--; + if (! dev) +@@ -676,7 +680,8 @@ poll_nonroot_hub (grub_usb_device_t dev) + + /* Add the device and assign a device address to it. */ + next_dev = grub_usb_hub_add_dev (&dev->controller, speed, +- split_hubport, split_hubaddr); ++ split_hubport, split_hubaddr, dev->root_port, ++ dev->route << 4 | (i & 0xf)); + if (dev->controller.dev->pending_reset) + { + dev->controller.dev->pending_reset = 0; +diff --git a/include/grub/usb.h b/include/grub/usb.h +index 4dd179db2..609faf7d0 100644 +--- a/include/grub/usb.h ++++ b/include/grub/usb.h +@@ -237,6 +237,11 @@ struct grub_usb_device + int split_hubport; + + int split_hubaddr; ++ ++ /* xHCI specific information */ ++ int root_port; ++ grub_uint32_t route; ++ void *xhci_priv; + }; + + +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0006-grub-core-bus-usb-Add-xhci-support.patch b/config/grub/patches/0005-xhci/0006-grub-core-bus-usb-Add-xhci-support.patch new file mode 100644 index 00000000..11df42d8 --- /dev/null +++ b/config/grub/patches/0005-xhci/0006-grub-core-bus-usb-Add-xhci-support.patch @@ -0,0 +1,2814 @@ +From fe3a0bce527e059e9121eb5ad2c3cc099f07a4bf Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph <patrick.rudolph@9elements.com> +Date: Sun, 15 Nov 2020 19:59:25 +0100 +Subject: [PATCH 6/8] grub-core/bus/usb: Add xhci support + +Add support for xHCI USB controllers. +The code is based on seabios implementation, but has been heavily +modified to match grubs internals. + +Changes done in version 2: +* Code cleanup +* Code style fixes +* Don't leak memory buffers +* Compile without warnings +* Add more defines +* Add more helper functions +* Don't assume a 1:1 virtual to physical mapping +* Flush cachelines after writing buffers +* Don't use hardcoded page size +* Proper scratchpad register setup +* xHCI bios ownership handoff + +Changes done in version 3: +* Fixed a race condition detecting events, which doesn't appear on + qemu based xHCI controllers +* Don't accidently disable USB3.0 devices after first command +* Support arbitrary protocol speed IDs +* Coding style cleanup + +Tested: +* Qemu system x86_64 + * virtual USB HID keyboard (usb-kbd) + * virtual USB HID mass storage (usb-storage) +* init Supermicro X11SSH-F + * iKVM HID keyboard + * USB3 HID mass storage (controller root port) + * USB HID keyboard + +TODO: + * Test on more hardware + * Test on USB3 hubs + * Support for USB 3.1 and USB 3.2 controllers + +Tested on qemu using coreboot and grub as payload: + +qemu-system-x86_64 -M q35 -bios $firmware -device qemu-xhci,id=xhci -accel kvm -m 1024M \ + -device usb-storage,drive=thumbdrive,bus=xhci.0,port=3 \ + -drive if=none,format=raw,id=thumbdrive,file=ubuntu-20.04.1-desktop-amd64.iso \ + -device usb-kbd,bus=xhci.0 + +Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> +Signed-off-by: sylv <sylv@sylv.io> +--- + Makefile.am | 2 +- + grub-core/Makefile.core.def | 7 + + grub-core/bus/usb/xhci-pci.c | 195 +++ + grub-core/bus/usb/xhci.c | 2496 ++++++++++++++++++++++++++++++++++ + include/grub/usb.h | 4 + + 5 files changed, 2703 insertions(+), 1 deletion(-) + create mode 100644 grub-core/bus/usb/xhci-pci.c + create mode 100644 grub-core/bus/usb/xhci.c + +diff --git a/Makefile.am b/Makefile.am +index 43635d5ff..65016f856 100644 +--- a/Makefile.am ++++ b/Makefile.am +@@ -434,7 +434,7 @@ if COND_i386_coreboot + FS_PAYLOAD_MODULES ?= $(shell cat grub-core/fs.lst) + default_payload.elf: grub-mkstandalone grub-mkimage FORCE + test -f $@ && rm $@ || true +- pkgdatadir=. ./grub-mkstandalone --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata ehci uhci ohci usb_keyboard usbms part_msdos ext2 fat at_keyboard part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc linux16 gzio echo help syslinuxcfg xnu $(FS_PAYLOAD_MODULES) password_pbkdf2 $(EXTRA_PAYLOAD_MODULES)' --fonts= --themes= --locales= -d grub-core/ /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg ++ pkgdatadir=. ./grub-mkstandalone --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata xhci ehci uhci ohci usb_keyboard usbms part_msdos ext2 fat at_keyboard part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc linux16 gzio echo help syslinuxcfg xnu $(FS_PAYLOAD_MODULES) password_pbkdf2 $(EXTRA_PAYLOAD_MODULES)' --fonts= --themes= --locales= -d grub-core/ /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg + endif + + endif +diff --git a/grub-core/Makefile.core.def b/grub-core/Makefile.core.def +index fb6078a34..64c3806ab 100644 +--- a/grub-core/Makefile.core.def ++++ b/grub-core/Makefile.core.def +@@ -667,6 +667,13 @@ module = { + enable = arm_coreboot; + }; + ++module = { ++ name = xhci; ++ common = bus/usb/xhci.c; ++ pci = bus/usb/xhci-pci.c; ++ enable = pci; ++}; ++ + module = { + name = pci; + common = bus/pci.c; +diff --git a/grub-core/bus/usb/xhci-pci.c b/grub-core/bus/usb/xhci-pci.c +new file mode 100644 +index 000000000..a5bd3c97d +--- /dev/null ++++ b/grub-core/bus/usb/xhci-pci.c +@@ -0,0 +1,195 @@ ++/* xhci.c - XHCI Support. */ ++/* ++ * GRUB -- GRand Unified Bootloader ++ * Copyright (C) 2020 9elements Cyber Security ++ * ++ * GRUB is free software: you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 3 of the License, or ++ * (at your option) any later version. ++ * ++ * GRUB is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with GRUB. If not, see <http://www.gnu.org/licenses/>. ++ */ ++ ++#include <grub/pci.h> ++#include <grub/cpu/pci.h> ++#include <grub/cs5536.h> ++#include <grub/misc.h> ++#include <grub/mm.h> ++#include <grub/time.h> ++#include <grub/usb.h> ++ ++#define GRUB_XHCI_PCI_SBRN_REG 0x60 ++#define GRUB_XHCI_ADDR_MEM_MASK (~0xff) ++ ++/* USBLEGSUP bits and related OS OWNED byte offset */ ++enum ++{ ++ GRUB_XHCI_BIOS_OWNED = (1 << 16), ++ GRUB_XHCI_OS_OWNED = (1 << 24) ++}; ++ ++/* PCI iteration function... */ ++static int ++grub_xhci_pci_iter (grub_pci_device_t dev, grub_pci_id_t pciid, ++ void *data __attribute__ ((unused))) ++{ ++ volatile grub_uint32_t *regs; ++ grub_uint32_t base, base_h; ++ grub_uint32_t eecp_offset; ++ grub_uint32_t usblegsup = 0; ++ grub_uint64_t maxtime; ++ grub_uint32_t interf; ++ grub_uint32_t subclass; ++ grub_uint32_t class; ++ grub_uint8_t release; ++ grub_uint32_t class_code; ++ ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: begin\n"); ++ ++ if (pciid == GRUB_CS5536_PCIID) ++ { ++ grub_dprintf ("xhci", "CS5536 not supported\n"); ++ return 0; ++ } ++ else ++ { ++ grub_pci_address_t addr; ++ addr = grub_pci_make_address (dev, GRUB_PCI_REG_CLASS); ++ class_code = grub_pci_read (addr) >> 8; ++ interf = class_code & 0xFF; ++ subclass = (class_code >> 8) & 0xFF; ++ class = class_code >> 16; ++ ++ /* If this is not an XHCI controller, just return. */ ++ if (class != 0x0c || subclass != 0x03 || interf != 0x30) ++ return 0; ++ ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: class OK\n"); ++ ++ /* Check Serial Bus Release Number */ ++ addr = grub_pci_make_address (dev, GRUB_XHCI_PCI_SBRN_REG); ++ release = grub_pci_read_byte (addr); ++ if (release != 0x30) ++ { ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: Wrong SBRN: %0x\n", ++ release); ++ return 0; ++ } ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: bus rev. num. OK\n"); ++ ++ /* Determine XHCI XHCC registers base address. */ ++ addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG0); ++ base = grub_pci_read (addr); ++ addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG1); ++ base_h = grub_pci_read (addr); ++ /* Stop if registers are mapped above 4G - GRUB does not currently ++ * work with registers mapped above 4G */ ++ if (((base & GRUB_PCI_ADDR_MEM_TYPE_MASK) != GRUB_PCI_ADDR_MEM_TYPE_32) ++ && (base_h != 0)) ++ { ++ grub_dprintf ("xhci", ++ "XHCI grub_xhci_pci_iter: registers above 4G are not supported\n"); ++ return 0; ++ } ++ base &= GRUB_PCI_ADDR_MEM_MASK; ++ if (!base) ++ { ++ grub_dprintf ("xhci", ++ "XHCI: XHCI is not mapped\n"); ++ return 0; ++ } ++ ++ /* Set bus master - needed for coreboot, VMware, broken BIOSes etc. */ ++ addr = grub_pci_make_address (dev, GRUB_PCI_REG_COMMAND); ++ grub_pci_write_word(addr, ++ GRUB_PCI_COMMAND_MEM_ENABLED ++ | GRUB_PCI_COMMAND_BUS_MASTER ++ | grub_pci_read_word(addr)); ++ ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: 32-bit XHCI OK\n"); ++ } ++ ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: iobase of XHCC: %08x\n", ++ (base & GRUB_XHCI_ADDR_MEM_MASK)); ++ ++ regs = grub_pci_device_map_range (dev, ++ (base & GRUB_XHCI_ADDR_MEM_MASK), ++ 0x100); ++ ++ /* Is there EECP ? */ ++ eecp_offset = (grub_le_to_cpu32 (regs[2]) >> 8) & 0xff; ++ ++ /* Determine and change ownership. */ ++ /* EECP offset valid in HCCPARAMS */ ++ /* Ownership can be changed via EECP only */ ++ if (pciid != GRUB_CS5536_PCIID && eecp_offset >= 0x40) ++ { ++ grub_pci_address_t pciaddr_eecp; ++ pciaddr_eecp = grub_pci_make_address (dev, eecp_offset); ++ ++ usblegsup = grub_pci_read (pciaddr_eecp); ++ if (usblegsup & GRUB_XHCI_BIOS_OWNED) ++ { ++ grub_boot_time ("Taking ownership of XHCI controller"); ++ grub_dprintf ("xhci", ++ "XHCI grub_xhci_pci_iter: XHCI owned by: BIOS\n"); ++ /* Ownership change - set OS_OWNED bit */ ++ grub_pci_write (pciaddr_eecp, usblegsup | GRUB_XHCI_OS_OWNED); ++ /* Ensure PCI register is written */ ++ grub_pci_read (pciaddr_eecp); ++ ++ /* Wait for finish of ownership change, XHCI specification ++ * doesn't say how long it can take... */ ++ maxtime = grub_get_time_ms () + 1000; ++ while ((grub_pci_read (pciaddr_eecp) & GRUB_XHCI_BIOS_OWNED) ++ && (grub_get_time_ms () < maxtime)); ++ if (grub_pci_read (pciaddr_eecp) & GRUB_XHCI_BIOS_OWNED) ++ { ++ grub_dprintf ("xhci", ++ "XHCI grub_xhci_pci_iter: XHCI change ownership timeout"); ++ /* Change ownership in "hard way" - reset BIOS ownership */ ++ grub_pci_write (pciaddr_eecp, GRUB_XHCI_OS_OWNED); ++ /* Ensure PCI register is written */ ++ grub_pci_read (pciaddr_eecp); ++ } ++ } ++ else if (usblegsup & GRUB_XHCI_OS_OWNED) ++ /* XXX: What to do in this case - nothing ? Can it happen ? */ ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: XHCI owned by: OS\n"); ++ else ++ { ++ grub_dprintf ("xhci", ++ "XHCI grub_Xhci_pci_iter: XHCI owned by: NONE\n"); ++ /* XXX: What to do in this case ? Can it happen ? ++ * Is code below correct ? */ ++ /* Ownership change - set OS_OWNED bit */ ++ grub_pci_write (pciaddr_eecp, GRUB_XHCI_OS_OWNED); ++ /* Ensure PCI register is written */ ++ grub_pci_read (pciaddr_eecp); ++ } ++ ++ /* Disable SMI, just to be sure. */ ++ pciaddr_eecp = grub_pci_make_address (dev, eecp_offset + 4); ++ grub_pci_write (pciaddr_eecp, 0); ++ /* Ensure PCI register is written */ ++ grub_pci_read (pciaddr_eecp); ++ } ++ ++ grub_dprintf ("xhci", "inithw: XHCI grub_xhci_pci_iter: ownership OK\n"); ++ ++ grub_xhci_init_device (regs); ++ return 0; ++} ++ ++void ++grub_xhci_pci_scan (void) ++{ ++ grub_pci_iterate (grub_xhci_pci_iter, NULL); ++} +diff --git a/grub-core/bus/usb/xhci.c b/grub-core/bus/usb/xhci.c +new file mode 100644 +index 000000000..f4591ffb5 +--- /dev/null ++++ b/grub-core/bus/usb/xhci.c +@@ -0,0 +1,2496 @@ ++/* xhci.c - XHCI Support. */ ++/* ++ * GRUB -- GRand Unified Bootloader ++ * Copyright (C) 2020 9elements Cyber Security ++ * ++ * GRUB is free software: you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 3 of the License, or ++ * (at your option) any later version. ++ * ++ * GRUB is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with GRUB. If not, see <http://www.gnu.org/licenses/>. ++ * ++ * Big parts of this software are inspired by seabios XHCI implementation ++ * Released under LGPLv3. Credits to: ++ * ++ * Copyright (C) 2013 Gerd Hoffmann <kraxel@redhat.com> ++ * Copyright (C) 2014 Kevin O'Connor <kevin@koconnor.net> ++ */ ++ ++#include <grub/dl.h> ++#include <grub/err.h> ++#include <grub/mm.h> ++#include <grub/usb.h> ++#include <grub/usbtrans.h> ++#include <grub/misc.h> ++#include <grub/time.h> ++#include <grub/loader.h> ++#include <grub/disk.h> ++#include <grub/dma.h> ++#include <grub/cache.h> ++#include <grub/i386/cpuid.h> ++ ++GRUB_MOD_LICENSE ("GPLv3+"); ++ ++/* This simple GRUB implementation of XHCI driver */ ++/* Based on the specification ++ * "eXtensible Host Controller Interface for Universal Serial Bus" Revision 1.2 ++ */ ++ ++ ++#define xhci_get_field(data, field) \ ++ (((data) >> field##_SHIFT) & field##_MASK) ++#define XHCI_PORTSC_PLS_MASK 0xf ++#define XHCI_PORTSC_PLS_SHIFT 5 ++#define XHCI_PORTSC_SPEED_MASK 0xf ++#define XHCI_PORTSC_SPEED_SHIFT 10 ++ ++enum ++{ ++ XHCI_USB_FULLSPEED = 1, ++ XHCI_USB_LOWSPEED, ++ XHCI_USB_HIGHSPEED, ++ XHCI_USB_SUPERSPEED ++}; ++ ++/* Chapter 5.3 Host Controller Capability Registers */ ++struct grub_xhci_caps { ++ grub_uint8_t caplength; ++ grub_uint8_t reserved_01; ++ grub_uint16_t hciversion; ++ grub_uint32_t hcsparams1; ++ grub_uint32_t hcsparams2; ++ grub_uint32_t hcsparams3; ++ grub_uint32_t hccparams; ++ grub_uint32_t dboff; ++ grub_uint32_t rtsoff; ++ grub_uint32_t hccparams2; ++} GRUB_PACKED; ++ ++/* extended capabilities */ ++struct grub_xhci_xcap { ++ grub_uint32_t cap; ++ grub_uint32_t data[]; ++} GRUB_PACKED; ++ ++#define XHCI_CAP_LEGACY_SUPPORT 1 ++#define XHCI_CAP_SUPPORTED_PROTOCOL 2 ++ ++struct xhci_portmap { ++ grub_uint8_t start; ++ grub_uint8_t count; ++} GRUB_PACKED; ++ ++struct grub_xhci_op { ++ grub_uint32_t usbcmd; ++ grub_uint32_t usbsts; ++ grub_uint32_t pagesize; ++ grub_uint32_t reserved_01[2]; ++ grub_uint32_t dnctl; ++ grub_uint32_t crcr_low; ++ grub_uint32_t crcr_high; ++ grub_uint32_t reserved_02[4]; ++ grub_uint32_t dcbaap_low; ++ grub_uint32_t dcbaap_high; ++ grub_uint32_t config; ++} GRUB_PACKED; ++ ++enum ++{ ++ GRUB_XHCI_CMD_RS = (1<<0), ++ GRUB_XHCI_CMD_HCRST = (1<<1), ++ GRUB_XHCI_CMD_INTE = (1<<2), ++ GRUB_XHCI_CMD_HSEE = (1<<3), ++ GRUB_XHCI_CMD_LHCRST = (1<<7), ++ GRUB_XHCI_CMD_CSS = (1<<8), ++ GRUB_XHCI_CMD_CRS = (1<<9), ++ GRUB_XHCI_CMD_EWE = (1<<10), ++ GRUB_XHCI_CMD_EU3S = (1<<11) ++}; ++ ++enum ++{ ++ GRUB_XHCI_STS_HCH = (1<<0), ++ GRUB_XHCI_STS_HSE = (1<<2), ++ GRUB_XHCI_STS_EINT = (1<<3), ++ GRUB_XHCI_STS_PCD = (1<<4), ++ GRUB_XHCI_STS_SSS = (1<<8), ++ GRUB_XHCI_STS_RSS = (1<<9), ++ GRUB_XHCI_STS_SRE = (1<<10), ++ GRUB_XHCI_STS_CNR = (1<<11), ++ GRUB_XHCI_STS_HCE = (1<<12) ++}; ++ ++ ++/* Port Registers Offset */ ++#define GRUB_XHCI_PR_OFFSET 0x400 ++/* Interrupter Registers Offset */ ++#define GRUB_XHCI_IR_OFFSET 0x20 ++ ++/* Port Status and Control registers offsets */ ++ ++/* Chapter 6 Data Structures */ ++#define ALIGN_SPBA 64 ++#define ALIGN_DCBAA 64 ++#define ALIGN_CMD_RING_SEG 64 ++#define ALIGN_EVT_RING_SEG 64 ++#define ALIGN_EVT_RING_TABLE 64 ++#define ALIGN_TRB 16 ++#define ALIGN_INCTX 64 ++#define ALIGN_SLOTCTX 32 ++ ++#define BOUNDARY_RING 0x10000 ++ ++enum ++{ ++ GRUB_XHCI_PORTSC_CCS = (1<<0), ++ GRUB_XHCI_PORTSC_PED = (1<<1), ++ GRUB_XHCI_PORTSC_OCA = (1<<3), ++ GRUB_XHCI_PORTSC_PR = (1<<4), ++ GRUB_XHCI_PORTSC_PP = (1<<9), ++ GRUB_XHCI_PORTSC_SPEED_FULL = (1<<10), ++ GRUB_XHCI_PORTSC_SPEED_LOW = (2<<10), ++ GRUB_XHCI_PORTSC_SPEED_HIGH = (3<<10), ++ GRUB_XHCI_PORTSC_SPEED_SUPER = (4<<10), ++ GRUB_XHCI_PORTSC_LWS = (1<<16), ++ GRUB_XHCI_PORTSC_CSC = (1<<17), ++ GRUB_XHCI_PORTSC_PEC = (1<<18), ++ GRUB_XHCI_PORTSC_WRC = (1<<19), ++ GRUB_XHCI_PORTSC_OCC = (1<<20), ++ GRUB_XHCI_PORTSC_PRC = (1<<21), ++ GRUB_XHCI_PORTSC_PLC = (1<<22), ++ GRUB_XHCI_PORTSC_CEC = (1<<23), ++ GRUB_XHCI_PORTSC_CAS = (1<<24), ++ GRUB_XHCI_PORTSC_WCE = (1<<25), ++ GRUB_XHCI_PORTSC_WDE = (1<<26), ++ GRUB_XHCI_PORTSC_WOE = (1<<27), ++ GRUB_XHCI_PORTSC_DR = (1<<30), ++ GRUB_XHCI_PORTSC_WPR = (1<<31) ++}; ++ ++/* XHCI memory data structs */ ++#define GRUB_XHCI_MAX_ENDPOINTS 32 ++ ++#define GRUB_XHCI_RING_ITEMS 128 ++#define GRUB_XHCI_RING_SIZE (GRUB_XHCI_RING_ITEMS*sizeof(struct grub_xhci_trb)) ++/* ++ * xhci_ring structs are allocated with XHCI_RING_SIZE alignment, ++ * then we can get it from a trb pointer (provided by evt ring). ++ */ ++#define XHCI_RING(_trb) \ ++ ((struct grub_xhci_ring*)((grub_uint32_t)(_trb) & ~(GRUB_XHCI_RING_SIZE-1))) ++ ++/* slot context */ ++struct grub_xhci_slotctx { ++ grub_uint32_t ctx[4]; ++ grub_uint32_t reserved_01[4]; ++} GRUB_PACKED; ++ ++/* endpoint context */ ++struct grub_xhci_epctx { ++ grub_uint32_t ctx[2]; ++ grub_uint32_t deq_low; ++ grub_uint32_t deq_high; ++ grub_uint32_t length; ++ grub_uint32_t reserved_01[3]; ++} GRUB_PACKED; ++ ++/* device context array element */ ++struct grub_xhci_devlist { ++ grub_uint32_t ptr_low; ++ grub_uint32_t ptr_high; ++} GRUB_PACKED; ++ ++/* input context */ ++struct grub_xhci_inctx { ++ grub_uint32_t del; ++ grub_uint32_t add; ++ grub_uint32_t reserved_01[6]; ++} GRUB_PACKED; ++ ++/* transfer block (ring element) */ ++struct grub_xhci_trb { ++ grub_uint32_t ptr_low; ++ grub_uint32_t ptr_high; ++ grub_uint32_t status; ++ grub_uint32_t control; ++} GRUB_PACKED; ++ ++#define TRB_C (1<<0) ++#define TRB_TYPE_SHIFT 10 ++#define TRB_TYPE_MASK 0x3f ++#define TRB_TYPE(t) (((t) >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) ++ ++#define TRB_EV_ED (1<<2) ++ ++#define TRB_TR_ENT (1<<1) ++#define TRB_TR_ISP (1<<2) ++#define TRB_TR_NS (1<<3) ++#define TRB_TR_CH (1<<4) ++#define TRB_TR_IOC (1<<5) ++#define TRB_TR_IDT (1<<6) ++#define TRB_TR_TBC_SHIFT 7 ++#define TRB_TR_TBC_MASK 0x3 ++#define TRB_TR_BEI (1<<9) ++#define TRB_TR_TLBPC_SHIFT 16 ++#define TRB_TR_TLBPC_MASK 0xf ++#define TRB_TR_FRAMEID_SHIFT 20 ++#define TRB_TR_FRAMEID_MASK 0x7ff ++#define TRB_TR_SIA (1<<31) ++ ++#define TRB_TR_DIR (1<<16) ++ ++#define TRB_CR_SLOTID_SHIFT 24 ++#define TRB_CR_SLOTID_MASK 0xff ++#define TRB_CR_EPID_SHIFT 16 ++#define TRB_CR_EPID_MASK 0x1f ++ ++#define TRB_CR_BSR (1<<9) ++#define TRB_CR_DC (1<<9) ++ ++#define TRB_LK_TC (1<<1) ++ ++#define TRB_INTR_SHIFT 22 ++#define TRB_INTR_MASK 0x3ff ++#define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) ++ ++typedef enum TRBType { ++ TRB_RESERVED = 0, ++ TR_NORMAL, ++ TR_SETUP, ++ TR_DATA, ++ TR_STATUS, ++ TR_ISOCH, ++ TR_LINK, ++ TR_EVDATA, ++ TR_NOOP, ++ CR_ENABLE_SLOT, ++ CR_DISABLE_SLOT, ++ CR_ADDRESS_DEVICE, ++ CR_CONFIGURE_ENDPOINT, ++ CR_EVALUATE_CONTEXT, ++ CR_RESET_ENDPOINT, ++ CR_STOP_ENDPOINT, ++ CR_SET_TR_DEQUEUE, ++ CR_RESET_DEVICE, ++ CR_FORCE_EVENT, ++ CR_NEGOTIATE_BW, ++ CR_SET_LATENCY_TOLERANCE, ++ CR_GET_PORT_BANDWIDTH, ++ CR_FORCE_HEADER, ++ CR_NOOP, ++ ER_TRANSFER = 32, ++ ER_COMMAND_COMPLETE, ++ ER_PORT_STATUS_CHANGE, ++ ER_BANDWIDTH_REQUEST, ++ ER_DOORBELL, ++ ER_HOST_CONTROLLER, ++ ER_DEVICE_NOTIFICATION, ++ ER_MFINDEX_WRAP, ++} TRBType; ++ ++typedef enum TRBCCode { ++ CC_INVALID = 0, ++ CC_SUCCESS, ++ CC_DATA_BUFFER_ERROR, ++ CC_BABBLE_DETECTED, ++ CC_USB_TRANSACTION_ERROR, ++ CC_TRB_ERROR, ++ CC_STALL_ERROR, ++ CC_RESOURCE_ERROR, ++ CC_BANDWIDTH_ERROR, ++ CC_NO_SLOTS_ERROR, ++ CC_INVALID_STREAM_TYPE_ERROR, ++ CC_SLOT_NOT_ENABLED_ERROR, ++ CC_EP_NOT_ENABLED_ERROR, ++ CC_SHORT_PACKET, ++ CC_RING_UNDERRUN, ++ CC_RING_OVERRUN, ++ CC_VF_ER_FULL, ++ CC_PARAMETER_ERROR, ++ CC_BANDWIDTH_OVERRUN, ++ CC_CONTEXT_STATE_ERROR, ++ CC_NO_PING_RESPONSE_ERROR, ++ CC_EVENT_RING_FULL_ERROR, ++ CC_INCOMPATIBLE_DEVICE_ERROR, ++ CC_MISSED_SERVICE_ERROR, ++ CC_COMMAND_RING_STOPPED, ++ CC_COMMAND_ABORTED, ++ CC_STOPPED, ++ CC_STOPPED_LENGTH_INVALID, ++ CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, ++ CC_ISOCH_BUFFER_OVERRUN = 31, ++ CC_EVENT_LOST_ERROR, ++ CC_UNDEFINED_ERROR, ++ CC_INVALID_STREAM_ID_ERROR, ++ CC_SECONDARY_BANDWIDTH_ERROR, ++ CC_SPLIT_TRANSACTION_ERROR ++} TRBCCode; ++ ++enum { ++ PLS_U0 = 0, ++ PLS_U1 = 1, ++ PLS_U2 = 2, ++ PLS_U3 = 3, ++ PLS_DISABLED = 4, ++ PLS_RX_DETECT = 5, ++ PLS_INACTIVE = 6, ++ PLS_POLLING = 7, ++ PLS_RECOVERY = 8, ++ PLS_HOT_RESET = 9, ++ PLS_COMPILANCE_MODE = 10, ++ PLS_TEST_MODE = 11, ++ PLS_RESUME = 15, ++}; ++ ++/* event ring segment */ ++struct grub_xhci_er_seg { ++ grub_uint32_t ptr_low; ++ grub_uint32_t ptr_high; ++ grub_uint32_t size; ++ grub_uint32_t reserved_01; ++} GRUB_PACKED; ++ ++struct grub_xhci_ring { ++ struct grub_xhci_trb ring[GRUB_XHCI_RING_ITEMS]; ++ struct grub_xhci_trb evt; ++ grub_uint32_t eidx; ++ grub_uint32_t nidx; ++ grub_uint32_t cs; ++}; ++ ++/* port registers */ ++struct grub_xhci_pr { ++ grub_uint32_t portsc; ++ grub_uint32_t portpmsc; ++ grub_uint32_t portli; ++ grub_uint32_t reserved_01; ++} GRUB_PACKED; ++ ++/* doorbell registers */ ++struct grub_xhci_db { ++ grub_uint32_t doorbell; ++} GRUB_PACKED; ++ ++/* runtime registers */ ++struct grub_xhci_rts { ++ grub_uint32_t mfindex; ++} GRUB_PACKED; ++ ++/* interrupter registers */ ++struct grub_xhci_ir { ++ grub_uint32_t iman; ++ grub_uint32_t imod; ++ grub_uint32_t erstsz; ++ grub_uint32_t reserved_01; ++ grub_uint32_t erstba_low; ++ grub_uint32_t erstba_high; ++ grub_uint32_t erdp_low; ++ grub_uint32_t erdp_high; ++} GRUB_PACKED; ++ ++struct grub_xhci_psid { ++ grub_uint8_t id; ++ grub_uint8_t psie; ++ grub_uint16_t psim; ++ grub_uint64_t bitrate; ++ grub_usb_speed_t grub_usb_speed; ++}; ++ ++struct grub_xhci_psids { ++ grub_uint8_t major; ++ grub_uint8_t minor; ++ struct grub_xhci_psid psids[16]; ++}; ++ ++struct grub_xhci ++{ ++ grub_uint8_t shutdown; /* 1 if preparing shutdown of controller */ ++ /* xhci registers */ ++ volatile struct grub_xhci_caps *caps; /* Capability registers */ ++ volatile struct grub_xhci_op *op; /* Operational registers */ ++ volatile struct grub_xhci_pr *pr; /* Port Registers */ ++ volatile struct grub_xhci_db *db; /* doorbell */ ++ volatile struct grub_xhci_ir *ir; /* Interrupt Registers */ ++ /* devinfo */ ++ grub_uint32_t xcap; ++ grub_uint32_t ports; ++ grub_uint32_t slots; ++ grub_uint8_t flag64; ++ grub_uint16_t spb; ++ grub_uint32_t pagesize; ++ struct xhci_portmap usb2; ++ struct xhci_portmap usb3; ++ struct grub_xhci_psids *psids; ++ /* xhci data structures */ ++ struct grub_pci_dma_chunk *devs_dma; ++ volatile struct grub_xhci_devlist *devs; ++ struct grub_pci_dma_chunk *cmds_dma; ++ volatile struct grub_xhci_ring *cmds; ++ struct grub_pci_dma_chunk *evts_dma; ++ volatile struct grub_xhci_ring *evts; ++ struct grub_pci_dma_chunk *eseg_dma; ++ volatile struct grub_xhci_er_seg *eseg; ++ struct grub_pci_dma_chunk *spba_dma; ++ struct grub_pci_dma_chunk *spad_dma; ++ ++ struct grub_xhci *next; ++}; ++ ++struct grub_xhci_priv { ++ grub_uint8_t slotid; ++ grub_uint32_t max_packet; ++ struct grub_pci_dma_chunk *enpoint_trbs_dma[32]; ++ volatile struct grub_xhci_ring *enpoint_trbs[32]; ++ struct grub_pci_dma_chunk *slotctx_dma; ++}; ++ ++struct grub_xhci_port { ++ grub_uint32_t portsc; ++ grub_uint32_t portpmsc; ++ grub_uint32_t portli; ++ grub_uint32_t reserved_01; ++}; ++ ++struct grub_xhci_transfer_controller_data { ++ grub_uint32_t transfer_size; ++}; ++ ++static struct grub_xhci *xhci; ++ ++/**************************************************************** ++ * general access functions ++ ****************************************************************/ ++ ++static inline void ++grub_xhci_write32(volatile void *addr, grub_uint32_t val) { ++ *(volatile grub_uint32_t *)addr = val; ++} ++static inline void ++grub_xhci_write16(volatile void *addr, grub_uint16_t val) { ++ *(volatile grub_uint16_t *)addr = val; ++} ++static inline void ++grub_xhci_write8(void *addr, grub_uint8_t val) { ++ *(volatile grub_uint8_t *)addr = val; ++} ++ ++static inline grub_uint32_t ++grub_xhci_read32(volatile void *addr) { ++ return grub_le_to_cpu32 (*((volatile grub_uint32_t *)addr)); ++} ++ ++static inline grub_uint16_t ++grub_xhci_read16(volatile void *addr) { ++ return grub_le_to_cpu16 (*((volatile grub_uint32_t *)addr)); ++} ++static inline grub_uint8_t ++grub_xhci_read8(volatile void *addr) { ++ return (*((volatile grub_uint32_t *)addr)); ++} ++ ++static inline grub_uint32_t ++grub_xhci_port_read (struct grub_xhci *x, grub_uint32_t port) ++{ ++ return grub_xhci_read32(&x->pr[port].portsc); ++} ++ ++static inline void ++grub_xhci_port_write (struct grub_xhci *x, grub_uint32_t port, ++ grub_uint32_t and_mask, grub_uint32_t or_mask) ++{ ++ grub_uint32_t reg = grub_xhci_port_read(x, port); ++ reg &= and_mask; ++ reg |= or_mask; ++ ++ grub_xhci_write32(&x->pr[port].portsc, reg); ++} ++ ++/**************************************************************** ++ * xhci status and support functions ++ ****************************************************************/ ++ ++static grub_uint32_t xhci_get_pagesize(struct grub_xhci *x) ++{ ++ /* Chapter 5.4.3 Page Size Register (PAGESIZE) */ ++ for (grub_uint8_t i = 0; i < 16; i++) ++ { ++ if (grub_xhci_read32(&x->op->pagesize) & (1 << i)) ++ return 1 << (12 + i); ++ } ++ return 0; ++} ++ ++static grub_uint8_t xhci_is_halted(struct grub_xhci *x) ++{ ++ return !!(grub_xhci_read32(&x->op->usbsts) & 1); ++} ++ ++/* Just for debugging */ ++static void xhci_check_status(struct grub_xhci *x) ++{ ++ grub_uint32_t reg; ++ ++ reg = grub_xhci_read32(&x->op->usbsts); ++ if (reg & 1) ++ grub_dprintf("xhci", "%s: xHCI halted\n", __func__); ++ if (reg & 2) ++ grub_dprintf("xhci", "%s: Host system error detected\n", __func__); ++ if (reg & (1 << 12)) ++ grub_dprintf("xhci", "%s: Internal error detected\n", __func__); ++ reg = grub_xhci_read32(&x->op->crcr_low); ++ if (reg & (1 << 3)) ++ grub_dprintf("xhci", "%s: Command ring running\n", __func__); ++} ++ ++/* xhci_memalign_dma32 allocates DMA memory satisfying alignment and boundary ++ * requirements without wasting to much memory */ ++static struct grub_pci_dma_chunk * ++xhci_memalign_dma32(grub_size_t align, ++ grub_size_t size, ++ grub_size_t boundary) ++{ ++ struct grub_pci_dma_chunk *tmp; ++ const grub_uint32_t mask = boundary - 1; ++ grub_uint32_t start, end; ++ ++ /* Allocate some memory and check if it doesn't cross boundary */ ++ tmp = grub_memalign_dma32(align, size); ++ start = grub_dma_get_phys(tmp); ++ end = start + size - 1; ++ if ((start & mask) == (end & mask)) ++ return tmp; ++ /* Buffer isn't usable, allocate bigger one */ ++ grub_dma_free(tmp); ++ ++ return grub_memalign_dma32(boundary, size); ++} ++ ++/**************************************************************** ++ * helper functions for in context DMA buffer ++ ****************************************************************/ ++ ++static int ++grub_xhci_inctx_size(struct grub_xhci *x) ++{ ++ const grub_uint8_t cnt = GRUB_XHCI_MAX_ENDPOINTS + 1; ++ return (sizeof(struct grub_xhci_inctx) * cnt) << x->flag64; ++} ++ ++static void ++grub_xhci_inctx_sync_dma_caches(struct grub_xhci *x, struct grub_pci_dma_chunk *inctx) ++{ ++ grub_arch_sync_dma_caches(inctx, grub_xhci_inctx_size(x)); ++} ++ ++static struct grub_pci_dma_chunk * ++grub_xhci_alloc_inctx(struct grub_xhci *x, int maxepid, ++ struct grub_usb_device *dev) ++{ ++ int size = grub_xhci_inctx_size(x); ++ struct grub_pci_dma_chunk *dma = xhci_memalign_dma32(ALIGN_INCTX, size, ++ x->pagesize); ++ if (!dma) ++ return NULL; ++ ++ volatile struct grub_xhci_inctx *in = grub_dma_get_virt(dma); ++ grub_memset((void *)in, 0, size); ++ ++ struct grub_xhci_slotctx *slot = (void*)&in[1 << x->flag64]; ++ slot->ctx[0] |= maxepid << 27; /* context entries */ ++ grub_dprintf("xhci", "%s: speed=%d root_port=%d\n", __func__, dev->speed, dev->root_port); ++ switch (dev->speed) { ++ case GRUB_USB_SPEED_FULL: ++ slot->ctx[0] |= XHCI_USB_FULLSPEED << 20; ++ break; ++ case GRUB_USB_SPEED_HIGH: ++ slot->ctx[0] |= XHCI_USB_HIGHSPEED << 20; ++ break; ++ case GRUB_USB_SPEED_LOW: ++ slot->ctx[0] |= XHCI_USB_LOWSPEED << 20; ++ break; ++ case GRUB_USB_SPEED_SUPER: ++ slot->ctx[0] |= XHCI_USB_SUPERSPEED << 20; ++ break; ++ case GRUB_USB_SPEED_NONE: ++ slot->ctx[0] |= 0 << 20; ++ break; ++ } ++ ++ /* Route is greater zero on devices that are connected to a non root hub */ ++ if (dev->route) ++ { ++ /* FIXME: Implement this code for non SuperSpeed hub devices */ ++ } ++ slot->ctx[0] |= dev->route; ++ slot->ctx[1] |= (dev->root_port+1) << 16; ++ ++ grub_arch_sync_dma_caches(in, size); ++ ++ return dma; ++} ++ ++/**************************************************************** ++ * xHCI event processing ++ ****************************************************************/ ++ ++/* Dequeue events on the XHCI event ring generated by the hardware */ ++static void xhci_process_events(struct grub_xhci *x) ++{ ++ volatile struct grub_xhci_ring *evts = x->evts; ++ /* XXX invalidate caches */ ++ ++ for (;;) { ++ /* check for event */ ++ grub_uint32_t nidx = grub_xhci_read32(&evts->nidx); ++ grub_uint32_t cs = grub_xhci_read32(&evts->cs); ++ volatile struct grub_xhci_trb *etrb = evts->ring + nidx; ++ grub_uint32_t control = grub_xhci_read32(&etrb->control); ++ if ((control & TRB_C) != (cs ? 1 : 0)) ++ return; ++ ++ /* process event */ ++ grub_uint32_t evt_type = TRB_TYPE(control); ++ grub_uint32_t evt_cc = (grub_xhci_read32(&etrb->status) >> 24) & 0xff; ++ ++ switch (evt_type) ++ { ++ case ER_TRANSFER: ++ case ER_COMMAND_COMPLETE: ++ { ++ struct grub_xhci_trb *rtrb = (void*)grub_xhci_read32(&etrb->ptr_low); ++ struct grub_xhci_ring *ring = XHCI_RING(rtrb); ++ volatile struct grub_xhci_trb *evt = &ring->evt; ++ grub_uint32_t eidx = rtrb - ring->ring + 1; ++ grub_dprintf("xhci", "%s: ring %p [trb %p, evt %p, type %d, eidx %d, cc %d]\n", ++ __func__, ring, rtrb, evt, evt_type, eidx, evt_cc); ++ *evt = *etrb; ++ grub_xhci_write32(&ring->eidx, eidx); ++ break; ++ } ++ case ER_PORT_STATUS_CHANGE: ++ { ++ /* Nothing to do here. grub_xhci_detect_dev will handle it */ ++ break; ++ } ++ default: ++ { ++ grub_dprintf("xhci", "%s: unknown event, type %d, cc %d\n", ++ __func__, evt_type, evt_cc); ++ break; ++ } ++ } ++ ++ /* move ring index, notify xhci */ ++ nidx++; ++ if (nidx == GRUB_XHCI_RING_ITEMS) ++ { ++ nidx = 0; ++ cs = cs ? 0 : 1; ++ grub_xhci_write32(&evts->cs, cs); ++ } ++ grub_xhci_write32(&evts->nidx, nidx); ++ volatile struct grub_xhci_ir *ir = x->ir; ++ grub_uint32_t erdp = (grub_uint32_t)(evts->ring + nidx); ++ grub_xhci_write32(&ir->erdp_low, erdp); ++ grub_xhci_write32(&ir->erdp_high, 0); ++ } ++} ++ ++/**************************************************************** ++ * TRB handling ++ ****************************************************************/ ++ ++/* Signal the hardware to process events on a TRB ring */ ++static void xhci_doorbell(struct grub_xhci *x, grub_uint32_t slotid, grub_uint32_t value) ++{ ++ xhci_check_status(x); ++ grub_dprintf("xhci", "%s: slotid %d, epid %d\n", __func__, slotid, value); ++ grub_xhci_write32(&x->db[slotid].doorbell, value); ++} ++ ++/* Check if a ring has any pending TRBs */ ++static int xhci_ring_busy(volatile struct grub_xhci_ring *ring) ++{ ++ grub_uint32_t eidx = grub_xhci_read32(&ring->eidx); ++ grub_uint32_t nidx = grub_xhci_read32(&ring->nidx); ++ ++ return (eidx != nidx); ++} ++ ++/* Returns free space in ring */ ++static int xhci_ring_free_space(volatile struct grub_xhci_ring *ring) ++{ ++ grub_uint32_t eidx = grub_xhci_read32(&ring->eidx); ++ grub_uint32_t nidx = grub_xhci_read32(&ring->nidx); ++ ++ /* nidx is never 0, so reduce ring buffer size by one */ ++ return (eidx > nidx) ? eidx-nidx ++ : (ARRAY_SIZE(ring->ring) - 1) - nidx + eidx; ++} ++ ++/* Check if a ring is full */ ++static int xhci_ring_full(volatile struct grub_xhci_ring *ring) ++{ ++ /* Might need to insert one link TRB */ ++ return xhci_ring_free_space(ring) <= 1; ++} ++ ++/* Check if a ring is almost full */ ++static int xhci_ring_almost_full(volatile struct grub_xhci_ring *ring) ++{ ++ /* Might need to insert one link TRB */ ++ return xhci_ring_free_space(ring) <= 2; ++} ++ ++/* Wait for a ring to empty (all TRBs processed by hardware) */ ++static int xhci_event_wait(struct grub_xhci *x, ++ volatile struct grub_xhci_ring *ring, ++ grub_uint32_t timeout) ++{ ++ grub_uint32_t end = grub_get_time_ms () + timeout; ++ ++ for (;;) ++ { ++ xhci_check_status(x); ++ xhci_process_events(x); ++ if (!xhci_ring_busy(ring)) ++ { ++ grub_uint32_t status = ring->evt.status; ++ return (status >> 24) & 0xff; ++ } ++ if (grub_get_time_ms () > end) ++ { ++ xhci_check_status(x); ++ grub_dprintf("xhci", "%s: Timeout waiting for event\n", __func__); ++ return -1; ++ } ++ } ++} ++ ++/* Add a TRB to the given ring, either regular or inline */ ++static void xhci_trb_fill(volatile struct grub_xhci_ring *ring, ++ grub_uint64_t ptr, grub_uint32_t xferlen, ++ grub_uint32_t flags) ++{ ++ volatile struct grub_xhci_trb *dst = &ring->ring[ring->nidx]; ++ dst->ptr_low = ptr & 0xffffffff; ++ dst->ptr_high = ptr >> 32; ++ dst->status = xferlen; ++ dst->control = flags | (ring->cs ? TRB_C : 0); ++ ++ grub_arch_sync_dma_caches(dst, sizeof(ring->ring[0])); ++} ++ ++/* ++ * Queue a TRB onto a ring. ++ * ++ * The caller must pass a pointer to the data in physical address-space or the ++ * data itself (but no more than 8 bytes) in data_or_addr. Inline data must have ++ * the flag TRB_TR_IDT set. ++ */ ++static void xhci_trb_queue(volatile struct grub_xhci_ring *ring, ++ grub_uint64_t data_or_addr, ++ grub_uint32_t xferlen, grub_uint32_t flags) ++{ ++ grub_dprintf("xhci", "%s: ring %p data %llx len %d flags 0x%x remain 0x%x\n", __func__, ++ ring, data_or_addr, xferlen & 0x1ffff, flags, xferlen >> 17); ++ ++ if (xhci_ring_full(ring)) ++ { ++ grub_dprintf("xhci", "%s: ERROR: ring %p is full, discarding TRB\n", ++ __func__, ring); ++ return; ++ } ++ ++ if (ring->nidx >= ARRAY_SIZE(ring->ring) - 1) ++ { ++ /* Reset to command buffer pointer to the first element */ ++ xhci_trb_fill(ring, (grub_addr_t)ring->ring, 0, (TR_LINK << 10) | TRB_LK_TC); ++ ring->nidx = 0; ++ ring->cs ^= 1; ++ grub_dprintf("xhci", "%s: ring %p [linked]\n", __func__, ring); ++ } ++ ++ xhci_trb_fill(ring, data_or_addr, xferlen, flags); ++ ring->nidx++; ++ grub_dprintf("xhci", "%s: ring %p [nidx %d, len %d]\n", ++ __func__, ring, ring->nidx, xferlen); ++} ++ ++/* ++ * Queue a TRB onto a ring and flush it if necessary. ++ * ++ * The caller must pass a pointer to the data in physical address-space or the ++ * data itself (but no more than 8 bytes) in data_or_addr. Inline data must have ++ * the flag TRB_TR_IDT set. ++ */ ++static int xhci_trb_queue_and_flush(struct grub_xhci *x, ++ grub_uint32_t slotid, ++ grub_uint32_t epid, ++ volatile struct grub_xhci_ring *ring, ++ grub_uint64_t data_or_addr, ++ grub_uint32_t xferlen, grub_uint32_t flags) ++{ ++ grub_uint8_t submit = 0; ++ if (xhci_ring_almost_full(ring)) ++ { ++ grub_dprintf("xhci", "%s: almost full e %d n %d\n", __func__, ring->eidx, ring->nidx); ++ flags |= TRB_TR_IOC; ++ submit = 1; ++ } ++ /* Note: xhci_trb_queue might queue on or two elements, if the end of the TRB ++ * has been reached. The caller must account for that when filling the TRB. */ ++ xhci_trb_queue(ring, data_or_addr, xferlen, flags); ++ /* Submit if less no free slot is remaining, we might need an additional ++ * one on the next call to this function. */ ++ if (submit) ++ { ++ xhci_doorbell(x, slotid, epid); ++ int rc = xhci_event_wait(x, ring, 1000); ++ grub_dprintf("xhci", "%s: xhci_event_wait = %d\n", __func__, rc); ++ return rc; ++ } ++ return 0; ++} ++ ++/**************************************************************** ++ * xHCI command functions ++ ****************************************************************/ ++ ++/* Submit a command to the xHCI command TRB */ ++static int xhci_cmd_submit(struct grub_xhci *x, ++ struct grub_pci_dma_chunk *inctx_dma, ++ grub_uint32_t flags) ++{ ++ volatile struct grub_xhci_inctx *inctx; ++ /* Don't submit if halted, it will fail */ ++ if (xhci_is_halted(x)) ++ return -1; ++ ++ if (inctx_dma) ++ { ++ grub_xhci_inctx_sync_dma_caches(x, inctx_dma); ++ ++ inctx = grub_dma_get_virt(inctx_dma); ++ ++ struct grub_xhci_slotctx *slot = (void*)&inctx[1 << x->flag64]; ++ grub_uint32_t port = ((slot->ctx[1] >> 16) & 0xff) - 1; ++ grub_uint32_t portsc = grub_xhci_port_read(x, port); ++ if (!(portsc & GRUB_XHCI_PORTSC_CCS)) ++ { ++ grub_dprintf("xhci", "%s: root port %d no longer connected\n", ++ __func__, port); ++ return -1; ++ } ++ xhci_trb_queue(x->cmds, grub_dma_get_phys(inctx_dma), 0, flags); ++ } ++ else ++ { ++ xhci_trb_queue(x->cmds, 0, 0, flags); ++ } ++ ++ xhci_doorbell(x, 0, 0); ++ int rc = xhci_event_wait(x, x->cmds, 1000); ++ grub_dprintf("xhci", "%s: xhci_event_wait = %d\n", __func__, rc); ++ ++ return rc; ++} ++ ++static int xhci_cmd_enable_slot(struct grub_xhci *x) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_ENABLE_SLOT << 10); ++ ++ grub_dprintf("xhci", "%s:\n", __func__); ++ int cc = xhci_cmd_submit(x, NULL, flags); ++ if (cc != CC_SUCCESS) ++ return -1; ++ grub_dprintf("xhci", "%s: %p\n", __func__, &x->cmds->evt.control); ++ grub_dprintf("xhci", "%s: %x\n", __func__, grub_xhci_read32(&x->cmds->evt.control)); ++ ++ return (grub_xhci_read32(&x->cmds->evt.control) >> 24) & 0xff; ++} ++ ++static int xhci_cmd_disable_slot(struct grub_xhci *x, grub_uint32_t slotid) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_DISABLE_SLOT << 10); ++ flags |= (slotid << 24); ++ ++ grub_dprintf("xhci", "%s: slotid %d\n", __func__, slotid); ++ return xhci_cmd_submit(x, NULL, flags); ++} ++ ++static int xhci_cmd_stop_endpoint(struct grub_xhci *x, grub_uint32_t slotid ++ , grub_uint32_t epid ++ , grub_uint32_t suspend) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_STOP_ENDPOINT << 10); ++ flags |= (epid << 16); ++ flags |= (suspend << 23) ; ++ flags |= (slotid << 24); ++ ++ return xhci_cmd_submit(x, NULL, flags); ++} ++ ++static int xhci_cmd_reset_endpoint(struct grub_xhci *x, grub_uint32_t slotid ++ , grub_uint32_t epid ++ , grub_uint32_t preserve) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (preserve << 9); ++ flags |= (CR_RESET_ENDPOINT << 10); ++ flags |= (epid << 16); ++ flags |= (slotid << 24); ++ ++ return xhci_cmd_submit(x, NULL, flags); ++} ++ ++static int xhci_cmd_set_dequeue_pointer(struct grub_xhci *x, grub_uint32_t slotid ++ , grub_uint32_t epid ++ , grub_addr_t tr_deque_pointer) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_SET_TR_DEQUEUE << 10); ++ flags |= (epid << 16); ++ flags |= (slotid << 24); ++ ++ xhci_trb_queue(x->cmds, tr_deque_pointer, 0, flags); ++ ++ xhci_doorbell(x, 0, 0); ++ int rc = xhci_event_wait(x, x->cmds, 1000); ++ grub_dprintf("xhci", "%s: xhci_event_wait = %d\n", __func__, rc); ++ ++ return rc; ++} ++ ++static int xhci_cmd_address_device(struct grub_xhci *x, grub_uint32_t slotid, ++ struct grub_pci_dma_chunk *inctx_dma) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_ADDRESS_DEVICE << 10); ++ flags |= (slotid << 24); ++ ++ grub_dprintf("xhci", "%s: slotid %d\n", __func__, slotid); ++ return xhci_cmd_submit(x, inctx_dma, flags); ++} ++ ++static int xhci_cmd_configure_endpoint(struct grub_xhci *x, grub_uint32_t slotid, ++ struct grub_pci_dma_chunk *inctx_dma) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_CONFIGURE_ENDPOINT << 10); ++ flags |= (slotid << 24); ++ ++ grub_dprintf("xhci", "%s: slotid %d\n", __func__, slotid); ++ return xhci_cmd_submit(x, inctx_dma, flags); ++} ++ ++static int xhci_cmd_evaluate_context(struct grub_xhci *x, grub_uint32_t slotid, ++ struct grub_pci_dma_chunk *inctx_dma) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_EVALUATE_CONTEXT << 10); ++ flags |= (slotid << 24); ++ ++ grub_dprintf("xhci", "%s: slotid %d\n", __func__, slotid); ++ return xhci_cmd_submit(x, inctx_dma, flags); ++} ++ ++/**************************************************************** ++ * xHCI host controller initialization ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_reset (struct grub_xhci *x) ++{ ++ grub_uint32_t reg; ++ grub_uint32_t end; ++ ++ reg = grub_xhci_read32(&x->op->usbcmd); ++ if (reg & GRUB_XHCI_CMD_RS) ++ { ++ reg &= ~GRUB_XHCI_CMD_RS; ++ grub_xhci_write32(&x->op->usbcmd, reg); ++ ++ end = grub_get_time_ms () + 32; ++ while (grub_xhci_read32(&x->op->usbcmd) & GRUB_XHCI_STS_HCH) ++ { ++ if (grub_get_time_ms () > end) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ grub_millisleep(1); ++ } ++ } ++ ++ grub_dprintf("xhci", "grub_xhci_reset: resetting HC\n"); ++ grub_xhci_write32(&x->op->usbcmd, GRUB_XHCI_CMD_HCRST); ++ ++ /* Wait for device to complete reset and be enabled */ ++ end = grub_get_time_ms () + 100; ++ while (grub_xhci_read32(&x->op->usbcmd) & GRUB_XHCI_CMD_HCRST) ++ { ++ if (grub_get_time_ms () > end) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ grub_millisleep(1); ++ } ++ ++ /* Wait for device to complete reset and be enabled */ ++ end = grub_get_time_ms () + 100; ++ while (grub_xhci_read32(&x->op->usbsts) & GRUB_XHCI_STS_CNR) ++ { ++ if (grub_get_time_ms () > end) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ grub_millisleep(1); ++ } ++ ++ grub_xhci_write32(&x->op->config, x->slots); ++ grub_xhci_write32(&x->op->dcbaap_low, grub_dma_get_phys(x->devs_dma)); ++ grub_xhci_write32(&x->op->dcbaap_high, 0); ++ grub_xhci_write32(&x->op->crcr_low, grub_dma_get_phys(x->cmds_dma)| 1); ++ grub_xhci_write32(&x->op->crcr_high, 0); ++ x->cmds->cs = 1; ++ ++ grub_arch_sync_dma_caches(x->cmds, sizeof(*x->cmds)); ++ ++ x->eseg->ptr_low = grub_dma_get_phys(x->evts_dma); ++ x->eseg->ptr_high = 0; ++ x->eseg->size = GRUB_XHCI_RING_ITEMS; ++ ++ grub_arch_sync_dma_caches(x->eseg, sizeof(*x->eseg)); ++ ++ grub_xhci_write32(&x->ir->erstsz, 1); ++ grub_xhci_write32(&x->ir->erdp_low, grub_dma_get_phys(x->evts_dma)); ++ grub_xhci_write32(&x->ir->erdp_high, 0); ++ grub_xhci_write32(&x->ir->erstba_low, grub_dma_get_phys(x->eseg_dma)); ++ grub_xhci_write32(&x->ir->erstba_high, 0); ++ x->evts->cs = 1; ++ ++ grub_arch_sync_dma_caches(x->evts, sizeof(*x->eseg)); ++ ++ xhci_check_status(x); ++ ++ grub_dprintf ("xhci", "XHCI OP COMMAND: %08x\n", ++ grub_xhci_read32 (&x->op->usbcmd)); ++ grub_dprintf ("xhci", "XHCI OP STATUS: %08x\n", ++ grub_xhci_read32 (&x->op->usbsts)); ++ grub_dprintf ("xhci", "XHCI OP PAGESIZE: %08x\n", ++ grub_xhci_read32 (&x->op->pagesize)); ++ grub_dprintf ("xhci", "XHCI OP DNCTRL: %08x\n", ++ grub_xhci_read32 (&x->op->dnctl)); ++ grub_dprintf ("xhci", "XHCI OP CRCR_LOW: %08x\n", ++ grub_xhci_read32 (&x->op->crcr_low)); ++ grub_dprintf ("xhci", "XHCI OP CRCR_HIGH: %08x\n", ++ grub_xhci_read32 (&x->op->crcr_high)); ++ grub_dprintf ("xhci", "XHCI OP DCBAAP_LOW: %08x\n", ++ grub_xhci_read32 (&x->op->dcbaap_low)); ++ grub_dprintf ("xhci", "XHCI OP DCBAAP_HIGH: %08x\n", ++ grub_xhci_read32 (&x->op->dcbaap_high)); ++ grub_dprintf ("xhci", "XHCI OP CONFIG: %08x\n", ++ grub_xhci_read32 (&x->op->config)); ++ grub_dprintf ("xhci", "XHCI IR ERSTSZ: %08x\n", ++ grub_xhci_read32 (&x->ir->erstsz)); ++ grub_dprintf ("xhci", "XHCI IR ERDP: %08x\n", ++ grub_xhci_read32 (&x->ir->erdp_low)); ++ grub_dprintf ("xhci", "XHCI IR ERSTBA: %08x\n", ++ grub_xhci_read32 (&x->ir->erstba_low)); ++ ++ xhci_check_status(x); ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++static grub_usb_err_t ++grub_xhci_request_legacy_handoff(volatile struct grub_xhci_xcap *xcap) ++{ ++ grub_uint32_t end; ++ ++ end = grub_get_time_ms () + 10; ++ for (;;) ++ { ++ grub_uint32_t cap = grub_xhci_read32(&xcap->cap); ++ if (cap & (1 << 16)) ++ grub_xhci_write32(&xcap->cap, cap | (1 << 24)); ++ else ++ break; ++ ++ if (grub_get_time_ms () > end) ++ { ++ grub_dprintf ("xhci","ERROR: %s TIMEOUT\n", __func__); ++ return GRUB_USB_ERR_TIMEOUT; ++ } ++ grub_millisleep(1); ++ } ++ return GRUB_USB_ERR_NONE; ++} ++ ++static void ++grub_xhci_fill_default_speed_mapping(struct grub_xhci_psids *ids) ++{ ++ /* Chapter 7.2.2.1.1 "Default USB Speed ID Mapping" */ ++ ids->psids[0].id = 1; ++ ids->psids[0].psie = 2; ++ ids->psids[0].psim = 12; ++ ids->psids[1].id = 2; ++ ids->psids[1].psie = 1; ++ ids->psids[1].psim = 1500; ++ ids->psids[2].id = 3; ++ ids->psids[2].psie = 2; ++ ids->psids[2].psim = 480; ++ ids->psids[3].id = 4; ++ ids->psids[3].psie = 3; ++ ids->psids[3].psim = 5; ++ ids->psids[4].id = 5; ++ ids->psids[4].psie = 3; ++ ids->psids[4].psim = 10; ++ ids->psids[5].id = 6; ++ ids->psids[5].psie = 3; ++ ids->psids[5].psim = 10; ++ ids->psids[6].id = 7; ++ ids->psids[6].psie = 3; ++ ids->psids[6].psim = 20; ++} ++ ++static void ++grub_xhci_calc_speed_mapping(struct grub_xhci_psids *ids) ++{ ++ const grub_uint64_t mult[4] = {1ULL, 1000ULL, 1000000ULL, 1000000000ULL}; ++ ++ for (grub_uint8_t i = 0; i < 16; i++) ++ { ++ if (ids->psids[i].id == 0) ++ continue; ++ ids->psids[i].bitrate = mult[ids->psids[i].psie & 3] * (grub_uint64_t)ids->psids[i].psim; ++ if (ids->psids[i].bitrate < 12000000ULL) ++ ids->psids[i].grub_usb_speed = GRUB_USB_SPEED_LOW; ++ else if (ids->psids[i].bitrate < 480000000ULL) ++ ids->psids[i].grub_usb_speed = GRUB_USB_SPEED_FULL; ++ else if (ids->psids[i].bitrate > 1200000000ULL) ++ ids->psids[i].grub_usb_speed = GRUB_USB_SPEED_SUPER; ++ else ++ ids->psids[i].grub_usb_speed = GRUB_USB_SPEED_HIGH; ++ } ++} ++ ++ ++/* PCI iteration function... */ ++void ++grub_xhci_init_device (volatile void *regs) ++{ ++ struct grub_xhci *x; ++ grub_uint32_t hcs1, hcc, reg; ++ ++ /* Allocate memory for the controller and fill basic values. */ ++ x = grub_zalloc (sizeof (*x)); ++ if (!x) ++ { ++ grub_dprintf("xhci", "Failed to allocate memory\n"); ++ return; ++ } ++ x->caps = (volatile struct grub_xhci_caps *) regs; ++ x->op = (volatile struct grub_xhci_op *) (((grub_uint8_t *)regs) + ++ grub_xhci_read8(&x->caps->caplength)); ++ x->pr = (volatile struct grub_xhci_pr *) (((grub_uint8_t *)x->op) + ++ GRUB_XHCI_PR_OFFSET); ++ x->db = (volatile struct grub_xhci_db *) (((grub_uint8_t *)regs) + ++ grub_xhci_read32(&x->caps->dboff)); ++ x->ir = (volatile struct grub_xhci_ir *) (((grub_uint8_t *)regs) + ++ grub_xhci_read32(&x->caps->rtsoff) + GRUB_XHCI_IR_OFFSET); ++ ++ grub_dprintf ("xhci", "XHCI init: CAPLENGTH: 0x%02x\n", ++ grub_xhci_read8 (&x->caps->caplength)); ++ grub_dprintf ("xhci", "XHCI init: HCIVERSION: 0x%04x\n", ++ grub_xhci_read16 (&x->caps->hciversion)); ++ grub_dprintf ("xhci", "XHCI init: HCSPARAMS1: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->hcsparams1)); ++ grub_dprintf ("xhci", "XHCI init: HCSPARAMS2: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->hcsparams2)); ++ grub_dprintf ("xhci", "XHCI init: HCSPARAMS3: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->hcsparams3)); ++ grub_dprintf ("xhci", "XHCI init: HCCPARAMS: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->hcsparams3)); ++ grub_dprintf ("xhci", "XHCI init: DBOFF: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->dboff)); ++ grub_dprintf ("xhci", "XHCI init: RTOFF: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->rtsoff)); ++ ++ hcs1 = grub_xhci_read32(&x->caps->hcsparams1); ++ hcc = grub_xhci_read32(&x->caps->hccparams); ++ x->ports = (grub_uint32_t) ((hcs1 >> 24) & 0xff); ++ x->slots = (grub_uint32_t) (hcs1 & 0xff); ++ x->xcap = (grub_uint32_t) ((hcc >> 16) & 0xffff) * sizeof(grub_uint32_t); ++ x->flag64 = (grub_uint8_t) ((hcc & 0x04) ? 1 : 0); ++ grub_dprintf("xhci", "XHCI init: %d ports, %d slots, %d byte contexts\n" ++ , x->ports, x->slots, x->flag64 ? 64 : 32); ++ ++ x->psids = grub_zalloc (sizeof (struct grub_xhci_psids) * x->ports); ++ if (x->xcap) ++ { ++ grub_uint32_t off; ++ volatile grub_uint8_t *addr = (grub_uint8_t *) x->caps + x->xcap; ++ do ++ { ++ volatile struct grub_xhci_xcap *xcap = (void *)addr; ++ grub_uint32_t ports, name, cap = grub_xhci_read32(&xcap->cap); ++ switch (cap & 0xff) { ++ case XHCI_CAP_LEGACY_SUPPORT: ++ { ++ if (grub_xhci_request_legacy_handoff(xcap) != GRUB_USB_ERR_NONE) ++ { ++ grub_dprintf("xhci", "XHCI init: Failed to get xHCI ownership\n"); ++ goto fail; ++ } ++ break; ++ } ++ case XHCI_CAP_SUPPORTED_PROTOCOL: ++ { ++ name = grub_xhci_read32(&xcap->data[0]); ++ ports = grub_xhci_read32(&xcap->data[1]); ++ const grub_uint8_t major = (cap >> 24) & 0xff; ++ const grub_uint8_t minor = (cap >> 16) & 0xff; ++ const grub_uint8_t psic = (ports >> 28) & 0xf; ++ const grub_uint8_t count = (ports >> 8) & 0xff; ++ const grub_uint8_t start = (ports >> 0) & 0xff; ++ grub_dprintf("xhci", "XHCI init: protocol %c%c%c%c %x.%02x" ++ ", %d ports (offset %d), def %x, psic %d\n" ++ , (name >> 0) & 0xff ++ , (name >> 8) & 0xff ++ , (name >> 16) & 0xff ++ , (name >> 24) & 0xff ++ , major, minor ++ , count, start ++ , ports >> 16 ++ , psic); ++ if (name == 0x20425355 /* "USB " */) ++ { ++ if (major == 2) ++ { ++ x->usb2.start = start; ++ x->usb2.count = count; ++ } ++ else if (major == 3) ++ { ++ x->usb3.start = start; ++ x->usb3.count = count; ++ } ++ ++ for (grub_uint32_t p = start - 1; p < start + count - 1UL; p++) ++ { ++ x->psids[p].major = major; ++ x->psids[p].minor = minor; ++ grub_xhci_fill_default_speed_mapping(&x->psids[p]); ++ for (grub_uint8_t i = 0; i < psic; i++) ++ { ++ grub_uint32_t psid = grub_xhci_read32(&xcap->data[3 + i]); ++ x->psids[p].psids[i].id = (psid >> 0) & 0xf; ++ x->psids[p].psids[i].psie = (psid >> 4) & 0x3; ++ x->psids[p].psids[i].psim = (psid >> 16) & 0xfffff; ++ } ++ grub_xhci_calc_speed_mapping(&x->psids[p]); ++ } ++ } ++ ++ break; ++ } ++ default: ++ { ++ grub_dprintf("xhci", "XHCI extcap 0x%x @ %p\n", cap & 0xff, addr); ++ break; ++ } ++ } ++ off = (cap >> 8) & 0xff; ++ addr += off << 2; ++ } ++ while (off > 0); ++ } ++ ++ x->pagesize = xhci_get_pagesize(x); ++ grub_dprintf("xhci", "XHCI init: Minimum supported page size 0x%x\n", ++ x->pagesize); ++ ++ /* Chapter 6.1 Device Context Base Address Array */ ++ x->devs_dma = xhci_memalign_dma32(ALIGN_DCBAA, ++ sizeof(*x->devs) * (x->slots + 1), ++ x->pagesize); ++ if (!x->devs_dma) ++ goto fail; ++ x->devs = grub_dma_get_virt(x->devs_dma); ++ grub_memset((void *)x->devs, 0, sizeof(*x->devs) * (x->slots + 1)); ++ grub_arch_sync_dma_caches(x->devs, sizeof(*x->devs) * (x->slots + 1)); ++ grub_dprintf ("xhci", "XHCI init: device memory %p (%x)\n", ++ grub_dma_get_virt(x->devs_dma), ++ grub_dma_get_phys(x->devs_dma)); ++ ++ /* Chapter 6.5 Event Ring Segment Table */ ++ x->eseg_dma = xhci_memalign_dma32(ALIGN_EVT_RING_TABLE, sizeof(*x->eseg), 0); ++ if (!x->eseg_dma) ++ goto fail; ++ x->eseg = grub_dma_get_virt(x->eseg_dma); ++ grub_memset((void *)x->eseg, 0, sizeof(*x->eseg)); ++ grub_arch_sync_dma_caches(x->eseg, sizeof(*x->eseg)); ++ grub_dprintf ("xhci", "XHCI init: event ring table memory %p (%x)\n", ++ grub_dma_get_virt(x->eseg_dma), ++ grub_dma_get_phys(x->eseg_dma)); ++ ++ x->cmds_dma = xhci_memalign_dma32(ALIGN_CMD_RING_SEG, sizeof(*x->cmds), ++ BOUNDARY_RING); ++ if (!x->cmds_dma) ++ goto fail; ++ x->cmds = grub_dma_get_virt(x->cmds_dma); ++ grub_memset((void *)x->cmds, 0, sizeof(*x->cmds)); ++ grub_arch_sync_dma_caches(x->cmds, sizeof(*x->cmds)); ++ grub_dprintf ("xhci", "XHCI init: command ring memory %p (%x)\n", ++ grub_dma_get_virt(x->cmds_dma), ++ grub_dma_get_phys(x->cmds_dma)); ++ ++ x->evts_dma = xhci_memalign_dma32(ALIGN_EVT_RING_SEG, sizeof(*x->evts), ++ BOUNDARY_RING); ++ if (!x->evts_dma) ++ goto fail; ++ x->evts = grub_dma_get_virt(x->evts_dma); ++ grub_memset((void *)x->evts, 0, sizeof(*x->evts)); ++ grub_arch_sync_dma_caches(x->evts, sizeof(*x->evts)); ++ grub_dprintf ("xhci", "XHCI init: event ring memory %p (%x)\n", ++ grub_dma_get_virt(x->evts_dma), ++ grub_dma_get_phys(x->evts_dma)); ++ ++ /* Chapter 4.20 Scratchpad Buffers */ ++ reg = grub_xhci_read32(&x->caps->hcsparams2); ++ x->spb = (reg >> 21 & 0x1f) << 5 | reg >> 27; ++ if (x->spb) ++ { ++ volatile grub_uint64_t *spba; ++ grub_dprintf("xhci", "XHCI init: set up %d scratch pad buffers\n", ++ x->spb); ++ x->spba_dma = xhci_memalign_dma32(ALIGN_SPBA, sizeof(*spba) * x->spb, ++ x->pagesize); ++ if (!x->spba_dma) ++ goto fail; ++ ++ x->spad_dma = xhci_memalign_dma32(x->pagesize, x->pagesize * x->spb, ++ x->pagesize); ++ if (!x->spad_dma) ++ { ++ grub_dma_free(x->spba_dma); ++ goto fail; ++ } ++ ++ spba = grub_dma_get_virt(x->spba_dma); ++ for (grub_uint32_t i = 0; i < x->spb; i++) ++ spba[i] = (grub_addr_t)grub_dma_get_phys(x->spad_dma) + (i * x->pagesize); ++ grub_arch_sync_dma_caches(x->spba_dma, sizeof(*spba) * x->spb); ++ ++ x->devs[0].ptr_low = grub_dma_get_phys(x->spba_dma); ++ x->devs[0].ptr_high = 0; ++ grub_arch_sync_dma_caches(x->devs_dma, sizeof(x->devs[0])); ++ grub_dprintf ("xhci", "XHCI init: Allocated %d scratch buffers of size 0x%x\n", ++ x->spb, x->pagesize); ++ } ++ ++ grub_xhci_reset(x); ++ ++ /* Set the running bit */ ++ reg = grub_xhci_read32 (&x->op->usbcmd); ++ reg |= GRUB_XHCI_CMD_RS; ++ grub_xhci_write32 (&x->op->usbcmd, reg); ++ ++ ++ /* Link to xhci now that initialisation is successful. */ ++ x->next = xhci; ++ xhci = x; ++ ++ return; ++ ++fail: ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: FAILED!\n"); ++ if (x) ++ { ++ if (x->devs_dma) ++ grub_dma_free (x->devs_dma); ++ if (x->eseg_dma) ++ grub_dma_free (x->eseg_dma); ++ if (x->cmds_dma) ++ grub_dma_free (x->cmds_dma); ++ if (x->evts_dma) ++ grub_dma_free (x->evts_dma); ++ if (x->spad_dma) ++ grub_dma_free (x->spad_dma); ++ if (x->spba_dma) ++ grub_dma_free (x->spba_dma); ++ } ++ grub_free (x); ++ ++ return; ++} ++ ++static int ++grub_xhci_iterate (grub_usb_controller_iterate_hook_t hook, void *hook_data) ++{ ++ struct grub_xhci *x; ++ struct grub_usb_controller dev; ++ ++ for (x = xhci; x; x = x->next) ++ { ++ dev.data = x; ++ if (hook (&dev, hook_data)) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++/**************************************************************** ++ * xHCI maintainance functions ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_update_hub_portcount (struct grub_xhci *x, ++ grub_usb_transfer_t transfer, ++ grub_uint32_t slotid) ++{ ++ struct grub_pci_dma_chunk *in_dma; ++ volatile struct grub_xhci_slotctx *hdslot; ++ grub_uint32_t epid = 0; ++ ++ if (!transfer || !transfer->dev || !transfer->dev->nports) ++ return GRUB_USB_ERR_NONE; ++ ++ hdslot = grub_dma_phys2virt(x->devs[slotid].ptr_low, x->devs_dma); ++ if ((hdslot->ctx[3] >> 27) == 3) ++ /* Already configured */ ++ return 0; ++ ++ grub_dprintf("xhci", "%s: updating hub config to %d ports\n", __func__, ++ transfer->dev->nports); ++ ++ xhci_check_status(x); ++ ++ /* Allocate input context and initialize endpoint info. */ ++ in_dma = grub_xhci_alloc_inctx(x, epid, transfer->dev); ++ if (!in_dma) ++ return GRUB_USB_ERR_INTERNAL; ++ volatile struct grub_xhci_inctx *in = grub_dma_get_virt(in_dma); ++ ++ in->add = (1 << epid); ++ ++ struct grub_xhci_epctx *ep = (void*)&in[(epid+1) << x->flag64]; ++ ep->ctx[0] |= 1 << 26; ++ ep->ctx[1] |= transfer->dev->nports << 24; ++ ++ int cc = xhci_cmd_configure_endpoint(x, slotid, in_dma); ++ grub_dma_free(in_dma); ++ ++ if (cc != CC_SUCCESS) ++ { ++ grub_dprintf("xhci", "%s: reconf ctl endpoint: failed (cc %d)\n", ++ __func__, cc); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++static grub_usb_err_t ++grub_xhci_update_max_paket_size (struct grub_xhci *x, ++ grub_usb_transfer_t transfer, ++ grub_uint32_t slotid, ++ grub_uint32_t max_packet) ++{ ++ struct grub_pci_dma_chunk *in_dma; ++ grub_uint32_t epid = 1; ++ ++ if (!transfer || !transfer->dev || !max_packet) ++ return GRUB_USB_ERR_NONE; ++ ++ grub_dprintf("xhci", "%s: updating max packet size to 0x%x\n", __func__, ++ max_packet); ++ ++ xhci_check_status(x); ++ ++ /* Allocate input context and initialize endpoint info. */ ++ in_dma = grub_xhci_alloc_inctx(x, epid, transfer->dev); ++ if (!in_dma) ++ return GRUB_USB_ERR_INTERNAL; ++ volatile struct grub_xhci_inctx *in = grub_dma_get_virt(in_dma); ++ in->add = (1 << epid); ++ ++ struct grub_xhci_epctx *ep = (void*)&in[(epid+1) << x->flag64]; ++ ep->ctx[1] |= max_packet << 16; ++ ++ int cc = xhci_cmd_evaluate_context(x, slotid, in_dma); ++ grub_dma_free(in_dma); ++ ++ if (cc != CC_SUCCESS) ++ { ++ grub_dprintf("xhci", "%s: reconf ctl endpoint: failed (cc %d)\n", ++ __func__, cc); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++/**************************************************************** ++ * xHCI endpoint enablement functions ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_prepare_endpoint (struct grub_xhci *x, ++ struct grub_usb_device *dev, ++ grub_uint8_t endpoint, ++ grub_transfer_type_t dir, ++ grub_transaction_type_t type, ++ grub_uint32_t maxpaket, ++ struct grub_xhci_priv *priv) ++{ ++ grub_uint32_t epid; ++ struct grub_pci_dma_chunk *reqs_dma; ++ struct grub_pci_dma_chunk *in_dma; ++ volatile struct grub_xhci_ring *reqs; ++ volatile struct grub_xhci_slotctx *slotctx; ++ ++ if (!x || !priv) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ xhci_check_status(x); ++ ++ if (endpoint == 0) ++ { ++ epid = 1; ++ } ++ else ++ { ++ epid = (endpoint & 0x0f) * 2; ++ epid += (dir == GRUB_USB_TRANSFER_TYPE_IN) ? 1 : 0; ++ } ++ grub_dprintf("xhci", "%s: epid %d\n", __func__, epid); ++ ++ /* Test if already prepared */ ++ if (priv->slotid > 0 && priv->enpoint_trbs[epid] != NULL) ++ return GRUB_USB_ERR_NONE; ++ ++ /* Allocate DMA buffer as endpoint cmd TRB */ ++ reqs_dma = xhci_memalign_dma32(ALIGN_TRB, sizeof(*reqs), ++ BOUNDARY_RING); ++ if (!reqs_dma) ++ return GRUB_USB_ERR_INTERNAL; ++ reqs = grub_dma_get_virt(reqs_dma); ++ grub_memset((void *)reqs, 0, sizeof(*reqs)); ++ reqs->cs = 1; ++ ++ grub_arch_sync_dma_caches(reqs, sizeof(*reqs)); ++ ++ /* Allocate input context and initialize endpoint info. */ ++ in_dma = grub_xhci_alloc_inctx(x, epid, dev); ++ if (!in_dma) ++ { ++ grub_dma_free(reqs_dma); ++ return GRUB_USB_ERR_INTERNAL; ++ } ++ volatile struct grub_xhci_inctx *in = grub_dma_get_virt(in_dma); ++ in->add = 0x01 | (1 << epid); ++ ++ struct grub_xhci_epctx *ep = (void*)&in[(epid+1) << x->flag64]; ++ switch (type) ++ { ++ case GRUB_USB_TRANSACTION_TYPE_CONTROL: ++ ep->ctx[1] |= 0 << 3; ++ break; ++ case GRUB_USB_TRANSACTION_TYPE_BULK: ++ ep->ctx[1] |= 2 << 3; ++ break; ++ } ++ if (dir == GRUB_USB_TRANSFER_TYPE_IN ++ || type== GRUB_USB_TRANSACTION_TYPE_CONTROL) ++ ep->ctx[1] |= 1 << 5; ++ ep->ctx[1] |= maxpaket << 16; ++ ep->deq_low = grub_dma_get_phys(reqs_dma); ++ ep->deq_low |= 1; /* dcs */ ++ ep->length = maxpaket; ++ ++ grub_dprintf("xhci", "%s: ring %p, epid %d, max %d\n", __func__, ++ reqs, epid, maxpaket); ++ if (epid == 1 || priv->slotid == 0) { ++ /* Enable slot. */ ++ int slotid = xhci_cmd_enable_slot(x); ++ if (slotid < 0) ++ { ++ grub_dprintf("xhci", "%s: enable slot: failed\n", __func__); ++ grub_dma_free(reqs_dma); ++ grub_dma_free(in_dma); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ grub_dprintf("xhci", "%s: get slot %d assigned\n", __func__, slotid); ++ ++ grub_uint32_t size = (sizeof(struct grub_xhci_slotctx) * GRUB_XHCI_MAX_ENDPOINTS) << x->flag64; ++ ++ /* Allocate memory for the device specific slot context */ ++ priv->slotctx_dma = xhci_memalign_dma32(ALIGN_SLOTCTX, size, ++ x->pagesize); ++ if (!priv->slotctx_dma) ++ { ++ grub_dprintf("xhci", "%s: grub_memalign_dma32 failed\n", __func__); ++ grub_dma_free(reqs_dma); ++ grub_dma_free(in_dma); ++ return GRUB_USB_ERR_INTERNAL; ++ } ++ slotctx = grub_dma_get_virt(priv->slotctx_dma); ++ ++ grub_dprintf("xhci", "%s: enable slot: got slotid %d\n", __func__, slotid); ++ grub_memset((void *)slotctx, 0, size); ++ grub_arch_sync_dma_caches(slotctx, size); ++ ++ x->devs[slotid].ptr_low = grub_dma_get_phys(priv->slotctx_dma); ++ x->devs[slotid].ptr_high = 0; ++ grub_arch_sync_dma_caches(&x->devs[slotid], sizeof(x->devs[0])); ++ ++ /* Send set_address command. */ ++ int cc = xhci_cmd_address_device(x, slotid, in_dma); ++ if (cc != CC_SUCCESS) ++ { ++ grub_dprintf("xhci","%s: address device: failed (cc %d)\n", __func__, cc); ++ cc = xhci_cmd_disable_slot(x, slotid); ++ if (cc != CC_SUCCESS) { ++ grub_dprintf("xhci", "%s: disable failed (cc %d)\n", __func__, cc); ++ } else { ++ x->devs[slotid].ptr_low = 0; ++ x->devs[slotid].ptr_high = 0; ++ grub_arch_sync_dma_caches(&x->devs[slotid], sizeof(x->devs[0])); ++ } ++ grub_dma_free(priv->slotctx_dma); ++ grub_dma_free(reqs_dma); ++ grub_dma_free(in_dma); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ priv->enpoint_trbs[epid] = reqs; ++ priv->enpoint_trbs_dma[epid] = reqs_dma; ++ priv->slotid = slotid; ++ priv->max_packet = 0; ++ } ++ if (epid != 1) ++ { ++ /* Send configure command. */ ++ int cc = xhci_cmd_configure_endpoint(x, priv->slotid, in_dma); ++ if (cc != CC_SUCCESS) ++ { ++ grub_dprintf("xhci", "%s: configure endpoint: failed (cc %d)\n", ++ __func__, cc); ++ grub_dma_free(reqs_dma); ++ grub_dma_free(in_dma); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ priv->enpoint_trbs[epid] = reqs; ++ priv->enpoint_trbs_dma[epid] = reqs_dma; ++ } ++ ++ grub_dprintf("xhci", "%s: done\n", __func__); ++ grub_dma_free(in_dma); ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++ ++/**************************************************************** ++ * xHCI transfer helper functions ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_usb_to_grub_err (unsigned char status) ++{ ++ if (status != CC_SUCCESS) ++ grub_dprintf("xhci", "%s: xfer failed (cc %d)\n", __func__, status); ++ else ++ grub_dprintf("xhci", "%s: xfer done (cc %d)\n", __func__, status); ++ ++ if (status == CC_BABBLE_DETECTED) ++ return GRUB_USB_ERR_BABBLE; ++ else if (status == CC_DATA_BUFFER_ERROR) ++ return GRUB_USB_ERR_DATA; ++ else if (status == CC_STALL_ERROR) ++ return GRUB_USB_ERR_STALL; ++ else if (status != CC_SUCCESS) ++ return GRUB_USB_ERR_NAK; ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++static int ++grub_xhci_transfer_is_zlp(grub_usb_transfer_t transfer, int idx) ++{ ++ if (idx >= transfer->transcnt) ++ return 0; ++ ++ grub_usb_transaction_t tr = &transfer->transactions[idx]; ++ ++ return (tr->size == 0) && ++ ((tr->pid == GRUB_USB_TRANSFER_TYPE_OUT) || ++ (tr->pid == GRUB_USB_TRANSFER_TYPE_IN)); ++} ++ ++static int ++grub_xhci_transfer_is_last(grub_usb_transfer_t transfer, int idx) ++{ ++ return (idx + 1) == transfer->transcnt; ++} ++ ++static int ++grub_xhci_transfer_is_data(grub_usb_transfer_t transfer, int idx) ++{ ++ grub_usb_transaction_t tr; ++ ++ if (idx >= transfer->transcnt) ++ return 0; ++ ++ tr = &transfer->transactions[idx]; ++ if (tr->size == 0 || ++ (tr->pid == GRUB_USB_TRANSFER_TYPE_SETUP)) ++ return 0; ++ ++ /* If there's are no DATA pakets before it's a DATA paket */ ++ for (int i = idx - 1; i >= 0; i--) ++ { ++ tr = &transfer->transactions[i]; ++ if (tr->size > 0 && ++ ((tr->pid == GRUB_USB_TRANSFER_TYPE_OUT) || ++ (tr->pid == GRUB_USB_TRANSFER_TYPE_IN))) ++ return 0; ++ } ++ return 1; ++} ++ ++static int ++grub_xhci_transfer_is_in(grub_usb_transfer_t transfer, int idx) ++{ ++ grub_usb_transaction_t tr; ++ ++ if (idx >= transfer->transcnt) ++ return 0; ++ ++ tr = &transfer->transactions[idx]; ++ ++ return tr->pid == GRUB_USB_TRANSFER_TYPE_IN; ++} ++ ++static int ++grub_xhci_transfer_is_normal(grub_usb_transfer_t transfer, int idx) ++{ ++ grub_usb_transaction_t tr; ++ ++ if (idx >= transfer->transcnt) ++ return 0; ++ ++ tr = &transfer->transactions[idx]; ++ if (tr->size == 0 || ++ (tr->pid == GRUB_USB_TRANSFER_TYPE_SETUP)) ++ return 0; ++ ++ /* If there's at least one DATA paket before it's a normal */ ++ for (int i = idx - 1; i >= 0; i--) ++ { ++ tr = &transfer->transactions[i]; ++ if (tr->size > 0 && ++ ((tr->pid == GRUB_USB_TRANSFER_TYPE_OUT) || ++ (tr->pid == GRUB_USB_TRANSFER_TYPE_IN))) ++ return 1; ++ ++ } ++ return 0; ++} ++ ++static int ++grub_xhci_transfer_next_is_normal(grub_usb_transfer_t transfer, int idx) ++{ ++ return grub_xhci_transfer_is_normal(transfer, idx + 1); ++} ++ ++static int ++grub_xhci_transfer_next_is_in(grub_usb_transfer_t transfer, int idx) ++{ ++ return grub_xhci_transfer_is_in(transfer, idx + 1); ++} ++ ++static grub_uint8_t grub_xhci_epid_from_transfer(grub_usb_transfer_t transfer) ++{ ++ grub_uint8_t epid; ++ ++ if (transfer->endpoint == 0) { ++ epid = 1; ++ } else { ++ epid = (transfer->endpoint & 0x0f) * 2; ++ epid += (transfer->dir == GRUB_USB_TRANSFER_TYPE_IN) ? 1 : 0; ++ } ++ return epid; ++} ++ ++/**************************************************************** ++ * xHCI transfer functions ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_setup_transfer (grub_usb_controller_t dev, ++ grub_usb_transfer_t transfer) ++{ ++ struct grub_xhci_transfer_controller_data *cdata; ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ grub_uint8_t epid; ++ grub_usb_err_t err; ++ volatile struct grub_xhci_ring *reqs; ++ int rc; ++ struct grub_xhci_priv *priv; ++ ++ xhci_check_status(x); ++ ++ if (!dev || !transfer || !transfer->dev || !transfer->dev->xhci_priv) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ priv = transfer->dev->xhci_priv; ++ err = grub_xhci_prepare_endpoint(x, transfer->dev, ++ transfer->endpoint, ++ transfer->dir, ++ transfer->type, ++ transfer->max, ++ priv); ++ ++ if (err != GRUB_USB_ERR_NONE) ++ return err; ++ ++ epid = grub_xhci_epid_from_transfer(transfer); ++ ++ /* Update the max packet size once descdev.maxsize0 is valid */ ++ if (epid == 1 && ++ (priv->max_packet == 0) && ++ (transfer->dev->descdev.maxsize0 > 0)) ++ { ++ if (transfer->dev->speed == GRUB_USB_SPEED_SUPER) ++ priv->max_packet = 1UL << transfer->dev->descdev.maxsize0; ++ else ++ priv->max_packet = transfer->dev->descdev.maxsize0; ++ err = grub_xhci_update_max_paket_size(x, transfer, priv->slotid, priv->max_packet); ++ if (err != GRUB_USB_ERR_NONE) ++ { ++ grub_dprintf("xhci", "%s: Updating max paket size failed\n", __func__); ++ return err; ++ } ++ } ++ if (epid == 1 && ++ transfer->dev->descdev.class == 9 && ++ transfer->dev->nports > 0) ++ { ++ err = grub_xhci_update_hub_portcount(x, transfer, priv->slotid); ++ if (err != GRUB_USB_ERR_NONE) ++ { ++ grub_dprintf("xhci", "%s: Updating max paket size failed\n", __func__); ++ return err; ++ } ++ } ++ ++ /* Allocate private data for the transfer */ ++ cdata = grub_zalloc(sizeof(*cdata)); ++ if (!cdata) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ reqs = priv->enpoint_trbs[epid]; ++ ++ transfer->controller_data = cdata; ++ ++ /* Now queue the transfer onto the TRB */ ++ if (transfer->type == GRUB_USB_TRANSACTION_TYPE_CONTROL) ++ { ++ volatile struct grub_usb_packet_setup *setupdata; ++ setupdata = (void *)transfer->transactions[0].data; ++ grub_dprintf("xhci", "%s: CONTROLL TRANS req %d\n", __func__, setupdata->request); ++ grub_dprintf("xhci", "%s: CONTROLL TRANS length %d\n", __func__, setupdata->length); ++ ++ if (setupdata && setupdata->request == GRUB_USB_REQ_SET_ADDRESS) ++ return GRUB_USB_ERR_NONE; ++ ++ if (transfer->transcnt < 2) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ for (int i = 0; i < transfer->transcnt; i++) ++ { ++ grub_uint32_t flags = 0; ++ grub_uint64_t inline_data; ++ grub_usb_transaction_t tr = &transfer->transactions[i]; ++ ++ switch (tr->pid) ++ { ++ case GRUB_USB_TRANSFER_TYPE_SETUP: ++ { ++ grub_dprintf("xhci", "%s: SETUP PKG\n", __func__); ++ grub_dprintf("xhci", "%s: transfer->size %d\n", __func__, transfer->size); ++ grub_dprintf("xhci", "%s: tr->size %d SETUP PKG\n", __func__, tr->size); ++ ++ flags |= (TR_SETUP << 10); ++ flags |= TRB_TR_IDT; ++ ++ if (transfer->size > 0) ++ { ++ if (grub_xhci_transfer_next_is_in(transfer, i)) ++ flags |= (3 << 16); /* TRT IN */ ++ else ++ flags |= (2 << 16); /* TRT OUT */ ++ } ++ break; ++ } ++ case GRUB_USB_TRANSFER_TYPE_OUT: ++ { ++ grub_dprintf("xhci", "%s: OUT PKG\n", __func__); ++ cdata->transfer_size += tr->size; ++ break; ++ } ++ case GRUB_USB_TRANSFER_TYPE_IN: ++ { ++ grub_dprintf("xhci", "%s: IN PKG\n", __func__); ++ cdata->transfer_size += tr->size; ++ flags |= TRB_TR_DIR; ++ break; ++ } ++ } ++ ++ if (grub_xhci_transfer_is_normal(transfer, i)) ++ flags |= (TR_NORMAL << 10); ++ else if (grub_xhci_transfer_is_data(transfer, i)) ++ flags |= (TR_DATA << 10); ++ else if (grub_xhci_transfer_is_zlp(transfer, i)) ++ flags |= (TR_STATUS << 10); ++ ++ if (grub_xhci_transfer_next_is_normal(transfer, i)) ++ flags |= TRB_TR_CH; ++ ++ if (grub_xhci_transfer_is_last(transfer, i)) ++ flags |= TRB_TR_IOC; ++ ++ /* Assume the ring has enough free space for all TRBs */ ++ if (flags & TRB_TR_IDT && tr->size <= (int)sizeof(inline_data)) ++ { ++ grub_memcpy(&inline_data, (void *)tr->data, tr->size); ++ xhci_trb_queue(reqs, inline_data, tr->size, flags); ++ } ++ else ++ { ++ xhci_trb_queue(reqs, tr->data, tr->size, flags); ++ } ++ } ++ } ++ else if (transfer->type == GRUB_USB_TRANSACTION_TYPE_BULK) ++ { ++ for (int i = 0; i < transfer->transcnt; i++) ++ { ++ grub_uint32_t flags = (TR_NORMAL << 10); ++ grub_usb_transaction_t tr = &transfer->transactions[i]; ++ switch (tr->pid) ++ { ++ case GRUB_USB_TRANSFER_TYPE_OUT: ++ { ++ grub_dprintf("xhci", "%s: OUT PKG\n", __func__); ++ cdata->transfer_size += tr->size; ++ break; ++ } ++ case GRUB_USB_TRANSFER_TYPE_IN: ++ { ++ grub_dprintf("xhci", "%s: IN PKG\n", __func__); ++ cdata->transfer_size += tr->size; ++ flags |= TRB_TR_DIR; ++ break; ++ } ++ case GRUB_USB_TRANSFER_TYPE_SETUP: ++ break; ++ } ++ if (grub_xhci_transfer_is_last(transfer, i)) ++ flags |= TRB_TR_IOC; ++ ++ /* The ring might be to small, submit while adding new entries */ ++ rc = xhci_trb_queue_and_flush(x, priv->slotid, epid, ++ reqs, tr->data, tr->size, flags); ++ if (rc < 0) ++ return GRUB_USB_ERR_TIMEOUT; ++ else if (rc > 1) ++ return grub_xhci_usb_to_grub_err(rc); ++ ++ } ++ } ++ xhci_doorbell(x, priv->slotid, epid); ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++static grub_usb_err_t ++grub_xhci_check_transfer (grub_usb_controller_t dev, ++ grub_usb_transfer_t transfer, grub_size_t * actual) ++{ ++ grub_uint32_t status; ++ grub_uint32_t remaining; ++ grub_uint8_t epid; ++ volatile struct grub_xhci_ring *reqs; ++ grub_usb_err_t err; ++ int rc; ++ ++ if (!dev->data || !transfer->controller_data || !transfer->dev || ++ !transfer->dev->xhci_priv) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ ++ struct grub_xhci_priv *priv = transfer->dev->xhci_priv; ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ struct grub_xhci_transfer_controller_data *cdata = ++ transfer->controller_data; ++ ++ xhci_check_status(x); ++ xhci_process_events(x); ++ ++ epid = grub_xhci_epid_from_transfer(transfer); ++ ++ reqs = priv->enpoint_trbs[epid]; ++ ++ /* XXX: invalidate caches */ ++ ++ /* Get current status from event ring buffer */ ++ status = (reqs->evt.status>> 24) & 0xff; ++ remaining = reqs->evt.status & 0xffffff; ++ ++ if (status != CC_STOPPED_LENGTH_INVALID) ++ *actual = cdata->transfer_size - remaining; ++ else ++ *actual = 0; ++ ++ if (xhci_ring_busy(reqs)) ++ return GRUB_USB_ERR_WAIT; ++ ++ grub_free(cdata); ++ ++ grub_dprintf("xhci", "%s: xfer done\n", __func__); ++ ++ err = grub_xhci_usb_to_grub_err(status); ++ if (err != GRUB_USB_ERR_NONE) ++ { ++ if (status == CC_STALL_ERROR) ++ { ++ /* Clear the stall by resetting the endpoint */ ++ rc = xhci_cmd_reset_endpoint(x, priv->slotid, epid, 1); ++ ++ if (rc < 0) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ return GRUB_USB_ERR_STALL; ++ } ++ else if (remaining > 0) ++ { ++ return GRUB_USB_ERR_DATA; ++ } ++ } ++ ++ return err; ++} ++ ++static grub_usb_err_t ++grub_xhci_cancel_transfer (grub_usb_controller_t dev, ++ grub_usb_transfer_t transfer) ++{ ++ grub_uint8_t epid; ++ volatile struct grub_xhci_ring *reqs; ++ struct grub_pci_dma_chunk *enpoint_trbs_dma; ++ grub_addr_t deque_pointer; ++ int rc; ++ ++ if (!dev->data || !transfer->controller_data || !transfer->dev || ++ !transfer->dev->xhci_priv) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ struct grub_xhci_transfer_controller_data *cdata = ++ transfer->controller_data; ++ struct grub_xhci_priv *priv = transfer->dev->xhci_priv; ++ ++ epid = grub_xhci_epid_from_transfer(transfer); ++ ++ enpoint_trbs_dma = priv->enpoint_trbs_dma[epid]; ++ reqs = priv->enpoint_trbs[epid]; ++ ++ /* Abort current command */ ++ rc = xhci_cmd_stop_endpoint(x, priv->slotid, epid, 0); ++ if (rc < 0) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ /* Reset state */ ++ reqs->nidx = 0; ++ reqs->eidx = 0; ++ reqs->cs = 1; ++ ++ grub_arch_sync_dma_caches(reqs, sizeof(*reqs)); ++ ++ /* Reset the dequeue pointer to the begging of the TRB */ ++ deque_pointer = grub_dma_get_phys(enpoint_trbs_dma); ++ rc = xhci_cmd_set_dequeue_pointer(x, priv->slotid, epid, deque_pointer| 1 ); ++ if (rc < 0) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ reqs->evt.ptr_low = 0; ++ reqs->evt.ptr_high = 0; ++ reqs->evt.control = 0; ++ reqs->evt.status = 0; ++ ++ grub_arch_sync_dma_caches(reqs, sizeof(*reqs)); ++ ++ /* Restart ring buffer processing */ ++ xhci_doorbell(x, priv->slotid, epid); ++ ++ grub_free (cdata); ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++/**************************************************************** ++ * xHCI port status functions ++ ****************************************************************/ ++ ++static int ++grub_xhci_hubports (grub_usb_controller_t dev) ++{ ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ grub_uint32_t portinfo; ++ ++ portinfo = x->ports; ++ grub_dprintf ("xhci", "root hub ports=%d\n", portinfo); ++ return portinfo; ++} ++ ++static grub_usb_err_t ++grub_xhci_portstatus (grub_usb_controller_t dev, ++ unsigned int port, unsigned int enable) ++{ ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ grub_uint32_t portsc, pls; ++ grub_uint32_t end; ++ ++ portsc = grub_xhci_port_read(x, port); ++ pls = xhci_get_field(portsc, XHCI_PORTSC_PLS); ++ ++ grub_dprintf("xhci", "grub_xhci_portstatus port #%d: 0x%08x,%s%s pls %d enable %d\n", ++ port, portsc, ++ (portsc & GRUB_XHCI_PORTSC_PP) ? " powered," : "", ++ (portsc & GRUB_XHCI_PORTSC_PED) ? " enabled," : "", ++ pls, enable); ++ xhci_check_status(x); ++ ++ if ((enable && (portsc & GRUB_XHCI_PORTSC_PED)) || ++ (!enable && !(portsc & GRUB_XHCI_PORTSC_PED))) ++ return GRUB_USB_ERR_NONE; ++ ++ if (!enable) ++ { ++ /* Disable port */ ++ grub_xhci_port_write(x, port, ~0, GRUB_XHCI_PORTSC_PED); ++ return GRUB_USB_ERR_NONE; ++ } ++ ++ grub_dprintf ("xhci", "portstatus: XHCI STATUS: %08x\n", ++ grub_xhci_read32(&x->op->usbsts)); ++ grub_dprintf ("xhci", ++ "portstatus: begin, iobase=%p, port=%d, status=0x%08x\n", ++ x->caps, port, portsc); ++ ++ switch (pls) ++ { ++ case PLS_U0: ++ /* A USB3 port - controller automatically performs reset */ ++ break; ++ case PLS_POLLING: ++ /* A USB2 port - perform device reset */ ++ grub_xhci_port_write(x, port, ~GRUB_XHCI_PORTSC_PED, GRUB_XHCI_PORTSC_PR); ++ break; ++ default: ++ return GRUB_USB_ERR_NONE; ++ } ++ ++ /* Wait for device to complete reset and be enabled */ ++ end = grub_get_time_ms () + 100; ++ for (;;) ++ { ++ portsc = grub_xhci_port_read(x, port); ++ if (!(portsc & GRUB_XHCI_PORTSC_CCS)) ++ { ++ /* Device disconnected during reset */ ++ grub_dprintf ("xhci","ERROR: %s device disconnected\n", __func__); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ if (portsc & GRUB_XHCI_PORTSC_PED) ++ /* Reset complete */ ++ break; ++ if (grub_get_time_ms () > end) ++ { ++ grub_dprintf ("xhci","ERROR: %s TIMEOUT\n", __func__); ++ return GRUB_USB_ERR_TIMEOUT; ++ } ++ } ++ xhci_check_status(x); ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++/**************************************************************** ++ * xHCI detect device functions ++ ****************************************************************/ ++ ++static grub_usb_speed_t ++grub_xhci_detect_dev (grub_usb_controller_t dev, int port, int *changed) ++{ ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ grub_uint32_t portsc, speed; ++ ++ *changed = 0; ++ grub_dprintf("xhci", "%s: dev=%p USB%d_%d port %d\n", __func__, dev, ++ x->psids[port-1].major, x->psids[port-1].minor, port); ++ ++ /* On shutdown advertise all ports as disconnected. This will trigger ++ * a gracefull detatch. */ ++ if (x->shutdown) ++ { ++ *changed = 1; ++ return GRUB_USB_SPEED_NONE; ++ } ++ ++ /* Don't advertise new devices, connecting will fail if halted */ ++ if (xhci_is_halted(x)) ++ return GRUB_USB_SPEED_NONE; ++ ++ portsc = grub_xhci_port_read(x, port); ++ speed = xhci_get_field(portsc, XHCI_PORTSC_SPEED); ++ grub_uint8_t pls = xhci_get_field(portsc, XHCI_PORTSC_PLS); ++ ++ grub_dprintf("xhci", "grub_xhci_portstatus port #%d: 0x%08x,%s%s pls %d\n", ++ port, portsc, ++ (portsc & GRUB_XHCI_PORTSC_PP) ? " powered," : "", ++ (portsc & GRUB_XHCI_PORTSC_PED) ? " enabled," : "", ++ pls); ++ ++ /* Connect Status Change bit - it detects change of connection */ ++ if (portsc & GRUB_XHCI_PORTSC_CSC) ++ { ++ *changed = 1; ++ ++ grub_xhci_port_write(x, port, ~GRUB_XHCI_PORTSC_PED, GRUB_XHCI_PORTSC_CSC); ++ } ++ ++ if (!(portsc & GRUB_XHCI_PORTSC_CCS)) ++ return GRUB_USB_SPEED_NONE; ++ ++ for (grub_uint8_t i = 0; i < 16 && x->psids[port-1].psids[i].id > 0; i++) ++ { ++ if (x->psids[port-1].psids[i].id == speed) ++ { ++ grub_dprintf("xhci", "%s: grub_usb_speed = %d\n", __func__, ++ x->psids[port-1].psids[i].grub_usb_speed ); ++ return x->psids[port-1].psids[i].grub_usb_speed; ++ } ++ } ++ ++ return GRUB_USB_SPEED_NONE; ++} ++ ++/**************************************************************** ++ * xHCI attach/detach functions ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_attach_dev (grub_usb_controller_t ctrl, grub_usb_device_t dev) ++{ ++ struct grub_xhci *x = (struct grub_xhci *) ctrl->data; ++ grub_usb_err_t err; ++ grub_uint32_t max; ++ ++ grub_dprintf("xhci", "%s: dev=%p\n", __func__, dev); ++ ++ if (!dev || !x) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ dev->xhci_priv = grub_zalloc (sizeof (struct grub_xhci_priv)); ++ if (!dev->xhci_priv) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ ++ switch (dev->speed) ++ { ++ case GRUB_USB_SPEED_LOW: ++ { ++ max = 8; ++ break; ++ } ++ case GRUB_USB_SPEED_FULL: ++ case GRUB_USB_SPEED_HIGH: ++ { ++ max = 64; ++ break; ++ } ++ case GRUB_USB_SPEED_SUPER: ++ { ++ max = 512; ++ break; ++ } ++ default: ++ case GRUB_USB_SPEED_NONE: ++ { ++ max = 0; ++ } ++ } ++ ++ /* Assign a slot, assign an address and configure endpoint 0 */ ++ err = grub_xhci_prepare_endpoint(x, dev, ++ 0, ++ 0, ++ GRUB_USB_TRANSACTION_TYPE_CONTROL, ++ max, ++ dev->xhci_priv); ++ ++ return err; ++} ++ ++static grub_usb_err_t ++grub_xhci_detach_dev (grub_usb_controller_t ctrl, grub_usb_device_t dev) ++{ ++ struct grub_xhci *x = (struct grub_xhci *) ctrl->data; ++ struct grub_xhci_priv *priv; ++ int cc = CC_SUCCESS; ++ ++ grub_dprintf("xhci", "%s: dev=%p\n", __func__, dev); ++ ++ if (!dev) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ if (dev->xhci_priv) ++ { ++ priv = dev->xhci_priv; ++ /* Stop endpoints and free ring buffer */ ++ for (int i = 0; i < GRUB_XHCI_MAX_ENDPOINTS; i++) ++ { ++ if (priv->enpoint_trbs[i] != NULL) ++ { ++ cc = xhci_cmd_stop_endpoint(x, priv->slotid, i, 1); ++ if (cc != CC_SUCCESS) ++ grub_dprintf("xhci", "Failed to disable EP%d on slot %d\n", i, ++ priv->slotid); ++ ++ grub_dprintf("xhci", "grub_dma_free[%d]\n", i); ++ ++ grub_dma_free(priv->enpoint_trbs_dma[i]); ++ priv->enpoint_trbs[i] = NULL; ++ priv->enpoint_trbs_dma[i] = NULL; ++ } ++ } ++ ++ cc = xhci_cmd_disable_slot(x, priv->slotid); ++ if (cc == CC_SUCCESS) ++ { ++ if (priv->slotctx_dma) ++ grub_dma_free(priv->slotctx_dma); ++ x->devs[priv->slotid].ptr_low = 0; ++ x->devs[priv->slotid].ptr_high = 0; ++ grub_arch_sync_dma_caches(&x->devs[priv->slotid], sizeof(x->devs[0])); ++ } ++ else ++ grub_dprintf("xhci", "Failed to disable slot %d\n", priv->slotid); ++ ++ grub_free(dev->xhci_priv); ++ } ++ ++ dev->xhci_priv = NULL; ++ ++ if (cc != CC_SUCCESS) ++ return GRUB_USB_ERR_BADDEVICE; ++ return GRUB_USB_ERR_NONE; ++} ++ ++/**************************************************************** ++ * xHCI terminate functions ++ ****************************************************************/ ++ ++static void ++grub_xhci_halt(struct grub_xhci *x) ++{ ++ grub_uint32_t reg; ++ ++ /* Halt the command ring */ ++ reg = grub_xhci_read32(&x->op->crcr_low); ++ grub_xhci_write32(&x->op->crcr_low, reg | 4); ++ ++ int rc = xhci_event_wait(x, x->cmds, 100); ++ grub_dprintf("xhci", "%s: xhci_event_wait = %d\n", __func__, rc); ++ if (rc < 0) ++ return; ++ ++ /* Stop the controller */ ++ reg = grub_xhci_read32(&x->op->usbcmd); ++ if (reg & GRUB_XHCI_CMD_RS) ++ { ++ reg &= ~GRUB_XHCI_CMD_RS; ++ grub_xhci_write32(&x->op->usbcmd, reg); ++ } ++ ++ return; ++} ++ ++static grub_err_t ++grub_xhci_fini_hw (int noreturn __attribute__ ((unused))) ++{ ++ struct grub_xhci *x; ++ ++ /* We should disable all XHCI HW to prevent any DMA access etc. */ ++ for (x = xhci; x; x = x->next) ++ { ++ x->shutdown = 1; ++ ++ /* Gracefully detach active devices */ ++ grub_usb_poll_devices(0); ++ ++ /* Check if xHCI is halted and halt it if not */ ++ grub_xhci_halt (x); ++ ++ /* Reset xHCI */ ++ if (grub_xhci_reset (x) != GRUB_USB_ERR_NONE) ++ return GRUB_ERR_BAD_DEVICE; ++ } ++ ++ return GRUB_ERR_NONE; ++} ++ ++static struct grub_usb_controller_dev usb_controller = { ++ .name = "xhci", ++ .iterate = grub_xhci_iterate, ++ .setup_transfer = grub_xhci_setup_transfer, ++ .check_transfer = grub_xhci_check_transfer, ++ .cancel_transfer = grub_xhci_cancel_transfer, ++ .hubports = grub_xhci_hubports, ++ .portstatus = grub_xhci_portstatus, ++ .detect_dev = grub_xhci_detect_dev, ++ .attach_dev = grub_xhci_attach_dev, ++ .detach_dev = grub_xhci_detach_dev, ++ /* estimated max. count of TDs for one bulk transfer */ ++ .max_bulk_tds = GRUB_XHCI_RING_ITEMS - 3 ++}; ++ ++GRUB_MOD_INIT (xhci) ++{ ++ grub_stop_disk_firmware (); ++ ++ grub_boot_time ("Initing XHCI hardware"); ++ grub_xhci_pci_scan (); ++ grub_boot_time ("Registering XHCI driver"); ++ grub_usb_controller_dev_register (&usb_controller); ++ grub_boot_time ("XHCI driver registered"); ++} ++ ++GRUB_MOD_FINI (xhci) ++{ ++ grub_xhci_fini_hw (0); ++ grub_usb_controller_dev_unregister (&usb_controller); ++} +diff --git a/include/grub/usb.h b/include/grub/usb.h +index 609faf7d0..eb71fa1c7 100644 +--- a/include/grub/usb.h ++++ b/include/grub/usb.h +@@ -338,6 +338,10 @@ grub_usb_cancel_transfer (grub_usb_transfer_t trans); + void + grub_ehci_init_device (volatile void *regs); + void ++grub_xhci_init_device (volatile void *regs); ++void + grub_ehci_pci_scan (void); ++void ++grub_xhci_pci_scan (void); + + #endif /* GRUB_USB_H */ +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0007-grub-core-bus-usb-usbhub-Add-xHCI-non-root-hub-suppo.patch b/config/grub/patches/0005-xhci/0007-grub-core-bus-usb-usbhub-Add-xHCI-non-root-hub-suppo.patch new file mode 100644 index 00000000..a37bbd6b --- /dev/null +++ b/config/grub/patches/0005-xhci/0007-grub-core-bus-usb-usbhub-Add-xHCI-non-root-hub-suppo.patch @@ -0,0 +1,127 @@ +From 2a2c64f6ea62337c1263a70f6ca9a9bade66b78b Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph <patrick.rudolph@9elements.com> +Date: Thu, 3 Dec 2020 13:44:55 +0100 +Subject: [PATCH 7/8] grub-core/bus/usb/usbhub: Add xHCI non root hub support + +Tested on Intel PCH C246, the USB3 hub can be configured by grub. + +Issues: +* USB3 devices connected behind that hub are sometimes not detected. + +Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> +--- + grub-core/bus/usb/usbhub.c | 38 +++++++++++++++++++++++++++++++++----- + include/grub/usbdesc.h | 1 + + include/grub/usbtrans.h | 4 ++++ + 3 files changed, 38 insertions(+), 5 deletions(-) + +diff --git a/grub-core/bus/usb/usbhub.c b/grub-core/bus/usb/usbhub.c +index b4b3a1a61..e96505aa9 100644 +--- a/grub-core/bus/usb/usbhub.c ++++ b/grub-core/bus/usb/usbhub.c +@@ -148,19 +148,32 @@ grub_usb_hub_add_dev (grub_usb_controller_t controller, + return dev; + } + +- ++static grub_usb_err_t ++grub_usb_set_hub_depth(grub_usb_device_t dev, grub_uint8_t depth) ++{ ++ return grub_usb_control_msg (dev, (GRUB_USB_REQTYPE_OUT ++ | GRUB_USB_REQTYPE_CLASS ++ | GRUB_USB_REQTYPE_TARGET_DEV), ++ GRUB_USB_HUB_REQ_SET_HUB_DEPTH, depth, ++ 0, 0, NULL); ++} ++ + static grub_usb_err_t + grub_usb_add_hub (grub_usb_device_t dev) + { + struct grub_usb_usb_hubdesc hubdesc; + grub_usb_err_t err; ++ grub_uint16_t req; + int i; + ++ req = (dev->speed == GRUB_USB_SPEED_SUPER) ? GRUB_USB_DESCRIPTOR_SS_HUB : ++ GRUB_USB_DESCRIPTOR_HUB; ++ + err = grub_usb_control_msg (dev, (GRUB_USB_REQTYPE_IN + | GRUB_USB_REQTYPE_CLASS + | GRUB_USB_REQTYPE_TARGET_DEV), +- GRUB_USB_REQ_GET_DESCRIPTOR, +- (GRUB_USB_DESCRIPTOR_HUB << 8) | 0, ++ GRUB_USB_REQ_GET_DESCRIPTOR, ++ (req << 8) | 0, + 0, sizeof (hubdesc), (char *) &hubdesc); + if (err) + return err; +@@ -183,6 +196,19 @@ grub_usb_add_hub (grub_usb_device_t dev) + return GRUB_USB_ERR_INTERNAL; + } + ++ if (dev->speed == GRUB_USB_SPEED_SUPER) ++ { ++ grub_uint8_t depth; ++ grub_uint32_t route; ++ /* Depth maximum value is 5, but root hubs doesn't count */ ++ for (depth = 0, route = dev->route; (route & 0xf) > 0; route >>= 4) ++ depth++; ++ ++ err = grub_usb_set_hub_depth(dev, depth); ++ if (err) ++ return err; ++ } ++ + /* Power on all Hub ports. */ + for (i = 1; i <= hubdesc.portcnt; i++) + { +@@ -637,7 +663,9 @@ poll_nonroot_hub (grub_usb_device_t dev) + int split_hubaddr = 0; + + /* Determine the device speed. */ +- if (status & GRUB_USB_HUB_STATUS_PORT_LOWSPEED) ++ if (dev->speed == GRUB_USB_SPEED_SUPER) ++ speed = GRUB_USB_SPEED_SUPER; ++ else if (status & GRUB_USB_HUB_STATUS_PORT_LOWSPEED) + speed = GRUB_USB_SPEED_LOW; + else + { +@@ -651,7 +679,7 @@ poll_nonroot_hub (grub_usb_device_t dev) + grub_millisleep (10); + + /* Find correct values for SPLIT hubport and hubaddr */ +- if (speed == GRUB_USB_SPEED_HIGH) ++ if (speed == GRUB_USB_SPEED_HIGH || speed == GRUB_USB_SPEED_SUPER) + { + /* HIGH speed device needs not transaction translation */ + split_hubport = 0; +diff --git a/include/grub/usbdesc.h b/include/grub/usbdesc.h +index bb2ab2e27..1697aa465 100644 +--- a/include/grub/usbdesc.h ++++ b/include/grub/usbdesc.h +@@ -30,6 +30,7 @@ typedef enum { + GRUB_USB_DESCRIPTOR_ENDPOINT, + GRUB_USB_DESCRIPTOR_DEBUG = 10, + GRUB_USB_DESCRIPTOR_HUB = 0x29, ++ GRUB_USB_DESCRIPTOR_SS_HUB = 0x2a, + GRUB_USB_DESCRIPTOR_SS_ENDPOINT_COMPANION = 0x30 + } grub_usb_descriptor_t; + +diff --git a/include/grub/usbtrans.h b/include/grub/usbtrans.h +index 039ebed65..d6c3f71dc 100644 +--- a/include/grub/usbtrans.h ++++ b/include/grub/usbtrans.h +@@ -110,6 +110,10 @@ enum + GRUB_USB_REQ_SET_INTERFACE = 0x0B, + GRUB_USB_REQ_SYNC_FRAME = 0x0C + }; ++enum ++ { ++ GRUB_USB_HUB_REQ_SET_HUB_DEPTH = 0x0C, ++ }; + + #define GRUB_USB_FEATURE_ENDP_HALT 0x00 + #define GRUB_USB_FEATURE_DEV_REMOTE_WU 0x01 +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0008-Fix-compilation-on-x86_64.patch b/config/grub/patches/0005-xhci/0008-Fix-compilation-on-x86_64.patch new file mode 100644 index 00000000..af79c3d0 --- /dev/null +++ b/config/grub/patches/0005-xhci/0008-Fix-compilation-on-x86_64.patch @@ -0,0 +1,90 @@ +From 871d768f8c5c960cb0d9761a9028b16882e1a7d3 Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph <patrick.rudolph@9elements.com> +Date: Wed, 24 Feb 2021 08:25:41 +0100 +Subject: [PATCH 8/8] Fix compilation on x86_64 + +Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> +--- + grub-core/bus/usb/xhci.c | 24 ++++++++++++++++-------- + 1 file changed, 16 insertions(+), 8 deletions(-) + +diff --git a/grub-core/bus/usb/xhci.c b/grub-core/bus/usb/xhci.c +index f4591ffb5..3495bb919 100644 +--- a/grub-core/bus/usb/xhci.c ++++ b/grub-core/bus/usb/xhci.c +@@ -184,7 +184,7 @@ enum + * then we can get it from a trb pointer (provided by evt ring). + */ + #define XHCI_RING(_trb) \ +- ((struct grub_xhci_ring*)((grub_uint32_t)(_trb) & ~(GRUB_XHCI_RING_SIZE-1))) ++ ((struct grub_xhci_ring*)((grub_addr_t)(_trb) & ~(GRUB_XHCI_RING_SIZE-1))) + + /* slot context */ + struct grub_xhci_slotctx { +@@ -495,6 +495,14 @@ grub_xhci_read8(volatile void *addr) { + return (*((volatile grub_uint32_t *)addr)); + } + ++static inline void * ++grub_xhci_read_etrb_ptr(volatile struct grub_xhci_trb *trb) { ++ grub_uint64_t tmp; ++ tmp = (grub_uint64_t)grub_xhci_read32(&trb->ptr_low); ++ tmp |= ((grub_uint64_t)grub_xhci_read32(&trb->ptr_high)) << 32; ++ return (void *)(grub_addr_t)tmp; ++} ++ + static inline grub_uint32_t + grub_xhci_port_read (struct grub_xhci *x, grub_uint32_t port) + { +@@ -664,7 +672,7 @@ static void xhci_process_events(struct grub_xhci *x) + case ER_TRANSFER: + case ER_COMMAND_COMPLETE: + { +- struct grub_xhci_trb *rtrb = (void*)grub_xhci_read32(&etrb->ptr_low); ++ struct grub_xhci_trb *rtrb = grub_xhci_read_etrb_ptr(etrb); + struct grub_xhci_ring *ring = XHCI_RING(rtrb); + volatile struct grub_xhci_trb *evt = &ring->evt; + grub_uint32_t eidx = rtrb - ring->ring + 1; +@@ -697,9 +705,9 @@ static void xhci_process_events(struct grub_xhci *x) + } + grub_xhci_write32(&evts->nidx, nidx); + volatile struct grub_xhci_ir *ir = x->ir; +- grub_uint32_t erdp = (grub_uint32_t)(evts->ring + nidx); +- grub_xhci_write32(&ir->erdp_low, erdp); +- grub_xhci_write32(&ir->erdp_high, 0); ++ grub_uint64_t erdp = (grub_addr_t)(void *)(&evts->ring[nidx]); ++ grub_xhci_write32(&ir->erdp_low, erdp & 0xffffffff); ++ grub_xhci_write32(&ir->erdp_high, erdp >> 32); + } + } + +@@ -800,7 +808,7 @@ static void xhci_trb_queue(volatile struct grub_xhci_ring *ring, + grub_uint32_t xferlen, grub_uint32_t flags) + { + grub_dprintf("xhci", "%s: ring %p data %llx len %d flags 0x%x remain 0x%x\n", __func__, +- ring, data_or_addr, xferlen & 0x1ffff, flags, xferlen >> 17); ++ ring, (unsigned long long)data_or_addr, xferlen & 0x1ffff, flags, xferlen >> 17); + + if (xhci_ring_full(ring)) + { +@@ -1907,7 +1915,7 @@ grub_xhci_setup_transfer (grub_usb_controller_t dev, + if (transfer->type == GRUB_USB_TRANSACTION_TYPE_CONTROL) + { + volatile struct grub_usb_packet_setup *setupdata; +- setupdata = (void *)transfer->transactions[0].data; ++ setupdata = (void *)(grub_addr_t)transfer->transactions[0].data; + grub_dprintf("xhci", "%s: CONTROLL TRANS req %d\n", __func__, setupdata->request); + grub_dprintf("xhci", "%s: CONTROLL TRANS length %d\n", __func__, setupdata->length); + +@@ -1974,7 +1982,7 @@ grub_xhci_setup_transfer (grub_usb_controller_t dev, + /* Assume the ring has enough free space for all TRBs */ + if (flags & TRB_TR_IDT && tr->size <= (int)sizeof(inline_data)) + { +- grub_memcpy(&inline_data, (void *)tr->data, tr->size); ++ grub_memcpy(&inline_data, (void *)(grub_addr_t)tr->data, tr->size); + xhci_trb_queue(reqs, inline_data, tr->size, flags); + } + else +-- +2.39.2 + diff --git a/config/vendor/sources b/config/vendor/sources index f60ad862..2653c877 100644 --- a/config/vendor/sources +++ b/config/vendor/sources @@ -21,9 +21,21 @@ DL_url_bkup https://web.archive.org/web/20220202201637/https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe } +# haswell boards, but use broadwell mrc.bin. uses me9 and +# the broadwell mrc, but without broadwell refcode +{dell9020sffbmrc dell9020mtbmrc t440pbmrc w541bmrc}{ + DL_hash f3d79aec805c8b0094a4081be76b3a22d329c479ad18210449b7acc3236ccfc4a2103eaa7c5b79a4872bfd699eede047efd46dfb06dc8f47e3216fc254612998 + DL_url https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe + DL_url_bkup https://web.archive.org/web/20211120031520/https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe + MRC_url https://dl.google.com/dl/edgedl/chromeos/recovery/chromeos_13904.77.0_samus_recovery_stable-channel_mp-v3.bin.zip + MRC_url_bkup https://web.archive.org/web/20220310155922/https://dl.google.com/dl/edgedl/chromeos/recovery/chromeos_13904.77.0_samus_recovery_stable-channel_mp-v3.bin.zip + MRC_hash 3ff1599c52539f0707a07a8664a84ce51cd3fed1569df4bb7aa6722fc8dec0af1754250333b6ca1a9794d970a4de7b29a5cf2499f5b61e4c3eab64d1314aaea9 + MRC_board samus +} + # NOTE: google's manifest for archives containing mrc.bin, used here: # https://web.archive.org/web/20210211071412/https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf -{t440pmrc w541mrc t440plibremrc w541 dell9020mt dell9020sff}{ +{t440pmrc w541mrc t440plibremrc w541 dell9020mt dell9020sff dell9020sff-nri dell9020mt-nri}{ DL_hash f3d79aec805c8b0094a4081be76b3a22d329c479ad18210449b7acc3236ccfc4a2103eaa7c5b79a4872bfd699eede047efd46dfb06dc8f47e3216fc254612998 DL_url https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe DL_url_bkup https://web.archive.org/web/20211120031520/https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe @@ -33,6 +45,7 @@ MRC_board peppy } +# broadwell mrc, and use me10 plus broadwell refcode {hp820g2}{ DL_hash 1ac05a3e4f46426eeb77f89c4aca25ed1ad64479d8fcba6a3ab63a944512bacbc5d148cc7b9c4ff4b8c90a1fb1de4776e46f14aca8021900e0df37246aa0b717 DL_url https://download.lenovo.com/pccbbs/mobiles/n10rg50w.exe @@ -156,7 +169,7 @@ E6400_VGA_romname mod_21.bin } -{e5520 e6420 e6520}{ +{e5420 e5520 e6420 e6520}{ DL_hash 81c9917938c4a2a4f128c976250451931efd0f25b51ff34f058ddacb8eec27272691371864a683ec7abcb924fea32592d061584c7b2571a5d3e84eb870281cc3 DL_url https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe DL_url_bkup https://web.archive.org/web/20220202201637/https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe |