diff options
Diffstat (limited to 'config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch')
| -rw-r--r-- | config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch | 8 | 
1 files changed, 4 insertions, 4 deletions
| diff --git a/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch b/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch index 32647ed0..8227b076 100644 --- a/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch +++ b/config/u-boot/default/patches/0001-clk-rockchip-rk3399-Set-hardcoded-clock-rates-same-a.patch @@ -1,4 +1,4 @@ -From bc5204d0d28bb431186fd106f9a79f69bfad005d Mon Sep 17 00:00:00 2001 +From ee94f55d37fc8c133faa5055184f75f99830cfdc Mon Sep 17 00:00:00 2001  From: Alper Nebi Yasak <alpernebiyasak@gmail.com>  Date: Fri, 8 Oct 2021 17:33:22 +0300  Subject: [PATCH] clk: rockchip: rk3399: Set hardcoded clock rates same as @@ -60,7 +60,7 @@ index d941a129f3e5..54035c0df1f3 100644   #define PWM_CLOCK_HZ    PMU_PCLK_HZ  diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c -index 24cefebd1b2a..6f874bd347e0 100644 +index 6e87db18be07..1b8ffe9e794e 100644  --- a/drivers/clk/rockchip/clk_rk3399.c  +++ b/drivers/clk/rockchip/clk_rk3399.c  @@ -53,10 +53,11 @@ struct pll_div { @@ -72,7 +72,7 @@ index 24cefebd1b2a..6f874bd347e0 100644  +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);  +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 3, 1);  +static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 3, 1); - #if !defined(CONFIG_SPL_BUILD) + #if !defined(CONFIG_XPL_BUILD)  -static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);  +static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 3, 2, 1);   #endif @@ -96,5 +96,5 @@ index 24cefebd1b2a..6f874bd347e0 100644   	/* configure perihp aclk, hclk, pclk */   	aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;  --  -2.45.2 +2.49.0 | 
