diff options
Diffstat (limited to 'config/coreboot')
42 files changed, 275 insertions, 1619 deletions
diff --git a/config/coreboot/haswell/patches/0001-haswell-NRI-Initialise-MPLL.patch b/config/coreboot/default/patches/0043-haswell-NRI-Initialise-MPLL.patch index 0de1a4ec..9b733998 100644 --- a/config/coreboot/haswell/patches/0001-haswell-NRI-Initialise-MPLL.patch +++ b/config/coreboot/default/patches/0043-haswell-NRI-Initialise-MPLL.patch @@ -1,7 +1,7 @@ -From cce5392f272b0acc493f47f9b5ca3cf90ce901e8 Mon Sep 17 00:00:00 2001 +From 8b584165a99c69cc808f86efcdd55acb06a4464c Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Thu, 11 Apr 2024 17:25:07 +0200 -Subject: [PATCH 01/20] haswell NRI: Initialise MPLL +Subject: [PATCH 01/17] haswell NRI: Initialise MPLL Add code to initialise the MPLL (Memory PLL). The procedure is similar to the one for Sandy/Ivy Bridge, but it is not worth factoring out. @@ -290,10 +290,10 @@ index 19ec5859ac..bf745e943f 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 1a0793947e..a54581abc7 100644 +index 8078c9c386..15a1550424 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -23,6 +23,8 @@ enum raminit_status { +@@ -24,6 +24,8 @@ enum raminit_status { RAMINIT_STATUS_SUCCESS = 0, RAMINIT_STATUS_NO_MEMORY_INSTALLED, RAMINIT_STATUS_UNSUPPORTED_MEMORY, @@ -302,7 +302,7 @@ index 1a0793947e..a54581abc7 100644 RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ }; -@@ -82,10 +84,19 @@ struct sysinfo { +@@ -83,10 +85,19 @@ struct sysinfo { uint8_t rankmap[NUM_CHANNELS]; uint8_t rank_mirrored[NUM_CHANNELS]; uint32_t channel_size_mb[NUM_CHANNELS]; diff --git a/config/coreboot/haswell/patches/0002-haswell-NRI-Post-process-selected-timings.patch b/config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch index 0cc95cdd..924385ed 100644 --- a/config/coreboot/haswell/patches/0002-haswell-NRI-Post-process-selected-timings.patch +++ b/config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch @@ -1,7 +1,7 @@ -From 42b21fdce8c8bade53d9d86515f88b0665a4c1b1 Mon Sep 17 00:00:00 2001 +From adde2e8d038b2d07ab7287eedab5888d92a56a60 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 16:29:55 +0200 -Subject: [PATCH 02/20] haswell NRI: Post-process selected timings +Subject: [PATCH 02/17] haswell NRI: Post-process selected timings Once the MPLL has been initialised, convert the timings from the SPD to be in DCLKs, which is what the hardware expects. In addition, calculate @@ -110,10 +110,10 @@ index bf745e943f..2fea658415 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index a54581abc7..01e5ed1bd6 100644 +index 15a1550424..e0ebd3a2a7 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -78,6 +78,9 @@ struct sysinfo { +@@ -79,6 +79,9 @@ struct sysinfo { uint32_t tCWL; uint32_t tCMD; @@ -123,7 +123,7 @@ index a54581abc7..01e5ed1bd6 100644 uint8_t lanes; /* 8 or 9 */ uint8_t chanmap; uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */ -@@ -96,7 +99,12 @@ void raminit_main(enum raminit_boot_mode bootmode); +@@ -97,7 +100,12 @@ void raminit_main(enum raminit_boot_mode bootmode); enum raminit_status collect_spd_info(struct sysinfo *ctrl); enum raminit_status initialise_mpll(struct sysinfo *ctrl); @@ -137,7 +137,7 @@ index a54581abc7..01e5ed1bd6 100644 + #endif diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c -index 2dab8504c4..7d98341a7e 100644 +index eff993800b..4f7fe46494 100644 --- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c +++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c @@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl) diff --git a/config/coreboot/haswell/patches/0003-haswell-NRI-Configure-initial-MC-settings.patch b/config/coreboot/default/patches/0045-haswell-NRI-Configure-initial-MC-settings.patch index f44eb029..b51839d2 100644 --- a/config/coreboot/haswell/patches/0003-haswell-NRI-Configure-initial-MC-settings.patch +++ b/config/coreboot/default/patches/0045-haswell-NRI-Configure-initial-MC-settings.patch @@ -1,7 +1,7 @@ -From 574f4965976b56f98a825dea71e919fefb2c8547 Mon Sep 17 00:00:00 2001 +From 0001039f5ea6be6700a453f511069be2ce1b4e7e Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 17:22:07 +0200 -Subject: [PATCH 03/20] haswell NRI: Configure initial MC settings +Subject: [PATCH 03/17] haswell NRI: Configure initial MC settings Program initial memory controller settings. Many of these values will be adjusted later during training. @@ -885,10 +885,10 @@ index 2fea658415..fcc981ad04 100644 ctrl->bootmode = bootmode; } diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 01e5ed1bd6..aa86b9aa39 100644 +index e0ebd3a2a7..fffa6d5450 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -3,15 +3,40 @@ +@@ -3,16 +3,41 @@ #ifndef HASWELL_RAMINIT_NATIVE_H #define HASWELL_RAMINIT_NATIVE_H @@ -900,7 +900,8 @@ index 01e5ed1bd6..aa86b9aa39 100644 + +#include "reg_structs.h" - #define SPD_LEN 256 + /** TODO (Angel): Remove this after in-review patches are submitted **/ + #define SPD_LEN SPD_SIZE_MAX_DDR3 +/* Each channel has 4 ranks, spread across 2 slots */ +#define NUM_SLOTRANKS 4 @@ -929,7 +930,7 @@ index 01e5ed1bd6..aa86b9aa39 100644 enum raminit_boot_mode { BOOTMODE_COLD, BOOTMODE_WARM, -@@ -57,6 +82,9 @@ struct sysinfo { +@@ -58,6 +83,9 @@ struct sysinfo { * LPDDR-specific functions have stubs which will halt upon execution. */ bool lpddr; @@ -939,7 +940,7 @@ index 01e5ed1bd6..aa86b9aa39 100644 struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS]; union dimm_flags_ddr3_st flags; -@@ -93,16 +121,89 @@ struct sysinfo { +@@ -94,16 +122,89 @@ struct sysinfo { uint32_t mem_clock_mhz; uint32_t mem_clock_fs; /* Memory clock period in femtoseconds */ uint32_t qclkps; /* Quadrature clock period in picoseconds */ diff --git a/config/coreboot/haswell/patches/0004-haswell-NRI-Add-timings-refresh-programming.patch b/config/coreboot/default/patches/0046-haswell-NRI-Add-timings-refresh-programming.patch index 74c21227..2b8b453e 100644 --- a/config/coreboot/haswell/patches/0004-haswell-NRI-Add-timings-refresh-programming.patch +++ b/config/coreboot/default/patches/0046-haswell-NRI-Add-timings-refresh-programming.patch @@ -1,7 +1,7 @@ -From d94843c7c0e25cb6da4040b845556034fdb0e2c3 Mon Sep 17 00:00:00 2001 +From 44032c7df6f4537c43ba80ae2f4a239616bd8d2d Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 20:59:58 +0200 -Subject: [PATCH 04/20] haswell NRI: Add timings/refresh programming +Subject: [PATCH 04/17] haswell NRI: Add timings/refresh programming Program the registers with timing and refresh parameters. @@ -126,10 +126,10 @@ index 8b81c7c341..b8d6c1ef40 100644 + return DIV_ROUND_UP(get_tZQOPER(mem_clock_mhz, lpddr), 4); +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index aa86b9aa39..cd1f2eb2a5 100644 +index fffa6d5450..5915a2bab0 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -155,6 +155,12 @@ struct sysinfo { +@@ -156,6 +156,12 @@ struct sysinfo { uint8_t cke_cmd_pi_code[NUM_CHANNELS][NUM_GROUPS]; uint8_t cmd_north_pi_code[NUM_CHANNELS][NUM_GROUPS]; uint8_t cmd_south_pi_code[NUM_CHANNELS][NUM_GROUPS]; @@ -142,7 +142,7 @@ index aa86b9aa39..cd1f2eb2a5 100644 }; static inline bool is_hsw_ult(void) -@@ -200,6 +206,14 @@ enum raminit_status configure_mc(struct sysinfo *ctrl); +@@ -201,6 +207,14 @@ enum raminit_status configure_mc(struct sysinfo *ctrl); void configure_timings(struct sysinfo *ctrl); void configure_refresh(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0005-haswell-NRI-Program-memory-map.patch b/config/coreboot/default/patches/0047-haswell-NRI-Program-memory-map.patch index e095417c..5628286a 100644 --- a/config/coreboot/haswell/patches/0005-haswell-NRI-Program-memory-map.patch +++ b/config/coreboot/default/patches/0047-haswell-NRI-Program-memory-map.patch @@ -1,7 +1,7 @@ -From b872fb9fc10d1789989072b8533b797152e6cb54 Mon Sep 17 00:00:00 2001 +From 406e474c7f9f83dc10c7c0fa7cd9765ae822ad4e Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 21:24:50 +0200 -Subject: [PATCH 05/20] haswell NRI: Program memory map +Subject: [PATCH 05/17] haswell NRI: Program memory map This is very similar to Sandy/Ivy Bridge, except that there's several registers to program in GDXCBAR. One of these GDXCBAR registers has a @@ -234,10 +234,10 @@ index fcc981ad04..559dfc3a4e 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index cd1f2eb2a5..4763b25e8d 100644 +index 5915a2bab0..8f937c4ccd 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -202,6 +202,7 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl); +@@ -203,6 +203,7 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl); enum raminit_status initialise_mpll(struct sysinfo *ctrl); enum raminit_status convert_timings(struct sysinfo *ctrl); enum raminit_status configure_mc(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0006-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch b/config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch index ea46364f..9f074e17 100644 --- a/config/coreboot/haswell/patches/0006-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch +++ b/config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch @@ -1,7 +1,7 @@ -From 1ea9b05694da7ee61d49d9cd2b7e533a98e42321 Mon Sep 17 00:00:00 2001 +From eb8150a07c472078ad37887de13a166e6cf8bdad Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 21:49:40 +0200 -Subject: [PATCH 06/20] haswell NRI: Add DDR3 JEDEC reset and init +Subject: [PATCH 06/17] haswell NRI: Add DDR3 JEDEC reset and init Implement JEDEC reset and init sequence for DDR3. The MRS commands are issued through the REUT (Robust Electrical Unified Testing) hardware. @@ -443,10 +443,10 @@ index 559dfc3a4e..94b268468c 100644 } diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 4763b25e8d..4bc2a4955f 100644 +index 8f937c4ccd..759d755d6d 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -27,6 +27,30 @@ +@@ -28,6 +28,30 @@ /* Always use 12 legs for emphasis (not trained) */ #define TXEQFULLDRV (3 << 4) @@ -477,7 +477,7 @@ index 4763b25e8d..4bc2a4955f 100644 enum command_training_iteration { CT_ITERATION_CLOCK = 0, CT_ITERATION_CMD_NORTH, -@@ -50,6 +74,7 @@ enum raminit_status { +@@ -51,6 +75,7 @@ enum raminit_status { RAMINIT_STATUS_UNSUPPORTED_MEMORY, RAMINIT_STATUS_MPLL_INIT_FAILURE, RAMINIT_STATUS_POLL_TIMEOUT, @@ -485,7 +485,7 @@ index 4763b25e8d..4bc2a4955f 100644 RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ }; -@@ -72,6 +97,7 @@ struct sysinfo { +@@ -73,6 +98,7 @@ struct sysinfo { uint32_t cpu; /* CPUID value */ bool dq_pins_interleaved; @@ -493,7 +493,7 @@ index 4763b25e8d..4bc2a4955f 100644 /** TODO: ECC support untested **/ bool is_ecc; -@@ -161,6 +187,11 @@ struct sysinfo { +@@ -162,6 +188,11 @@ struct sysinfo { union tc_bank_rank_b_reg tc_bankrank_b[NUM_CHANNELS]; union tc_bank_rank_c_reg tc_bankrank_c[NUM_CHANNELS]; union tc_bank_rank_d_reg tc_bankrank_d[NUM_CHANNELS]; @@ -505,7 +505,7 @@ index 4763b25e8d..4bc2a4955f 100644 }; static inline bool is_hsw_ult(void) -@@ -196,6 +227,53 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl) +@@ -197,6 +228,53 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl) memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train)); } @@ -559,7 +559,7 @@ index 4763b25e8d..4bc2a4955f 100644 void raminit_main(enum raminit_boot_mode bootmode); enum raminit_status collect_spd_info(struct sysinfo *ctrl); -@@ -203,6 +281,7 @@ enum raminit_status initialise_mpll(struct sysinfo *ctrl); +@@ -204,6 +282,7 @@ enum raminit_status initialise_mpll(struct sysinfo *ctrl); enum raminit_status convert_timings(struct sysinfo *ctrl); enum raminit_status configure_mc(struct sysinfo *ctrl); enum raminit_status configure_memory_map(struct sysinfo *ctrl); @@ -567,7 +567,7 @@ index 4763b25e8d..4bc2a4955f 100644 void configure_timings(struct sysinfo *ctrl); void configure_refresh(struct sysinfo *ctrl); -@@ -215,8 +294,28 @@ uint32_t get_tXS_offset(uint32_t mem_clock_mhz); +@@ -216,8 +295,28 @@ uint32_t get_tXS_offset(uint32_t mem_clock_mhz); uint32_t get_tZQOPER(uint32_t mem_clock_mhz, bool lpddr); uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr); diff --git a/config/coreboot/haswell/patches/0007-haswell-NRI-Add-pre-training-steps.patch b/config/coreboot/default/patches/0049-haswell-NRI-Add-pre-training-steps.patch index 8b73df88..c6beea66 100644 --- a/config/coreboot/haswell/patches/0007-haswell-NRI-Add-pre-training-steps.patch +++ b/config/coreboot/default/patches/0049-haswell-NRI-Add-pre-training-steps.patch @@ -1,7 +1,7 @@ -From 936d432822fcd9aa2f018444cdc89e48e6d257d5 Mon Sep 17 00:00:00 2001 +From 19890277e3a0d411b016efbe1b54e511d4f36c0d Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 7 May 2022 23:12:18 +0200 -Subject: [PATCH 07/20] haswell NRI: Add pre-training steps +Subject: [PATCH 07/17] haswell NRI: Add pre-training steps Implement pre-training steps, which consist of enabling ECC I/O and filling the WDB (Write Data Buffer, stores test patterns) through a @@ -91,10 +91,10 @@ index 94b268468c..5e4674957d 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 4bc2a4955f..1971b44b66 100644 +index 759d755d6d..4d9487d79c 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -35,6 +35,13 @@ +@@ -36,6 +36,13 @@ #define RTTNOM_MASK (BIT(9) | BIT(6) | BIT(2)) @@ -108,7 +108,7 @@ index 4bc2a4955f..1971b44b66 100644 /* ZQ calibration types */ enum { ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */ -@@ -316,6 +323,23 @@ void reut_issue_mrs_all( +@@ -317,6 +324,23 @@ void reut_issue_mrs_all( enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type); diff --git a/config/coreboot/haswell/patches/0008-haswell-NRI-Add-REUT-I-O-test-library.patch b/config/coreboot/default/patches/0050-haswell-NRI-Add-REUT-I-O-test-library.patch index 2225f18c..6588c376 100644 --- a/config/coreboot/haswell/patches/0008-haswell-NRI-Add-REUT-I-O-test-library.patch +++ b/config/coreboot/default/patches/0050-haswell-NRI-Add-REUT-I-O-test-library.patch @@ -1,7 +1,7 @@ -From 49a7ef2401922a8492ba577a43235bcfba7ea822 Mon Sep 17 00:00:00 2001 +From 5ea55ac3f02a8a10f05e84ab9fbace424194869f Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 00:11:29 +0200 -Subject: [PATCH 08/20] haswell NRI: Add REUT I/O test library +Subject: [PATCH 08/17] haswell NRI: Add REUT I/O test library Implement a library to run I/O tests using the REUT hardware. @@ -27,10 +27,10 @@ index 8d7d4e4db0..6e1b365602 100644 +romstage-y += testing_io.c romstage-y += timings_refresh.c diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 1971b44b66..7f19fde4cc 100644 +index 4d9487d79c..f029e7f076 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -58,6 +58,88 @@ enum { +@@ -59,6 +59,88 @@ enum { REUT_MODE_NOP = 3, /* Normal operation mode */ }; @@ -119,7 +119,7 @@ index 1971b44b66..7f19fde4cc 100644 enum command_training_iteration { CT_ITERATION_CLOCK = 0, CT_ITERATION_CMD_NORTH, -@@ -199,6 +281,10 @@ struct sysinfo { +@@ -200,6 +282,10 @@ struct sysinfo { uint16_t mr1[NUM_CHANNELS][NUM_SLOTS]; uint16_t mr2[NUM_CHANNELS][NUM_SLOTS]; uint16_t mr3[NUM_CHANNELS][NUM_SLOTS]; @@ -130,7 +130,7 @@ index 1971b44b66..7f19fde4cc 100644 }; static inline bool is_hsw_ult(void) -@@ -340,6 +426,30 @@ void write_wdb_va_pat( +@@ -341,6 +427,30 @@ void write_wdb_va_pat( void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup); void setup_wdb(const struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0009-haswell-NRI-Add-range-tracking-library.patch b/config/coreboot/default/patches/0051-haswell-NRI-Add-range-tracking-library.patch index 9c3fe1c9..3b78012f 100644 --- a/config/coreboot/haswell/patches/0009-haswell-NRI-Add-range-tracking-library.patch +++ b/config/coreboot/default/patches/0051-haswell-NRI-Add-range-tracking-library.patch @@ -1,7 +1,7 @@ -From 7f5c3f8c6c8960d1c374b9c95821c19f230fa34f Mon Sep 17 00:00:00 2001 +From 07970f6dc64e5563c26013d842a929734e2bf8ed Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 00:56:00 +0200 -Subject: [PATCH 09/20] haswell NRI: Add range tracking library +Subject: [PATCH 09/17] haswell NRI: Add range tracking library Implement a small library used to keep track of passing ranges. This will be used by 1D training algorithms when margining some parameter. diff --git a/config/coreboot/haswell/patches/0010-haswell-NRI-Add-library-to-change-margins.patch b/config/coreboot/default/patches/0052-haswell-NRI-Add-library-to-change-margins.patch index 622fac5a..ac096936 100644 --- a/config/coreboot/haswell/patches/0010-haswell-NRI-Add-library-to-change-margins.patch +++ b/config/coreboot/default/patches/0052-haswell-NRI-Add-library-to-change-margins.patch @@ -1,7 +1,7 @@ -From 8ad18cc335f60a78f47ab9e5a7994f6075b6a176 Mon Sep 17 00:00:00 2001 +From 66db8447d6cf724c4b25618c94d5a53d501f214e Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 01:11:03 +0200 -Subject: [PATCH 10/20] haswell NRI: Add library to change margins +Subject: [PATCH 10/17] haswell NRI: Add library to change margins Implement a library to change Rx/Tx margins. It will be expanded later. @@ -187,10 +187,10 @@ index 0000000000..055c666eee + mchbar_write32(reg, ddr_data_control_0.raw); +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 7f19fde4cc..906b3143b9 100644 +index f029e7f076..8707257b27 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -117,6 +117,30 @@ enum test_stop { +@@ -118,6 +118,30 @@ enum test_stop { ALSOE = 3, /* Stop on all lanes error */ }; @@ -221,7 +221,7 @@ index 7f19fde4cc..906b3143b9 100644 struct wdb_pat { uint32_t start_ptr; /* Starting pointer in WDB */ uint32_t stop_ptr; /* Stopping pointer in WDB */ -@@ -450,6 +474,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas +@@ -451,6 +475,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas void run_mpr_io_test(bool clear_errors); uint8_t run_io_test(struct sysinfo *ctrl, uint8_t chanmask, uint8_t dq_pat, bool clear_errors); diff --git a/config/coreboot/haswell/patches/0011-haswell-NRI-Add-RcvEn-training.patch b/config/coreboot/default/patches/0053-haswell-NRI-Add-RcvEn-training.patch index 4815be9a..a9821796 100644 --- a/config/coreboot/haswell/patches/0011-haswell-NRI-Add-RcvEn-training.patch +++ b/config/coreboot/default/patches/0053-haswell-NRI-Add-RcvEn-training.patch @@ -1,7 +1,7 @@ -From 4254a9ff03658d7a6f1a4e32cfe4c65dbfc072f8 Mon Sep 17 00:00:00 2001 +From 0826d1e9ba50daad13c3d5adccba4b180c82296b Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 00:05:41 +0200 -Subject: [PATCH 11/20] haswell NRI: Add RcvEn training +Subject: [PATCH 11/17] haswell NRI: Add RcvEn training Implement the RcvEn (Receive Enable) calibration procedure. @@ -39,10 +39,10 @@ index 5e4674957d..7d444659c3 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 906b3143b9..b4e8c7de5a 100644 +index 8707257b27..eaaaedad1e 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -42,6 +42,9 @@ +@@ -43,6 +43,9 @@ #define NUM_WDB_CL_MUX_SEEDS 3 #define NUM_CADB_MUX_SEEDS 3 @@ -52,7 +52,7 @@ index 906b3143b9..b4e8c7de5a 100644 /* ZQ calibration types */ enum { ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */ -@@ -188,6 +191,7 @@ enum raminit_status { +@@ -189,6 +192,7 @@ enum raminit_status { RAMINIT_STATUS_MPLL_INIT_FAILURE, RAMINIT_STATUS_POLL_TIMEOUT, RAMINIT_STATUS_REUT_ERROR, @@ -60,7 +60,7 @@ index 906b3143b9..b4e8c7de5a 100644 RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ }; -@@ -270,6 +274,10 @@ struct sysinfo { +@@ -271,6 +275,10 @@ struct sysinfo { union ddr_data_vref_adjust_reg dimm_vref; @@ -71,7 +71,7 @@ index 906b3143b9..b4e8c7de5a 100644 uint32_t data_offset_train[NUM_CHANNELS][NUM_LANES]; uint32_t data_offset_comp[NUM_CHANNELS][NUM_LANES]; -@@ -344,6 +352,11 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl) +@@ -345,6 +353,11 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl) memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train)); } @@ -83,7 +83,7 @@ index 906b3143b9..b4e8c7de5a 100644 /* Number of ticks to wait in units of 69.841279 ns (citation needed) */ static inline void tick_delay(const uint32_t delay) { -@@ -399,6 +412,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl); +@@ -400,6 +413,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl); enum raminit_status configure_mc(struct sysinfo *ctrl); enum raminit_status configure_memory_map(struct sysinfo *ctrl); enum raminit_status do_jedec_init(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0012-haswell-NRI-Add-function-to-change-margins.patch b/config/coreboot/default/patches/0054-haswell-NRI-Add-function-to-change-margins.patch index f4f5161e..881b81d6 100644 --- a/config/coreboot/haswell/patches/0012-haswell-NRI-Add-function-to-change-margins.patch +++ b/config/coreboot/default/patches/0054-haswell-NRI-Add-function-to-change-margins.patch @@ -1,7 +1,7 @@ -From c24b26594bfab47a8709ed7fb5cb77307fb73a53 Mon Sep 17 00:00:00 2001 +From 36ec2cfa730ba720ef7ded21cc3e84c47f4e2623 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 11:58:59 +0200 -Subject: [PATCH 12/20] haswell NRI: Add function to change margins +Subject: [PATCH 12/17] haswell NRI: Add function to change margins Implement a function to change margin parameters. Haswell provides a register to apply an offset to margin parameters during training, so @@ -169,10 +169,10 @@ index 055c666eee..299c44a6b0 100644 + change_margin(ctrl, param, value0, true, 0, rank, 0, update_ctrl, regfile); +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index b4e8c7de5a..5242b16f28 100644 +index eaaaedad1e..1c8473056b 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -35,6 +35,18 @@ +@@ -36,6 +36,18 @@ #define RTTNOM_MASK (BIT(9) | BIT(6) | BIT(2)) @@ -191,7 +191,7 @@ index b4e8c7de5a..5242b16f28 100644 #define BASIC_VA_PAT_SPREAD_8 0x01010101 #define WDB_CACHE_LINE_SIZE 8 -@@ -45,6 +57,14 @@ +@@ -46,6 +58,14 @@ /* Specified in PI ticks. 64 PI ticks == 1 qclk */ #define tDQSCK_DRIFT 64 @@ -206,7 +206,7 @@ index b4e8c7de5a..5242b16f28 100644 /* ZQ calibration types */ enum { ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */ -@@ -514,6 +534,25 @@ void download_regfile( +@@ -515,6 +535,25 @@ void download_regfile( bool read_rf_rd, bool read_rf_wr); diff --git a/config/coreboot/haswell/patches/0013-haswell-NRI-Add-read-MPR-training.patch b/config/coreboot/default/patches/0055-haswell-NRI-Add-read-MPR-training.patch index 5f154bcc..8a9a3daa 100644 --- a/config/coreboot/haswell/patches/0013-haswell-NRI-Add-read-MPR-training.patch +++ b/config/coreboot/default/patches/0055-haswell-NRI-Add-read-MPR-training.patch @@ -1,7 +1,7 @@ -From e263f0d2e9d6d016d603342651da261bbcb6af1f Mon Sep 17 00:00:00 2001 +From 87015f060aa208f37481deef460b3545ce2d757f Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 11:35:49 +0200 -Subject: [PATCH 13/20] haswell NRI: Add read MPR training +Subject: [PATCH 13/17] haswell NRI: Add read MPR training Implement read training using DDR3 MPR (Multi-Purpose Register). @@ -39,10 +39,10 @@ index 7d444659c3..264d1468f5 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 5242b16f28..49e9214656 100644 +index 1c8473056b..7a486479ea 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -27,6 +27,8 @@ +@@ -28,6 +28,8 @@ /* Always use 12 legs for emphasis (not trained) */ #define TXEQFULLDRV (3 << 4) @@ -51,7 +51,7 @@ index 5242b16f28..49e9214656 100644 /* DDR3 mode register bits */ #define MR0_DLL_RESET BIT(8) -@@ -212,6 +214,7 @@ enum raminit_status { +@@ -213,6 +215,7 @@ enum raminit_status { RAMINIT_STATUS_POLL_TIMEOUT, RAMINIT_STATUS_REUT_ERROR, RAMINIT_STATUS_RCVEN_FAILURE, @@ -59,7 +59,7 @@ index 5242b16f28..49e9214656 100644 RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ }; -@@ -433,6 +436,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl); +@@ -434,6 +437,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl); enum raminit_status configure_memory_map(struct sysinfo *ctrl); enum raminit_status do_jedec_init(struct sysinfo *ctrl); enum raminit_status train_receive_enable(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0014-haswell-NRI-Add-write-leveling.patch b/config/coreboot/default/patches/0056-haswell-NRI-Add-write-leveling.patch index 5a96cd1f..a3f3e839 100644 --- a/config/coreboot/haswell/patches/0014-haswell-NRI-Add-write-leveling.patch +++ b/config/coreboot/default/patches/0056-haswell-NRI-Add-write-leveling.patch @@ -1,7 +1,7 @@ -From bebe0b74bede64b03aa1e3781310ef539465627b Mon Sep 17 00:00:00 2001 +From ce0ed94f993506e75b711c214b49ba480037e7d3 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 12:56:04 +0200 -Subject: [PATCH 14/20] haswell NRI: Add write leveling +Subject: [PATCH 14/17] haswell NRI: Add write leveling Implement JEDEC write leveling, which is done in two steps. The first step uses the JEDEC procedure to do "fine" write leveling, i.e. align @@ -43,10 +43,10 @@ index 264d1468f5..1ff23be615 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 49e9214656..86d89f2120 100644 +index 7a486479ea..d6b11b9d3c 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -59,6 +59,9 @@ +@@ -60,6 +60,9 @@ /* Specified in PI ticks. 64 PI ticks == 1 qclk */ #define tDQSCK_DRIFT 64 @@ -56,7 +56,7 @@ index 49e9214656..86d89f2120 100644 enum margin_parameter { RcvEna, RdT, -@@ -215,6 +218,7 @@ enum raminit_status { +@@ -216,6 +219,7 @@ enum raminit_status { RAMINIT_STATUS_REUT_ERROR, RAMINIT_STATUS_RCVEN_FAILURE, RAMINIT_STATUS_RMPR_FAILURE, @@ -64,7 +64,7 @@ index 49e9214656..86d89f2120 100644 RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ }; -@@ -380,6 +384,11 @@ static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint +@@ -381,6 +385,11 @@ static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte)); } @@ -76,7 +76,7 @@ index 49e9214656..86d89f2120 100644 /* Number of ticks to wait in units of 69.841279 ns (citation needed) */ static inline void tick_delay(const uint32_t delay) { -@@ -437,6 +446,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl); +@@ -438,6 +447,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl); enum raminit_status do_jedec_init(struct sysinfo *ctrl); enum raminit_status train_receive_enable(struct sysinfo *ctrl); enum raminit_status train_read_mpr(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0015-haswell-NRI-Add-final-raminit-steps.patch b/config/coreboot/default/patches/0057-haswell-NRI-Add-final-raminit-steps.patch index 3626bf6d..db111ee1 100644 --- a/config/coreboot/haswell/patches/0015-haswell-NRI-Add-final-raminit-steps.patch +++ b/config/coreboot/default/patches/0057-haswell-NRI-Add-final-raminit-steps.patch @@ -1,7 +1,7 @@ -From eba8680d618db95028e3f984f25881df0e67abf7 Mon Sep 17 00:00:00 2001 +From e30c9c431ef11d87c6f46071ec43cc34391b8349 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sun, 8 May 2022 14:29:05 +0200 -Subject: [PATCH 15/20] haswell NRI: Add final raminit steps +Subject: [PATCH 15/17] haswell NRI: Add final raminit steps Implement the remaining raminit steps. Although many training steps are missing, this is enough to boot on the Asrock B85M Pro4. @@ -489,10 +489,10 @@ index 2fed93de5b..5f7ceec222 100644 /** TODO: setup_sdram_meminfo **/ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 86d89f2120..9bab57b518 100644 +index d6b11b9d3c..a0a913f926 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -447,6 +447,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl); +@@ -448,6 +448,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl); enum raminit_status train_receive_enable(struct sysinfo *ctrl); enum raminit_status train_read_mpr(struct sysinfo *ctrl); enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0016-Haswell-NRI-Implement-fast-boot-path.patch b/config/coreboot/default/patches/0058-Haswell-NRI-Implement-fast-boot-path.patch index c2fd8b60..40e86a7a 100644 --- a/config/coreboot/haswell/patches/0016-Haswell-NRI-Implement-fast-boot-path.patch +++ b/config/coreboot/default/patches/0058-Haswell-NRI-Implement-fast-boot-path.patch @@ -1,7 +1,7 @@ -From c7d6a901edf648f0f02dd2053337bcf3a319e49b Mon Sep 17 00:00:00 2001 +From 50c9d184cc89cd718c1cb95e1a3cabed24e09e1e Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Sat, 13 Apr 2024 01:16:30 +0200 -Subject: [PATCH 16/20] Haswell NRI: Implement fast boot path +Subject: [PATCH 16/17] Haswell NRI: Implement fast boot path When the memory configuration hasn't changed, there is no need to do full memory training. Instead, boot firmware can use saved training @@ -269,10 +269,10 @@ index 5f7ceec222..3ad8ce29e7 100644 /** TODO: setup_sdram_meminfo **/ } diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 9bab57b518..0750904aec 100644 +index a0a913f926..2ac16eaad3 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -169,6 +169,8 @@ enum regfile_mode { +@@ -170,6 +170,8 @@ enum regfile_mode { REG_FILE_USE_CURRENT, /* Used when changing parameters after the test */ }; @@ -281,7 +281,7 @@ index 9bab57b518..0750904aec 100644 struct wdb_pat { uint32_t start_ptr; /* Starting pointer in WDB */ uint32_t stop_ptr; /* Stopping pointer in WDB */ -@@ -219,6 +221,7 @@ enum raminit_status { +@@ -220,6 +222,7 @@ enum raminit_status { RAMINIT_STATUS_RCVEN_FAILURE, RAMINIT_STATUS_RMPR_FAILURE, RAMINIT_STATUS_JWRL_FAILURE, @@ -289,7 +289,7 @@ index 9bab57b518..0750904aec 100644 RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ }; -@@ -228,6 +231,11 @@ enum generic_stepping { +@@ -229,6 +232,11 @@ enum generic_stepping { STEPPING_C0 = 3, }; @@ -299,9 +299,9 @@ index 9bab57b518..0750904aec 100644 +}; + struct raminit_dimm_info { - spd_raw_data raw_spd; + spd_ddr3_raw_data raw_spd; struct dimm_attr_ddr3_st data; -@@ -447,12 +455,22 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl); +@@ -448,12 +456,22 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl); enum raminit_status train_receive_enable(struct sysinfo *ctrl); enum raminit_status train_read_mpr(struct sysinfo *ctrl); enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0017-haswell-NRI-Do-sense-amplifier-offset-training.patch b/config/coreboot/default/patches/0059-haswell-NRI-Do-sense-amplifier-offset-training.patch index 846fe9a3..c51560c7 100644 --- a/config/coreboot/haswell/patches/0017-haswell-NRI-Do-sense-amplifier-offset-training.patch +++ b/config/coreboot/default/patches/0059-haswell-NRI-Do-sense-amplifier-offset-training.patch @@ -1,7 +1,7 @@ -From be58501141aa97aa544b670e566cd6cf6797c18e Mon Sep 17 00:00:00 2001 +From 8528c7aa2a3cfcf0fe494a515a2e531ff0f1dab8 Mon Sep 17 00:00:00 2001 From: Angel Pons <th3fanbus@gmail.com> Date: Wed, 17 Apr 2024 13:20:32 +0200 -Subject: [PATCH 17/20] haswell NRI: Do sense amplifier offset training +Subject: [PATCH 17/17] haswell NRI: Do sense amplifier offset training Quoting Wikipedia: @@ -61,10 +61,10 @@ index 056dde1adc..ce637e2d03 100644 { train_read_mpr, true, "RDMPRT", }, { train_jedec_write_leveling, true, "JWRL", }, diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 0750904aec..95ccd0a8b3 100644 +index 2ac16eaad3..07eea98831 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -22,6 +22,8 @@ +@@ -23,6 +23,8 @@ #define NUM_LANES 9 #define NUM_LANES_NO_ECC 8 @@ -73,7 +73,7 @@ index 0750904aec..95ccd0a8b3 100644 #define COMP_INT 10 /* Always use 12 legs for emphasis (not trained) */ -@@ -218,6 +220,7 @@ enum raminit_status { +@@ -219,6 +221,7 @@ enum raminit_status { RAMINIT_STATUS_MPLL_INIT_FAILURE, RAMINIT_STATUS_POLL_TIMEOUT, RAMINIT_STATUS_REUT_ERROR, @@ -81,7 +81,7 @@ index 0750904aec..95ccd0a8b3 100644 RAMINIT_STATUS_RCVEN_FAILURE, RAMINIT_STATUS_RMPR_FAILURE, RAMINIT_STATUS_JWRL_FAILURE, -@@ -243,6 +246,12 @@ struct raminit_dimm_info { +@@ -244,6 +247,12 @@ struct raminit_dimm_info { bool valid; }; @@ -94,7 +94,7 @@ index 0750904aec..95ccd0a8b3 100644 struct sysinfo { enum raminit_boot_mode bootmode; enum generic_stepping stepping; -@@ -330,6 +339,8 @@ struct sysinfo { +@@ -331,6 +340,8 @@ struct sysinfo { uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int8_t rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -103,7 +103,7 @@ index 0750904aec..95ccd0a8b3 100644 uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS]; uint8_t ctl_pi_code[NUM_CHANNELS][NUM_SLOTRANKS]; uint8_t cke_pi_code[NUM_CHANNELS][NUM_SLOTRANKS]; -@@ -452,6 +463,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl); +@@ -453,6 +464,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl); enum raminit_status configure_mc(struct sysinfo *ctrl); enum raminit_status configure_memory_map(struct sysinfo *ctrl); enum raminit_status do_jedec_init(struct sysinfo *ctrl); diff --git a/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_corebootfb index 509e784e..c4929a14 100644 --- a/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_corebootfb @@ -37,7 +37,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +54,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +66,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +94,7 @@ CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -127,19 +129,36 @@ CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb" # CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" @@ -159,6 +178,7 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y @@ -170,14 +190,14 @@ CONFIG_PS2M_EISAID="PNP0F13" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_TTYS0_BAUD=115200 CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" # CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -354,6 +374,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -476,8 +497,8 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -# CONFIG_NO_TPM is not set CONFIG_TPM1=y +# CONFIG_TPM2 is not set CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set diff --git a/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_txtmode index 428bed87..14f8e433 100644 --- a/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020mt_nri_12mb/config/libgfxinit_txtmode @@ -37,7 +37,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +54,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +66,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +94,7 @@ CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -125,19 +127,36 @@ CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb" # CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" @@ -157,6 +176,7 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y @@ -168,14 +188,14 @@ CONFIG_PS2M_EISAID="PNP0F13" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_TTYS0_BAUD=115200 CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" # CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -352,6 +372,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -473,8 +494,8 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -# CONFIG_NO_TPM is not set CONFIG_TPM1=y +# CONFIG_TPM2 is not set CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set diff --git a/config/coreboot/dell9020mt_nri_12mb/target.cfg b/config/coreboot/dell9020mt_nri_12mb/target.cfg index 6d2e9a22..e7411d7f 100644 --- a/config/coreboot/dell9020mt_nri_12mb/target.cfg +++ b/config/coreboot/dell9020mt_nri_12mb/target.cfg @@ -1,4 +1,4 @@ -tree="haswell" +tree="default" xarch="i386-elf" payload_seabios="y" payload_grub="y" diff --git a/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_corebootfb index ac1d9f16..4edbb341 100644 --- a/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_corebootfb @@ -37,7 +37,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +54,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +66,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +94,7 @@ CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -127,19 +129,36 @@ CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" @@ -159,6 +178,7 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y @@ -170,14 +190,14 @@ CONFIG_PS2M_EISAID="PNP0F13" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_TTYS0_BAUD=115200 CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" # CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -354,6 +374,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -476,8 +497,8 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -# CONFIG_NO_TPM is not set CONFIG_TPM1=y +# CONFIG_TPM2 is not set CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set diff --git a/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_txtmode index 179af9cc..6a454101 100644 --- a/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020sff_nri_12mb/config/libgfxinit_txtmode @@ -37,7 +37,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +54,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +66,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +94,7 @@ CONFIG_VENDOR_DELL=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -125,19 +127,36 @@ CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set # CONFIG_BOARD_DELL_PRECISION_T1650 is not set +# CONFIG_BOARD_DELL_XPS_8300 is not set CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" @@ -157,6 +176,7 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y @@ -168,14 +188,14 @@ CONFIG_PS2M_EISAID="PNP0F13" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_TTYS0_BAUD=115200 CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" # CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -352,6 +372,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -473,8 +494,8 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -# CONFIG_NO_TPM is not set CONFIG_TPM1=y +# CONFIG_TPM2 is not set CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set diff --git a/config/coreboot/dell9020sff_nri_12mb/target.cfg b/config/coreboot/dell9020sff_nri_12mb/target.cfg index 6d2e9a22..e7411d7f 100644 --- a/config/coreboot/dell9020sff_nri_12mb/target.cfg +++ b/config/coreboot/dell9020sff_nri_12mb/target.cfg @@ -1,4 +1,4 @@ -tree="haswell" +tree="default" xarch="i386-elf" payload_seabios="y" payload_grub="y" diff --git a/config/coreboot/haswell/patches/0018-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/haswell/patches/0018-Remove-warning-for-coreboot-images-built-without-a-p.patch deleted file mode 100644 index 34309242..00000000 --- a/config/coreboot/haswell/patches/0018-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ /dev/null @@ -1,39 +0,0 @@ -From c25dcd8ac80598939edffd011df0fd9ba3d8a1a8 Mon Sep 17 00:00:00 2001 -From: Nicholas Chin <nic.c3.14@gmail.com> -Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 18/20] Remove warning for coreboot images built without a - payload - -I added this in upstream to prevent people from accidentally flashing -roms without a payload resulting in a no boot situation, but in -libreboot lbmk handles the payload and thus this warning always comes -up. This has caused confusion and concern so just patch it out. ---- - payloads/Makefile.mk | 13 +------------ - 1 file changed, 1 insertion(+), 12 deletions(-) - -diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk -index a2336aa876..4f1692a873 100644 ---- a/payloads/Makefile.mk -+++ b/payloads/Makefile.mk -@@ -49,16 +49,5 @@ distclean-payloads: - print-repo-info-payloads: - -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) - --ifeq ($(CONFIG_PAYLOAD_NONE),y) --show_notices:: warn_no_payload --endif -- --warn_no_payload: -- printf "\n\t** WARNING **\n" -- printf "coreboot has been built without a payload. Writing\n" -- printf "a coreboot image without a payload to your board's\n" -- printf "flash chip will result in a non-booting system. You\n" -- printf "can use cbfstool to add a payload to the image.\n\n" -- - .PHONY: force-payload coreinfo nvramcui --.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload -+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch deleted file mode 100644 index e197b3f3..00000000 --- a/config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 081890bab8d454247b6f7e9cb209f46159c45c8b Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 5 Nov 2023 23:19:42 +0000 -Subject: [PATCH 19/20] use mirrorservice.org for gcc downloads - -the gnu.org 302 redirect often fails - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/crossgcc/buildgcc | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 0a0462e2f6..6ae201239d 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -69,11 +69,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" - # to the jenkins build as well, or the builder won't download it. - - # GCC toolchain archive locations --GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" --MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" --MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" --GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" --BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" -+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp" -+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" -+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" -+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" -+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" - IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" - # CLANG toolchain archive locations - LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch deleted file mode 100644 index 60490608..00000000 --- a/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ /dev/null @@ -1,204 +0,0 @@ -From 1a4f454e05b613cb080cdd063dd3efb1fdbb748b Mon Sep 17 00:00:00 2001 -From: Leah Rowe <leah@libreboot.org> -Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 20/20] util/ifdtool: add --nuke flag (all 0xFF on region) - -When this option is used, the region's contents are overwritten -with all ones (0xFF). - -Example: - -./ifdtool --nuke gbe coreboot.rom -./ifdtool --nuke bios coreboot.com -./ifdtool --nuke me coreboot.com - -Rebased since the last revision update in lbmk. - -Signed-off-by: Leah Rowe <leah@libreboot.org> ---- - util/ifdtool/ifdtool.c | 113 ++++++++++++++++++++++++++++++----------- - 1 file changed, 82 insertions(+), 31 deletions(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 516570e0a3..1638e1710e 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -2143,6 +2143,7 @@ static void print_usage(const char *name) - " tgl - Tiger Lake\n" - " wbg - Wellsburg\n" - " -S | --setpchstrap Write a PCH strap\n" -+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n" - " -V | --newvalue The new value to write into PCH strap specified by -S\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" -@@ -2151,6 +2152,60 @@ static void print_usage(const char *name) - "\n"); - } - -+static int -+get_region_type_string(const char *region_type_string) -+{ -+ if (!strcasecmp("Descriptor", region_type_string)) -+ return 0; -+ else if (!strcasecmp("BIOS", region_type_string)) -+ return 1; -+ else if (!strcasecmp("ME", region_type_string)) -+ return 2; -+ else if (!strcasecmp("GbE", region_type_string)) -+ return 3; -+ else if (!strcasecmp("Platform Data", region_type_string)) -+ return 4; -+ else if (!strcasecmp("Device Exp1", region_type_string)) -+ return 5; -+ else if (!strcasecmp("Secondary BIOS", region_type_string)) -+ return 6; -+ else if (!strcasecmp("Reserved", region_type_string)) -+ return 7; -+ else if (!strcasecmp("EC", region_type_string)) -+ return 8; -+ else if (!strcasecmp("Device Exp2", region_type_string)) -+ return 9; -+ else if (!strcasecmp("IE", region_type_string)) -+ return 10; -+ else if (!strcasecmp("10GbE_0", region_type_string)) -+ return 11; -+ else if (!strcasecmp("10GbE_1", region_type_string)) -+ return 12; -+ else if (!strcasecmp("PTT", region_type_string)) -+ return 15; -+ return -1; -+} -+ -+static void -+nuke(const char *filename, char *image, int size, int region_type) -+{ -+ int i; -+ struct region region; -+ const struct frba *frba = find_frba(image, size); -+ if (!frba) -+ exit(EXIT_FAILURE); -+ -+ region = get_region(frba, region_type); -+ if (region.size > 0) { -+ for (i = region.base; i <= region.limit; i++) { -+ if ((i + 1) > (size)) -+ break; -+ image[i] = 0xFF; -+ } -+ write_image(filename, image, size); -+ } -+} -+ - int main(int argc, char *argv[]) - { - int opt, option_index = 0; -@@ -2158,6 +2213,7 @@ int main(int argc, char *argv[]) - int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; - int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; - int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; -+ int mode_nuke = 0; - int mode_gpr0_disable = 0, mode_gpr0_enable = 0; - char *region_type_string = NULL, *region_fname = NULL; - const char *layout_fname = NULL; -@@ -2192,6 +2248,7 @@ int main(int argc, char *argv[]) - {"validate", 0, NULL, 't'}, - {"setpchstrap", 1, NULL, 'S'}, - {"newvalue", 1, NULL, 'V'}, -+ {"nuke", 1, NULL, 'N'}, - {0, 0, 0, 0} - }; - -@@ -2241,35 +2298,8 @@ int main(int argc, char *argv[]) - region_fname++; - // Descriptor, BIOS, ME, GbE, Platform - // valid type? -- if (!strcasecmp("Descriptor", region_type_string)) -- region_type = 0; -- else if (!strcasecmp("BIOS", region_type_string)) -- region_type = 1; -- else if (!strcasecmp("ME", region_type_string)) -- region_type = 2; -- else if (!strcasecmp("GbE", region_type_string)) -- region_type = 3; -- else if (!strcasecmp("Platform Data", region_type_string)) -- region_type = 4; -- else if (!strcasecmp("Device Exp1", region_type_string)) -- region_type = 5; -- else if (!strcasecmp("Secondary BIOS", region_type_string)) -- region_type = 6; -- else if (!strcasecmp("Reserved", region_type_string)) -- region_type = 7; -- else if (!strcasecmp("EC", region_type_string)) -- region_type = 8; -- else if (!strcasecmp("Device Exp2", region_type_string)) -- region_type = 9; -- else if (!strcasecmp("IE", region_type_string)) -- region_type = 10; -- else if (!strcasecmp("10GbE_0", region_type_string)) -- region_type = 11; -- else if (!strcasecmp("10GbE_1", region_type_string)) -- region_type = 12; -- else if (!strcasecmp("PTT", region_type_string)) -- region_type = 15; -- if (region_type == -1) { -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { - fprintf(stderr, "No such region type: '%s'\n\n", - region_type_string); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); -@@ -2441,6 +2471,22 @@ int main(int argc, char *argv[]) - case 't': - mode_validate = 1; - break; -+ case 'N': -+ region_type_string = strdup(optarg); -+ if (!region_type_string) { -+ fprintf(stderr, "No region specified\n"); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { -+ fprintf(stderr, "No such region type: '%s'\n\n", -+ region_type_string); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ mode_nuke = 1; -+ break; - case 'v': - print_version(); - exit(EXIT_SUCCESS); -@@ -2457,7 +2503,7 @@ int main(int argc, char *argv[]) - if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | - mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + -- (mode_gpr0_disable | mode_gpr0_enable)) > 1) { -+ (mode_gpr0_disable | mode_gpr0_enable) + mode_nuke) > 1) { - fprintf(stderr, "You may not specify more than one mode.\n\n"); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); - exit(EXIT_FAILURE); -@@ -2466,7 +2512,8 @@ int main(int argc, char *argv[]) - if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + - mode_locked + mode_unlocked + mode_density + mode_altmedisable + -- mode_validate + (mode_gpr0_disable | mode_gpr0_enable)) == 0) { -+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + -+ mode_nuke) == 0) { - fprintf(stderr, "You need to specify a mode.\n\n"); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); - exit(EXIT_FAILURE); -@@ -2576,6 +2623,10 @@ int main(int argc, char *argv[]) - write_image(new_filename, image, size); - } - -+ if (mode_nuke) { -+ nuke(new_filename, image, size, region_type); -+ } -+ - if (mode_altmedisable) { - struct fpsba *fpsba = find_fpsba(image, size); - struct fmsba *fmsba = find_fmsba(image, size); --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch deleted file mode 100644 index 81b8e839..00000000 --- a/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch +++ /dev/null @@ -1,292 +0,0 @@ -From d97b865a2210e70583e8bf5ee3a73d3c131b29c1 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Sat, 2 Mar 2024 22:51:09 +0000 -Subject: [PATCH 1/4] nb/intel/haswell: make IOMMU a runtime option - -When I tested graphics cards on a coreboot port for Dell -OptiPlex 9020 SFF, I could not use a graphics card unless -I set iommu=off on the Linux cmdline. - -Coreboot's current behaviour is to check whether the CPU -has vt-d support and, if it does, initialise the IOMMU. - -This patch maintains the current behaviour by default, but -allows the user to turn *off* the IOMMU, even if vt-d is -supported by the host CPU. - -If iommu=Disable is specified, the check will not be -performed, and the IOMMU will be left disabled. This option -has been added to all current Haswell boards, though it is -recommended to leave the IOMMU turned on in most setups. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/mainboard/asrock/b85m_pro4/cmos.default | 1 + - src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++ - src/mainboard/asrock/h81m-hds/cmos.default | 1 + - src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++ - src/mainboard/dell/optiplex_9020/cmos.default | 1 + - src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++ - src/mainboard/google/beltino/cmos.layout | 5 +++++ - src/mainboard/google/slippy/cmos.layout | 5 +++++ - src/mainboard/intel/baskingridge/cmos.layout | 4 ++++ - src/mainboard/lenovo/haswell/cmos.default | 1 + - src/mainboard/lenovo/haswell/cmos.layout | 3 +++ - src/mainboard/supermicro/x10slm-f/cmos.default | 1 + - src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++ - src/northbridge/intel/haswell/early_init.c | 5 +++++ - 14 files changed, 48 insertions(+) - -diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default -index 01bf20ad16..dfc8b80fb0 100644 ---- a/src/mainboard/asrock/b85m_pro4/cmos.default -+++ b/src/mainboard/asrock/b85m_pro4/cmos.default -@@ -4,3 +4,4 @@ boot_option=Fallback - debug_level=Debug - nmi=Enable - power_on_after_fail=Disable -+iommu=Enable -diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout -index efdc333fc2..c9883ea71d 100644 ---- a/src/mainboard/asrock/b85m_pro4/cmos.layout -+++ b/src/mainboard/asrock/b85m_pro4/cmos.layout -@@ -11,6 +11,7 @@ - 395 4 e 4 debug_level - 408 1 e 1 nmi - 409 2 e 5 power_on_after_fail -+ 412 1 e 6 iommu - 984 16 h 0 check_sum - # ----------------------------------------------------------------- - -@@ -38,6 +39,8 @@ - 5 0 Disable - 5 1 Enable - 5 2 Keep -+ 6 0 Disable -+ 6 1 Enable - # ----------------------------------------------------------------- - - # ----------------------------------------------------------------- -diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default -index 01bf20ad16..dfc8b80fb0 100644 ---- a/src/mainboard/asrock/h81m-hds/cmos.default -+++ b/src/mainboard/asrock/h81m-hds/cmos.default -@@ -4,3 +4,4 @@ boot_option=Fallback - debug_level=Debug - nmi=Enable - power_on_after_fail=Disable -+iommu=Enable -diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout -index c9ba76c78f..95ee3d36fb 100644 ---- a/src/mainboard/asrock/h81m-hds/cmos.layout -+++ b/src/mainboard/asrock/h81m-hds/cmos.layout -@@ -21,6 +21,9 @@ entries - 408 1 e 1 nmi - 409 2 e 5 power_on_after_fail - -+# enable or disable iommu -+412 1 e 6 iommu -+ - # coreboot config options: check sums - 984 16 h 0 check_sum - -@@ -52,6 +55,9 @@ enumerations - 5 1 Enable - 5 2 Keep - -+6 0 Disable -+6 1 Enable -+ - # ----------------------------------------------------------------- - checksums - -diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -index cd4046f1ab..c974022472 100644 ---- a/src/mainboard/dell/optiplex_9020/cmos.default -+++ b/src/mainboard/dell/optiplex_9020/cmos.default -@@ -3,3 +3,4 @@ boot_option=Fallback - debug_level=Debug - nmi=Disable - power_on_after_fail=Disable -+iommu=Enable -diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout -index c9ba76c78f..72ff9c4bee 100644 ---- a/src/mainboard/dell/optiplex_9020/cmos.layout -+++ b/src/mainboard/dell/optiplex_9020/cmos.layout -@@ -21,6 +21,9 @@ entries - 408 1 e 1 nmi - 409 2 e 5 power_on_after_fail - -+# turn iommu on or off -+412 1 e 6 iommu -+ - # coreboot config options: check sums - 984 16 h 0 check_sum - -@@ -52,6 +55,9 @@ enumerations - 5 1 Enable - 5 2 Keep - -+6 0 Disable -+6 1 Enable -+ - # ----------------------------------------------------------------- - checksums - -diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout -index 78d44c1415..c143979ae1 100644 ---- a/src/mainboard/google/beltino/cmos.layout -+++ b/src/mainboard/google/beltino/cmos.layout -@@ -19,6 +19,9 @@ entries - 408 1 e 1 nmi - 409 2 e 7 power_on_after_fail - -+# enable or disable iommu -+412 1 e 8 iommu -+ - # coreboot config options: bootloader - #Used by ChromeOS: - 416 128 r 0 vbnv -@@ -47,6 +50,8 @@ enumerations - 7 0 Disable - 7 1 Enable - 7 2 Keep -+8 0 Disable -+8 1 Enable - # ----------------------------------------------------------------- - checksums - -diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout -index 78d44c1415..c143979ae1 100644 ---- a/src/mainboard/google/slippy/cmos.layout -+++ b/src/mainboard/google/slippy/cmos.layout -@@ -19,6 +19,9 @@ entries - 408 1 e 1 nmi - 409 2 e 7 power_on_after_fail - -+# enable or disable iommu -+412 1 e 8 iommu -+ - # coreboot config options: bootloader - #Used by ChromeOS: - 416 128 r 0 vbnv -@@ -47,6 +50,8 @@ enumerations - 7 0 Disable - 7 1 Enable - 7 2 Keep -+8 0 Disable -+8 1 Enable - # ----------------------------------------------------------------- - checksums - -diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout -index 78d44c1415..f2c602f541 100644 ---- a/src/mainboard/intel/baskingridge/cmos.layout -+++ b/src/mainboard/intel/baskingridge/cmos.layout -@@ -19,6 +19,8 @@ entries - 408 1 e 1 nmi - 409 2 e 7 power_on_after_fail - -+412 1 e 8 iommu -+ - # coreboot config options: bootloader - #Used by ChromeOS: - 416 128 r 0 vbnv -@@ -47,6 +49,8 @@ enumerations - 7 0 Disable - 7 1 Enable - 7 2 Keep -+8 0 Disable -+8 1 Enable - # ----------------------------------------------------------------- - checksums - -diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default -index 08db97c5a9..cc6b363cd9 100644 ---- a/src/mainboard/lenovo/haswell/cmos.default -+++ b/src/mainboard/lenovo/haswell/cmos.default -@@ -14,3 +14,4 @@ trackpoint=Enable - backlight=Keyboard - enable_dual_graphics=Disable - usb_always_on=Disable -+iommu=Enable -diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout -index 27915d3ab7..59df76b64c 100644 ---- a/src/mainboard/lenovo/haswell/cmos.layout -+++ b/src/mainboard/lenovo/haswell/cmos.layout -@@ -23,6 +23,7 @@ entries - - # coreboot config options: EC - 411 1 e 8 first_battery -+413 1 e 14 iommu - 415 1 e 1 wlan - 416 1 e 1 trackpoint - 417 1 e 1 fn_ctrl_swap -@@ -72,6 +73,8 @@ enumerations - 13 0 Disable - 13 1 AC and battery - 13 2 AC only -+14 0 Disable -+14 1 Enable - - # ----------------------------------------------------------------- - checksums -diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default -index 7ce38fb5d7..6049e7938a 100644 ---- a/src/mainboard/supermicro/x10slm-f/cmos.default -+++ b/src/mainboard/supermicro/x10slm-f/cmos.default -@@ -5,3 +5,4 @@ debug_level=Debug - nmi=Enable - power_on_after_fail=Keep - hide_ast2400=Disable -+iommu=Enable -diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout -index 38ba87aa45..24d39e97ee 100644 ---- a/src/mainboard/supermicro/x10slm-f/cmos.layout -+++ b/src/mainboard/supermicro/x10slm-f/cmos.layout -@@ -21,6 +21,9 @@ entries - 408 1 e 1 nmi - 409 2 e 5 power_on_after_fail - -+# enable or disable iommu -+412 1 e 6 iommu -+ - # coreboot config options: mainboard - 416 1 e 1 hide_ast2400 - -@@ -55,6 +58,9 @@ enumerations - 5 1 Enable - 5 2 Keep - -+6 0 Disable -+6 1 Enable -+ - # ----------------------------------------------------------------- - checksums - -diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c -index e47deb5da6..1a7e0b1076 100644 ---- a/src/northbridge/intel/haswell/early_init.c -+++ b/src/northbridge/intel/haswell/early_init.c -@@ -5,6 +5,7 @@ - #include <device/mmio.h> - #include <device/pci_def.h> - #include <device/pci_ops.h> -+#include <option.h> - - #include "haswell.h" - -@@ -157,6 +158,10 @@ static void haswell_setup_misc(void) - static void haswell_setup_iommu(void) - { - const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); -+ u8 enable_iommu = get_uint_option("iommu", 1); -+ -+ if (!enable_iommu) -+ return; - - if (capid0_a & VTD_DISABLE) - return; --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch deleted file mode 100644 index fbb40293..00000000 --- a/config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 153ca1a43c2c978fa2b2b82d988b0f838953cfb9 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Sat, 2 Mar 2024 23:00:09 +0000 -Subject: [PATCH 2/4] dell/optiplex_9020: Disable IOMMU by default - -Needed to make graphics cards work. Turning it on is -recommended if only using iGPU, otherwise leave it off -by default. The IOMMU is extremely buggy when a graphics -card is used. Leaving it off by default will ensure that -the default ROM images in Libreboot will work on any setup. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/mainboard/dell/optiplex_9020/cmos.default | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -index c974022472..a0acd7b6bb 100644 ---- a/src/mainboard/dell/optiplex_9020/cmos.default -+++ b/src/mainboard/dell/optiplex_9020/cmos.default -@@ -3,4 +3,4 @@ boot_option=Fallback - debug_level=Debug - nmi=Disable - power_on_after_fail=Disable --iommu=Enable -+iommu=Disable --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch b/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch deleted file mode 100644 index e2db6a17..00000000 --- a/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch +++ /dev/null @@ -1,602 +0,0 @@ -From 05cc767d1398f91533e87db5ceaa0aabb7918425 Mon Sep 17 00:00:00 2001 -From: Mate Kukri <kukri.mate@gmail.com> -Date: Thu, 18 Apr 2024 20:28:45 +0100 -Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization - -There are 4 different chassis types specified by vendor firmware, each -with a slightly different HWM configuration. - -The chassis type to use is determined at runtime by reading a set of -4 PCH GPIOs: 70, 38, 17, and 1. - -Additionally vendor firmware also provides an option to run the fans at -full speed. This is substituted with a coreboot nvram option in this -implementation. - -This was tested to make fan control work on my OptiPlex 7020 SFF. - -NOTE: This is superficially similar to the OptiPlex 9010's SCH5545 -however the OptiPlex 9020's SCH5555 does not use externally -programmed EC firmware. - -Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 -Signed-off-by: Mate Kukri <kukri.mate@gmail.com> ---- - src/mainboard/dell/optiplex_9020/Makefile.mk | 3 +- - src/mainboard/dell/optiplex_9020/bootblock.c | 25 +- - src/mainboard/dell/optiplex_9020/cmos.default | 1 + - src/mainboard/dell/optiplex_9020/cmos.layout | 5 +- - src/mainboard/dell/optiplex_9020/mainboard.c | 387 ++++++++++++++++++ - src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++ - src/mainboard/dell/optiplex_9020/sch5555_ec.h | 10 + - 7 files changed, 463 insertions(+), 22 deletions(-) - create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c - create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h - -diff --git a/src/mainboard/dell/optiplex_9020/Makefile.mk b/src/mainboard/dell/optiplex_9020/Makefile.mk -index 6ca2f2afaa..08e2e53577 100644 ---- a/src/mainboard/dell/optiplex_9020/Makefile.mk -+++ b/src/mainboard/dell/optiplex_9020/Makefile.mk -@@ -2,4 +2,5 @@ - - romstage-y += gpio.c - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads --bootblock-y += bootblock.c -+ramstage-y += sch5555_ec.c -+bootblock-y += bootblock.c sch5555_ec.c -diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c -index 2837cf9cf1..e5e759273e 100644 ---- a/src/mainboard/dell/optiplex_9020/bootblock.c -+++ b/src/mainboard/dell/optiplex_9020/bootblock.c -@@ -4,29 +4,14 @@ - #include <device/pnp_ops.h> - #include <superio/smsc/sch555x/sch555x.h> - #include <southbridge/intel/lynxpoint/pch.h> -- --static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) --{ -- // Clear EC-to-Host mailbox -- uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -- outb(tmp, SCH555x_EMI_IOBASE + 1); -- -- // Send address and value to the EC -- sch555x_emi_write16(0, (addr1 * 2) | 0x101); -- sch555x_emi_write32(4, val | (addr2 << 16)); -- -- // Wait for acknowledgement message from EC -- outb(1, SCH555x_EMI_IOBASE); -- size_t timeout = 0; -- do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0); --} -+#include "sch5555_ec.h" - - struct ec_init_entry { - uint16_t addr; - uint8_t val; - }; - --static void ec_init(void) -+static void bootblock_ec_init(void) - { - /* - * Tables from CORE_PEI -@@ -108,9 +93,9 @@ void mainboard_config_superio(void) - outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); - outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); - -- // Magic EC init -- ec_init(); -+ // Perform bootblock EC initialization -+ bootblock_ec_init(); - -- // Magic EC init is needed for UART1 initialization to work -+ // Bootblock EC initialization is required for UART1 to work - sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - } -diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default -index a0acd7b6bb..9e02534c16 100644 ---- a/src/mainboard/dell/optiplex_9020/cmos.default -+++ b/src/mainboard/dell/optiplex_9020/cmos.default -@@ -4,3 +4,4 @@ debug_level=Debug - nmi=Disable - power_on_after_fail=Disable - iommu=Disable -+fan_full_speed=Disable -diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout -index 72ff9c4bee..4a1496a878 100644 ---- a/src/mainboard/dell/optiplex_9020/cmos.layout -+++ b/src/mainboard/dell/optiplex_9020/cmos.layout -@@ -22,7 +22,10 @@ entries - 409 2 e 5 power_on_after_fail - - # turn iommu on or off --412 1 e 6 iommu -+411 1 e 6 iommu -+ -+# coreboot config options: EC -+412 1 e 1 fan_full_speed - - # coreboot config options: check sums - 984 16 h 0 check_sum -diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c -index c834fea5d3..0b7829c736 100644 ---- a/src/mainboard/dell/optiplex_9020/mainboard.c -+++ b/src/mainboard/dell/optiplex_9020/mainboard.c -@@ -1,7 +1,12 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ - -+#include <bootstate.h> -+#include <cpu/x86/msr.h> - #include <device/device.h> - #include <drivers/intel/gma/int15.h> -+#include <option.h> -+#include <southbridge/intel/common/gpio.h> -+#include "sch5555_ec.h" - - static void mainboard_enable(struct device *dev) - { -@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev) - struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - }; -+ -+#define HWM_TAB_ADD_TEMP_TARGET 1 -+#define HWM_TAB_PKG_POWER_ANY 0xffff -+#define CHASSIS_TYPE_UNKNOWN 0xff -+ -+struct hwm_tab_entry { -+ uint16_t addr; -+ uint8_t val; -+ uint8_t flags; -+ uint16_t pkg_power; -+}; -+ -+struct hwm_tab_entry HWM_TAB3[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x8a, 0, 0x0010 }, -+ { 0x086, 0x4c, 0, 0x0010 }, -+ { 0x08a, 0x66, 0, 0x0010 }, -+ { 0x08b, 0x5b, 0, 0x0010 }, -+ { 0x090, 0x65, 0, 0xffff }, -+ { 0x091, 0x70, 0, 0xffff }, -+ { 0x092, 0x86, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x0e, 0, 0xffff }, -+ { 0x0a1, 0x0e, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x86, 0, 0xffff }, -+ { 0x0b0, 0x9a, 0, 0xffff }, -+ { 0x0b3, 0x9a, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x08, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0x0020 }, -+ { 0x0ea, 0x5c, 0, 0x0010 }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x00, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x08, 0, 0xffff }, -+ { 0x1be, 0x99, 0, 0xffff }, -+ { 0x280, 0xa0, 0, 0x0010 }, -+ { 0x281, 0x0f, 0, 0x0010 }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x288, 0x68, 0, 0x0010 }, -+ { 0x289, 0x10, 0, 0x0010 }, -+ { 0x28a, 0x03, 0, 0xffff }, -+ { 0x28b, 0x0a, 0, 0xffff }, -+ { 0x28c, 0x80, 0, 0xffff }, -+ { 0x28d, 0x03, 0, 0xffff }, -+}; -+ -+struct hwm_tab_entry HWM_TAB4[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x99, 0, 0x0020 }, -+ { 0x085, 0xad, 0, 0x0010 }, -+ { 0x086, 0x1c, 0, 0xffff }, -+ { 0x08a, 0x39, 0, 0x0020 }, -+ { 0x08a, 0x41, 0, 0x0010 }, -+ { 0x08b, 0x76, 0, 0x0020 }, -+ { 0x08b, 0x8b, 0, 0x0010 }, -+ { 0x090, 0x5e, 0, 0xffff }, -+ { 0x091, 0x5e, 0, 0xffff }, -+ { 0x092, 0x86, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa4, 0, 0xffff }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x0a, 0, 0xffff }, -+ { 0x0a1, 0x0a, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x7c, 0, 0xffff }, -+ { 0x0b0, 0x9a, 0, 0xffff }, -+ { 0x0b3, 0x7c, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x08, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0x0020 }, -+ { 0x0ea, 0x5c, 0, 0x0010 }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x00, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x08, 0, 0xffff }, -+ { 0x1be, 0x90, 0, 0xffff }, -+ { 0x280, 0x94, 0, 0x0020 }, -+ { 0x281, 0x11, 0, 0x0020 }, -+ { 0x280, 0x94, 0, 0x0010 }, -+ { 0x281, 0x11, 0, 0x0010 }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x288, 0x28, 0, 0x0020 }, -+ { 0x289, 0x0a, 0, 0x0020 }, -+ { 0x288, 0x28, 0, 0x0010 }, -+ { 0x289, 0x0a, 0, 0x0010 }, -+ { 0x28a, 0x03, 0, 0xffff }, -+ { 0x28b, 0x0a, 0, 0xffff }, -+ { 0x28c, 0x80, 0, 0xffff }, -+ { 0x28d, 0x03, 0, 0xffff }, -+}; -+ -+struct hwm_tab_entry HWM_TAB5[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x66, 0, 0x0020 }, -+ { 0x085, 0x5d, 0, 0x0010 }, -+ { 0x086, 0x1c, 0, 0xffff }, -+ { 0x08a, 0x39, 0, 0x0020 }, -+ { 0x08a, 0x41, 0, 0x0010 }, -+ { 0x08b, 0x76, 0, 0x0020 }, -+ { 0x08b, 0x80, 0, 0x0010 }, -+ { 0x090, 0x5d, 0, 0x0020 }, -+ { 0x090, 0x5e, 0, 0x0010 }, -+ { 0x091, 0x5e, 0, 0xffff }, -+ { 0x092, 0x86, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0xa3, 0, 0x0020 }, -+ { 0x098, 0xa4, 0, 0x0010 }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x08, 0, 0xffff }, -+ { 0x0a1, 0x0a, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x7c, 0, 0xffff }, -+ { 0x0b0, 0x9a, 0, 0xffff }, -+ { 0x0b3, 0x7c, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x08, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0x0020 }, -+ { 0x0ea, 0x5c, 0, 0x0010 }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x00, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x08, 0, 0xffff }, -+ { 0x1be, 0x98, 0, 0x0020 }, -+ { 0x1be, 0x90, 0, 0x0010 }, -+ { 0x280, 0x94, 0, 0x0020 }, -+ { 0x281, 0x11, 0, 0x0020 }, -+ { 0x280, 0x94, 0, 0x0010 }, -+ { 0x281, 0x11, 0, 0x0010 }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x288, 0x28, 0, 0x0020 }, -+ { 0x289, 0x0a, 0, 0x0020 }, -+ { 0x288, 0x28, 0, 0x0010 }, -+ { 0x289, 0x0a, 0, 0x0010 }, -+ { 0x28a, 0x03, 0, 0xffff }, -+ { 0x28b, 0x0a, 0, 0xffff }, -+ { 0x28c, 0x80, 0, 0xffff }, -+ { 0x28d, 0x03, 0, 0xffff }, -+}; -+ -+struct hwm_tab_entry HWM_TAB6[] = { -+ { 0x005, 0x33, 0, 0xffff }, -+ { 0x018, 0x2f, 0, 0xffff }, -+ { 0x019, 0x2f, 0, 0xffff }, -+ { 0x01a, 0x2f, 0, 0xffff }, -+ { 0x080, 0x00, 0, 0xffff }, -+ { 0x081, 0x00, 0, 0xffff }, -+ { 0x083, 0xbb, 0, 0xffff }, -+ { 0x085, 0x98, 0, 0xffff }, -+ { 0x086, 0x3c, 0, 0xffff }, -+ { 0x08a, 0x39, 0, 0x0020 }, -+ { 0x08a, 0x3d, 0, 0x0010 }, -+ { 0x08b, 0x44, 0, 0x0020 }, -+ { 0x08b, 0x51, 0, 0x0010 }, -+ { 0x090, 0x61, 0, 0xffff }, -+ { 0x091, 0x6d, 0, 0xffff }, -+ { 0x092, 0x86, 0, 0xffff }, -+ { 0x096, 0xa4, 0, 0xffff }, -+ { 0x097, 0xa4, 0, 0xffff }, -+ { 0x098, 0x9f, 0, 0x0020 }, -+ { 0x098, 0xa4, 0, 0x0010 }, -+ { 0x09b, 0xa4, 0, 0xffff }, -+ { 0x0a0, 0x0e, 0, 0xffff }, -+ { 0x0a1, 0x0e, 0, 0xffff }, -+ { 0x0ae, 0x7c, 0, 0xffff }, -+ { 0x0af, 0x7c, 0, 0xffff }, -+ { 0x0b0, 0x9b, 0, 0x0020 }, -+ { 0x0b0, 0x98, 0, 0x0010 }, -+ { 0x0b3, 0x9a, 0, 0xffff }, -+ { 0x0b6, 0x08, 0, 0xffff }, -+ { 0x0b7, 0x08, 0, 0xffff }, -+ { 0x0ea, 0x64, 0, 0x0020 }, -+ { 0x0ea, 0x5c, 0, 0x0010 }, -+ { 0x0ef, 0xff, 0, 0xffff }, -+ { 0x0f8, 0x15, 0, 0xffff }, -+ { 0x0f9, 0x00, 0, 0xffff }, -+ { 0x0f0, 0x30, 0, 0xffff }, -+ { 0x0fd, 0x01, 0, 0xffff }, -+ { 0x1a1, 0x00, 0, 0xffff }, -+ { 0x1a2, 0x00, 0, 0xffff }, -+ { 0x1b1, 0x08, 0, 0xffff }, -+ { 0x1be, 0x9a, 0, 0x0020 }, -+ { 0x1be, 0x96, 0, 0x0010 }, -+ { 0x280, 0x94, 0, 0x0020 }, -+ { 0x281, 0x11, 0, 0x0020 }, -+ { 0x280, 0x94, 0, 0x0010 }, -+ { 0x281, 0x11, 0, 0x0010 }, -+ { 0x282, 0x03, 0, 0xffff }, -+ { 0x283, 0x0a, 0, 0xffff }, -+ { 0x284, 0x80, 0, 0xffff }, -+ { 0x285, 0x03, 0, 0xffff }, -+ { 0x288, 0x94, 0, 0x0020 }, -+ { 0x289, 0x11, 0, 0x0020 }, -+ { 0x288, 0x94, 0, 0x0010 }, -+ { 0x289, 0x11, 0, 0x0010 }, -+ { 0x28a, 0x03, 0, 0xffff }, -+ { 0x28b, 0x0a, 0, 0xffff }, -+ { 0x28c, 0x80, 0, 0xffff }, -+ { 0x28d, 0x03, 0, 0xffff }, -+}; -+ -+static uint8_t get_chassis_type(void) -+{ -+ uint8_t gpio_chassis_type; -+ -+ // Read chassis type from GPIO -+ gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 | -+ get_gpio(17) << 1 | get_gpio(1); -+ -+ printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type); -+ -+ // Turn it into internal chassis index -+ switch (gpio_chassis_type) { -+ case 0x08: -+ case 0x0a: -+ return 4; -+ case 0x0b: -+ return 3; -+ case 0x0c: -+ return 5; -+ case 0x0d: // SFF -+ case 0x0e: -+ case 0x0f: -+ return 6; -+ default: -+ return CHASSIS_TYPE_UNKNOWN; -+ } -+ -+} -+ -+static uint8_t get_temp_target(void) -+{ -+ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; -+ if (!val) -+ val = 20; -+ return 0x95 - val; -+} -+ -+static uint16_t get_pkg_power(void) -+{ -+ uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf; -+ if (rapl_power_unit) -+ rapl_power_unit = 2 << (rapl_power_unit - 1); -+ uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff; -+ if (pkg_power_info / rapl_power_unit > 0x41) -+ return 32; -+ else -+ return 16; -+} -+ -+static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size) -+{ -+ uint8_t temp_target = get_temp_target(); -+ uint16_t pkg_power = get_pkg_power(); -+ -+ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); -+ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); -+ -+ for (size_t i = 0; i < size; ++i) { -+ // Skip entry if it doesn't apply for this package power -+ if (arr[i].pkg_power != pkg_power && -+ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) -+ continue; -+ -+ uint8_t val = arr[i].val; -+ -+ // Add temp target to value if requested (current tables never do) -+ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) -+ val += temp_target; -+ -+ // Perform write -+ ec_write(1, arr[i].addr, val); -+ -+ } -+} -+ -+static void sch5555_ec_hwm_init(void *arg) -+{ -+ uint8_t chassis_type, saved_2fc; -+ -+ printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n"); -+ -+ saved_2fc = ec_read(1, 0x2fc); -+ ec_write(1, 0x2fc, 0xa0); -+ ec_write(1, 0x2fd, 0x32); -+ -+ chassis_type = get_chassis_type(); -+ -+ if (chassis_type != CHASSIS_TYPE_UNKNOWN) { -+ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); -+ } else { -+ printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n"); -+ } -+ -+ // Apply HWM table based on chassis type -+ switch (chassis_type) { -+ case 3: -+ apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3)); -+ break; -+ case 4: -+ apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4)); -+ break; -+ case 5: -+ apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5)); -+ break; -+ case 6: -+ apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6)); -+ break; -+ } -+ -+ // NOTE: vendor firmware applies these when "max core address" > 2 -+ // i think this is always the case -+ ec_write(1, 0x9e, 0x30); -+ ec_write(1, 0xeb, ec_read(1, 0xea)); -+ -+ ec_write(1, 0x2fc, saved_2fc); -+ -+ // Apply full speed fan config if requested or if the chassis type is unknown -+ if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) { -+ printk(BIOS_DEBUG, "Setting full fan speed\n"); -+ ec_write(1, 0x80, 0x60 | ec_read(1, 0x80)); -+ ec_write(1, 0x81, 0x60 | ec_read(1, 0x81)); -+ } -+ -+ ec_read(1, 0xb8); -+ -+ if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) { -+ ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb); -+ ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb); -+ ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb); -+ ec_write(1, 0x8a, 0x99); -+ ec_write(1, 0x8b, 0x47); -+ ec_write(1, 0x8c, 0x91); -+ } -+} -+ -+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); -diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c -new file mode 100644 -index 0000000000..a1067ac063 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c -@@ -0,0 +1,54 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#include <arch/io.h> -+#include <device/pnp_ops.h> -+#include <superio/smsc/sch555x/sch555x.h> -+#include "sch5555_ec.h" -+ -+uint8_t ec_read(uint8_t addr1, uint16_t addr2) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+ -+ // read result -+ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); -+ return inb(SCH555x_EMI_IOBASE + 4); -+} -+ -+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) -+{ -+ // clear ec-to-host mailbox -+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); -+ outb(tmp, SCH555x_EMI_IOBASE + 1); -+ -+ // send address and value -+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); -+ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); -+ -+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); -+ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); -+ -+ // send message to ec -+ outb(1, SCH555x_EMI_IOBASE); -+ -+ // wait for ack -+ for (size_t retry = 0; retry < 0xfff; ++retry) -+ if (inb(SCH555x_EMI_IOBASE + 1) & 1) -+ break; -+} -diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h -new file mode 100644 -index 0000000000..7e399e8e74 ---- /dev/null -+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h -@@ -0,0 +1,10 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __SCH5555_EC_H__ -+#define __SCH5555_EC_H__ -+ -+uint8_t ec_read(uint8_t addr1, uint16_t addr2); -+ -+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val); -+ -+#endif --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch deleted file mode 100644 index fb112f8c..00000000 --- a/config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch +++ /dev/null @@ -1,51 +0,0 @@ -From ae494dc1b1dde92ec42390b85ced0ffe816f5110 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Sat, 6 Apr 2024 01:22:47 +0100 -Subject: [PATCH 4/4] nb/haswell: Fully disable iGPU when dGPU is used - -My earlier patch disabled decode *and* disabled the iGPU itself, but -a subsequent revision disabled only VGA decode. Upon revisiting, I -found that, actually, yes, you also need to disable the iGPU entirely. - -Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU. -With this patch, the iGPU is completely disabled when you install a -graphics card, but the iGPU is available to use when no graphics card -is present. - -For more context, see: - -Author: Leah Rowe <info@minifree.org> -Date: Fri Feb 23 13:33:31 2024 +0000 - - nb/haswell: Disable iGPU when dGPU is used - -And look at the Gerrit comments: - -https://review.coreboot.org/c/coreboot/+/80717/ - -So, my original submission on change 80717 was actually correct. -This patch fixes the issue. I tested on iGPU and dGPU, with both -broadwell and haswell mrc.bin. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/northbridge/intel/haswell/gma.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c -index 9e9f9804f5..526a51aff0 100644 ---- a/src/northbridge/intel/haswell/gma.c -+++ b/src/northbridge/intel/haswell/gma.c -@@ -464,6 +464,9 @@ static void gma_func0_disable(struct device *dev) - { - /* Disable VGA decode */ - pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); -+ -+ /* Required or else the graphics card doesn't work */ -+ dev->enabled = 0; - } - - static struct device_operations gma_func0_ops = { --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch b/config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch deleted file mode 100644 index 52147426..00000000 --- a/config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 355536155898e649fa50277136ccd2df53a52bb1 Mon Sep 17 00:00:00 2001 -From: Mate Kukri <kukri.mate@gmail.com> -Date: Wed, 10 Apr 2024 20:31:35 +0100 -Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device - -These machines come with a TPM1.2 device by default. It is somewhat -obsolete these days, but there is no harm in enabling it. - -Change-Id: Iec05321862aed58695c256b00494e5953219786d -Signed-off-by: Mate Kukri <kukri.mate@gmail.com> -Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827 -Reviewed-by: Angel Pons <th3fanbus@gmail.com> -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> ---- - src/mainboard/dell/optiplex_9020/Kconfig | 2 ++ - src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++ - 2 files changed, 5 insertions(+) - -diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig -index 2de4a9abd6..38c3281e70 100644 ---- a/src/mainboard/dell/optiplex_9020/Kconfig -+++ b/src/mainboard/dell/optiplex_9020/Kconfig -@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS - select INTEL_GMA_HAVE_VBT - select INTEL_INT15 - select MAINBOARD_HAS_LIBGFXINIT -+ select MAINBOARD_HAS_TPM1 - select MAINBOARD_USES_IFD_GBE_REGION -+ select MEMORY_MAPPED_TPM - select NORTHBRIDGE_INTEL_HASWELL - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_LYNXPOINT -diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb -index dce5869478..841285bb9c 100644 ---- a/src/mainboard/dell/optiplex_9020/devicetree.cb -+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb -@@ -70,6 +70,9 @@ chip northbridge/intel/haswell - device pnp 2e.b off end # Floppy Controller - device pnp 2e.11 off end # Parallel Port - end -+ chip drivers/pc80/tpm -+ device pnp 0c31.0 on end -+ end - end - device pci 1f.2 on end # SATA controller 1 - device pci 1f.3 on end # SMBus --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0026-use-mirrorservice.org-for-iasl-downloads.patch b/config/coreboot/haswell/patches/0026-use-mirrorservice.org-for-iasl-downloads.patch deleted file mode 100644 index f9981abd..00000000 --- a/config/coreboot/haswell/patches/0026-use-mirrorservice.org-for-iasl-downloads.patch +++ /dev/null @@ -1,28 +0,0 @@ -From ed30cca924fa576dd5b69ce4a348b5a1466a8db1 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Sun, 28 Apr 2024 01:57:46 +0100 -Subject: [PATCH 1/1] use mirrorservice.org for iasl downloads - -github is unreliable. i mirror these files myself. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - util/crossgcc/buildgcc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 6ae201239d..a8433a25e5 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -74,7 +74,7 @@ MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" - MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" - GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" - BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" --IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" -+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" - # CLANG toolchain archive locations - LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" - CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0027-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/haswell/patches/0027-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch deleted file mode 100644 index 9b6020a2..00000000 --- a/config/coreboot/haswell/patches/0027-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch +++ /dev/null @@ -1,55 +0,0 @@ -From b75d9e385137b3b561fc7220c04f742817d319b2 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Sat, 4 May 2024 02:00:53 +0100 -Subject: [PATCH 1/1] nb/haswell: lock policy regs when disabling IOMMU - -Angel Pons told me I should do it. See comments here: -https://review.coreboot.org/c/coreboot/+/81016 - -I see no harm in complying with the request. I'll merge -this into the main patch at a later date and try to -get this upstreamed. - -Just a reminder: on Optiplex 9020 variants, Xorg locks up -under Linux when tested with a graphics card; disabling -IOMMU works around the issue. Intel graphics work just fine -with IOMMU turned on. Libreboot disables IOMMU by default, -on the 9020, so that users can install graphics cards easily. - -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/northbridge/intel/haswell/early_init.c | 15 +++++++-------- - 1 file changed, 7 insertions(+), 8 deletions(-) - -diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c -index 1a7e0b1076..e9506ee830 100644 ---- a/src/northbridge/intel/haswell/early_init.c -+++ b/src/northbridge/intel/haswell/early_init.c -@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void) - const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); - u8 enable_iommu = get_uint_option("iommu", 1); - -- if (!enable_iommu) -- return; -- - if (capid0_a & VTD_DISABLE) - return; - -- /* Setup BARs: zeroize top 32 bits; set enable bit */ -- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); -- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); -- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); -- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); -+ if (enable_iommu) { -+ /* Setup BARs: zeroize top 32 bits; set enable bit */ -+ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); -+ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); -+ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); -+ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); -+ } - - /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ - u32 reg32; --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0028-nb-intel-haswell-Synchronize-lists-of-graphics-PCI-I.patch b/config/coreboot/haswell/patches/0028-nb-intel-haswell-Synchronize-lists-of-graphics-PCI-I.patch deleted file mode 100644 index 422b291e..00000000 --- a/config/coreboot/haswell/patches/0028-nb-intel-haswell-Synchronize-lists-of-graphics-PCI-I.patch +++ /dev/null @@ -1,44 +0,0 @@ -From bfb39806c9edbfee7383c99a73e228a5314ee2c2 Mon Sep 17 00:00:00 2001 -From: Nico Huber <nico.h@gmx.de> -Date: Mon, 03 Jun 2024 20:08:26 +0200 -Subject: [PATCH] nb/intel/haswell: Synchronize lists of graphics PCI IDs - -Both, the list of IDs that we hooked our driver up to and the list -that we use for VBIOS mapping, had gaps. Fill those. - -Change-Id: I97c09bb113cf0f35ae158abbd0ba2632dbad7cad -Signed-off-by: Nico Huber <nico.h@gmx.de> -Reviewed-on: https://review.coreboot.org/c/coreboot/+/82787 -Tested-by: build bot (Jenkins) <no-reply@coreboot.org> -Reviewed-by: Angel Pons <th3fanbus@gmail.com> ---- - -diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c -index 9e9f980..f7fad31 100644 ---- a/src/northbridge/intel/haswell/gma.c -+++ b/src/northbridge/intel/haswell/gma.c -@@ -93,12 +93,14 @@ - case 0x80860406: /* GT1 Mobile */ - case 0x8086040a: /* GT1 Server */ - case 0x80860a06: /* GT1 ULT */ -+ case 0x80860a0e: /* GT1 ULX */ - - case 0x80860412: /* GT2 Desktop */ - case 0x80860416: /* GT2 Mobile */ - case 0x8086041a: /* GT2 Server */ - case 0x8086041e: /* GT1.5 Desktop */ - case 0x80860a16: /* GT2 ULT */ -+ case 0x80860a1e: /* GT2 ULX */ - - case 0x80860422: /* GT3 Desktop */ - case 0x80860426: /* GT3 Mobile */ -@@ -485,6 +487,9 @@ - 0x0406, /* Mobile GT1 */ - 0x0416, /* Mobile GT2 */ - 0x0426, /* Mobile GT3 */ -+ 0x040a, /* Server GT1 */ -+ 0x041a, /* Server GT2 */ -+ 0x042a, /* Server GT3 */ - 0x0d16, /* Mobile 4+3 GT1 */ - 0x0d26, /* Mobile 4+3 GT2, Mobile GT3e */ - 0x0d36, /* Mobile 4+3 GT3 */ diff --git a/config/coreboot/haswell/patches/0029-mb-dell-optiplex_9020-Fix-integrated-video-port-list.patch b/config/coreboot/haswell/patches/0029-mb-dell-optiplex_9020-Fix-integrated-video-port-list.patch deleted file mode 100644 index b599e236..00000000 --- a/config/coreboot/haswell/patches/0029-mb-dell-optiplex_9020-Fix-integrated-video-port-list.patch +++ /dev/null @@ -1,30 +0,0 @@ -From c8929f5fb43b6e9b491ae00885be507d01b2a896 Mon Sep 17 00:00:00 2001 -From: Mate Kukri <kukri.mate@gmail.com> -Date: Tue, 11 Jun 2024 20:26:16 +0100 -Subject: [PATCH] mb/dell/optiplex_9020: Fix integrated video port list - -- Physical DP ports are DP2/DP3 (HDMI2/HDMI3 for DP++) -- VGA port is Analog -- DP1 is not connected - -Signed-off-by: Mate Kukri <kukri.mate@gmail.com> -Change-Id: I8ed79167d5445d607acbee491c3382ff2585583f ---- - -diff --git a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads -index 173f2f1..7d95061 100644 ---- a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads -+++ b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads -@@ -9,9 +9,10 @@ - private package GMA.Mainboard is - - ports : constant Port_List := -- (DP1, -- DP2, -+ (DP2, - DP3, -+ HDMI2, -+ HDMI3, - Analog, - others => Disabled); - diff --git a/config/coreboot/haswell/target.cfg b/config/coreboot/haswell/target.cfg deleted file mode 100644 index 69f9bd39..00000000 --- a/config/coreboot/haswell/target.cfg +++ /dev/null @@ -1,2 +0,0 @@ -tree="haswell" -rev="b7341da19133991efd29880849bdaab29a6e243d" diff --git a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb index dd614202..19816005 100644 --- a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb @@ -37,7 +37,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +54,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +66,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set # CONFIG_VENDOR_DELL is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +94,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -126,12 +128,16 @@ CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" CONFIG_VARIANT_DIR="t440p" CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 @@ -154,6 +160,7 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y @@ -205,14 +212,14 @@ CONFIG_PS2M_EISAID="LEN0036" CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" # CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -400,6 +407,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -522,8 +530,8 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -# CONFIG_NO_TPM is not set CONFIG_TPM1=y +# CONFIG_TPM2 is not set CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set diff --git a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode index a0dce901..d9627c4e 100644 --- a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode @@ -37,7 +37,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +54,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +66,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set # CONFIG_VENDOR_DELL is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +94,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -124,12 +126,16 @@ CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" CONFIG_VARIANT_DIR="t440p" CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 @@ -152,6 +158,7 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y @@ -203,14 +210,14 @@ CONFIG_PS2M_EISAID="LEN0036" CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" # CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -398,6 +405,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -519,8 +527,8 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -# CONFIG_NO_TPM is not set CONFIG_TPM1=y +# CONFIG_TPM2 is not set CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set diff --git a/config/coreboot/t440plibremrc_12mb/target.cfg b/config/coreboot/t440plibremrc_12mb/target.cfg index 6d2e9a22..e7411d7f 100644 --- a/config/coreboot/t440plibremrc_12mb/target.cfg +++ b/config/coreboot/t440plibremrc_12mb/target.cfg @@ -1,4 +1,4 @@ -tree="haswell" +tree="default" xarch="i386-elf" payload_seabios="y" payload_grub="y" diff --git a/config/coreboot/w541_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541_12mb/config/libgfxinit_corebootfb index ae155585..944e3b3d 100644 --- a/config/coreboot/w541_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w541_12mb/config/libgfxinit_corebootfb @@ -37,7 +37,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +54,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +66,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set # CONFIG_VENDOR_DELL is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +94,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -126,12 +128,16 @@ CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" CONFIG_VARIANT_DIR="w541" CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 @@ -154,6 +160,7 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y @@ -205,14 +212,14 @@ CONFIG_PS2M_EISAID="LEN004A" CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" CONFIG_GFX_GMA_PANEL_1_PORT="DP3" CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" # CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -400,6 +407,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -521,8 +529,8 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -# CONFIG_NO_TPM is not set CONFIG_TPM1=y +# CONFIG_TPM2 is not set CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set diff --git a/config/coreboot/w541_12mb/config/libgfxinit_txtmode b/config/coreboot/w541_12mb/config/libgfxinit_txtmode index 9a891434..e07e8867 100644 --- a/config/coreboot/w541_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w541_12mb/config/libgfxinit_txtmode @@ -37,7 +37,6 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set # # Software Bill Of Materials (SBOM) @@ -55,8 +54,8 @@ CONFIG_NO_STAGE_CACHE=y # # CONFIG_VENDOR_51NB is not set # CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set @@ -67,11 +66,13 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set # CONFIG_VENDOR_DELL is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GOOGLE is not set @@ -93,6 +94,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_PRODRIVE is not set # CONFIG_VENDOR_PROTECTLI is not set # CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set # CONFIG_VENDOR_RAZER is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set @@ -124,12 +126,16 @@ CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" CONFIG_VARIANT_DIR="w541" CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_MAX_SOCKET=1 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 @@ -152,6 +158,7 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_STMICRO=y @@ -203,14 +210,14 @@ CONFIG_PS2M_EISAID="LEN004A" CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" CONFIG_GFX_GMA_PANEL_1_PORT="DP3" CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" # CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -398,6 +405,7 @@ CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y # CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 # end of Chipset # @@ -518,8 +526,8 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -# CONFIG_NO_TPM is not set CONFIG_TPM1=y +# CONFIG_TPM2 is not set CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set diff --git a/config/coreboot/w541_12mb/target.cfg b/config/coreboot/w541_12mb/target.cfg index 6d2e9a22..e7411d7f 100644 --- a/config/coreboot/w541_12mb/target.cfg +++ b/config/coreboot/w541_12mb/target.cfg @@ -1,4 +1,4 @@ -tree="haswell" +tree="default" xarch="i386-elf" payload_seabios="y" payload_grub="y" |